1 /* 2 * SMSC LAN9118 Ethernet interface emulation 3 * 4 * Copyright (c) 2009 CodeSourcery, LLC. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GNU GPL v2 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "hw/sysbus.h" 14 #include "net/net.h" 15 #include "hw/devices.h" 16 #include "sysemu/sysemu.h" 17 #include "hw/ptimer.h" 18 /* For crc32 */ 19 #include <zlib.h> 20 21 //#define DEBUG_LAN9118 22 23 #ifdef DEBUG_LAN9118 24 #define DPRINTF(fmt, ...) \ 25 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) 26 #define BADF(fmt, ...) \ 27 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) 28 #else 29 #define DPRINTF(fmt, ...) do {} while(0) 30 #define BADF(fmt, ...) \ 31 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) 32 #endif 33 34 #define CSR_ID_REV 0x50 35 #define CSR_IRQ_CFG 0x54 36 #define CSR_INT_STS 0x58 37 #define CSR_INT_EN 0x5c 38 #define CSR_BYTE_TEST 0x64 39 #define CSR_FIFO_INT 0x68 40 #define CSR_RX_CFG 0x6c 41 #define CSR_TX_CFG 0x70 42 #define CSR_HW_CFG 0x74 43 #define CSR_RX_DP_CTRL 0x78 44 #define CSR_RX_FIFO_INF 0x7c 45 #define CSR_TX_FIFO_INF 0x80 46 #define CSR_PMT_CTRL 0x84 47 #define CSR_GPIO_CFG 0x88 48 #define CSR_GPT_CFG 0x8c 49 #define CSR_GPT_CNT 0x90 50 #define CSR_WORD_SWAP 0x98 51 #define CSR_FREE_RUN 0x9c 52 #define CSR_RX_DROP 0xa0 53 #define CSR_MAC_CSR_CMD 0xa4 54 #define CSR_MAC_CSR_DATA 0xa8 55 #define CSR_AFC_CFG 0xac 56 #define CSR_E2P_CMD 0xb0 57 #define CSR_E2P_DATA 0xb4 58 59 /* IRQ_CFG */ 60 #define IRQ_INT 0x00001000 61 #define IRQ_EN 0x00000100 62 #define IRQ_POL 0x00000010 63 #define IRQ_TYPE 0x00000001 64 65 /* INT_STS/INT_EN */ 66 #define SW_INT 0x80000000 67 #define TXSTOP_INT 0x02000000 68 #define RXSTOP_INT 0x01000000 69 #define RXDFH_INT 0x00800000 70 #define TX_IOC_INT 0x00200000 71 #define RXD_INT 0x00100000 72 #define GPT_INT 0x00080000 73 #define PHY_INT 0x00040000 74 #define PME_INT 0x00020000 75 #define TXSO_INT 0x00010000 76 #define RWT_INT 0x00008000 77 #define RXE_INT 0x00004000 78 #define TXE_INT 0x00002000 79 #define TDFU_INT 0x00000800 80 #define TDFO_INT 0x00000400 81 #define TDFA_INT 0x00000200 82 #define TSFF_INT 0x00000100 83 #define TSFL_INT 0x00000080 84 #define RXDF_INT 0x00000040 85 #define RDFL_INT 0x00000020 86 #define RSFF_INT 0x00000010 87 #define RSFL_INT 0x00000008 88 #define GPIO2_INT 0x00000004 89 #define GPIO1_INT 0x00000002 90 #define GPIO0_INT 0x00000001 91 #define RESERVED_INT 0x7c001000 92 93 #define MAC_CR 1 94 #define MAC_ADDRH 2 95 #define MAC_ADDRL 3 96 #define MAC_HASHH 4 97 #define MAC_HASHL 5 98 #define MAC_MII_ACC 6 99 #define MAC_MII_DATA 7 100 #define MAC_FLOW 8 101 #define MAC_VLAN1 9 /* TODO */ 102 #define MAC_VLAN2 10 /* TODO */ 103 #define MAC_WUFF 11 /* TODO */ 104 #define MAC_WUCSR 12 /* TODO */ 105 106 #define MAC_CR_RXALL 0x80000000 107 #define MAC_CR_RCVOWN 0x00800000 108 #define MAC_CR_LOOPBK 0x00200000 109 #define MAC_CR_FDPX 0x00100000 110 #define MAC_CR_MCPAS 0x00080000 111 #define MAC_CR_PRMS 0x00040000 112 #define MAC_CR_INVFILT 0x00020000 113 #define MAC_CR_PASSBAD 0x00010000 114 #define MAC_CR_HO 0x00008000 115 #define MAC_CR_HPFILT 0x00002000 116 #define MAC_CR_LCOLL 0x00001000 117 #define MAC_CR_BCAST 0x00000800 118 #define MAC_CR_DISRTY 0x00000400 119 #define MAC_CR_PADSTR 0x00000100 120 #define MAC_CR_BOLMT 0x000000c0 121 #define MAC_CR_DFCHK 0x00000020 122 #define MAC_CR_TXEN 0x00000008 123 #define MAC_CR_RXEN 0x00000004 124 #define MAC_CR_RESERVED 0x7f404213 125 126 #define PHY_INT_ENERGYON 0x80 127 #define PHY_INT_AUTONEG_COMPLETE 0x40 128 #define PHY_INT_FAULT 0x20 129 #define PHY_INT_DOWN 0x10 130 #define PHY_INT_AUTONEG_LP 0x08 131 #define PHY_INT_PARFAULT 0x04 132 #define PHY_INT_AUTONEG_PAGE 0x02 133 134 #define GPT_TIMER_EN 0x20000000 135 136 enum tx_state { 137 TX_IDLE, 138 TX_B, 139 TX_DATA 140 }; 141 142 typedef struct { 143 /* state is a tx_state but we can't put enums in VMStateDescriptions. */ 144 uint32_t state; 145 uint32_t cmd_a; 146 uint32_t cmd_b; 147 int32_t buffer_size; 148 int32_t offset; 149 int32_t pad; 150 int32_t fifo_used; 151 int32_t len; 152 uint8_t data[2048]; 153 } LAN9118Packet; 154 155 static const VMStateDescription vmstate_lan9118_packet = { 156 .name = "lan9118_packet", 157 .version_id = 1, 158 .minimum_version_id = 1, 159 .fields = (VMStateField[]) { 160 VMSTATE_UINT32(state, LAN9118Packet), 161 VMSTATE_UINT32(cmd_a, LAN9118Packet), 162 VMSTATE_UINT32(cmd_b, LAN9118Packet), 163 VMSTATE_INT32(buffer_size, LAN9118Packet), 164 VMSTATE_INT32(offset, LAN9118Packet), 165 VMSTATE_INT32(pad, LAN9118Packet), 166 VMSTATE_INT32(fifo_used, LAN9118Packet), 167 VMSTATE_INT32(len, LAN9118Packet), 168 VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048), 169 VMSTATE_END_OF_LIST() 170 } 171 }; 172 173 typedef struct { 174 SysBusDevice busdev; 175 NICState *nic; 176 NICConf conf; 177 qemu_irq irq; 178 MemoryRegion mmio; 179 ptimer_state *timer; 180 181 uint32_t irq_cfg; 182 uint32_t int_sts; 183 uint32_t int_en; 184 uint32_t fifo_int; 185 uint32_t rx_cfg; 186 uint32_t tx_cfg; 187 uint32_t hw_cfg; 188 uint32_t pmt_ctrl; 189 uint32_t gpio_cfg; 190 uint32_t gpt_cfg; 191 uint32_t word_swap; 192 uint32_t free_timer_start; 193 uint32_t mac_cmd; 194 uint32_t mac_data; 195 uint32_t afc_cfg; 196 uint32_t e2p_cmd; 197 uint32_t e2p_data; 198 199 uint32_t mac_cr; 200 uint32_t mac_hashh; 201 uint32_t mac_hashl; 202 uint32_t mac_mii_acc; 203 uint32_t mac_mii_data; 204 uint32_t mac_flow; 205 206 uint32_t phy_status; 207 uint32_t phy_control; 208 uint32_t phy_advertise; 209 uint32_t phy_int; 210 uint32_t phy_int_mask; 211 212 int32_t eeprom_writable; 213 uint8_t eeprom[128]; 214 215 int32_t tx_fifo_size; 216 LAN9118Packet *txp; 217 LAN9118Packet tx_packet; 218 219 int32_t tx_status_fifo_used; 220 int32_t tx_status_fifo_head; 221 uint32_t tx_status_fifo[512]; 222 223 int32_t rx_status_fifo_size; 224 int32_t rx_status_fifo_used; 225 int32_t rx_status_fifo_head; 226 uint32_t rx_status_fifo[896]; 227 int32_t rx_fifo_size; 228 int32_t rx_fifo_used; 229 int32_t rx_fifo_head; 230 uint32_t rx_fifo[3360]; 231 int32_t rx_packet_size_head; 232 int32_t rx_packet_size_tail; 233 int32_t rx_packet_size[1024]; 234 235 int32_t rxp_offset; 236 int32_t rxp_size; 237 int32_t rxp_pad; 238 239 uint32_t write_word_prev_offset; 240 uint32_t write_word_n; 241 uint16_t write_word_l; 242 uint16_t write_word_h; 243 uint32_t read_word_prev_offset; 244 uint32_t read_word_n; 245 uint32_t read_long; 246 247 uint32_t mode_16bit; 248 } lan9118_state; 249 250 static const VMStateDescription vmstate_lan9118 = { 251 .name = "lan9118", 252 .version_id = 2, 253 .minimum_version_id = 1, 254 .fields = (VMStateField[]) { 255 VMSTATE_PTIMER(timer, lan9118_state), 256 VMSTATE_UINT32(irq_cfg, lan9118_state), 257 VMSTATE_UINT32(int_sts, lan9118_state), 258 VMSTATE_UINT32(int_en, lan9118_state), 259 VMSTATE_UINT32(fifo_int, lan9118_state), 260 VMSTATE_UINT32(rx_cfg, lan9118_state), 261 VMSTATE_UINT32(tx_cfg, lan9118_state), 262 VMSTATE_UINT32(hw_cfg, lan9118_state), 263 VMSTATE_UINT32(pmt_ctrl, lan9118_state), 264 VMSTATE_UINT32(gpio_cfg, lan9118_state), 265 VMSTATE_UINT32(gpt_cfg, lan9118_state), 266 VMSTATE_UINT32(word_swap, lan9118_state), 267 VMSTATE_UINT32(free_timer_start, lan9118_state), 268 VMSTATE_UINT32(mac_cmd, lan9118_state), 269 VMSTATE_UINT32(mac_data, lan9118_state), 270 VMSTATE_UINT32(afc_cfg, lan9118_state), 271 VMSTATE_UINT32(e2p_cmd, lan9118_state), 272 VMSTATE_UINT32(e2p_data, lan9118_state), 273 VMSTATE_UINT32(mac_cr, lan9118_state), 274 VMSTATE_UINT32(mac_hashh, lan9118_state), 275 VMSTATE_UINT32(mac_hashl, lan9118_state), 276 VMSTATE_UINT32(mac_mii_acc, lan9118_state), 277 VMSTATE_UINT32(mac_mii_data, lan9118_state), 278 VMSTATE_UINT32(mac_flow, lan9118_state), 279 VMSTATE_UINT32(phy_status, lan9118_state), 280 VMSTATE_UINT32(phy_control, lan9118_state), 281 VMSTATE_UINT32(phy_advertise, lan9118_state), 282 VMSTATE_UINT32(phy_int, lan9118_state), 283 VMSTATE_UINT32(phy_int_mask, lan9118_state), 284 VMSTATE_INT32(eeprom_writable, lan9118_state), 285 VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), 286 VMSTATE_INT32(tx_fifo_size, lan9118_state), 287 /* txp always points at tx_packet so need not be saved */ 288 VMSTATE_STRUCT(tx_packet, lan9118_state, 0, 289 vmstate_lan9118_packet, LAN9118Packet), 290 VMSTATE_INT32(tx_status_fifo_used, lan9118_state), 291 VMSTATE_INT32(tx_status_fifo_head, lan9118_state), 292 VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512), 293 VMSTATE_INT32(rx_status_fifo_size, lan9118_state), 294 VMSTATE_INT32(rx_status_fifo_used, lan9118_state), 295 VMSTATE_INT32(rx_status_fifo_head, lan9118_state), 296 VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896), 297 VMSTATE_INT32(rx_fifo_size, lan9118_state), 298 VMSTATE_INT32(rx_fifo_used, lan9118_state), 299 VMSTATE_INT32(rx_fifo_head, lan9118_state), 300 VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360), 301 VMSTATE_INT32(rx_packet_size_head, lan9118_state), 302 VMSTATE_INT32(rx_packet_size_tail, lan9118_state), 303 VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024), 304 VMSTATE_INT32(rxp_offset, lan9118_state), 305 VMSTATE_INT32(rxp_size, lan9118_state), 306 VMSTATE_INT32(rxp_pad, lan9118_state), 307 VMSTATE_UINT32_V(write_word_prev_offset, lan9118_state, 2), 308 VMSTATE_UINT32_V(write_word_n, lan9118_state, 2), 309 VMSTATE_UINT16_V(write_word_l, lan9118_state, 2), 310 VMSTATE_UINT16_V(write_word_h, lan9118_state, 2), 311 VMSTATE_UINT32_V(read_word_prev_offset, lan9118_state, 2), 312 VMSTATE_UINT32_V(read_word_n, lan9118_state, 2), 313 VMSTATE_UINT32_V(read_long, lan9118_state, 2), 314 VMSTATE_UINT32_V(mode_16bit, lan9118_state, 2), 315 VMSTATE_END_OF_LIST() 316 } 317 }; 318 319 static void lan9118_update(lan9118_state *s) 320 { 321 int level; 322 323 /* TODO: Implement FIFO level IRQs. */ 324 level = (s->int_sts & s->int_en) != 0; 325 if (level) { 326 s->irq_cfg |= IRQ_INT; 327 } else { 328 s->irq_cfg &= ~IRQ_INT; 329 } 330 if ((s->irq_cfg & IRQ_EN) == 0) { 331 level = 0; 332 } 333 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) { 334 /* Interrupt is active low unless we're configured as 335 * active-high polarity, push-pull type. 336 */ 337 level = !level; 338 } 339 qemu_set_irq(s->irq, level); 340 } 341 342 static void lan9118_mac_changed(lan9118_state *s) 343 { 344 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 345 } 346 347 static void lan9118_reload_eeprom(lan9118_state *s) 348 { 349 int i; 350 if (s->eeprom[0] != 0xa5) { 351 s->e2p_cmd &= ~0x10; 352 DPRINTF("MACADDR load failed\n"); 353 return; 354 } 355 for (i = 0; i < 6; i++) { 356 s->conf.macaddr.a[i] = s->eeprom[i + 1]; 357 } 358 s->e2p_cmd |= 0x10; 359 DPRINTF("MACADDR loaded from eeprom\n"); 360 lan9118_mac_changed(s); 361 } 362 363 static void phy_update_irq(lan9118_state *s) 364 { 365 if (s->phy_int & s->phy_int_mask) { 366 s->int_sts |= PHY_INT; 367 } else { 368 s->int_sts &= ~PHY_INT; 369 } 370 lan9118_update(s); 371 } 372 373 static void phy_update_link(lan9118_state *s) 374 { 375 /* Autonegotiation status mirrors link status. */ 376 if (qemu_get_queue(s->nic)->link_down) { 377 s->phy_status &= ~0x0024; 378 s->phy_int |= PHY_INT_DOWN; 379 } else { 380 s->phy_status |= 0x0024; 381 s->phy_int |= PHY_INT_ENERGYON; 382 s->phy_int |= PHY_INT_AUTONEG_COMPLETE; 383 } 384 phy_update_irq(s); 385 } 386 387 static void lan9118_set_link(NetClientState *nc) 388 { 389 phy_update_link(qemu_get_nic_opaque(nc)); 390 } 391 392 static void phy_reset(lan9118_state *s) 393 { 394 s->phy_status = 0x7809; 395 s->phy_control = 0x3000; 396 s->phy_advertise = 0x01e1; 397 s->phy_int_mask = 0; 398 s->phy_int = 0; 399 phy_update_link(s); 400 } 401 402 static void lan9118_reset(DeviceState *d) 403 { 404 lan9118_state *s = FROM_SYSBUS(lan9118_state, SYS_BUS_DEVICE(d)); 405 s->irq_cfg &= (IRQ_TYPE | IRQ_POL); 406 s->int_sts = 0; 407 s->int_en = 0; 408 s->fifo_int = 0x48000000; 409 s->rx_cfg = 0; 410 s->tx_cfg = 0; 411 s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004; 412 s->pmt_ctrl &= 0x45; 413 s->gpio_cfg = 0; 414 s->txp->fifo_used = 0; 415 s->txp->state = TX_IDLE; 416 s->txp->cmd_a = 0xffffffffu; 417 s->txp->cmd_b = 0xffffffffu; 418 s->txp->len = 0; 419 s->txp->fifo_used = 0; 420 s->tx_fifo_size = 4608; 421 s->tx_status_fifo_used = 0; 422 s->rx_status_fifo_size = 704; 423 s->rx_fifo_size = 2640; 424 s->rx_fifo_used = 0; 425 s->rx_status_fifo_size = 176; 426 s->rx_status_fifo_used = 0; 427 s->rxp_offset = 0; 428 s->rxp_size = 0; 429 s->rxp_pad = 0; 430 s->rx_packet_size_tail = s->rx_packet_size_head; 431 s->rx_packet_size[s->rx_packet_size_head] = 0; 432 s->mac_cmd = 0; 433 s->mac_data = 0; 434 s->afc_cfg = 0; 435 s->e2p_cmd = 0; 436 s->e2p_data = 0; 437 s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40; 438 439 ptimer_stop(s->timer); 440 ptimer_set_count(s->timer, 0xffff); 441 s->gpt_cfg = 0xffff; 442 443 s->mac_cr = MAC_CR_PRMS; 444 s->mac_hashh = 0; 445 s->mac_hashl = 0; 446 s->mac_mii_acc = 0; 447 s->mac_mii_data = 0; 448 s->mac_flow = 0; 449 450 s->read_word_n = 0; 451 s->write_word_n = 0; 452 453 phy_reset(s); 454 455 s->eeprom_writable = 0; 456 lan9118_reload_eeprom(s); 457 } 458 459 static int lan9118_can_receive(NetClientState *nc) 460 { 461 return 1; 462 } 463 464 static void rx_fifo_push(lan9118_state *s, uint32_t val) 465 { 466 int fifo_pos; 467 fifo_pos = s->rx_fifo_head + s->rx_fifo_used; 468 if (fifo_pos >= s->rx_fifo_size) 469 fifo_pos -= s->rx_fifo_size; 470 s->rx_fifo[fifo_pos] = val; 471 s->rx_fifo_used++; 472 } 473 474 /* Return nonzero if the packet is accepted by the filter. */ 475 static int lan9118_filter(lan9118_state *s, const uint8_t *addr) 476 { 477 int multicast; 478 uint32_t hash; 479 480 if (s->mac_cr & MAC_CR_PRMS) { 481 return 1; 482 } 483 if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff && 484 addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) { 485 return (s->mac_cr & MAC_CR_BCAST) == 0; 486 } 487 488 multicast = addr[0] & 1; 489 if (multicast &&s->mac_cr & MAC_CR_MCPAS) { 490 return 1; 491 } 492 if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0 493 : (s->mac_cr & MAC_CR_HO) == 0) { 494 /* Exact matching. */ 495 hash = memcmp(addr, s->conf.macaddr.a, 6); 496 if (s->mac_cr & MAC_CR_INVFILT) { 497 return hash != 0; 498 } else { 499 return hash == 0; 500 } 501 } else { 502 /* Hash matching */ 503 hash = compute_mcast_idx(addr); 504 if (hash & 0x20) { 505 return (s->mac_hashh >> (hash & 0x1f)) & 1; 506 } else { 507 return (s->mac_hashl >> (hash & 0x1f)) & 1; 508 } 509 } 510 } 511 512 static ssize_t lan9118_receive(NetClientState *nc, const uint8_t *buf, 513 size_t size) 514 { 515 lan9118_state *s = qemu_get_nic_opaque(nc); 516 int fifo_len; 517 int offset; 518 int src_pos; 519 int n; 520 int filter; 521 uint32_t val; 522 uint32_t crc; 523 uint32_t status; 524 525 if ((s->mac_cr & MAC_CR_RXEN) == 0) { 526 return -1; 527 } 528 529 if (size >= 2048 || size < 14) { 530 return -1; 531 } 532 533 /* TODO: Implement FIFO overflow notification. */ 534 if (s->rx_status_fifo_used == s->rx_status_fifo_size) { 535 return -1; 536 } 537 538 filter = lan9118_filter(s, buf); 539 if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) { 540 return size; 541 } 542 543 offset = (s->rx_cfg >> 8) & 0x1f; 544 n = offset & 3; 545 fifo_len = (size + n + 3) >> 2; 546 /* Add a word for the CRC. */ 547 fifo_len++; 548 if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) { 549 return -1; 550 } 551 552 DPRINTF("Got packet len:%d fifo:%d filter:%s\n", 553 (int)size, fifo_len, filter ? "pass" : "fail"); 554 val = 0; 555 crc = bswap32(crc32(~0, buf, size)); 556 for (src_pos = 0; src_pos < size; src_pos++) { 557 val = (val >> 8) | ((uint32_t)buf[src_pos] << 24); 558 n++; 559 if (n == 4) { 560 n = 0; 561 rx_fifo_push(s, val); 562 val = 0; 563 } 564 } 565 if (n) { 566 val >>= ((4 - n) * 8); 567 val |= crc << (n * 8); 568 rx_fifo_push(s, val); 569 val = crc >> ((4 - n) * 8); 570 rx_fifo_push(s, val); 571 } else { 572 rx_fifo_push(s, crc); 573 } 574 n = s->rx_status_fifo_head + s->rx_status_fifo_used; 575 if (n >= s->rx_status_fifo_size) { 576 n -= s->rx_status_fifo_size; 577 } 578 s->rx_packet_size[s->rx_packet_size_tail] = fifo_len; 579 s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023; 580 s->rx_status_fifo_used++; 581 582 status = (size + 4) << 16; 583 if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && 584 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) { 585 status |= 0x00002000; 586 } else if (buf[0] & 1) { 587 status |= 0x00000400; 588 } 589 if (!filter) { 590 status |= 0x40000000; 591 } 592 s->rx_status_fifo[n] = status; 593 594 if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) { 595 s->int_sts |= RSFL_INT; 596 } 597 lan9118_update(s); 598 599 return size; 600 } 601 602 static uint32_t rx_fifo_pop(lan9118_state *s) 603 { 604 int n; 605 uint32_t val; 606 607 if (s->rxp_size == 0 && s->rxp_pad == 0) { 608 s->rxp_size = s->rx_packet_size[s->rx_packet_size_head]; 609 s->rx_packet_size[s->rx_packet_size_head] = 0; 610 if (s->rxp_size != 0) { 611 s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023; 612 s->rxp_offset = (s->rx_cfg >> 10) & 7; 613 n = s->rxp_offset + s->rxp_size; 614 switch (s->rx_cfg >> 30) { 615 case 1: 616 n = (-n) & 3; 617 break; 618 case 2: 619 n = (-n) & 7; 620 break; 621 default: 622 n = 0; 623 break; 624 } 625 s->rxp_pad = n; 626 DPRINTF("Pop packet size:%d offset:%d pad: %d\n", 627 s->rxp_size, s->rxp_offset, s->rxp_pad); 628 } 629 } 630 if (s->rxp_offset > 0) { 631 s->rxp_offset--; 632 val = 0; 633 } else if (s->rxp_size > 0) { 634 s->rxp_size--; 635 val = s->rx_fifo[s->rx_fifo_head++]; 636 if (s->rx_fifo_head >= s->rx_fifo_size) { 637 s->rx_fifo_head -= s->rx_fifo_size; 638 } 639 s->rx_fifo_used--; 640 } else if (s->rxp_pad > 0) { 641 s->rxp_pad--; 642 val = 0; 643 } else { 644 DPRINTF("RX underflow\n"); 645 s->int_sts |= RXE_INT; 646 val = 0; 647 } 648 lan9118_update(s); 649 return val; 650 } 651 652 static void do_tx_packet(lan9118_state *s) 653 { 654 int n; 655 uint32_t status; 656 657 /* FIXME: Honor TX disable, and allow queueing of packets. */ 658 if (s->phy_control & 0x4000) { 659 /* This assumes the receive routine doesn't touch the VLANClient. */ 660 lan9118_receive(qemu_get_queue(s->nic), s->txp->data, s->txp->len); 661 } else { 662 qemu_send_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); 663 } 664 s->txp->fifo_used = 0; 665 666 if (s->tx_status_fifo_used == 512) { 667 /* Status FIFO full */ 668 return; 669 } 670 /* Add entry to status FIFO. */ 671 status = s->txp->cmd_b & 0xffff0000u; 672 DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len); 673 n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511; 674 s->tx_status_fifo[n] = status; 675 s->tx_status_fifo_used++; 676 if (s->tx_status_fifo_used == 512) { 677 s->int_sts |= TSFF_INT; 678 /* TODO: Stop transmission. */ 679 } 680 } 681 682 static uint32_t rx_status_fifo_pop(lan9118_state *s) 683 { 684 uint32_t val; 685 686 val = s->rx_status_fifo[s->rx_status_fifo_head]; 687 if (s->rx_status_fifo_used != 0) { 688 s->rx_status_fifo_used--; 689 s->rx_status_fifo_head++; 690 if (s->rx_status_fifo_head >= s->rx_status_fifo_size) { 691 s->rx_status_fifo_head -= s->rx_status_fifo_size; 692 } 693 /* ??? What value should be returned when the FIFO is empty? */ 694 DPRINTF("RX status pop 0x%08x\n", val); 695 } 696 return val; 697 } 698 699 static uint32_t tx_status_fifo_pop(lan9118_state *s) 700 { 701 uint32_t val; 702 703 val = s->tx_status_fifo[s->tx_status_fifo_head]; 704 if (s->tx_status_fifo_used != 0) { 705 s->tx_status_fifo_used--; 706 s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511; 707 /* ??? What value should be returned when the FIFO is empty? */ 708 } 709 return val; 710 } 711 712 static void tx_fifo_push(lan9118_state *s, uint32_t val) 713 { 714 int n; 715 716 if (s->txp->fifo_used == s->tx_fifo_size) { 717 s->int_sts |= TDFO_INT; 718 return; 719 } 720 switch (s->txp->state) { 721 case TX_IDLE: 722 s->txp->cmd_a = val & 0x831f37ff; 723 s->txp->fifo_used++; 724 s->txp->state = TX_B; 725 break; 726 case TX_B: 727 if (s->txp->cmd_a & 0x2000) { 728 /* First segment */ 729 s->txp->cmd_b = val; 730 s->txp->fifo_used++; 731 s->txp->buffer_size = s->txp->cmd_a & 0x7ff; 732 s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f; 733 /* End alignment does not include command words. */ 734 n = (s->txp->buffer_size + s->txp->offset + 3) >> 2; 735 switch ((n >> 24) & 3) { 736 case 1: 737 n = (-n) & 3; 738 break; 739 case 2: 740 n = (-n) & 7; 741 break; 742 default: 743 n = 0; 744 } 745 s->txp->pad = n; 746 s->txp->len = 0; 747 } 748 DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n", 749 s->txp->buffer_size, s->txp->offset, s->txp->pad, 750 s->txp->cmd_a); 751 s->txp->state = TX_DATA; 752 break; 753 case TX_DATA: 754 if (s->txp->offset >= 4) { 755 s->txp->offset -= 4; 756 break; 757 } 758 if (s->txp->buffer_size <= 0 && s->txp->pad != 0) { 759 s->txp->pad--; 760 } else { 761 n = 4; 762 while (s->txp->offset) { 763 val >>= 8; 764 n--; 765 s->txp->offset--; 766 } 767 /* Documentation is somewhat unclear on the ordering of bytes 768 in FIFO words. Empirical results show it to be little-endian. 769 */ 770 /* TODO: FIFO overflow checking. */ 771 while (n--) { 772 s->txp->data[s->txp->len] = val & 0xff; 773 s->txp->len++; 774 val >>= 8; 775 s->txp->buffer_size--; 776 } 777 s->txp->fifo_used++; 778 } 779 if (s->txp->buffer_size <= 0 && s->txp->pad == 0) { 780 if (s->txp->cmd_a & 0x1000) { 781 do_tx_packet(s); 782 } 783 if (s->txp->cmd_a & 0x80000000) { 784 s->int_sts |= TX_IOC_INT; 785 } 786 s->txp->state = TX_IDLE; 787 } 788 break; 789 } 790 } 791 792 static uint32_t do_phy_read(lan9118_state *s, int reg) 793 { 794 uint32_t val; 795 796 switch (reg) { 797 case 0: /* Basic Control */ 798 return s->phy_control; 799 case 1: /* Basic Status */ 800 return s->phy_status; 801 case 2: /* ID1 */ 802 return 0x0007; 803 case 3: /* ID2 */ 804 return 0xc0d1; 805 case 4: /* Auto-neg advertisement */ 806 return s->phy_advertise; 807 case 5: /* Auto-neg Link Partner Ability */ 808 return 0x0f71; 809 case 6: /* Auto-neg Expansion */ 810 return 1; 811 /* TODO 17, 18, 27, 29, 30, 31 */ 812 case 29: /* Interrupt source. */ 813 val = s->phy_int; 814 s->phy_int = 0; 815 phy_update_irq(s); 816 return val; 817 case 30: /* Interrupt mask */ 818 return s->phy_int_mask; 819 default: 820 BADF("PHY read reg %d\n", reg); 821 return 0; 822 } 823 } 824 825 static void do_phy_write(lan9118_state *s, int reg, uint32_t val) 826 { 827 switch (reg) { 828 case 0: /* Basic Control */ 829 if (val & 0x8000) { 830 phy_reset(s); 831 break; 832 } 833 s->phy_control = val & 0x7980; 834 /* Complete autonegotiation immediately. */ 835 if (val & 0x1000) { 836 s->phy_status |= 0x0020; 837 } 838 break; 839 case 4: /* Auto-neg advertisement */ 840 s->phy_advertise = (val & 0x2d7f) | 0x80; 841 break; 842 /* TODO 17, 18, 27, 31 */ 843 case 30: /* Interrupt mask */ 844 s->phy_int_mask = val & 0xff; 845 phy_update_irq(s); 846 break; 847 default: 848 BADF("PHY write reg %d = 0x%04x\n", reg, val); 849 } 850 } 851 852 static void do_mac_write(lan9118_state *s, int reg, uint32_t val) 853 { 854 switch (reg) { 855 case MAC_CR: 856 if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) { 857 s->int_sts |= RXSTOP_INT; 858 } 859 s->mac_cr = val & ~MAC_CR_RESERVED; 860 DPRINTF("MAC_CR: %08x\n", val); 861 break; 862 case MAC_ADDRH: 863 s->conf.macaddr.a[4] = val & 0xff; 864 s->conf.macaddr.a[5] = (val >> 8) & 0xff; 865 lan9118_mac_changed(s); 866 break; 867 case MAC_ADDRL: 868 s->conf.macaddr.a[0] = val & 0xff; 869 s->conf.macaddr.a[1] = (val >> 8) & 0xff; 870 s->conf.macaddr.a[2] = (val >> 16) & 0xff; 871 s->conf.macaddr.a[3] = (val >> 24) & 0xff; 872 lan9118_mac_changed(s); 873 break; 874 case MAC_HASHH: 875 s->mac_hashh = val; 876 break; 877 case MAC_HASHL: 878 s->mac_hashl = val; 879 break; 880 case MAC_MII_ACC: 881 s->mac_mii_acc = val & 0xffc2; 882 if (val & 2) { 883 DPRINTF("PHY write %d = 0x%04x\n", 884 (val >> 6) & 0x1f, s->mac_mii_data); 885 do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); 886 } else { 887 s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); 888 DPRINTF("PHY read %d = 0x%04x\n", 889 (val >> 6) & 0x1f, s->mac_mii_data); 890 } 891 break; 892 case MAC_MII_DATA: 893 s->mac_mii_data = val & 0xffff; 894 break; 895 case MAC_FLOW: 896 s->mac_flow = val & 0xffff0000; 897 break; 898 case MAC_VLAN1: 899 /* Writing to this register changes a condition for 900 * FrameTooLong bit in rx_status. Since we do not set 901 * FrameTooLong anyway, just ignore write to this. 902 */ 903 break; 904 default: 905 hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n", 906 s->mac_cmd & 0xf, val); 907 } 908 } 909 910 static uint32_t do_mac_read(lan9118_state *s, int reg) 911 { 912 switch (reg) { 913 case MAC_CR: 914 return s->mac_cr; 915 case MAC_ADDRH: 916 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); 917 case MAC_ADDRL: 918 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) 919 | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24); 920 case MAC_HASHH: 921 return s->mac_hashh; 922 break; 923 case MAC_HASHL: 924 return s->mac_hashl; 925 break; 926 case MAC_MII_ACC: 927 return s->mac_mii_acc; 928 case MAC_MII_DATA: 929 return s->mac_mii_data; 930 case MAC_FLOW: 931 return s->mac_flow; 932 default: 933 hw_error("lan9118: Unimplemented MAC register read: %d\n", 934 s->mac_cmd & 0xf); 935 } 936 } 937 938 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr) 939 { 940 s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr; 941 switch (cmd) { 942 case 0: 943 s->e2p_data = s->eeprom[addr]; 944 DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data); 945 break; 946 case 1: 947 s->eeprom_writable = 0; 948 DPRINTF("EEPROM Write Disable\n"); 949 break; 950 case 2: /* EWEN */ 951 s->eeprom_writable = 1; 952 DPRINTF("EEPROM Write Enable\n"); 953 break; 954 case 3: /* WRITE */ 955 if (s->eeprom_writable) { 956 s->eeprom[addr] &= s->e2p_data; 957 DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data); 958 } else { 959 DPRINTF("EEPROM Write %d (ignored)\n", addr); 960 } 961 break; 962 case 4: /* WRAL */ 963 if (s->eeprom_writable) { 964 for (addr = 0; addr < 128; addr++) { 965 s->eeprom[addr] &= s->e2p_data; 966 } 967 DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data); 968 } else { 969 DPRINTF("EEPROM Write All (ignored)\n"); 970 } 971 break; 972 case 5: /* ERASE */ 973 if (s->eeprom_writable) { 974 s->eeprom[addr] = 0xff; 975 DPRINTF("EEPROM Erase %d\n", addr); 976 } else { 977 DPRINTF("EEPROM Erase %d (ignored)\n", addr); 978 } 979 break; 980 case 6: /* ERAL */ 981 if (s->eeprom_writable) { 982 memset(s->eeprom, 0xff, 128); 983 DPRINTF("EEPROM Erase All\n"); 984 } else { 985 DPRINTF("EEPROM Erase All (ignored)\n"); 986 } 987 break; 988 case 7: /* RELOAD */ 989 lan9118_reload_eeprom(s); 990 break; 991 } 992 } 993 994 static void lan9118_tick(void *opaque) 995 { 996 lan9118_state *s = (lan9118_state *)opaque; 997 if (s->int_en & GPT_INT) { 998 s->int_sts |= GPT_INT; 999 } 1000 lan9118_update(s); 1001 } 1002 1003 static void lan9118_writel(void *opaque, hwaddr offset, 1004 uint64_t val, unsigned size) 1005 { 1006 lan9118_state *s = (lan9118_state *)opaque; 1007 offset &= 0xff; 1008 1009 //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); 1010 if (offset >= 0x20 && offset < 0x40) { 1011 /* TX FIFO */ 1012 tx_fifo_push(s, val); 1013 return; 1014 } 1015 switch (offset) { 1016 case CSR_IRQ_CFG: 1017 /* TODO: Implement interrupt deassertion intervals. */ 1018 val &= (IRQ_EN | IRQ_POL | IRQ_TYPE); 1019 s->irq_cfg = (s->irq_cfg & IRQ_INT) | val; 1020 break; 1021 case CSR_INT_STS: 1022 s->int_sts &= ~val; 1023 break; 1024 case CSR_INT_EN: 1025 s->int_en = val & ~RESERVED_INT; 1026 s->int_sts |= val & SW_INT; 1027 break; 1028 case CSR_FIFO_INT: 1029 DPRINTF("FIFO INT levels %08x\n", val); 1030 s->fifo_int = val; 1031 break; 1032 case CSR_RX_CFG: 1033 if (val & 0x8000) { 1034 /* RX_DUMP */ 1035 s->rx_fifo_used = 0; 1036 s->rx_status_fifo_used = 0; 1037 s->rx_packet_size_tail = s->rx_packet_size_head; 1038 s->rx_packet_size[s->rx_packet_size_head] = 0; 1039 } 1040 s->rx_cfg = val & 0xcfff1ff0; 1041 break; 1042 case CSR_TX_CFG: 1043 if (val & 0x8000) { 1044 s->tx_status_fifo_used = 0; 1045 } 1046 if (val & 0x4000) { 1047 s->txp->state = TX_IDLE; 1048 s->txp->fifo_used = 0; 1049 s->txp->cmd_a = 0xffffffff; 1050 } 1051 s->tx_cfg = val & 6; 1052 break; 1053 case CSR_HW_CFG: 1054 if (val & 1) { 1055 /* SRST */ 1056 lan9118_reset(&s->busdev.qdev); 1057 } else { 1058 s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4); 1059 } 1060 break; 1061 case CSR_RX_DP_CTRL: 1062 if (val & 0x80000000) { 1063 /* Skip forward to next packet. */ 1064 s->rxp_pad = 0; 1065 s->rxp_offset = 0; 1066 if (s->rxp_size == 0) { 1067 /* Pop a word to start the next packet. */ 1068 rx_fifo_pop(s); 1069 s->rxp_pad = 0; 1070 s->rxp_offset = 0; 1071 } 1072 s->rx_fifo_head += s->rxp_size; 1073 if (s->rx_fifo_head >= s->rx_fifo_size) { 1074 s->rx_fifo_head -= s->rx_fifo_size; 1075 } 1076 } 1077 break; 1078 case CSR_PMT_CTRL: 1079 if (val & 0x400) { 1080 phy_reset(s); 1081 } 1082 s->pmt_ctrl &= ~0x34e; 1083 s->pmt_ctrl |= (val & 0x34e); 1084 break; 1085 case CSR_GPIO_CFG: 1086 /* Probably just enabling LEDs. */ 1087 s->gpio_cfg = val & 0x7777071f; 1088 break; 1089 case CSR_GPT_CFG: 1090 if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) { 1091 if (val & GPT_TIMER_EN) { 1092 ptimer_set_count(s->timer, val & 0xffff); 1093 ptimer_run(s->timer, 0); 1094 } else { 1095 ptimer_stop(s->timer); 1096 ptimer_set_count(s->timer, 0xffff); 1097 } 1098 } 1099 s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff); 1100 break; 1101 case CSR_WORD_SWAP: 1102 /* Ignored because we're in 32-bit mode. */ 1103 s->word_swap = val; 1104 break; 1105 case CSR_MAC_CSR_CMD: 1106 s->mac_cmd = val & 0x4000000f; 1107 if (val & 0x80000000) { 1108 if (val & 0x40000000) { 1109 s->mac_data = do_mac_read(s, val & 0xf); 1110 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data); 1111 } else { 1112 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data); 1113 do_mac_write(s, val & 0xf, s->mac_data); 1114 } 1115 } 1116 break; 1117 case CSR_MAC_CSR_DATA: 1118 s->mac_data = val; 1119 break; 1120 case CSR_AFC_CFG: 1121 s->afc_cfg = val & 0x00ffffff; 1122 break; 1123 case CSR_E2P_CMD: 1124 lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f); 1125 break; 1126 case CSR_E2P_DATA: 1127 s->e2p_data = val & 0xff; 1128 break; 1129 1130 default: 1131 hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, (int)val); 1132 break; 1133 } 1134 lan9118_update(s); 1135 } 1136 1137 static void lan9118_writew(void *opaque, hwaddr offset, 1138 uint32_t val) 1139 { 1140 lan9118_state *s = (lan9118_state *)opaque; 1141 offset &= 0xff; 1142 1143 if (s->write_word_prev_offset != (offset & ~0x3)) { 1144 /* New offset, reset word counter */ 1145 s->write_word_n = 0; 1146 s->write_word_prev_offset = offset & ~0x3; 1147 } 1148 1149 if (offset & 0x2) { 1150 s->write_word_h = val; 1151 } else { 1152 s->write_word_l = val; 1153 } 1154 1155 //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val); 1156 s->write_word_n++; 1157 if (s->write_word_n == 2) { 1158 s->write_word_n = 0; 1159 lan9118_writel(s, offset & ~3, s->write_word_l + 1160 (s->write_word_h << 16), 4); 1161 } 1162 } 1163 1164 static void lan9118_16bit_mode_write(void *opaque, hwaddr offset, 1165 uint64_t val, unsigned size) 1166 { 1167 switch (size) { 1168 case 2: 1169 lan9118_writew(opaque, offset, (uint32_t)val); 1170 return; 1171 case 4: 1172 lan9118_writel(opaque, offset, val, size); 1173 return; 1174 } 1175 1176 hw_error("lan9118_write: Bad size 0x%x\n", size); 1177 } 1178 1179 static uint64_t lan9118_readl(void *opaque, hwaddr offset, 1180 unsigned size) 1181 { 1182 lan9118_state *s = (lan9118_state *)opaque; 1183 1184 //DPRINTF("Read reg 0x%02x\n", (int)offset); 1185 if (offset < 0x20) { 1186 /* RX FIFO */ 1187 return rx_fifo_pop(s); 1188 } 1189 switch (offset) { 1190 case 0x40: 1191 return rx_status_fifo_pop(s); 1192 case 0x44: 1193 return s->rx_status_fifo[s->tx_status_fifo_head]; 1194 case 0x48: 1195 return tx_status_fifo_pop(s); 1196 case 0x4c: 1197 return s->tx_status_fifo[s->tx_status_fifo_head]; 1198 case CSR_ID_REV: 1199 return 0x01180001; 1200 case CSR_IRQ_CFG: 1201 return s->irq_cfg; 1202 case CSR_INT_STS: 1203 return s->int_sts; 1204 case CSR_INT_EN: 1205 return s->int_en; 1206 case CSR_BYTE_TEST: 1207 return 0x87654321; 1208 case CSR_FIFO_INT: 1209 return s->fifo_int; 1210 case CSR_RX_CFG: 1211 return s->rx_cfg; 1212 case CSR_TX_CFG: 1213 return s->tx_cfg; 1214 case CSR_HW_CFG: 1215 return s->hw_cfg; 1216 case CSR_RX_DP_CTRL: 1217 return 0; 1218 case CSR_RX_FIFO_INF: 1219 return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2); 1220 case CSR_TX_FIFO_INF: 1221 return (s->tx_status_fifo_used << 16) 1222 | (s->tx_fifo_size - s->txp->fifo_used); 1223 case CSR_PMT_CTRL: 1224 return s->pmt_ctrl; 1225 case CSR_GPIO_CFG: 1226 return s->gpio_cfg; 1227 case CSR_GPT_CFG: 1228 return s->gpt_cfg; 1229 case CSR_GPT_CNT: 1230 return ptimer_get_count(s->timer); 1231 case CSR_WORD_SWAP: 1232 return s->word_swap; 1233 case CSR_FREE_RUN: 1234 return (qemu_get_clock_ns(vm_clock) / 40) - s->free_timer_start; 1235 case CSR_RX_DROP: 1236 /* TODO: Implement dropped frames counter. */ 1237 return 0; 1238 case CSR_MAC_CSR_CMD: 1239 return s->mac_cmd; 1240 case CSR_MAC_CSR_DATA: 1241 return s->mac_data; 1242 case CSR_AFC_CFG: 1243 return s->afc_cfg; 1244 case CSR_E2P_CMD: 1245 return s->e2p_cmd; 1246 case CSR_E2P_DATA: 1247 return s->e2p_data; 1248 } 1249 hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset); 1250 return 0; 1251 } 1252 1253 static uint32_t lan9118_readw(void *opaque, hwaddr offset) 1254 { 1255 lan9118_state *s = (lan9118_state *)opaque; 1256 uint32_t val; 1257 1258 if (s->read_word_prev_offset != (offset & ~0x3)) { 1259 /* New offset, reset word counter */ 1260 s->read_word_n = 0; 1261 s->read_word_prev_offset = offset & ~0x3; 1262 } 1263 1264 s->read_word_n++; 1265 if (s->read_word_n == 1) { 1266 s->read_long = lan9118_readl(s, offset & ~3, 4); 1267 } else { 1268 s->read_word_n = 0; 1269 } 1270 1271 if (offset & 2) { 1272 val = s->read_long >> 16; 1273 } else { 1274 val = s->read_long & 0xFFFF; 1275 } 1276 1277 //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val); 1278 return val; 1279 } 1280 1281 static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset, 1282 unsigned size) 1283 { 1284 switch (size) { 1285 case 2: 1286 return lan9118_readw(opaque, offset); 1287 case 4: 1288 return lan9118_readl(opaque, offset, size); 1289 } 1290 1291 hw_error("lan9118_read: Bad size 0x%x\n", size); 1292 return 0; 1293 } 1294 1295 static const MemoryRegionOps lan9118_mem_ops = { 1296 .read = lan9118_readl, 1297 .write = lan9118_writel, 1298 .endianness = DEVICE_NATIVE_ENDIAN, 1299 }; 1300 1301 static const MemoryRegionOps lan9118_16bit_mem_ops = { 1302 .read = lan9118_16bit_mode_read, 1303 .write = lan9118_16bit_mode_write, 1304 .endianness = DEVICE_NATIVE_ENDIAN, 1305 }; 1306 1307 static void lan9118_cleanup(NetClientState *nc) 1308 { 1309 lan9118_state *s = qemu_get_nic_opaque(nc); 1310 1311 s->nic = NULL; 1312 } 1313 1314 static NetClientInfo net_lan9118_info = { 1315 .type = NET_CLIENT_OPTIONS_KIND_NIC, 1316 .size = sizeof(NICState), 1317 .can_receive = lan9118_can_receive, 1318 .receive = lan9118_receive, 1319 .cleanup = lan9118_cleanup, 1320 .link_status_changed = lan9118_set_link, 1321 }; 1322 1323 static int lan9118_init1(SysBusDevice *dev) 1324 { 1325 lan9118_state *s = FROM_SYSBUS(lan9118_state, dev); 1326 QEMUBH *bh; 1327 int i; 1328 const MemoryRegionOps *mem_ops = 1329 s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; 1330 1331 memory_region_init_io(&s->mmio, mem_ops, s, "lan9118-mmio", 0x100); 1332 sysbus_init_mmio(dev, &s->mmio); 1333 sysbus_init_irq(dev, &s->irq); 1334 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1335 1336 s->nic = qemu_new_nic(&net_lan9118_info, &s->conf, 1337 object_get_typename(OBJECT(dev)), dev->qdev.id, s); 1338 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 1339 s->eeprom[0] = 0xa5; 1340 for (i = 0; i < 6; i++) { 1341 s->eeprom[i + 1] = s->conf.macaddr.a[i]; 1342 } 1343 s->pmt_ctrl = 1; 1344 s->txp = &s->tx_packet; 1345 1346 bh = qemu_bh_new(lan9118_tick, s); 1347 s->timer = ptimer_init(bh); 1348 ptimer_set_freq(s->timer, 10000); 1349 ptimer_set_limit(s->timer, 0xffff, 1); 1350 1351 return 0; 1352 } 1353 1354 static Property lan9118_properties[] = { 1355 DEFINE_NIC_PROPERTIES(lan9118_state, conf), 1356 DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0), 1357 DEFINE_PROP_END_OF_LIST(), 1358 }; 1359 1360 static void lan9118_class_init(ObjectClass *klass, void *data) 1361 { 1362 DeviceClass *dc = DEVICE_CLASS(klass); 1363 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1364 1365 k->init = lan9118_init1; 1366 dc->reset = lan9118_reset; 1367 dc->props = lan9118_properties; 1368 dc->vmsd = &vmstate_lan9118; 1369 } 1370 1371 static const TypeInfo lan9118_info = { 1372 .name = "lan9118", 1373 .parent = TYPE_SYS_BUS_DEVICE, 1374 .instance_size = sizeof(lan9118_state), 1375 .class_init = lan9118_class_init, 1376 }; 1377 1378 static void lan9118_register_types(void) 1379 { 1380 type_register_static(&lan9118_info); 1381 } 1382 1383 /* Legacy helper function. Should go away when machine config files are 1384 implemented. */ 1385 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq) 1386 { 1387 DeviceState *dev; 1388 SysBusDevice *s; 1389 1390 qemu_check_nic_model(nd, "lan9118"); 1391 dev = qdev_create(NULL, "lan9118"); 1392 qdev_set_nic_properties(dev, nd); 1393 qdev_init_nofail(dev); 1394 s = SYS_BUS_DEVICE(dev); 1395 sysbus_mmio_map(s, 0, base); 1396 sysbus_connect_irq(s, 0, irq); 1397 } 1398 1399 type_init(lan9118_register_types) 1400