1 /* 2 * SMSC LAN9118 Ethernet interface emulation 3 * 4 * Copyright (c) 2009 CodeSourcery, LLC. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GNU GPL v2 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/sysbus.h" 15 #include "migration/vmstate.h" 16 #include "net/net.h" 17 #include "net/eth.h" 18 #include "hw/hw.h" 19 #include "hw/irq.h" 20 #include "hw/net/lan9118.h" 21 #include "hw/ptimer.h" 22 #include "hw/qdev-properties.h" 23 #include "qapi/error.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 /* For crc32 */ 27 #include <zlib.h> 28 #include "qom/object.h" 29 30 //#define DEBUG_LAN9118 31 32 #ifdef DEBUG_LAN9118 33 #define DPRINTF(fmt, ...) \ 34 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) 35 #define BADF(fmt, ...) \ 36 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) 37 #else 38 #define DPRINTF(fmt, ...) do {} while(0) 39 #define BADF(fmt, ...) \ 40 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) 41 #endif 42 43 #define CSR_ID_REV 0x50 44 #define CSR_IRQ_CFG 0x54 45 #define CSR_INT_STS 0x58 46 #define CSR_INT_EN 0x5c 47 #define CSR_BYTE_TEST 0x64 48 #define CSR_FIFO_INT 0x68 49 #define CSR_RX_CFG 0x6c 50 #define CSR_TX_CFG 0x70 51 #define CSR_HW_CFG 0x74 52 #define CSR_RX_DP_CTRL 0x78 53 #define CSR_RX_FIFO_INF 0x7c 54 #define CSR_TX_FIFO_INF 0x80 55 #define CSR_PMT_CTRL 0x84 56 #define CSR_GPIO_CFG 0x88 57 #define CSR_GPT_CFG 0x8c 58 #define CSR_GPT_CNT 0x90 59 #define CSR_WORD_SWAP 0x98 60 #define CSR_FREE_RUN 0x9c 61 #define CSR_RX_DROP 0xa0 62 #define CSR_MAC_CSR_CMD 0xa4 63 #define CSR_MAC_CSR_DATA 0xa8 64 #define CSR_AFC_CFG 0xac 65 #define CSR_E2P_CMD 0xb0 66 #define CSR_E2P_DATA 0xb4 67 68 #define E2P_CMD_MAC_ADDR_LOADED 0x100 69 70 /* IRQ_CFG */ 71 #define IRQ_INT 0x00001000 72 #define IRQ_EN 0x00000100 73 #define IRQ_POL 0x00000010 74 #define IRQ_TYPE 0x00000001 75 76 /* INT_STS/INT_EN */ 77 #define SW_INT 0x80000000 78 #define TXSTOP_INT 0x02000000 79 #define RXSTOP_INT 0x01000000 80 #define RXDFH_INT 0x00800000 81 #define TX_IOC_INT 0x00200000 82 #define RXD_INT 0x00100000 83 #define GPT_INT 0x00080000 84 #define PHY_INT 0x00040000 85 #define PME_INT 0x00020000 86 #define TXSO_INT 0x00010000 87 #define RWT_INT 0x00008000 88 #define RXE_INT 0x00004000 89 #define TXE_INT 0x00002000 90 #define TDFU_INT 0x00000800 91 #define TDFO_INT 0x00000400 92 #define TDFA_INT 0x00000200 93 #define TSFF_INT 0x00000100 94 #define TSFL_INT 0x00000080 95 #define RXDF_INT 0x00000040 96 #define RDFL_INT 0x00000020 97 #define RSFF_INT 0x00000010 98 #define RSFL_INT 0x00000008 99 #define GPIO2_INT 0x00000004 100 #define GPIO1_INT 0x00000002 101 #define GPIO0_INT 0x00000001 102 #define RESERVED_INT 0x7c001000 103 104 #define MAC_CR 1 105 #define MAC_ADDRH 2 106 #define MAC_ADDRL 3 107 #define MAC_HASHH 4 108 #define MAC_HASHL 5 109 #define MAC_MII_ACC 6 110 #define MAC_MII_DATA 7 111 #define MAC_FLOW 8 112 #define MAC_VLAN1 9 /* TODO */ 113 #define MAC_VLAN2 10 /* TODO */ 114 #define MAC_WUFF 11 /* TODO */ 115 #define MAC_WUCSR 12 /* TODO */ 116 117 #define MAC_CR_RXALL 0x80000000 118 #define MAC_CR_RCVOWN 0x00800000 119 #define MAC_CR_LOOPBK 0x00200000 120 #define MAC_CR_FDPX 0x00100000 121 #define MAC_CR_MCPAS 0x00080000 122 #define MAC_CR_PRMS 0x00040000 123 #define MAC_CR_INVFILT 0x00020000 124 #define MAC_CR_PASSBAD 0x00010000 125 #define MAC_CR_HO 0x00008000 126 #define MAC_CR_HPFILT 0x00002000 127 #define MAC_CR_LCOLL 0x00001000 128 #define MAC_CR_BCAST 0x00000800 129 #define MAC_CR_DISRTY 0x00000400 130 #define MAC_CR_PADSTR 0x00000100 131 #define MAC_CR_BOLMT 0x000000c0 132 #define MAC_CR_DFCHK 0x00000020 133 #define MAC_CR_TXEN 0x00000008 134 #define MAC_CR_RXEN 0x00000004 135 #define MAC_CR_RESERVED 0x7f404213 136 137 #define PHY_INT_ENERGYON 0x80 138 #define PHY_INT_AUTONEG_COMPLETE 0x40 139 #define PHY_INT_FAULT 0x20 140 #define PHY_INT_DOWN 0x10 141 #define PHY_INT_AUTONEG_LP 0x08 142 #define PHY_INT_PARFAULT 0x04 143 #define PHY_INT_AUTONEG_PAGE 0x02 144 145 #define GPT_TIMER_EN 0x20000000 146 147 enum tx_state { 148 TX_IDLE, 149 TX_B, 150 TX_DATA 151 }; 152 153 typedef struct { 154 /* state is a tx_state but we can't put enums in VMStateDescriptions. */ 155 uint32_t state; 156 uint32_t cmd_a; 157 uint32_t cmd_b; 158 int32_t buffer_size; 159 int32_t offset; 160 int32_t pad; 161 int32_t fifo_used; 162 int32_t len; 163 uint8_t data[2048]; 164 } LAN9118Packet; 165 166 static const VMStateDescription vmstate_lan9118_packet = { 167 .name = "lan9118_packet", 168 .version_id = 1, 169 .minimum_version_id = 1, 170 .fields = (VMStateField[]) { 171 VMSTATE_UINT32(state, LAN9118Packet), 172 VMSTATE_UINT32(cmd_a, LAN9118Packet), 173 VMSTATE_UINT32(cmd_b, LAN9118Packet), 174 VMSTATE_INT32(buffer_size, LAN9118Packet), 175 VMSTATE_INT32(offset, LAN9118Packet), 176 VMSTATE_INT32(pad, LAN9118Packet), 177 VMSTATE_INT32(fifo_used, LAN9118Packet), 178 VMSTATE_INT32(len, LAN9118Packet), 179 VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048), 180 VMSTATE_END_OF_LIST() 181 } 182 }; 183 184 OBJECT_DECLARE_SIMPLE_TYPE(lan9118_state, LAN9118) 185 186 struct lan9118_state { 187 SysBusDevice parent_obj; 188 189 NICState *nic; 190 NICConf conf; 191 qemu_irq irq; 192 MemoryRegion mmio; 193 ptimer_state *timer; 194 195 uint32_t irq_cfg; 196 uint32_t int_sts; 197 uint32_t int_en; 198 uint32_t fifo_int; 199 uint32_t rx_cfg; 200 uint32_t tx_cfg; 201 uint32_t hw_cfg; 202 uint32_t pmt_ctrl; 203 uint32_t gpio_cfg; 204 uint32_t gpt_cfg; 205 uint32_t word_swap; 206 uint32_t free_timer_start; 207 uint32_t mac_cmd; 208 uint32_t mac_data; 209 uint32_t afc_cfg; 210 uint32_t e2p_cmd; 211 uint32_t e2p_data; 212 213 uint32_t mac_cr; 214 uint32_t mac_hashh; 215 uint32_t mac_hashl; 216 uint32_t mac_mii_acc; 217 uint32_t mac_mii_data; 218 uint32_t mac_flow; 219 220 uint32_t phy_status; 221 uint32_t phy_control; 222 uint32_t phy_advertise; 223 uint32_t phy_int; 224 uint32_t phy_int_mask; 225 226 int32_t eeprom_writable; 227 uint8_t eeprom[128]; 228 229 int32_t tx_fifo_size; 230 LAN9118Packet *txp; 231 LAN9118Packet tx_packet; 232 233 int32_t tx_status_fifo_used; 234 int32_t tx_status_fifo_head; 235 uint32_t tx_status_fifo[512]; 236 237 int32_t rx_status_fifo_size; 238 int32_t rx_status_fifo_used; 239 int32_t rx_status_fifo_head; 240 uint32_t rx_status_fifo[896]; 241 int32_t rx_fifo_size; 242 int32_t rx_fifo_used; 243 int32_t rx_fifo_head; 244 uint32_t rx_fifo[3360]; 245 int32_t rx_packet_size_head; 246 int32_t rx_packet_size_tail; 247 int32_t rx_packet_size[1024]; 248 249 int32_t rxp_offset; 250 int32_t rxp_size; 251 int32_t rxp_pad; 252 253 uint32_t write_word_prev_offset; 254 uint32_t write_word_n; 255 uint16_t write_word_l; 256 uint16_t write_word_h; 257 uint32_t read_word_prev_offset; 258 uint32_t read_word_n; 259 uint32_t read_long; 260 261 uint32_t mode_16bit; 262 }; 263 264 static const VMStateDescription vmstate_lan9118 = { 265 .name = "lan9118", 266 .version_id = 2, 267 .minimum_version_id = 1, 268 .fields = (VMStateField[]) { 269 VMSTATE_PTIMER(timer, lan9118_state), 270 VMSTATE_UINT32(irq_cfg, lan9118_state), 271 VMSTATE_UINT32(int_sts, lan9118_state), 272 VMSTATE_UINT32(int_en, lan9118_state), 273 VMSTATE_UINT32(fifo_int, lan9118_state), 274 VMSTATE_UINT32(rx_cfg, lan9118_state), 275 VMSTATE_UINT32(tx_cfg, lan9118_state), 276 VMSTATE_UINT32(hw_cfg, lan9118_state), 277 VMSTATE_UINT32(pmt_ctrl, lan9118_state), 278 VMSTATE_UINT32(gpio_cfg, lan9118_state), 279 VMSTATE_UINT32(gpt_cfg, lan9118_state), 280 VMSTATE_UINT32(word_swap, lan9118_state), 281 VMSTATE_UINT32(free_timer_start, lan9118_state), 282 VMSTATE_UINT32(mac_cmd, lan9118_state), 283 VMSTATE_UINT32(mac_data, lan9118_state), 284 VMSTATE_UINT32(afc_cfg, lan9118_state), 285 VMSTATE_UINT32(e2p_cmd, lan9118_state), 286 VMSTATE_UINT32(e2p_data, lan9118_state), 287 VMSTATE_UINT32(mac_cr, lan9118_state), 288 VMSTATE_UINT32(mac_hashh, lan9118_state), 289 VMSTATE_UINT32(mac_hashl, lan9118_state), 290 VMSTATE_UINT32(mac_mii_acc, lan9118_state), 291 VMSTATE_UINT32(mac_mii_data, lan9118_state), 292 VMSTATE_UINT32(mac_flow, lan9118_state), 293 VMSTATE_UINT32(phy_status, lan9118_state), 294 VMSTATE_UINT32(phy_control, lan9118_state), 295 VMSTATE_UINT32(phy_advertise, lan9118_state), 296 VMSTATE_UINT32(phy_int, lan9118_state), 297 VMSTATE_UINT32(phy_int_mask, lan9118_state), 298 VMSTATE_INT32(eeprom_writable, lan9118_state), 299 VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), 300 VMSTATE_INT32(tx_fifo_size, lan9118_state), 301 /* txp always points at tx_packet so need not be saved */ 302 VMSTATE_STRUCT(tx_packet, lan9118_state, 0, 303 vmstate_lan9118_packet, LAN9118Packet), 304 VMSTATE_INT32(tx_status_fifo_used, lan9118_state), 305 VMSTATE_INT32(tx_status_fifo_head, lan9118_state), 306 VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512), 307 VMSTATE_INT32(rx_status_fifo_size, lan9118_state), 308 VMSTATE_INT32(rx_status_fifo_used, lan9118_state), 309 VMSTATE_INT32(rx_status_fifo_head, lan9118_state), 310 VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896), 311 VMSTATE_INT32(rx_fifo_size, lan9118_state), 312 VMSTATE_INT32(rx_fifo_used, lan9118_state), 313 VMSTATE_INT32(rx_fifo_head, lan9118_state), 314 VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360), 315 VMSTATE_INT32(rx_packet_size_head, lan9118_state), 316 VMSTATE_INT32(rx_packet_size_tail, lan9118_state), 317 VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024), 318 VMSTATE_INT32(rxp_offset, lan9118_state), 319 VMSTATE_INT32(rxp_size, lan9118_state), 320 VMSTATE_INT32(rxp_pad, lan9118_state), 321 VMSTATE_UINT32_V(write_word_prev_offset, lan9118_state, 2), 322 VMSTATE_UINT32_V(write_word_n, lan9118_state, 2), 323 VMSTATE_UINT16_V(write_word_l, lan9118_state, 2), 324 VMSTATE_UINT16_V(write_word_h, lan9118_state, 2), 325 VMSTATE_UINT32_V(read_word_prev_offset, lan9118_state, 2), 326 VMSTATE_UINT32_V(read_word_n, lan9118_state, 2), 327 VMSTATE_UINT32_V(read_long, lan9118_state, 2), 328 VMSTATE_UINT32_V(mode_16bit, lan9118_state, 2), 329 VMSTATE_END_OF_LIST() 330 } 331 }; 332 333 static void lan9118_update(lan9118_state *s) 334 { 335 int level; 336 337 /* TODO: Implement FIFO level IRQs. */ 338 level = (s->int_sts & s->int_en) != 0; 339 if (level) { 340 s->irq_cfg |= IRQ_INT; 341 } else { 342 s->irq_cfg &= ~IRQ_INT; 343 } 344 if ((s->irq_cfg & IRQ_EN) == 0) { 345 level = 0; 346 } 347 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) { 348 /* Interrupt is active low unless we're configured as 349 * active-high polarity, push-pull type. 350 */ 351 level = !level; 352 } 353 qemu_set_irq(s->irq, level); 354 } 355 356 static void lan9118_mac_changed(lan9118_state *s) 357 { 358 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 359 } 360 361 static void lan9118_reload_eeprom(lan9118_state *s) 362 { 363 int i; 364 if (s->eeprom[0] != 0xa5) { 365 s->e2p_cmd &= ~E2P_CMD_MAC_ADDR_LOADED; 366 DPRINTF("MACADDR load failed\n"); 367 return; 368 } 369 for (i = 0; i < 6; i++) { 370 s->conf.macaddr.a[i] = s->eeprom[i + 1]; 371 } 372 s->e2p_cmd |= E2P_CMD_MAC_ADDR_LOADED; 373 DPRINTF("MACADDR loaded from eeprom\n"); 374 lan9118_mac_changed(s); 375 } 376 377 static void phy_update_irq(lan9118_state *s) 378 { 379 if (s->phy_int & s->phy_int_mask) { 380 s->int_sts |= PHY_INT; 381 } else { 382 s->int_sts &= ~PHY_INT; 383 } 384 lan9118_update(s); 385 } 386 387 static void phy_update_link(lan9118_state *s) 388 { 389 /* Autonegotiation status mirrors link status. */ 390 if (qemu_get_queue(s->nic)->link_down) { 391 s->phy_status &= ~0x0024; 392 s->phy_int |= PHY_INT_DOWN; 393 } else { 394 s->phy_status |= 0x0024; 395 s->phy_int |= PHY_INT_ENERGYON; 396 s->phy_int |= PHY_INT_AUTONEG_COMPLETE; 397 } 398 phy_update_irq(s); 399 } 400 401 static void lan9118_set_link(NetClientState *nc) 402 { 403 phy_update_link(qemu_get_nic_opaque(nc)); 404 } 405 406 static void phy_reset(lan9118_state *s) 407 { 408 s->phy_status = 0x7809; 409 s->phy_control = 0x3000; 410 s->phy_advertise = 0x01e1; 411 s->phy_int_mask = 0; 412 s->phy_int = 0; 413 phy_update_link(s); 414 } 415 416 static void lan9118_reset(DeviceState *d) 417 { 418 lan9118_state *s = LAN9118(d); 419 420 s->irq_cfg &= (IRQ_TYPE | IRQ_POL); 421 s->int_sts = 0; 422 s->int_en = 0; 423 s->fifo_int = 0x48000000; 424 s->rx_cfg = 0; 425 s->tx_cfg = 0; 426 s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004; 427 s->pmt_ctrl &= 0x45; 428 s->gpio_cfg = 0; 429 s->txp->fifo_used = 0; 430 s->txp->state = TX_IDLE; 431 s->txp->cmd_a = 0xffffffffu; 432 s->txp->cmd_b = 0xffffffffu; 433 s->txp->len = 0; 434 s->txp->fifo_used = 0; 435 s->tx_fifo_size = 4608; 436 s->tx_status_fifo_used = 0; 437 s->rx_status_fifo_size = 704; 438 s->rx_fifo_size = 2640; 439 s->rx_fifo_used = 0; 440 s->rx_status_fifo_size = 176; 441 s->rx_status_fifo_used = 0; 442 s->rxp_offset = 0; 443 s->rxp_size = 0; 444 s->rxp_pad = 0; 445 s->rx_packet_size_tail = s->rx_packet_size_head; 446 s->rx_packet_size[s->rx_packet_size_head] = 0; 447 s->mac_cmd = 0; 448 s->mac_data = 0; 449 s->afc_cfg = 0; 450 s->e2p_cmd = 0; 451 s->e2p_data = 0; 452 s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40; 453 454 ptimer_transaction_begin(s->timer); 455 ptimer_stop(s->timer); 456 ptimer_set_count(s->timer, 0xffff); 457 ptimer_transaction_commit(s->timer); 458 s->gpt_cfg = 0xffff; 459 460 s->mac_cr = MAC_CR_PRMS; 461 s->mac_hashh = 0; 462 s->mac_hashl = 0; 463 s->mac_mii_acc = 0; 464 s->mac_mii_data = 0; 465 s->mac_flow = 0; 466 467 s->read_word_n = 0; 468 s->write_word_n = 0; 469 470 phy_reset(s); 471 472 s->eeprom_writable = 0; 473 lan9118_reload_eeprom(s); 474 } 475 476 static void rx_fifo_push(lan9118_state *s, uint32_t val) 477 { 478 int fifo_pos; 479 fifo_pos = s->rx_fifo_head + s->rx_fifo_used; 480 if (fifo_pos >= s->rx_fifo_size) 481 fifo_pos -= s->rx_fifo_size; 482 s->rx_fifo[fifo_pos] = val; 483 s->rx_fifo_used++; 484 } 485 486 /* Return nonzero if the packet is accepted by the filter. */ 487 static int lan9118_filter(lan9118_state *s, const uint8_t *addr) 488 { 489 int multicast; 490 uint32_t hash; 491 492 if (s->mac_cr & MAC_CR_PRMS) { 493 return 1; 494 } 495 if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff && 496 addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) { 497 return (s->mac_cr & MAC_CR_BCAST) == 0; 498 } 499 500 multicast = addr[0] & 1; 501 if (multicast &&s->mac_cr & MAC_CR_MCPAS) { 502 return 1; 503 } 504 if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0 505 : (s->mac_cr & MAC_CR_HO) == 0) { 506 /* Exact matching. */ 507 hash = memcmp(addr, s->conf.macaddr.a, 6); 508 if (s->mac_cr & MAC_CR_INVFILT) { 509 return hash != 0; 510 } else { 511 return hash == 0; 512 } 513 } else { 514 /* Hash matching */ 515 hash = net_crc32(addr, ETH_ALEN) >> 26; 516 if (hash & 0x20) { 517 return (s->mac_hashh >> (hash & 0x1f)) & 1; 518 } else { 519 return (s->mac_hashl >> (hash & 0x1f)) & 1; 520 } 521 } 522 } 523 524 static ssize_t lan9118_receive(NetClientState *nc, const uint8_t *buf, 525 size_t size) 526 { 527 lan9118_state *s = qemu_get_nic_opaque(nc); 528 int fifo_len; 529 int offset; 530 int src_pos; 531 int n; 532 int filter; 533 uint32_t val; 534 uint32_t crc; 535 uint32_t status; 536 537 if ((s->mac_cr & MAC_CR_RXEN) == 0) { 538 return -1; 539 } 540 541 if (size >= 2048 || size < 14) { 542 return -1; 543 } 544 545 /* TODO: Implement FIFO overflow notification. */ 546 if (s->rx_status_fifo_used == s->rx_status_fifo_size) { 547 return -1; 548 } 549 550 filter = lan9118_filter(s, buf); 551 if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) { 552 return size; 553 } 554 555 offset = (s->rx_cfg >> 8) & 0x1f; 556 n = offset & 3; 557 fifo_len = (size + n + 3) >> 2; 558 /* Add a word for the CRC. */ 559 fifo_len++; 560 if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) { 561 return -1; 562 } 563 564 DPRINTF("Got packet len:%d fifo:%d filter:%s\n", 565 (int)size, fifo_len, filter ? "pass" : "fail"); 566 val = 0; 567 crc = bswap32(crc32(~0, buf, size)); 568 for (src_pos = 0; src_pos < size; src_pos++) { 569 val = (val >> 8) | ((uint32_t)buf[src_pos] << 24); 570 n++; 571 if (n == 4) { 572 n = 0; 573 rx_fifo_push(s, val); 574 val = 0; 575 } 576 } 577 if (n) { 578 val >>= ((4 - n) * 8); 579 val |= crc << (n * 8); 580 rx_fifo_push(s, val); 581 val = crc >> ((4 - n) * 8); 582 rx_fifo_push(s, val); 583 } else { 584 rx_fifo_push(s, crc); 585 } 586 n = s->rx_status_fifo_head + s->rx_status_fifo_used; 587 if (n >= s->rx_status_fifo_size) { 588 n -= s->rx_status_fifo_size; 589 } 590 s->rx_packet_size[s->rx_packet_size_tail] = fifo_len; 591 s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023; 592 s->rx_status_fifo_used++; 593 594 status = (size + 4) << 16; 595 if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && 596 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) { 597 status |= 0x00002000; 598 } else if (buf[0] & 1) { 599 status |= 0x00000400; 600 } 601 if (!filter) { 602 status |= 0x40000000; 603 } 604 s->rx_status_fifo[n] = status; 605 606 if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) { 607 s->int_sts |= RSFL_INT; 608 } 609 lan9118_update(s); 610 611 return size; 612 } 613 614 static uint32_t rx_fifo_pop(lan9118_state *s) 615 { 616 int n; 617 uint32_t val; 618 619 if (s->rxp_size == 0 && s->rxp_pad == 0) { 620 s->rxp_size = s->rx_packet_size[s->rx_packet_size_head]; 621 s->rx_packet_size[s->rx_packet_size_head] = 0; 622 if (s->rxp_size != 0) { 623 s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023; 624 s->rxp_offset = (s->rx_cfg >> 10) & 7; 625 n = s->rxp_offset + s->rxp_size; 626 switch (s->rx_cfg >> 30) { 627 case 1: 628 n = (-n) & 3; 629 break; 630 case 2: 631 n = (-n) & 7; 632 break; 633 default: 634 n = 0; 635 break; 636 } 637 s->rxp_pad = n; 638 DPRINTF("Pop packet size:%d offset:%d pad: %d\n", 639 s->rxp_size, s->rxp_offset, s->rxp_pad); 640 } 641 } 642 if (s->rxp_offset > 0) { 643 s->rxp_offset--; 644 val = 0; 645 } else if (s->rxp_size > 0) { 646 s->rxp_size--; 647 val = s->rx_fifo[s->rx_fifo_head++]; 648 if (s->rx_fifo_head >= s->rx_fifo_size) { 649 s->rx_fifo_head -= s->rx_fifo_size; 650 } 651 s->rx_fifo_used--; 652 } else if (s->rxp_pad > 0) { 653 s->rxp_pad--; 654 val = 0; 655 } else { 656 DPRINTF("RX underflow\n"); 657 s->int_sts |= RXE_INT; 658 val = 0; 659 } 660 lan9118_update(s); 661 return val; 662 } 663 664 static void do_tx_packet(lan9118_state *s) 665 { 666 int n; 667 uint32_t status; 668 669 /* FIXME: Honor TX disable, and allow queueing of packets. */ 670 if (s->phy_control & 0x4000) { 671 /* This assumes the receive routine doesn't touch the VLANClient. */ 672 lan9118_receive(qemu_get_queue(s->nic), s->txp->data, s->txp->len); 673 } else { 674 qemu_send_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); 675 } 676 s->txp->fifo_used = 0; 677 678 if (s->tx_status_fifo_used == 512) { 679 /* Status FIFO full */ 680 return; 681 } 682 /* Add entry to status FIFO. */ 683 status = s->txp->cmd_b & 0xffff0000u; 684 DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len); 685 n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511; 686 s->tx_status_fifo[n] = status; 687 s->tx_status_fifo_used++; 688 if (s->tx_status_fifo_used == 512) { 689 s->int_sts |= TSFF_INT; 690 /* TODO: Stop transmission. */ 691 } 692 } 693 694 static uint32_t rx_status_fifo_pop(lan9118_state *s) 695 { 696 uint32_t val; 697 698 val = s->rx_status_fifo[s->rx_status_fifo_head]; 699 if (s->rx_status_fifo_used != 0) { 700 s->rx_status_fifo_used--; 701 s->rx_status_fifo_head++; 702 if (s->rx_status_fifo_head >= s->rx_status_fifo_size) { 703 s->rx_status_fifo_head -= s->rx_status_fifo_size; 704 } 705 /* ??? What value should be returned when the FIFO is empty? */ 706 DPRINTF("RX status pop 0x%08x\n", val); 707 } 708 return val; 709 } 710 711 static uint32_t tx_status_fifo_pop(lan9118_state *s) 712 { 713 uint32_t val; 714 715 val = s->tx_status_fifo[s->tx_status_fifo_head]; 716 if (s->tx_status_fifo_used != 0) { 717 s->tx_status_fifo_used--; 718 s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511; 719 /* ??? What value should be returned when the FIFO is empty? */ 720 } 721 return val; 722 } 723 724 static void tx_fifo_push(lan9118_state *s, uint32_t val) 725 { 726 int n; 727 728 if (s->txp->fifo_used == s->tx_fifo_size) { 729 s->int_sts |= TDFO_INT; 730 return; 731 } 732 switch (s->txp->state) { 733 case TX_IDLE: 734 s->txp->cmd_a = val & 0x831f37ff; 735 s->txp->fifo_used++; 736 s->txp->state = TX_B; 737 s->txp->buffer_size = extract32(s->txp->cmd_a, 0, 11); 738 s->txp->offset = extract32(s->txp->cmd_a, 16, 5); 739 break; 740 case TX_B: 741 if (s->txp->cmd_a & 0x2000) { 742 /* First segment */ 743 s->txp->cmd_b = val; 744 s->txp->fifo_used++; 745 /* End alignment does not include command words. */ 746 n = (s->txp->buffer_size + s->txp->offset + 3) >> 2; 747 switch ((n >> 24) & 3) { 748 case 1: 749 n = (-n) & 3; 750 break; 751 case 2: 752 n = (-n) & 7; 753 break; 754 default: 755 n = 0; 756 } 757 s->txp->pad = n; 758 s->txp->len = 0; 759 } 760 DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n", 761 s->txp->buffer_size, s->txp->offset, s->txp->pad, 762 s->txp->cmd_a); 763 s->txp->state = TX_DATA; 764 break; 765 case TX_DATA: 766 if (s->txp->offset >= 4) { 767 s->txp->offset -= 4; 768 break; 769 } 770 if (s->txp->buffer_size <= 0 && s->txp->pad != 0) { 771 s->txp->pad--; 772 } else { 773 n = MIN(4, s->txp->buffer_size + s->txp->offset); 774 while (s->txp->offset) { 775 val >>= 8; 776 n--; 777 s->txp->offset--; 778 } 779 /* Documentation is somewhat unclear on the ordering of bytes 780 in FIFO words. Empirical results show it to be little-endian. 781 */ 782 /* TODO: FIFO overflow checking. */ 783 while (n--) { 784 s->txp->data[s->txp->len] = val & 0xff; 785 s->txp->len++; 786 val >>= 8; 787 s->txp->buffer_size--; 788 } 789 s->txp->fifo_used++; 790 } 791 if (s->txp->buffer_size <= 0 && s->txp->pad == 0) { 792 if (s->txp->cmd_a & 0x1000) { 793 do_tx_packet(s); 794 } 795 if (s->txp->cmd_a & 0x80000000) { 796 s->int_sts |= TX_IOC_INT; 797 } 798 s->txp->state = TX_IDLE; 799 } 800 break; 801 } 802 } 803 804 static uint32_t do_phy_read(lan9118_state *s, int reg) 805 { 806 uint32_t val; 807 808 switch (reg) { 809 case 0: /* Basic Control */ 810 return s->phy_control; 811 case 1: /* Basic Status */ 812 return s->phy_status; 813 case 2: /* ID1 */ 814 return 0x0007; 815 case 3: /* ID2 */ 816 return 0xc0d1; 817 case 4: /* Auto-neg advertisement */ 818 return s->phy_advertise; 819 case 5: /* Auto-neg Link Partner Ability */ 820 return 0x0f71; 821 case 6: /* Auto-neg Expansion */ 822 return 1; 823 /* TODO 17, 18, 27, 29, 30, 31 */ 824 case 29: /* Interrupt source. */ 825 val = s->phy_int; 826 s->phy_int = 0; 827 phy_update_irq(s); 828 return val; 829 case 30: /* Interrupt mask */ 830 return s->phy_int_mask; 831 default: 832 BADF("PHY read reg %d\n", reg); 833 return 0; 834 } 835 } 836 837 static void do_phy_write(lan9118_state *s, int reg, uint32_t val) 838 { 839 switch (reg) { 840 case 0: /* Basic Control */ 841 if (val & 0x8000) { 842 phy_reset(s); 843 break; 844 } 845 s->phy_control = val & 0x7980; 846 /* Complete autonegotiation immediately. */ 847 if (val & 0x1000) { 848 s->phy_status |= 0x0020; 849 } 850 break; 851 case 4: /* Auto-neg advertisement */ 852 s->phy_advertise = (val & 0x2d7f) | 0x80; 853 break; 854 /* TODO 17, 18, 27, 31 */ 855 case 30: /* Interrupt mask */ 856 s->phy_int_mask = val & 0xff; 857 phy_update_irq(s); 858 break; 859 default: 860 BADF("PHY write reg %d = 0x%04x\n", reg, val); 861 } 862 } 863 864 static void do_mac_write(lan9118_state *s, int reg, uint32_t val) 865 { 866 switch (reg) { 867 case MAC_CR: 868 if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) { 869 s->int_sts |= RXSTOP_INT; 870 } 871 s->mac_cr = val & ~MAC_CR_RESERVED; 872 DPRINTF("MAC_CR: %08x\n", val); 873 break; 874 case MAC_ADDRH: 875 s->conf.macaddr.a[4] = val & 0xff; 876 s->conf.macaddr.a[5] = (val >> 8) & 0xff; 877 lan9118_mac_changed(s); 878 break; 879 case MAC_ADDRL: 880 s->conf.macaddr.a[0] = val & 0xff; 881 s->conf.macaddr.a[1] = (val >> 8) & 0xff; 882 s->conf.macaddr.a[2] = (val >> 16) & 0xff; 883 s->conf.macaddr.a[3] = (val >> 24) & 0xff; 884 lan9118_mac_changed(s); 885 break; 886 case MAC_HASHH: 887 s->mac_hashh = val; 888 break; 889 case MAC_HASHL: 890 s->mac_hashl = val; 891 break; 892 case MAC_MII_ACC: 893 s->mac_mii_acc = val & 0xffc2; 894 if (val & 2) { 895 DPRINTF("PHY write %d = 0x%04x\n", 896 (val >> 6) & 0x1f, s->mac_mii_data); 897 do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); 898 } else { 899 s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); 900 DPRINTF("PHY read %d = 0x%04x\n", 901 (val >> 6) & 0x1f, s->mac_mii_data); 902 } 903 break; 904 case MAC_MII_DATA: 905 s->mac_mii_data = val & 0xffff; 906 break; 907 case MAC_FLOW: 908 s->mac_flow = val & 0xffff0000; 909 break; 910 case MAC_VLAN1: 911 /* Writing to this register changes a condition for 912 * FrameTooLong bit in rx_status. Since we do not set 913 * FrameTooLong anyway, just ignore write to this. 914 */ 915 break; 916 default: 917 qemu_log_mask(LOG_GUEST_ERROR, 918 "lan9118: Unimplemented MAC register write: %d = 0x%x\n", 919 s->mac_cmd & 0xf, val); 920 } 921 } 922 923 static uint32_t do_mac_read(lan9118_state *s, int reg) 924 { 925 switch (reg) { 926 case MAC_CR: 927 return s->mac_cr; 928 case MAC_ADDRH: 929 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); 930 case MAC_ADDRL: 931 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) 932 | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24); 933 case MAC_HASHH: 934 return s->mac_hashh; 935 case MAC_HASHL: 936 return s->mac_hashl; 937 case MAC_MII_ACC: 938 return s->mac_mii_acc; 939 case MAC_MII_DATA: 940 return s->mac_mii_data; 941 case MAC_FLOW: 942 return s->mac_flow; 943 default: 944 qemu_log_mask(LOG_GUEST_ERROR, 945 "lan9118: Unimplemented MAC register read: %d\n", 946 s->mac_cmd & 0xf); 947 return 0; 948 } 949 } 950 951 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr) 952 { 953 s->e2p_cmd = (s->e2p_cmd & E2P_CMD_MAC_ADDR_LOADED) | (cmd << 28) | addr; 954 switch (cmd) { 955 case 0: 956 s->e2p_data = s->eeprom[addr]; 957 DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data); 958 break; 959 case 1: 960 s->eeprom_writable = 0; 961 DPRINTF("EEPROM Write Disable\n"); 962 break; 963 case 2: /* EWEN */ 964 s->eeprom_writable = 1; 965 DPRINTF("EEPROM Write Enable\n"); 966 break; 967 case 3: /* WRITE */ 968 if (s->eeprom_writable) { 969 s->eeprom[addr] &= s->e2p_data; 970 DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data); 971 } else { 972 DPRINTF("EEPROM Write %d (ignored)\n", addr); 973 } 974 break; 975 case 4: /* WRAL */ 976 if (s->eeprom_writable) { 977 for (addr = 0; addr < 128; addr++) { 978 s->eeprom[addr] &= s->e2p_data; 979 } 980 DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data); 981 } else { 982 DPRINTF("EEPROM Write All (ignored)\n"); 983 } 984 break; 985 case 5: /* ERASE */ 986 if (s->eeprom_writable) { 987 s->eeprom[addr] = 0xff; 988 DPRINTF("EEPROM Erase %d\n", addr); 989 } else { 990 DPRINTF("EEPROM Erase %d (ignored)\n", addr); 991 } 992 break; 993 case 6: /* ERAL */ 994 if (s->eeprom_writable) { 995 memset(s->eeprom, 0xff, 128); 996 DPRINTF("EEPROM Erase All\n"); 997 } else { 998 DPRINTF("EEPROM Erase All (ignored)\n"); 999 } 1000 break; 1001 case 7: /* RELOAD */ 1002 lan9118_reload_eeprom(s); 1003 break; 1004 } 1005 } 1006 1007 static void lan9118_tick(void *opaque) 1008 { 1009 lan9118_state *s = (lan9118_state *)opaque; 1010 if (s->int_en & GPT_INT) { 1011 s->int_sts |= GPT_INT; 1012 } 1013 lan9118_update(s); 1014 } 1015 1016 static void lan9118_writel(void *opaque, hwaddr offset, 1017 uint64_t val, unsigned size) 1018 { 1019 lan9118_state *s = (lan9118_state *)opaque; 1020 offset &= 0xff; 1021 1022 //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); 1023 if (offset >= 0x20 && offset < 0x40) { 1024 /* TX FIFO */ 1025 tx_fifo_push(s, val); 1026 return; 1027 } 1028 switch (offset) { 1029 case CSR_IRQ_CFG: 1030 /* TODO: Implement interrupt deassertion intervals. */ 1031 val &= (IRQ_EN | IRQ_POL | IRQ_TYPE); 1032 s->irq_cfg = (s->irq_cfg & IRQ_INT) | val; 1033 break; 1034 case CSR_INT_STS: 1035 s->int_sts &= ~val; 1036 break; 1037 case CSR_INT_EN: 1038 s->int_en = val & ~RESERVED_INT; 1039 s->int_sts |= val & SW_INT; 1040 break; 1041 case CSR_FIFO_INT: 1042 DPRINTF("FIFO INT levels %08x\n", val); 1043 s->fifo_int = val; 1044 break; 1045 case CSR_RX_CFG: 1046 if (val & 0x8000) { 1047 /* RX_DUMP */ 1048 s->rx_fifo_used = 0; 1049 s->rx_status_fifo_used = 0; 1050 s->rx_packet_size_tail = s->rx_packet_size_head; 1051 s->rx_packet_size[s->rx_packet_size_head] = 0; 1052 } 1053 s->rx_cfg = val & 0xcfff1ff0; 1054 break; 1055 case CSR_TX_CFG: 1056 if (val & 0x8000) { 1057 s->tx_status_fifo_used = 0; 1058 } 1059 if (val & 0x4000) { 1060 s->txp->state = TX_IDLE; 1061 s->txp->fifo_used = 0; 1062 s->txp->cmd_a = 0xffffffff; 1063 } 1064 s->tx_cfg = val & 6; 1065 break; 1066 case CSR_HW_CFG: 1067 if (val & 1) { 1068 /* SRST */ 1069 lan9118_reset(DEVICE(s)); 1070 } else { 1071 s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4); 1072 } 1073 break; 1074 case CSR_RX_DP_CTRL: 1075 if (val & 0x80000000) { 1076 /* Skip forward to next packet. */ 1077 s->rxp_pad = 0; 1078 s->rxp_offset = 0; 1079 if (s->rxp_size == 0) { 1080 /* Pop a word to start the next packet. */ 1081 rx_fifo_pop(s); 1082 s->rxp_pad = 0; 1083 s->rxp_offset = 0; 1084 } 1085 s->rx_fifo_head += s->rxp_size; 1086 if (s->rx_fifo_head >= s->rx_fifo_size) { 1087 s->rx_fifo_head -= s->rx_fifo_size; 1088 } 1089 } 1090 break; 1091 case CSR_PMT_CTRL: 1092 if (val & 0x400) { 1093 phy_reset(s); 1094 } 1095 s->pmt_ctrl &= ~0x34e; 1096 s->pmt_ctrl |= (val & 0x34e); 1097 break; 1098 case CSR_GPIO_CFG: 1099 /* Probably just enabling LEDs. */ 1100 s->gpio_cfg = val & 0x7777071f; 1101 break; 1102 case CSR_GPT_CFG: 1103 if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) { 1104 ptimer_transaction_begin(s->timer); 1105 if (val & GPT_TIMER_EN) { 1106 ptimer_set_count(s->timer, val & 0xffff); 1107 ptimer_run(s->timer, 0); 1108 } else { 1109 ptimer_stop(s->timer); 1110 ptimer_set_count(s->timer, 0xffff); 1111 } 1112 ptimer_transaction_commit(s->timer); 1113 } 1114 s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff); 1115 break; 1116 case CSR_WORD_SWAP: 1117 /* Ignored because we're in 32-bit mode. */ 1118 s->word_swap = val; 1119 break; 1120 case CSR_MAC_CSR_CMD: 1121 s->mac_cmd = val & 0x4000000f; 1122 if (val & 0x80000000) { 1123 if (val & 0x40000000) { 1124 s->mac_data = do_mac_read(s, val & 0xf); 1125 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data); 1126 } else { 1127 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data); 1128 do_mac_write(s, val & 0xf, s->mac_data); 1129 } 1130 } 1131 break; 1132 case CSR_MAC_CSR_DATA: 1133 s->mac_data = val; 1134 break; 1135 case CSR_AFC_CFG: 1136 s->afc_cfg = val & 0x00ffffff; 1137 break; 1138 case CSR_E2P_CMD: 1139 lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f); 1140 break; 1141 case CSR_E2P_DATA: 1142 s->e2p_data = val & 0xff; 1143 break; 1144 1145 default: 1146 qemu_log_mask(LOG_GUEST_ERROR, "lan9118_write: Bad reg 0x%x = %x\n", 1147 (int)offset, (int)val); 1148 break; 1149 } 1150 lan9118_update(s); 1151 } 1152 1153 static void lan9118_writew(void *opaque, hwaddr offset, 1154 uint32_t val) 1155 { 1156 lan9118_state *s = (lan9118_state *)opaque; 1157 offset &= 0xff; 1158 1159 if (s->write_word_prev_offset != (offset & ~0x3)) { 1160 /* New offset, reset word counter */ 1161 s->write_word_n = 0; 1162 s->write_word_prev_offset = offset & ~0x3; 1163 } 1164 1165 if (offset & 0x2) { 1166 s->write_word_h = val; 1167 } else { 1168 s->write_word_l = val; 1169 } 1170 1171 //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val); 1172 s->write_word_n++; 1173 if (s->write_word_n == 2) { 1174 s->write_word_n = 0; 1175 lan9118_writel(s, offset & ~3, s->write_word_l + 1176 (s->write_word_h << 16), 4); 1177 } 1178 } 1179 1180 static void lan9118_16bit_mode_write(void *opaque, hwaddr offset, 1181 uint64_t val, unsigned size) 1182 { 1183 switch (size) { 1184 case 2: 1185 lan9118_writew(opaque, offset, (uint32_t)val); 1186 return; 1187 case 4: 1188 lan9118_writel(opaque, offset, val, size); 1189 return; 1190 } 1191 1192 hw_error("lan9118_write: Bad size 0x%x\n", size); 1193 } 1194 1195 static uint64_t lan9118_readl(void *opaque, hwaddr offset, 1196 unsigned size) 1197 { 1198 lan9118_state *s = (lan9118_state *)opaque; 1199 1200 //DPRINTF("Read reg 0x%02x\n", (int)offset); 1201 if (offset < 0x20) { 1202 /* RX FIFO */ 1203 return rx_fifo_pop(s); 1204 } 1205 switch (offset) { 1206 case 0x40: 1207 return rx_status_fifo_pop(s); 1208 case 0x44: 1209 return s->rx_status_fifo[s->tx_status_fifo_head]; 1210 case 0x48: 1211 return tx_status_fifo_pop(s); 1212 case 0x4c: 1213 return s->tx_status_fifo[s->tx_status_fifo_head]; 1214 case CSR_ID_REV: 1215 return 0x01180001; 1216 case CSR_IRQ_CFG: 1217 return s->irq_cfg; 1218 case CSR_INT_STS: 1219 return s->int_sts; 1220 case CSR_INT_EN: 1221 return s->int_en; 1222 case CSR_BYTE_TEST: 1223 return 0x87654321; 1224 case CSR_FIFO_INT: 1225 return s->fifo_int; 1226 case CSR_RX_CFG: 1227 return s->rx_cfg; 1228 case CSR_TX_CFG: 1229 return s->tx_cfg; 1230 case CSR_HW_CFG: 1231 return s->hw_cfg; 1232 case CSR_RX_DP_CTRL: 1233 return 0; 1234 case CSR_RX_FIFO_INF: 1235 return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2); 1236 case CSR_TX_FIFO_INF: 1237 return (s->tx_status_fifo_used << 16) 1238 | (s->tx_fifo_size - s->txp->fifo_used); 1239 case CSR_PMT_CTRL: 1240 return s->pmt_ctrl; 1241 case CSR_GPIO_CFG: 1242 return s->gpio_cfg; 1243 case CSR_GPT_CFG: 1244 return s->gpt_cfg; 1245 case CSR_GPT_CNT: 1246 return ptimer_get_count(s->timer); 1247 case CSR_WORD_SWAP: 1248 return s->word_swap; 1249 case CSR_FREE_RUN: 1250 return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40) - s->free_timer_start; 1251 case CSR_RX_DROP: 1252 /* TODO: Implement dropped frames counter. */ 1253 return 0; 1254 case CSR_MAC_CSR_CMD: 1255 return s->mac_cmd; 1256 case CSR_MAC_CSR_DATA: 1257 return s->mac_data; 1258 case CSR_AFC_CFG: 1259 return s->afc_cfg; 1260 case CSR_E2P_CMD: 1261 return s->e2p_cmd; 1262 case CSR_E2P_DATA: 1263 return s->e2p_data; 1264 } 1265 qemu_log_mask(LOG_GUEST_ERROR, "lan9118_read: Bad reg 0x%x\n", (int)offset); 1266 return 0; 1267 } 1268 1269 static uint32_t lan9118_readw(void *opaque, hwaddr offset) 1270 { 1271 lan9118_state *s = (lan9118_state *)opaque; 1272 uint32_t val; 1273 1274 if (s->read_word_prev_offset != (offset & ~0x3)) { 1275 /* New offset, reset word counter */ 1276 s->read_word_n = 0; 1277 s->read_word_prev_offset = offset & ~0x3; 1278 } 1279 1280 s->read_word_n++; 1281 if (s->read_word_n == 1) { 1282 s->read_long = lan9118_readl(s, offset & ~3, 4); 1283 } else { 1284 s->read_word_n = 0; 1285 } 1286 1287 if (offset & 2) { 1288 val = s->read_long >> 16; 1289 } else { 1290 val = s->read_long & 0xFFFF; 1291 } 1292 1293 //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val); 1294 return val; 1295 } 1296 1297 static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset, 1298 unsigned size) 1299 { 1300 switch (size) { 1301 case 2: 1302 return lan9118_readw(opaque, offset); 1303 case 4: 1304 return lan9118_readl(opaque, offset, size); 1305 } 1306 1307 hw_error("lan9118_read: Bad size 0x%x\n", size); 1308 return 0; 1309 } 1310 1311 static const MemoryRegionOps lan9118_mem_ops = { 1312 .read = lan9118_readl, 1313 .write = lan9118_writel, 1314 .endianness = DEVICE_NATIVE_ENDIAN, 1315 }; 1316 1317 static const MemoryRegionOps lan9118_16bit_mem_ops = { 1318 .read = lan9118_16bit_mode_read, 1319 .write = lan9118_16bit_mode_write, 1320 .endianness = DEVICE_NATIVE_ENDIAN, 1321 }; 1322 1323 static NetClientInfo net_lan9118_info = { 1324 .type = NET_CLIENT_DRIVER_NIC, 1325 .size = sizeof(NICState), 1326 .receive = lan9118_receive, 1327 .link_status_changed = lan9118_set_link, 1328 }; 1329 1330 static void lan9118_realize(DeviceState *dev, Error **errp) 1331 { 1332 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1333 lan9118_state *s = LAN9118(dev); 1334 int i; 1335 const MemoryRegionOps *mem_ops = 1336 s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; 1337 1338 memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, 1339 "lan9118-mmio", 0x100); 1340 sysbus_init_mmio(sbd, &s->mmio); 1341 sysbus_init_irq(sbd, &s->irq); 1342 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1343 1344 s->nic = qemu_new_nic(&net_lan9118_info, &s->conf, 1345 object_get_typename(OBJECT(dev)), dev->id, s); 1346 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 1347 s->eeprom[0] = 0xa5; 1348 for (i = 0; i < 6; i++) { 1349 s->eeprom[i + 1] = s->conf.macaddr.a[i]; 1350 } 1351 s->pmt_ctrl = 1; 1352 s->txp = &s->tx_packet; 1353 1354 s->timer = ptimer_init(lan9118_tick, s, PTIMER_POLICY_DEFAULT); 1355 ptimer_transaction_begin(s->timer); 1356 ptimer_set_freq(s->timer, 10000); 1357 ptimer_set_limit(s->timer, 0xffff, 1); 1358 ptimer_transaction_commit(s->timer); 1359 } 1360 1361 static Property lan9118_properties[] = { 1362 DEFINE_NIC_PROPERTIES(lan9118_state, conf), 1363 DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0), 1364 DEFINE_PROP_END_OF_LIST(), 1365 }; 1366 1367 static void lan9118_class_init(ObjectClass *klass, void *data) 1368 { 1369 DeviceClass *dc = DEVICE_CLASS(klass); 1370 1371 dc->reset = lan9118_reset; 1372 device_class_set_props(dc, lan9118_properties); 1373 dc->vmsd = &vmstate_lan9118; 1374 dc->realize = lan9118_realize; 1375 } 1376 1377 static const TypeInfo lan9118_info = { 1378 .name = TYPE_LAN9118, 1379 .parent = TYPE_SYS_BUS_DEVICE, 1380 .instance_size = sizeof(lan9118_state), 1381 .class_init = lan9118_class_init, 1382 }; 1383 1384 static void lan9118_register_types(void) 1385 { 1386 type_register_static(&lan9118_info); 1387 } 1388 1389 /* Legacy helper function. Should go away when machine config files are 1390 implemented. */ 1391 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq) 1392 { 1393 DeviceState *dev; 1394 SysBusDevice *s; 1395 1396 qemu_check_nic_model(nd, "lan9118"); 1397 dev = qdev_new(TYPE_LAN9118); 1398 qdev_set_nic_properties(dev, nd); 1399 s = SYS_BUS_DEVICE(dev); 1400 sysbus_realize_and_unref(s, &error_fatal); 1401 sysbus_mmio_map(s, 0, base); 1402 sysbus_connect_irq(s, 0, irq); 1403 } 1404 1405 type_init(lan9118_register_types) 1406