xref: /openbmc/qemu/hw/net/lan9118.c (revision 650d103d3ea959212f826acb9d3fe80cf30e347b)
1 /*
2  * SMSC LAN9118 Ethernet interface emulation
3  *
4  * Copyright (c) 2009 CodeSourcery, LLC.
5  * Written by Paul Brook
6  *
7  * This code is licensed under the GNU GPL v2
8  *
9  * Contributions after 2012-01-13 are licensed under the terms of the
10  * GNU GPL, version 2 or (at your option) any later version.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "hw/sysbus.h"
15 #include "migration/vmstate.h"
16 #include "net/net.h"
17 #include "net/eth.h"
18 #include "hw/hw.h"
19 #include "hw/irq.h"
20 #include "hw/net/lan9118.h"
21 #include "sysemu/sysemu.h"
22 #include "hw/ptimer.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 /* For crc32 */
26 #include <zlib.h>
27 
28 //#define DEBUG_LAN9118
29 
30 #ifdef DEBUG_LAN9118
31 #define DPRINTF(fmt, ...) \
32 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
33 #define BADF(fmt, ...) \
34 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
35 #else
36 #define DPRINTF(fmt, ...) do {} while(0)
37 #define BADF(fmt, ...) \
38 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
39 #endif
40 
41 #define CSR_ID_REV      0x50
42 #define CSR_IRQ_CFG     0x54
43 #define CSR_INT_STS     0x58
44 #define CSR_INT_EN      0x5c
45 #define CSR_BYTE_TEST   0x64
46 #define CSR_FIFO_INT    0x68
47 #define CSR_RX_CFG      0x6c
48 #define CSR_TX_CFG      0x70
49 #define CSR_HW_CFG      0x74
50 #define CSR_RX_DP_CTRL  0x78
51 #define CSR_RX_FIFO_INF 0x7c
52 #define CSR_TX_FIFO_INF 0x80
53 #define CSR_PMT_CTRL    0x84
54 #define CSR_GPIO_CFG    0x88
55 #define CSR_GPT_CFG     0x8c
56 #define CSR_GPT_CNT     0x90
57 #define CSR_WORD_SWAP   0x98
58 #define CSR_FREE_RUN    0x9c
59 #define CSR_RX_DROP     0xa0
60 #define CSR_MAC_CSR_CMD 0xa4
61 #define CSR_MAC_CSR_DATA 0xa8
62 #define CSR_AFC_CFG     0xac
63 #define CSR_E2P_CMD     0xb0
64 #define CSR_E2P_DATA    0xb4
65 
66 #define E2P_CMD_MAC_ADDR_LOADED 0x100
67 
68 /* IRQ_CFG */
69 #define IRQ_INT         0x00001000
70 #define IRQ_EN          0x00000100
71 #define IRQ_POL         0x00000010
72 #define IRQ_TYPE        0x00000001
73 
74 /* INT_STS/INT_EN */
75 #define SW_INT          0x80000000
76 #define TXSTOP_INT      0x02000000
77 #define RXSTOP_INT      0x01000000
78 #define RXDFH_INT       0x00800000
79 #define TX_IOC_INT      0x00200000
80 #define RXD_INT         0x00100000
81 #define GPT_INT         0x00080000
82 #define PHY_INT         0x00040000
83 #define PME_INT         0x00020000
84 #define TXSO_INT        0x00010000
85 #define RWT_INT         0x00008000
86 #define RXE_INT         0x00004000
87 #define TXE_INT         0x00002000
88 #define TDFU_INT        0x00000800
89 #define TDFO_INT        0x00000400
90 #define TDFA_INT        0x00000200
91 #define TSFF_INT        0x00000100
92 #define TSFL_INT        0x00000080
93 #define RXDF_INT        0x00000040
94 #define RDFL_INT        0x00000020
95 #define RSFF_INT        0x00000010
96 #define RSFL_INT        0x00000008
97 #define GPIO2_INT       0x00000004
98 #define GPIO1_INT       0x00000002
99 #define GPIO0_INT       0x00000001
100 #define RESERVED_INT    0x7c001000
101 
102 #define MAC_CR          1
103 #define MAC_ADDRH       2
104 #define MAC_ADDRL       3
105 #define MAC_HASHH       4
106 #define MAC_HASHL       5
107 #define MAC_MII_ACC     6
108 #define MAC_MII_DATA    7
109 #define MAC_FLOW        8
110 #define MAC_VLAN1       9 /* TODO */
111 #define MAC_VLAN2       10 /* TODO */
112 #define MAC_WUFF        11 /* TODO */
113 #define MAC_WUCSR       12 /* TODO */
114 
115 #define MAC_CR_RXALL    0x80000000
116 #define MAC_CR_RCVOWN   0x00800000
117 #define MAC_CR_LOOPBK   0x00200000
118 #define MAC_CR_FDPX     0x00100000
119 #define MAC_CR_MCPAS    0x00080000
120 #define MAC_CR_PRMS     0x00040000
121 #define MAC_CR_INVFILT  0x00020000
122 #define MAC_CR_PASSBAD  0x00010000
123 #define MAC_CR_HO       0x00008000
124 #define MAC_CR_HPFILT   0x00002000
125 #define MAC_CR_LCOLL    0x00001000
126 #define MAC_CR_BCAST    0x00000800
127 #define MAC_CR_DISRTY   0x00000400
128 #define MAC_CR_PADSTR   0x00000100
129 #define MAC_CR_BOLMT    0x000000c0
130 #define MAC_CR_DFCHK    0x00000020
131 #define MAC_CR_TXEN     0x00000008
132 #define MAC_CR_RXEN     0x00000004
133 #define MAC_CR_RESERVED 0x7f404213
134 
135 #define PHY_INT_ENERGYON            0x80
136 #define PHY_INT_AUTONEG_COMPLETE    0x40
137 #define PHY_INT_FAULT               0x20
138 #define PHY_INT_DOWN                0x10
139 #define PHY_INT_AUTONEG_LP          0x08
140 #define PHY_INT_PARFAULT            0x04
141 #define PHY_INT_AUTONEG_PAGE        0x02
142 
143 #define GPT_TIMER_EN    0x20000000
144 
145 enum tx_state {
146     TX_IDLE,
147     TX_B,
148     TX_DATA
149 };
150 
151 typedef struct {
152     /* state is a tx_state but we can't put enums in VMStateDescriptions. */
153     uint32_t state;
154     uint32_t cmd_a;
155     uint32_t cmd_b;
156     int32_t buffer_size;
157     int32_t offset;
158     int32_t pad;
159     int32_t fifo_used;
160     int32_t len;
161     uint8_t data[2048];
162 } LAN9118Packet;
163 
164 static const VMStateDescription vmstate_lan9118_packet = {
165     .name = "lan9118_packet",
166     .version_id = 1,
167     .minimum_version_id = 1,
168     .fields = (VMStateField[]) {
169         VMSTATE_UINT32(state, LAN9118Packet),
170         VMSTATE_UINT32(cmd_a, LAN9118Packet),
171         VMSTATE_UINT32(cmd_b, LAN9118Packet),
172         VMSTATE_INT32(buffer_size, LAN9118Packet),
173         VMSTATE_INT32(offset, LAN9118Packet),
174         VMSTATE_INT32(pad, LAN9118Packet),
175         VMSTATE_INT32(fifo_used, LAN9118Packet),
176         VMSTATE_INT32(len, LAN9118Packet),
177         VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
178         VMSTATE_END_OF_LIST()
179     }
180 };
181 
182 #define LAN9118(obj) OBJECT_CHECK(lan9118_state, (obj), TYPE_LAN9118)
183 
184 typedef struct {
185     SysBusDevice parent_obj;
186 
187     NICState *nic;
188     NICConf conf;
189     qemu_irq irq;
190     MemoryRegion mmio;
191     ptimer_state *timer;
192 
193     uint32_t irq_cfg;
194     uint32_t int_sts;
195     uint32_t int_en;
196     uint32_t fifo_int;
197     uint32_t rx_cfg;
198     uint32_t tx_cfg;
199     uint32_t hw_cfg;
200     uint32_t pmt_ctrl;
201     uint32_t gpio_cfg;
202     uint32_t gpt_cfg;
203     uint32_t word_swap;
204     uint32_t free_timer_start;
205     uint32_t mac_cmd;
206     uint32_t mac_data;
207     uint32_t afc_cfg;
208     uint32_t e2p_cmd;
209     uint32_t e2p_data;
210 
211     uint32_t mac_cr;
212     uint32_t mac_hashh;
213     uint32_t mac_hashl;
214     uint32_t mac_mii_acc;
215     uint32_t mac_mii_data;
216     uint32_t mac_flow;
217 
218     uint32_t phy_status;
219     uint32_t phy_control;
220     uint32_t phy_advertise;
221     uint32_t phy_int;
222     uint32_t phy_int_mask;
223 
224     int32_t eeprom_writable;
225     uint8_t eeprom[128];
226 
227     int32_t tx_fifo_size;
228     LAN9118Packet *txp;
229     LAN9118Packet tx_packet;
230 
231     int32_t tx_status_fifo_used;
232     int32_t tx_status_fifo_head;
233     uint32_t tx_status_fifo[512];
234 
235     int32_t rx_status_fifo_size;
236     int32_t rx_status_fifo_used;
237     int32_t rx_status_fifo_head;
238     uint32_t rx_status_fifo[896];
239     int32_t rx_fifo_size;
240     int32_t rx_fifo_used;
241     int32_t rx_fifo_head;
242     uint32_t rx_fifo[3360];
243     int32_t rx_packet_size_head;
244     int32_t rx_packet_size_tail;
245     int32_t rx_packet_size[1024];
246 
247     int32_t rxp_offset;
248     int32_t rxp_size;
249     int32_t rxp_pad;
250 
251     uint32_t write_word_prev_offset;
252     uint32_t write_word_n;
253     uint16_t write_word_l;
254     uint16_t write_word_h;
255     uint32_t read_word_prev_offset;
256     uint32_t read_word_n;
257     uint32_t read_long;
258 
259     uint32_t mode_16bit;
260 } lan9118_state;
261 
262 static const VMStateDescription vmstate_lan9118 = {
263     .name = "lan9118",
264     .version_id = 2,
265     .minimum_version_id = 1,
266     .fields = (VMStateField[]) {
267         VMSTATE_PTIMER(timer, lan9118_state),
268         VMSTATE_UINT32(irq_cfg, lan9118_state),
269         VMSTATE_UINT32(int_sts, lan9118_state),
270         VMSTATE_UINT32(int_en, lan9118_state),
271         VMSTATE_UINT32(fifo_int, lan9118_state),
272         VMSTATE_UINT32(rx_cfg, lan9118_state),
273         VMSTATE_UINT32(tx_cfg, lan9118_state),
274         VMSTATE_UINT32(hw_cfg, lan9118_state),
275         VMSTATE_UINT32(pmt_ctrl, lan9118_state),
276         VMSTATE_UINT32(gpio_cfg, lan9118_state),
277         VMSTATE_UINT32(gpt_cfg, lan9118_state),
278         VMSTATE_UINT32(word_swap, lan9118_state),
279         VMSTATE_UINT32(free_timer_start, lan9118_state),
280         VMSTATE_UINT32(mac_cmd, lan9118_state),
281         VMSTATE_UINT32(mac_data, lan9118_state),
282         VMSTATE_UINT32(afc_cfg, lan9118_state),
283         VMSTATE_UINT32(e2p_cmd, lan9118_state),
284         VMSTATE_UINT32(e2p_data, lan9118_state),
285         VMSTATE_UINT32(mac_cr, lan9118_state),
286         VMSTATE_UINT32(mac_hashh, lan9118_state),
287         VMSTATE_UINT32(mac_hashl, lan9118_state),
288         VMSTATE_UINT32(mac_mii_acc, lan9118_state),
289         VMSTATE_UINT32(mac_mii_data, lan9118_state),
290         VMSTATE_UINT32(mac_flow, lan9118_state),
291         VMSTATE_UINT32(phy_status, lan9118_state),
292         VMSTATE_UINT32(phy_control, lan9118_state),
293         VMSTATE_UINT32(phy_advertise, lan9118_state),
294         VMSTATE_UINT32(phy_int, lan9118_state),
295         VMSTATE_UINT32(phy_int_mask, lan9118_state),
296         VMSTATE_INT32(eeprom_writable, lan9118_state),
297         VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
298         VMSTATE_INT32(tx_fifo_size, lan9118_state),
299         /* txp always points at tx_packet so need not be saved */
300         VMSTATE_STRUCT(tx_packet, lan9118_state, 0,
301                        vmstate_lan9118_packet, LAN9118Packet),
302         VMSTATE_INT32(tx_status_fifo_used, lan9118_state),
303         VMSTATE_INT32(tx_status_fifo_head, lan9118_state),
304         VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512),
305         VMSTATE_INT32(rx_status_fifo_size, lan9118_state),
306         VMSTATE_INT32(rx_status_fifo_used, lan9118_state),
307         VMSTATE_INT32(rx_status_fifo_head, lan9118_state),
308         VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896),
309         VMSTATE_INT32(rx_fifo_size, lan9118_state),
310         VMSTATE_INT32(rx_fifo_used, lan9118_state),
311         VMSTATE_INT32(rx_fifo_head, lan9118_state),
312         VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360),
313         VMSTATE_INT32(rx_packet_size_head, lan9118_state),
314         VMSTATE_INT32(rx_packet_size_tail, lan9118_state),
315         VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024),
316         VMSTATE_INT32(rxp_offset, lan9118_state),
317         VMSTATE_INT32(rxp_size, lan9118_state),
318         VMSTATE_INT32(rxp_pad, lan9118_state),
319         VMSTATE_UINT32_V(write_word_prev_offset, lan9118_state, 2),
320         VMSTATE_UINT32_V(write_word_n, lan9118_state, 2),
321         VMSTATE_UINT16_V(write_word_l, lan9118_state, 2),
322         VMSTATE_UINT16_V(write_word_h, lan9118_state, 2),
323         VMSTATE_UINT32_V(read_word_prev_offset, lan9118_state, 2),
324         VMSTATE_UINT32_V(read_word_n, lan9118_state, 2),
325         VMSTATE_UINT32_V(read_long, lan9118_state, 2),
326         VMSTATE_UINT32_V(mode_16bit, lan9118_state, 2),
327         VMSTATE_END_OF_LIST()
328     }
329 };
330 
331 static void lan9118_update(lan9118_state *s)
332 {
333     int level;
334 
335     /* TODO: Implement FIFO level IRQs.  */
336     level = (s->int_sts & s->int_en) != 0;
337     if (level) {
338         s->irq_cfg |= IRQ_INT;
339     } else {
340         s->irq_cfg &= ~IRQ_INT;
341     }
342     if ((s->irq_cfg & IRQ_EN) == 0) {
343         level = 0;
344     }
345     if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
346         /* Interrupt is active low unless we're configured as
347          * active-high polarity, push-pull type.
348          */
349         level = !level;
350     }
351     qemu_set_irq(s->irq, level);
352 }
353 
354 static void lan9118_mac_changed(lan9118_state *s)
355 {
356     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
357 }
358 
359 static void lan9118_reload_eeprom(lan9118_state *s)
360 {
361     int i;
362     if (s->eeprom[0] != 0xa5) {
363         s->e2p_cmd &= ~E2P_CMD_MAC_ADDR_LOADED;
364         DPRINTF("MACADDR load failed\n");
365         return;
366     }
367     for (i = 0; i < 6; i++) {
368         s->conf.macaddr.a[i] = s->eeprom[i + 1];
369     }
370     s->e2p_cmd |= E2P_CMD_MAC_ADDR_LOADED;
371     DPRINTF("MACADDR loaded from eeprom\n");
372     lan9118_mac_changed(s);
373 }
374 
375 static void phy_update_irq(lan9118_state *s)
376 {
377     if (s->phy_int & s->phy_int_mask) {
378         s->int_sts |= PHY_INT;
379     } else {
380         s->int_sts &= ~PHY_INT;
381     }
382     lan9118_update(s);
383 }
384 
385 static void phy_update_link(lan9118_state *s)
386 {
387     /* Autonegotiation status mirrors link status.  */
388     if (qemu_get_queue(s->nic)->link_down) {
389         s->phy_status &= ~0x0024;
390         s->phy_int |= PHY_INT_DOWN;
391     } else {
392         s->phy_status |= 0x0024;
393         s->phy_int |= PHY_INT_ENERGYON;
394         s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
395     }
396     phy_update_irq(s);
397 }
398 
399 static void lan9118_set_link(NetClientState *nc)
400 {
401     phy_update_link(qemu_get_nic_opaque(nc));
402 }
403 
404 static void phy_reset(lan9118_state *s)
405 {
406     s->phy_status = 0x7809;
407     s->phy_control = 0x3000;
408     s->phy_advertise = 0x01e1;
409     s->phy_int_mask = 0;
410     s->phy_int = 0;
411     phy_update_link(s);
412 }
413 
414 static void lan9118_reset(DeviceState *d)
415 {
416     lan9118_state *s = LAN9118(d);
417 
418     s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
419     s->int_sts = 0;
420     s->int_en = 0;
421     s->fifo_int = 0x48000000;
422     s->rx_cfg = 0;
423     s->tx_cfg = 0;
424     s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004;
425     s->pmt_ctrl &= 0x45;
426     s->gpio_cfg = 0;
427     s->txp->fifo_used = 0;
428     s->txp->state = TX_IDLE;
429     s->txp->cmd_a = 0xffffffffu;
430     s->txp->cmd_b = 0xffffffffu;
431     s->txp->len = 0;
432     s->txp->fifo_used = 0;
433     s->tx_fifo_size = 4608;
434     s->tx_status_fifo_used = 0;
435     s->rx_status_fifo_size = 704;
436     s->rx_fifo_size = 2640;
437     s->rx_fifo_used = 0;
438     s->rx_status_fifo_size = 176;
439     s->rx_status_fifo_used = 0;
440     s->rxp_offset = 0;
441     s->rxp_size = 0;
442     s->rxp_pad = 0;
443     s->rx_packet_size_tail = s->rx_packet_size_head;
444     s->rx_packet_size[s->rx_packet_size_head] = 0;
445     s->mac_cmd = 0;
446     s->mac_data = 0;
447     s->afc_cfg = 0;
448     s->e2p_cmd = 0;
449     s->e2p_data = 0;
450     s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40;
451 
452     ptimer_stop(s->timer);
453     ptimer_set_count(s->timer, 0xffff);
454     s->gpt_cfg = 0xffff;
455 
456     s->mac_cr = MAC_CR_PRMS;
457     s->mac_hashh = 0;
458     s->mac_hashl = 0;
459     s->mac_mii_acc = 0;
460     s->mac_mii_data = 0;
461     s->mac_flow = 0;
462 
463     s->read_word_n = 0;
464     s->write_word_n = 0;
465 
466     phy_reset(s);
467 
468     s->eeprom_writable = 0;
469     lan9118_reload_eeprom(s);
470 }
471 
472 static void rx_fifo_push(lan9118_state *s, uint32_t val)
473 {
474     int fifo_pos;
475     fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
476     if (fifo_pos >= s->rx_fifo_size)
477       fifo_pos -= s->rx_fifo_size;
478     s->rx_fifo[fifo_pos] = val;
479     s->rx_fifo_used++;
480 }
481 
482 /* Return nonzero if the packet is accepted by the filter.  */
483 static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
484 {
485     int multicast;
486     uint32_t hash;
487 
488     if (s->mac_cr & MAC_CR_PRMS) {
489         return 1;
490     }
491     if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
492         addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
493         return (s->mac_cr & MAC_CR_BCAST) == 0;
494     }
495 
496     multicast = addr[0] & 1;
497     if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
498         return 1;
499     }
500     if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
501                   : (s->mac_cr & MAC_CR_HO) == 0) {
502         /* Exact matching.  */
503         hash = memcmp(addr, s->conf.macaddr.a, 6);
504         if (s->mac_cr & MAC_CR_INVFILT) {
505             return hash != 0;
506         } else {
507             return hash == 0;
508         }
509     } else {
510         /* Hash matching  */
511         hash = net_crc32(addr, ETH_ALEN) >> 26;
512         if (hash & 0x20) {
513             return (s->mac_hashh >> (hash & 0x1f)) & 1;
514         } else {
515             return (s->mac_hashl >> (hash & 0x1f)) & 1;
516         }
517     }
518 }
519 
520 static ssize_t lan9118_receive(NetClientState *nc, const uint8_t *buf,
521                                size_t size)
522 {
523     lan9118_state *s = qemu_get_nic_opaque(nc);
524     int fifo_len;
525     int offset;
526     int src_pos;
527     int n;
528     int filter;
529     uint32_t val;
530     uint32_t crc;
531     uint32_t status;
532 
533     if ((s->mac_cr & MAC_CR_RXEN) == 0) {
534         return -1;
535     }
536 
537     if (size >= 2048 || size < 14) {
538         return -1;
539     }
540 
541     /* TODO: Implement FIFO overflow notification.  */
542     if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
543         return -1;
544     }
545 
546     filter = lan9118_filter(s, buf);
547     if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
548         return size;
549     }
550 
551     offset = (s->rx_cfg >> 8) & 0x1f;
552     n = offset & 3;
553     fifo_len = (size + n + 3) >> 2;
554     /* Add a word for the CRC.  */
555     fifo_len++;
556     if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
557         return -1;
558     }
559 
560     DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
561             (int)size, fifo_len, filter ? "pass" : "fail");
562     val = 0;
563     crc = bswap32(crc32(~0, buf, size));
564     for (src_pos = 0; src_pos < size; src_pos++) {
565         val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
566         n++;
567         if (n == 4) {
568             n = 0;
569             rx_fifo_push(s, val);
570             val = 0;
571         }
572     }
573     if (n) {
574         val >>= ((4 - n) * 8);
575         val |= crc << (n * 8);
576         rx_fifo_push(s, val);
577         val = crc >> ((4 - n) * 8);
578         rx_fifo_push(s, val);
579     } else {
580         rx_fifo_push(s, crc);
581     }
582     n = s->rx_status_fifo_head + s->rx_status_fifo_used;
583     if (n >= s->rx_status_fifo_size) {
584         n -= s->rx_status_fifo_size;
585     }
586     s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
587     s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
588     s->rx_status_fifo_used++;
589 
590     status = (size + 4) << 16;
591     if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
592         buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
593         status |= 0x00002000;
594     } else if (buf[0] & 1) {
595         status |= 0x00000400;
596     }
597     if (!filter) {
598         status |= 0x40000000;
599     }
600     s->rx_status_fifo[n] = status;
601 
602     if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
603         s->int_sts |= RSFL_INT;
604     }
605     lan9118_update(s);
606 
607     return size;
608 }
609 
610 static uint32_t rx_fifo_pop(lan9118_state *s)
611 {
612     int n;
613     uint32_t val;
614 
615     if (s->rxp_size == 0 && s->rxp_pad == 0) {
616         s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
617         s->rx_packet_size[s->rx_packet_size_head] = 0;
618         if (s->rxp_size != 0) {
619             s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
620             s->rxp_offset = (s->rx_cfg >> 10) & 7;
621             n = s->rxp_offset + s->rxp_size;
622             switch (s->rx_cfg >> 30) {
623             case 1:
624                 n = (-n) & 3;
625                 break;
626             case 2:
627                 n = (-n) & 7;
628                 break;
629             default:
630                 n = 0;
631                 break;
632             }
633             s->rxp_pad = n;
634             DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
635                     s->rxp_size, s->rxp_offset, s->rxp_pad);
636         }
637     }
638     if (s->rxp_offset > 0) {
639         s->rxp_offset--;
640         val = 0;
641     } else if (s->rxp_size > 0) {
642         s->rxp_size--;
643         val = s->rx_fifo[s->rx_fifo_head++];
644         if (s->rx_fifo_head >= s->rx_fifo_size) {
645             s->rx_fifo_head -= s->rx_fifo_size;
646         }
647         s->rx_fifo_used--;
648     } else if (s->rxp_pad > 0) {
649         s->rxp_pad--;
650         val =  0;
651     } else {
652         DPRINTF("RX underflow\n");
653         s->int_sts |= RXE_INT;
654         val =  0;
655     }
656     lan9118_update(s);
657     return val;
658 }
659 
660 static void do_tx_packet(lan9118_state *s)
661 {
662     int n;
663     uint32_t status;
664 
665     /* FIXME: Honor TX disable, and allow queueing of packets.  */
666     if (s->phy_control & 0x4000)  {
667         /* This assumes the receive routine doesn't touch the VLANClient.  */
668         lan9118_receive(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
669     } else {
670         qemu_send_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
671     }
672     s->txp->fifo_used = 0;
673 
674     if (s->tx_status_fifo_used == 512) {
675         /* Status FIFO full */
676         return;
677     }
678     /* Add entry to status FIFO.  */
679     status = s->txp->cmd_b & 0xffff0000u;
680     DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
681     n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
682     s->tx_status_fifo[n] = status;
683     s->tx_status_fifo_used++;
684     if (s->tx_status_fifo_used == 512) {
685         s->int_sts |= TSFF_INT;
686         /* TODO: Stop transmission.  */
687     }
688 }
689 
690 static uint32_t rx_status_fifo_pop(lan9118_state *s)
691 {
692     uint32_t val;
693 
694     val = s->rx_status_fifo[s->rx_status_fifo_head];
695     if (s->rx_status_fifo_used != 0) {
696         s->rx_status_fifo_used--;
697         s->rx_status_fifo_head++;
698         if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
699             s->rx_status_fifo_head -= s->rx_status_fifo_size;
700         }
701         /* ??? What value should be returned when the FIFO is empty?  */
702         DPRINTF("RX status pop 0x%08x\n", val);
703     }
704     return val;
705 }
706 
707 static uint32_t tx_status_fifo_pop(lan9118_state *s)
708 {
709     uint32_t val;
710 
711     val = s->tx_status_fifo[s->tx_status_fifo_head];
712     if (s->tx_status_fifo_used != 0) {
713         s->tx_status_fifo_used--;
714         s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
715         /* ??? What value should be returned when the FIFO is empty?  */
716     }
717     return val;
718 }
719 
720 static void tx_fifo_push(lan9118_state *s, uint32_t val)
721 {
722     int n;
723 
724     if (s->txp->fifo_used == s->tx_fifo_size) {
725         s->int_sts |= TDFO_INT;
726         return;
727     }
728     switch (s->txp->state) {
729     case TX_IDLE:
730         s->txp->cmd_a = val & 0x831f37ff;
731         s->txp->fifo_used++;
732         s->txp->state = TX_B;
733         s->txp->buffer_size = extract32(s->txp->cmd_a, 0, 11);
734         s->txp->offset = extract32(s->txp->cmd_a, 16, 5);
735         break;
736     case TX_B:
737         if (s->txp->cmd_a & 0x2000) {
738             /* First segment */
739             s->txp->cmd_b = val;
740             s->txp->fifo_used++;
741             /* End alignment does not include command words.  */
742             n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
743             switch ((n >> 24) & 3) {
744             case 1:
745                 n = (-n) & 3;
746                 break;
747             case 2:
748                 n = (-n) & 7;
749                 break;
750             default:
751                 n = 0;
752             }
753             s->txp->pad = n;
754             s->txp->len = 0;
755         }
756         DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
757                 s->txp->buffer_size, s->txp->offset, s->txp->pad,
758                 s->txp->cmd_a);
759         s->txp->state = TX_DATA;
760         break;
761     case TX_DATA:
762         if (s->txp->offset >= 4) {
763             s->txp->offset -= 4;
764             break;
765         }
766         if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
767             s->txp->pad--;
768         } else {
769             n = MIN(4, s->txp->buffer_size + s->txp->offset);
770             while (s->txp->offset) {
771                 val >>= 8;
772                 n--;
773                 s->txp->offset--;
774             }
775             /* Documentation is somewhat unclear on the ordering of bytes
776                in FIFO words.  Empirical results show it to be little-endian.
777                */
778             /* TODO: FIFO overflow checking.  */
779             while (n--) {
780                 s->txp->data[s->txp->len] = val & 0xff;
781                 s->txp->len++;
782                 val >>= 8;
783                 s->txp->buffer_size--;
784             }
785             s->txp->fifo_used++;
786         }
787         if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
788             if (s->txp->cmd_a & 0x1000) {
789                 do_tx_packet(s);
790             }
791             if (s->txp->cmd_a & 0x80000000) {
792                 s->int_sts |= TX_IOC_INT;
793             }
794             s->txp->state = TX_IDLE;
795         }
796         break;
797     }
798 }
799 
800 static uint32_t do_phy_read(lan9118_state *s, int reg)
801 {
802     uint32_t val;
803 
804     switch (reg) {
805     case 0: /* Basic Control */
806         return s->phy_control;
807     case 1: /* Basic Status */
808         return s->phy_status;
809     case 2: /* ID1 */
810         return 0x0007;
811     case 3: /* ID2 */
812         return 0xc0d1;
813     case 4: /* Auto-neg advertisement */
814         return s->phy_advertise;
815     case 5: /* Auto-neg Link Partner Ability */
816         return 0x0f71;
817     case 6: /* Auto-neg Expansion */
818         return 1;
819         /* TODO 17, 18, 27, 29, 30, 31 */
820     case 29: /* Interrupt source.  */
821         val = s->phy_int;
822         s->phy_int = 0;
823         phy_update_irq(s);
824         return val;
825     case 30: /* Interrupt mask */
826         return s->phy_int_mask;
827     default:
828         BADF("PHY read reg %d\n", reg);
829         return 0;
830     }
831 }
832 
833 static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
834 {
835     switch (reg) {
836     case 0: /* Basic Control */
837         if (val & 0x8000) {
838             phy_reset(s);
839             break;
840         }
841         s->phy_control = val & 0x7980;
842         /* Complete autonegotiation immediately.  */
843         if (val & 0x1000) {
844             s->phy_status |= 0x0020;
845         }
846         break;
847     case 4: /* Auto-neg advertisement */
848         s->phy_advertise = (val & 0x2d7f) | 0x80;
849         break;
850         /* TODO 17, 18, 27, 31 */
851     case 30: /* Interrupt mask */
852         s->phy_int_mask = val & 0xff;
853         phy_update_irq(s);
854         break;
855     default:
856         BADF("PHY write reg %d = 0x%04x\n", reg, val);
857     }
858 }
859 
860 static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
861 {
862     switch (reg) {
863     case MAC_CR:
864         if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
865             s->int_sts |= RXSTOP_INT;
866         }
867         s->mac_cr = val & ~MAC_CR_RESERVED;
868         DPRINTF("MAC_CR: %08x\n", val);
869         break;
870     case MAC_ADDRH:
871         s->conf.macaddr.a[4] = val & 0xff;
872         s->conf.macaddr.a[5] = (val >> 8) & 0xff;
873         lan9118_mac_changed(s);
874         break;
875     case MAC_ADDRL:
876         s->conf.macaddr.a[0] = val & 0xff;
877         s->conf.macaddr.a[1] = (val >> 8) & 0xff;
878         s->conf.macaddr.a[2] = (val >> 16) & 0xff;
879         s->conf.macaddr.a[3] = (val >> 24) & 0xff;
880         lan9118_mac_changed(s);
881         break;
882     case MAC_HASHH:
883         s->mac_hashh = val;
884         break;
885     case MAC_HASHL:
886         s->mac_hashl = val;
887         break;
888     case MAC_MII_ACC:
889         s->mac_mii_acc = val & 0xffc2;
890         if (val & 2) {
891             DPRINTF("PHY write %d = 0x%04x\n",
892                     (val >> 6) & 0x1f, s->mac_mii_data);
893             do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
894         } else {
895             s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
896             DPRINTF("PHY read %d = 0x%04x\n",
897                     (val >> 6) & 0x1f, s->mac_mii_data);
898         }
899         break;
900     case MAC_MII_DATA:
901         s->mac_mii_data = val & 0xffff;
902         break;
903     case MAC_FLOW:
904         s->mac_flow = val & 0xffff0000;
905         break;
906     case MAC_VLAN1:
907         /* Writing to this register changes a condition for
908          * FrameTooLong bit in rx_status.  Since we do not set
909          * FrameTooLong anyway, just ignore write to this.
910          */
911         break;
912     default:
913         qemu_log_mask(LOG_GUEST_ERROR,
914                       "lan9118: Unimplemented MAC register write: %d = 0x%x\n",
915                  s->mac_cmd & 0xf, val);
916     }
917 }
918 
919 static uint32_t do_mac_read(lan9118_state *s, int reg)
920 {
921     switch (reg) {
922     case MAC_CR:
923         return s->mac_cr;
924     case MAC_ADDRH:
925         return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
926     case MAC_ADDRL:
927         return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
928                | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
929     case MAC_HASHH:
930         return s->mac_hashh;
931         break;
932     case MAC_HASHL:
933         return s->mac_hashl;
934         break;
935     case MAC_MII_ACC:
936         return s->mac_mii_acc;
937     case MAC_MII_DATA:
938         return s->mac_mii_data;
939     case MAC_FLOW:
940         return s->mac_flow;
941     default:
942         qemu_log_mask(LOG_GUEST_ERROR,
943                       "lan9118: Unimplemented MAC register read: %d\n",
944                  s->mac_cmd & 0xf);
945         return 0;
946     }
947 }
948 
949 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
950 {
951     s->e2p_cmd = (s->e2p_cmd & E2P_CMD_MAC_ADDR_LOADED) | (cmd << 28) | addr;
952     switch (cmd) {
953     case 0:
954         s->e2p_data = s->eeprom[addr];
955         DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
956         break;
957     case 1:
958         s->eeprom_writable = 0;
959         DPRINTF("EEPROM Write Disable\n");
960         break;
961     case 2: /* EWEN */
962         s->eeprom_writable = 1;
963         DPRINTF("EEPROM Write Enable\n");
964         break;
965     case 3: /* WRITE */
966         if (s->eeprom_writable) {
967             s->eeprom[addr] &= s->e2p_data;
968             DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
969         } else {
970             DPRINTF("EEPROM Write %d (ignored)\n", addr);
971         }
972         break;
973     case 4: /* WRAL */
974         if (s->eeprom_writable) {
975             for (addr = 0; addr < 128; addr++) {
976                 s->eeprom[addr] &= s->e2p_data;
977             }
978             DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
979         } else {
980             DPRINTF("EEPROM Write All (ignored)\n");
981         }
982         break;
983     case 5: /* ERASE */
984         if (s->eeprom_writable) {
985             s->eeprom[addr] = 0xff;
986             DPRINTF("EEPROM Erase %d\n", addr);
987         } else {
988             DPRINTF("EEPROM Erase %d (ignored)\n", addr);
989         }
990         break;
991     case 6: /* ERAL */
992         if (s->eeprom_writable) {
993             memset(s->eeprom, 0xff, 128);
994             DPRINTF("EEPROM Erase All\n");
995         } else {
996             DPRINTF("EEPROM Erase All (ignored)\n");
997         }
998         break;
999     case 7: /* RELOAD */
1000         lan9118_reload_eeprom(s);
1001         break;
1002     }
1003 }
1004 
1005 static void lan9118_tick(void *opaque)
1006 {
1007     lan9118_state *s = (lan9118_state *)opaque;
1008     if (s->int_en & GPT_INT) {
1009         s->int_sts |= GPT_INT;
1010     }
1011     lan9118_update(s);
1012 }
1013 
1014 static void lan9118_writel(void *opaque, hwaddr offset,
1015                            uint64_t val, unsigned size)
1016 {
1017     lan9118_state *s = (lan9118_state *)opaque;
1018     offset &= 0xff;
1019 
1020     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
1021     if (offset >= 0x20 && offset < 0x40) {
1022         /* TX FIFO */
1023         tx_fifo_push(s, val);
1024         return;
1025     }
1026     switch (offset) {
1027     case CSR_IRQ_CFG:
1028         /* TODO: Implement interrupt deassertion intervals.  */
1029         val &= (IRQ_EN | IRQ_POL | IRQ_TYPE);
1030         s->irq_cfg = (s->irq_cfg & IRQ_INT) | val;
1031         break;
1032     case CSR_INT_STS:
1033         s->int_sts &= ~val;
1034         break;
1035     case CSR_INT_EN:
1036         s->int_en = val & ~RESERVED_INT;
1037         s->int_sts |= val & SW_INT;
1038         break;
1039     case CSR_FIFO_INT:
1040         DPRINTF("FIFO INT levels %08x\n", val);
1041         s->fifo_int = val;
1042         break;
1043     case CSR_RX_CFG:
1044         if (val & 0x8000) {
1045             /* RX_DUMP */
1046             s->rx_fifo_used = 0;
1047             s->rx_status_fifo_used = 0;
1048             s->rx_packet_size_tail = s->rx_packet_size_head;
1049             s->rx_packet_size[s->rx_packet_size_head] = 0;
1050         }
1051         s->rx_cfg = val & 0xcfff1ff0;
1052         break;
1053     case CSR_TX_CFG:
1054         if (val & 0x8000) {
1055             s->tx_status_fifo_used = 0;
1056         }
1057         if (val & 0x4000) {
1058             s->txp->state = TX_IDLE;
1059             s->txp->fifo_used = 0;
1060             s->txp->cmd_a = 0xffffffff;
1061         }
1062         s->tx_cfg = val & 6;
1063         break;
1064     case CSR_HW_CFG:
1065         if (val & 1) {
1066             /* SRST */
1067             lan9118_reset(DEVICE(s));
1068         } else {
1069             s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4);
1070         }
1071         break;
1072     case CSR_RX_DP_CTRL:
1073         if (val & 0x80000000) {
1074             /* Skip forward to next packet.  */
1075             s->rxp_pad = 0;
1076             s->rxp_offset = 0;
1077             if (s->rxp_size == 0) {
1078                 /* Pop a word to start the next packet.  */
1079                 rx_fifo_pop(s);
1080                 s->rxp_pad = 0;
1081                 s->rxp_offset = 0;
1082             }
1083             s->rx_fifo_head += s->rxp_size;
1084             if (s->rx_fifo_head >= s->rx_fifo_size) {
1085                 s->rx_fifo_head -= s->rx_fifo_size;
1086             }
1087         }
1088         break;
1089     case CSR_PMT_CTRL:
1090         if (val & 0x400) {
1091             phy_reset(s);
1092         }
1093         s->pmt_ctrl &= ~0x34e;
1094         s->pmt_ctrl |= (val & 0x34e);
1095         break;
1096     case CSR_GPIO_CFG:
1097         /* Probably just enabling LEDs.  */
1098         s->gpio_cfg = val & 0x7777071f;
1099         break;
1100     case CSR_GPT_CFG:
1101         if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
1102             if (val & GPT_TIMER_EN) {
1103                 ptimer_set_count(s->timer, val & 0xffff);
1104                 ptimer_run(s->timer, 0);
1105             } else {
1106                 ptimer_stop(s->timer);
1107                 ptimer_set_count(s->timer, 0xffff);
1108             }
1109         }
1110         s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
1111         break;
1112     case CSR_WORD_SWAP:
1113         /* Ignored because we're in 32-bit mode.  */
1114         s->word_swap = val;
1115         break;
1116     case CSR_MAC_CSR_CMD:
1117         s->mac_cmd = val & 0x4000000f;
1118         if (val & 0x80000000) {
1119             if (val & 0x40000000) {
1120                 s->mac_data = do_mac_read(s, val & 0xf);
1121                 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
1122             } else {
1123                 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
1124                 do_mac_write(s, val & 0xf, s->mac_data);
1125             }
1126         }
1127         break;
1128     case CSR_MAC_CSR_DATA:
1129         s->mac_data = val;
1130         break;
1131     case CSR_AFC_CFG:
1132         s->afc_cfg = val & 0x00ffffff;
1133         break;
1134     case CSR_E2P_CMD:
1135         lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f);
1136         break;
1137     case CSR_E2P_DATA:
1138         s->e2p_data = val & 0xff;
1139         break;
1140 
1141     default:
1142         qemu_log_mask(LOG_GUEST_ERROR, "lan9118_write: Bad reg 0x%x = %x\n",
1143                       (int)offset, (int)val);
1144         break;
1145     }
1146     lan9118_update(s);
1147 }
1148 
1149 static void lan9118_writew(void *opaque, hwaddr offset,
1150                            uint32_t val)
1151 {
1152     lan9118_state *s = (lan9118_state *)opaque;
1153     offset &= 0xff;
1154 
1155     if (s->write_word_prev_offset != (offset & ~0x3)) {
1156         /* New offset, reset word counter */
1157         s->write_word_n = 0;
1158         s->write_word_prev_offset = offset & ~0x3;
1159     }
1160 
1161     if (offset & 0x2) {
1162         s->write_word_h = val;
1163     } else {
1164         s->write_word_l = val;
1165     }
1166 
1167     //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val);
1168     s->write_word_n++;
1169     if (s->write_word_n == 2) {
1170         s->write_word_n = 0;
1171         lan9118_writel(s, offset & ~3, s->write_word_l +
1172                 (s->write_word_h << 16), 4);
1173     }
1174 }
1175 
1176 static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
1177                                      uint64_t val, unsigned size)
1178 {
1179     switch (size) {
1180     case 2:
1181         lan9118_writew(opaque, offset, (uint32_t)val);
1182         return;
1183     case 4:
1184         lan9118_writel(opaque, offset, val, size);
1185         return;
1186     }
1187 
1188     hw_error("lan9118_write: Bad size 0x%x\n", size);
1189 }
1190 
1191 static uint64_t lan9118_readl(void *opaque, hwaddr offset,
1192                               unsigned size)
1193 {
1194     lan9118_state *s = (lan9118_state *)opaque;
1195 
1196     //DPRINTF("Read reg 0x%02x\n", (int)offset);
1197     if (offset < 0x20) {
1198         /* RX FIFO */
1199         return rx_fifo_pop(s);
1200     }
1201     switch (offset) {
1202     case 0x40:
1203         return rx_status_fifo_pop(s);
1204     case 0x44:
1205         return s->rx_status_fifo[s->tx_status_fifo_head];
1206     case 0x48:
1207         return tx_status_fifo_pop(s);
1208     case 0x4c:
1209         return s->tx_status_fifo[s->tx_status_fifo_head];
1210     case CSR_ID_REV:
1211         return 0x01180001;
1212     case CSR_IRQ_CFG:
1213         return s->irq_cfg;
1214     case CSR_INT_STS:
1215         return s->int_sts;
1216     case CSR_INT_EN:
1217         return s->int_en;
1218     case CSR_BYTE_TEST:
1219         return 0x87654321;
1220     case CSR_FIFO_INT:
1221         return s->fifo_int;
1222     case CSR_RX_CFG:
1223         return s->rx_cfg;
1224     case CSR_TX_CFG:
1225         return s->tx_cfg;
1226     case CSR_HW_CFG:
1227         return s->hw_cfg;
1228     case CSR_RX_DP_CTRL:
1229         return 0;
1230     case CSR_RX_FIFO_INF:
1231         return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
1232     case CSR_TX_FIFO_INF:
1233         return (s->tx_status_fifo_used << 16)
1234                | (s->tx_fifo_size - s->txp->fifo_used);
1235     case CSR_PMT_CTRL:
1236         return s->pmt_ctrl;
1237     case CSR_GPIO_CFG:
1238         return s->gpio_cfg;
1239     case CSR_GPT_CFG:
1240         return s->gpt_cfg;
1241     case CSR_GPT_CNT:
1242         return ptimer_get_count(s->timer);
1243     case CSR_WORD_SWAP:
1244         return s->word_swap;
1245     case CSR_FREE_RUN:
1246         return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40) - s->free_timer_start;
1247     case CSR_RX_DROP:
1248         /* TODO: Implement dropped frames counter.  */
1249         return 0;
1250     case CSR_MAC_CSR_CMD:
1251         return s->mac_cmd;
1252     case CSR_MAC_CSR_DATA:
1253         return s->mac_data;
1254     case CSR_AFC_CFG:
1255         return s->afc_cfg;
1256     case CSR_E2P_CMD:
1257         return s->e2p_cmd;
1258     case CSR_E2P_DATA:
1259         return s->e2p_data;
1260     }
1261     qemu_log_mask(LOG_GUEST_ERROR, "lan9118_read: Bad reg 0x%x\n", (int)offset);
1262     return 0;
1263 }
1264 
1265 static uint32_t lan9118_readw(void *opaque, hwaddr offset)
1266 {
1267     lan9118_state *s = (lan9118_state *)opaque;
1268     uint32_t val;
1269 
1270     if (s->read_word_prev_offset != (offset & ~0x3)) {
1271         /* New offset, reset word counter */
1272         s->read_word_n = 0;
1273         s->read_word_prev_offset = offset & ~0x3;
1274     }
1275 
1276     s->read_word_n++;
1277     if (s->read_word_n == 1) {
1278         s->read_long = lan9118_readl(s, offset & ~3, 4);
1279     } else {
1280         s->read_word_n = 0;
1281     }
1282 
1283     if (offset & 2) {
1284         val = s->read_long >> 16;
1285     } else {
1286         val = s->read_long & 0xFFFF;
1287     }
1288 
1289     //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val);
1290     return val;
1291 }
1292 
1293 static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
1294                                         unsigned size)
1295 {
1296     switch (size) {
1297     case 2:
1298         return lan9118_readw(opaque, offset);
1299     case 4:
1300         return lan9118_readl(opaque, offset, size);
1301     }
1302 
1303     hw_error("lan9118_read: Bad size 0x%x\n", size);
1304     return 0;
1305 }
1306 
1307 static const MemoryRegionOps lan9118_mem_ops = {
1308     .read = lan9118_readl,
1309     .write = lan9118_writel,
1310     .endianness = DEVICE_NATIVE_ENDIAN,
1311 };
1312 
1313 static const MemoryRegionOps lan9118_16bit_mem_ops = {
1314     .read = lan9118_16bit_mode_read,
1315     .write = lan9118_16bit_mode_write,
1316     .endianness = DEVICE_NATIVE_ENDIAN,
1317 };
1318 
1319 static NetClientInfo net_lan9118_info = {
1320     .type = NET_CLIENT_DRIVER_NIC,
1321     .size = sizeof(NICState),
1322     .receive = lan9118_receive,
1323     .link_status_changed = lan9118_set_link,
1324 };
1325 
1326 static void lan9118_realize(DeviceState *dev, Error **errp)
1327 {
1328     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1329     lan9118_state *s = LAN9118(dev);
1330     QEMUBH *bh;
1331     int i;
1332     const MemoryRegionOps *mem_ops =
1333             s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
1334 
1335     memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
1336                           "lan9118-mmio", 0x100);
1337     sysbus_init_mmio(sbd, &s->mmio);
1338     sysbus_init_irq(sbd, &s->irq);
1339     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1340 
1341     s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
1342                           object_get_typename(OBJECT(dev)), dev->id, s);
1343     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1344     s->eeprom[0] = 0xa5;
1345     for (i = 0; i < 6; i++) {
1346         s->eeprom[i + 1] = s->conf.macaddr.a[i];
1347     }
1348     s->pmt_ctrl = 1;
1349     s->txp = &s->tx_packet;
1350 
1351     bh = qemu_bh_new(lan9118_tick, s);
1352     s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
1353     ptimer_set_freq(s->timer, 10000);
1354     ptimer_set_limit(s->timer, 0xffff, 1);
1355 }
1356 
1357 static Property lan9118_properties[] = {
1358     DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1359     DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0),
1360     DEFINE_PROP_END_OF_LIST(),
1361 };
1362 
1363 static void lan9118_class_init(ObjectClass *klass, void *data)
1364 {
1365     DeviceClass *dc = DEVICE_CLASS(klass);
1366 
1367     dc->reset = lan9118_reset;
1368     dc->props = lan9118_properties;
1369     dc->vmsd = &vmstate_lan9118;
1370     dc->realize = lan9118_realize;
1371 }
1372 
1373 static const TypeInfo lan9118_info = {
1374     .name          = TYPE_LAN9118,
1375     .parent        = TYPE_SYS_BUS_DEVICE,
1376     .instance_size = sizeof(lan9118_state),
1377     .class_init    = lan9118_class_init,
1378 };
1379 
1380 static void lan9118_register_types(void)
1381 {
1382     type_register_static(&lan9118_info);
1383 }
1384 
1385 /* Legacy helper function.  Should go away when machine config files are
1386    implemented.  */
1387 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
1388 {
1389     DeviceState *dev;
1390     SysBusDevice *s;
1391 
1392     qemu_check_nic_model(nd, "lan9118");
1393     dev = qdev_create(NULL, TYPE_LAN9118);
1394     qdev_set_nic_properties(dev, nd);
1395     qdev_init_nofail(dev);
1396     s = SYS_BUS_DEVICE(dev);
1397     sysbus_mmio_map(s, 0, base);
1398     sysbus_connect_irq(s, 0, irq);
1399 }
1400 
1401 type_init(lan9118_register_types)
1402