1 /* 2 * i.MX Fast Ethernet Controller emulation. 3 * 4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> 5 * 6 * Based on Coldfire Fast Ethernet Controller emulation. 7 * 8 * Copyright (c) 2007 CodeSourcery. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #include "qemu/osdep.h" 25 #include "hw/net/imx_fec.h" 26 #include "sysemu/dma.h" 27 #include "qemu/log.h" 28 #include "net/checksum.h" 29 #include "net/eth.h" 30 31 /* For crc32 */ 32 #include <zlib.h> 33 34 #ifndef DEBUG_IMX_FEC 35 #define DEBUG_IMX_FEC 0 36 #endif 37 38 #define FEC_PRINTF(fmt, args...) \ 39 do { \ 40 if (DEBUG_IMX_FEC) { \ 41 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \ 42 __func__, ##args); \ 43 } \ 44 } while (0) 45 46 #ifndef DEBUG_IMX_PHY 47 #define DEBUG_IMX_PHY 0 48 #endif 49 50 #define PHY_PRINTF(fmt, args...) \ 51 do { \ 52 if (DEBUG_IMX_PHY) { \ 53 fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \ 54 __func__, ##args); \ 55 } \ 56 } while (0) 57 58 #define IMX_MAX_DESC 1024 59 60 static const char *imx_default_reg_name(IMXFECState *s, uint32_t index) 61 { 62 static char tmp[20]; 63 sprintf(tmp, "index %d", index); 64 return tmp; 65 } 66 67 static const char *imx_fec_reg_name(IMXFECState *s, uint32_t index) 68 { 69 switch (index) { 70 case ENET_FRBR: 71 return "FRBR"; 72 case ENET_FRSR: 73 return "FRSR"; 74 case ENET_MIIGSK_CFGR: 75 return "MIIGSK_CFGR"; 76 case ENET_MIIGSK_ENR: 77 return "MIIGSK_ENR"; 78 default: 79 return imx_default_reg_name(s, index); 80 } 81 } 82 83 static const char *imx_enet_reg_name(IMXFECState *s, uint32_t index) 84 { 85 switch (index) { 86 case ENET_RSFL: 87 return "RSFL"; 88 case ENET_RSEM: 89 return "RSEM"; 90 case ENET_RAEM: 91 return "RAEM"; 92 case ENET_RAFL: 93 return "RAFL"; 94 case ENET_TSEM: 95 return "TSEM"; 96 case ENET_TAEM: 97 return "TAEM"; 98 case ENET_TAFL: 99 return "TAFL"; 100 case ENET_TIPG: 101 return "TIPG"; 102 case ENET_FTRL: 103 return "FTRL"; 104 case ENET_TACC: 105 return "TACC"; 106 case ENET_RACC: 107 return "RACC"; 108 case ENET_ATCR: 109 return "ATCR"; 110 case ENET_ATVR: 111 return "ATVR"; 112 case ENET_ATOFF: 113 return "ATOFF"; 114 case ENET_ATPER: 115 return "ATPER"; 116 case ENET_ATCOR: 117 return "ATCOR"; 118 case ENET_ATINC: 119 return "ATINC"; 120 case ENET_ATSTMP: 121 return "ATSTMP"; 122 case ENET_TGSR: 123 return "TGSR"; 124 case ENET_TCSR0: 125 return "TCSR0"; 126 case ENET_TCCR0: 127 return "TCCR0"; 128 case ENET_TCSR1: 129 return "TCSR1"; 130 case ENET_TCCR1: 131 return "TCCR1"; 132 case ENET_TCSR2: 133 return "TCSR2"; 134 case ENET_TCCR2: 135 return "TCCR2"; 136 case ENET_TCSR3: 137 return "TCSR3"; 138 case ENET_TCCR3: 139 return "TCCR3"; 140 default: 141 return imx_default_reg_name(s, index); 142 } 143 } 144 145 static const char *imx_eth_reg_name(IMXFECState *s, uint32_t index) 146 { 147 switch (index) { 148 case ENET_EIR: 149 return "EIR"; 150 case ENET_EIMR: 151 return "EIMR"; 152 case ENET_RDAR: 153 return "RDAR"; 154 case ENET_TDAR: 155 return "TDAR"; 156 case ENET_ECR: 157 return "ECR"; 158 case ENET_MMFR: 159 return "MMFR"; 160 case ENET_MSCR: 161 return "MSCR"; 162 case ENET_MIBC: 163 return "MIBC"; 164 case ENET_RCR: 165 return "RCR"; 166 case ENET_TCR: 167 return "TCR"; 168 case ENET_PALR: 169 return "PALR"; 170 case ENET_PAUR: 171 return "PAUR"; 172 case ENET_OPD: 173 return "OPD"; 174 case ENET_IAUR: 175 return "IAUR"; 176 case ENET_IALR: 177 return "IALR"; 178 case ENET_GAUR: 179 return "GAUR"; 180 case ENET_GALR: 181 return "GALR"; 182 case ENET_TFWR: 183 return "TFWR"; 184 case ENET_RDSR: 185 return "RDSR"; 186 case ENET_TDSR: 187 return "TDSR"; 188 case ENET_MRBR: 189 return "MRBR"; 190 default: 191 if (s->is_fec) { 192 return imx_fec_reg_name(s, index); 193 } else { 194 return imx_enet_reg_name(s, index); 195 } 196 } 197 } 198 199 /* 200 * Versions of this device with more than one TX descriptor save the 201 * 2nd and 3rd descriptors in a subsection, to maintain migration 202 * compatibility with previous versions of the device that only 203 * supported a single descriptor. 204 */ 205 static bool imx_eth_is_multi_tx_ring(void *opaque) 206 { 207 IMXFECState *s = IMX_FEC(opaque); 208 209 return s->tx_ring_num > 1; 210 } 211 212 static const VMStateDescription vmstate_imx_eth_txdescs = { 213 .name = "imx.fec/txdescs", 214 .version_id = 1, 215 .minimum_version_id = 1, 216 .needed = imx_eth_is_multi_tx_ring, 217 .fields = (VMStateField[]) { 218 VMSTATE_UINT32(tx_descriptor[1], IMXFECState), 219 VMSTATE_UINT32(tx_descriptor[2], IMXFECState), 220 VMSTATE_END_OF_LIST() 221 } 222 }; 223 224 static const VMStateDescription vmstate_imx_eth = { 225 .name = TYPE_IMX_FEC, 226 .version_id = 2, 227 .minimum_version_id = 2, 228 .fields = (VMStateField[]) { 229 VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), 230 VMSTATE_UINT32(rx_descriptor, IMXFECState), 231 VMSTATE_UINT32(tx_descriptor[0], IMXFECState), 232 VMSTATE_UINT32(phy_status, IMXFECState), 233 VMSTATE_UINT32(phy_control, IMXFECState), 234 VMSTATE_UINT32(phy_advertise, IMXFECState), 235 VMSTATE_UINT32(phy_int, IMXFECState), 236 VMSTATE_UINT32(phy_int_mask, IMXFECState), 237 VMSTATE_END_OF_LIST() 238 }, 239 .subsections = (const VMStateDescription * []) { 240 &vmstate_imx_eth_txdescs, 241 NULL 242 }, 243 }; 244 245 #define PHY_INT_ENERGYON (1 << 7) 246 #define PHY_INT_AUTONEG_COMPLETE (1 << 6) 247 #define PHY_INT_FAULT (1 << 5) 248 #define PHY_INT_DOWN (1 << 4) 249 #define PHY_INT_AUTONEG_LP (1 << 3) 250 #define PHY_INT_PARFAULT (1 << 2) 251 #define PHY_INT_AUTONEG_PAGE (1 << 1) 252 253 static void imx_eth_update(IMXFECState *s); 254 255 /* 256 * The MII phy could raise a GPIO to the processor which in turn 257 * could be handled as an interrpt by the OS. 258 * For now we don't handle any GPIO/interrupt line, so the OS will 259 * have to poll for the PHY status. 260 */ 261 static void phy_update_irq(IMXFECState *s) 262 { 263 imx_eth_update(s); 264 } 265 266 static void phy_update_link(IMXFECState *s) 267 { 268 /* Autonegotiation status mirrors link status. */ 269 if (qemu_get_queue(s->nic)->link_down) { 270 PHY_PRINTF("link is down\n"); 271 s->phy_status &= ~0x0024; 272 s->phy_int |= PHY_INT_DOWN; 273 } else { 274 PHY_PRINTF("link is up\n"); 275 s->phy_status |= 0x0024; 276 s->phy_int |= PHY_INT_ENERGYON; 277 s->phy_int |= PHY_INT_AUTONEG_COMPLETE; 278 } 279 phy_update_irq(s); 280 } 281 282 static void imx_eth_set_link(NetClientState *nc) 283 { 284 phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); 285 } 286 287 static void phy_reset(IMXFECState *s) 288 { 289 s->phy_status = 0x7809; 290 s->phy_control = 0x3000; 291 s->phy_advertise = 0x01e1; 292 s->phy_int_mask = 0; 293 s->phy_int = 0; 294 phy_update_link(s); 295 } 296 297 static uint32_t do_phy_read(IMXFECState *s, int reg) 298 { 299 uint32_t val; 300 301 if (reg > 31) { 302 /* we only advertise one phy */ 303 return 0; 304 } 305 306 switch (reg) { 307 case 0: /* Basic Control */ 308 val = s->phy_control; 309 break; 310 case 1: /* Basic Status */ 311 val = s->phy_status; 312 break; 313 case 2: /* ID1 */ 314 val = 0x0007; 315 break; 316 case 3: /* ID2 */ 317 val = 0xc0d1; 318 break; 319 case 4: /* Auto-neg advertisement */ 320 val = s->phy_advertise; 321 break; 322 case 5: /* Auto-neg Link Partner Ability */ 323 val = 0x0f71; 324 break; 325 case 6: /* Auto-neg Expansion */ 326 val = 1; 327 break; 328 case 29: /* Interrupt source. */ 329 val = s->phy_int; 330 s->phy_int = 0; 331 phy_update_irq(s); 332 break; 333 case 30: /* Interrupt mask */ 334 val = s->phy_int_mask; 335 break; 336 case 17: 337 case 18: 338 case 27: 339 case 31: 340 qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", 341 TYPE_IMX_FEC, __func__, reg); 342 val = 0; 343 break; 344 default: 345 qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", 346 TYPE_IMX_FEC, __func__, reg); 347 val = 0; 348 break; 349 } 350 351 PHY_PRINTF("read 0x%04x @ %d\n", val, reg); 352 353 return val; 354 } 355 356 static void do_phy_write(IMXFECState *s, int reg, uint32_t val) 357 { 358 PHY_PRINTF("write 0x%04x @ %d\n", val, reg); 359 360 if (reg > 31) { 361 /* we only advertise one phy */ 362 return; 363 } 364 365 switch (reg) { 366 case 0: /* Basic Control */ 367 if (val & 0x8000) { 368 phy_reset(s); 369 } else { 370 s->phy_control = val & 0x7980; 371 /* Complete autonegotiation immediately. */ 372 if (val & 0x1000) { 373 s->phy_status |= 0x0020; 374 } 375 } 376 break; 377 case 4: /* Auto-neg advertisement */ 378 s->phy_advertise = (val & 0x2d7f) | 0x80; 379 break; 380 case 30: /* Interrupt mask */ 381 s->phy_int_mask = val & 0xff; 382 phy_update_irq(s); 383 break; 384 case 17: 385 case 18: 386 case 27: 387 case 31: 388 qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", 389 TYPE_IMX_FEC, __func__, reg); 390 break; 391 default: 392 qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", 393 TYPE_IMX_FEC, __func__, reg); 394 break; 395 } 396 } 397 398 static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) 399 { 400 dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); 401 } 402 403 static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr) 404 { 405 dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); 406 } 407 408 static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr) 409 { 410 dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); 411 } 412 413 static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) 414 { 415 dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); 416 } 417 418 static void imx_eth_update(IMXFECState *s) 419 { 420 if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_TS_TIMER) { 421 qemu_set_irq(s->irq[1], 1); 422 } else { 423 qemu_set_irq(s->irq[1], 0); 424 } 425 426 if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_MAC) { 427 qemu_set_irq(s->irq[0], 1); 428 } else { 429 qemu_set_irq(s->irq[0], 0); 430 } 431 } 432 433 static void imx_fec_do_tx(IMXFECState *s) 434 { 435 int frame_size = 0, descnt = 0; 436 uint8_t *ptr = s->frame; 437 uint32_t addr = s->tx_descriptor[0]; 438 439 while (descnt++ < IMX_MAX_DESC) { 440 IMXFECBufDesc bd; 441 int len; 442 443 imx_fec_read_bd(&bd, addr); 444 FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n", 445 addr, bd.flags, bd.length, bd.data); 446 if ((bd.flags & ENET_BD_R) == 0) { 447 /* Run out of descriptors to transmit. */ 448 FEC_PRINTF("tx_bd ran out of descriptors to transmit\n"); 449 break; 450 } 451 len = bd.length; 452 if (frame_size + len > ENET_MAX_FRAME_SIZE) { 453 len = ENET_MAX_FRAME_SIZE - frame_size; 454 s->regs[ENET_EIR] |= ENET_INT_BABT; 455 } 456 dma_memory_read(&address_space_memory, bd.data, ptr, len); 457 ptr += len; 458 frame_size += len; 459 if (bd.flags & ENET_BD_L) { 460 /* Last buffer in frame. */ 461 qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size); 462 ptr = s->frame; 463 frame_size = 0; 464 s->regs[ENET_EIR] |= ENET_INT_TXF; 465 } 466 s->regs[ENET_EIR] |= ENET_INT_TXB; 467 bd.flags &= ~ENET_BD_R; 468 /* Write back the modified descriptor. */ 469 imx_fec_write_bd(&bd, addr); 470 /* Advance to the next descriptor. */ 471 if ((bd.flags & ENET_BD_W) != 0) { 472 addr = s->regs[ENET_TDSR]; 473 } else { 474 addr += sizeof(bd); 475 } 476 } 477 478 s->tx_descriptor[0] = addr; 479 480 imx_eth_update(s); 481 } 482 483 static void imx_enet_do_tx(IMXFECState *s, uint32_t index) 484 { 485 int frame_size = 0, descnt = 0; 486 487 uint8_t *ptr = s->frame; 488 uint32_t addr, int_txb, int_txf, tdsr; 489 size_t ring; 490 491 switch (index) { 492 case ENET_TDAR: 493 ring = 0; 494 int_txb = ENET_INT_TXB; 495 int_txf = ENET_INT_TXF; 496 tdsr = ENET_TDSR; 497 break; 498 case ENET_TDAR1: 499 ring = 1; 500 int_txb = ENET_INT_TXB1; 501 int_txf = ENET_INT_TXF1; 502 tdsr = ENET_TDSR1; 503 break; 504 case ENET_TDAR2: 505 ring = 2; 506 int_txb = ENET_INT_TXB2; 507 int_txf = ENET_INT_TXF2; 508 tdsr = ENET_TDSR2; 509 break; 510 default: 511 qemu_log_mask(LOG_GUEST_ERROR, 512 "%s: bogus value for index %x\n", 513 __func__, index); 514 abort(); 515 break; 516 } 517 518 addr = s->tx_descriptor[ring]; 519 520 while (descnt++ < IMX_MAX_DESC) { 521 IMXENETBufDesc bd; 522 int len; 523 524 imx_enet_read_bd(&bd, addr); 525 FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x " 526 "status %04x\n", addr, bd.flags, bd.length, bd.data, 527 bd.option, bd.status); 528 if ((bd.flags & ENET_BD_R) == 0) { 529 /* Run out of descriptors to transmit. */ 530 break; 531 } 532 len = bd.length; 533 if (frame_size + len > ENET_MAX_FRAME_SIZE) { 534 len = ENET_MAX_FRAME_SIZE - frame_size; 535 s->regs[ENET_EIR] |= ENET_INT_BABT; 536 } 537 dma_memory_read(&address_space_memory, bd.data, ptr, len); 538 ptr += len; 539 frame_size += len; 540 if (bd.flags & ENET_BD_L) { 541 if (bd.option & ENET_BD_PINS) { 542 struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame); 543 if (IP_HEADER_VERSION(ip_hd) == 4) { 544 net_checksum_calculate(s->frame, frame_size); 545 } 546 } 547 if (bd.option & ENET_BD_IINS) { 548 struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame); 549 /* We compute checksum only for IPv4 frames */ 550 if (IP_HEADER_VERSION(ip_hd) == 4) { 551 uint16_t csum; 552 ip_hd->ip_sum = 0; 553 csum = net_raw_checksum((uint8_t *)ip_hd, sizeof(*ip_hd)); 554 ip_hd->ip_sum = cpu_to_be16(csum); 555 } 556 } 557 /* Last buffer in frame. */ 558 559 qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size); 560 ptr = s->frame; 561 562 frame_size = 0; 563 if (bd.option & ENET_BD_TX_INT) { 564 s->regs[ENET_EIR] |= int_txf; 565 } 566 } 567 if (bd.option & ENET_BD_TX_INT) { 568 s->regs[ENET_EIR] |= int_txb; 569 } 570 bd.flags &= ~ENET_BD_R; 571 /* Write back the modified descriptor. */ 572 imx_enet_write_bd(&bd, addr); 573 /* Advance to the next descriptor. */ 574 if ((bd.flags & ENET_BD_W) != 0) { 575 addr = s->regs[tdsr]; 576 } else { 577 addr += sizeof(bd); 578 } 579 } 580 581 s->tx_descriptor[ring] = addr; 582 583 imx_eth_update(s); 584 } 585 586 static void imx_eth_do_tx(IMXFECState *s, uint32_t index) 587 { 588 if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) { 589 imx_enet_do_tx(s, index); 590 } else { 591 imx_fec_do_tx(s); 592 } 593 } 594 595 static void imx_eth_enable_rx(IMXFECState *s, bool flush) 596 { 597 IMXFECBufDesc bd; 598 599 imx_fec_read_bd(&bd, s->rx_descriptor); 600 601 s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0; 602 603 if (!s->regs[ENET_RDAR]) { 604 FEC_PRINTF("RX buffer full\n"); 605 } else if (flush) { 606 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 607 } 608 } 609 610 static void imx_eth_reset(DeviceState *d) 611 { 612 IMXFECState *s = IMX_FEC(d); 613 614 /* Reset the Device */ 615 memset(s->regs, 0, sizeof(s->regs)); 616 s->regs[ENET_ECR] = 0xf0000000; 617 s->regs[ENET_MIBC] = 0xc0000000; 618 s->regs[ENET_RCR] = 0x05ee0001; 619 s->regs[ENET_OPD] = 0x00010000; 620 621 s->regs[ENET_PALR] = (s->conf.macaddr.a[0] << 24) 622 | (s->conf.macaddr.a[1] << 16) 623 | (s->conf.macaddr.a[2] << 8) 624 | s->conf.macaddr.a[3]; 625 s->regs[ENET_PAUR] = (s->conf.macaddr.a[4] << 24) 626 | (s->conf.macaddr.a[5] << 16) 627 | 0x8808; 628 629 if (s->is_fec) { 630 s->regs[ENET_FRBR] = 0x00000600; 631 s->regs[ENET_FRSR] = 0x00000500; 632 s->regs[ENET_MIIGSK_ENR] = 0x00000006; 633 } else { 634 s->regs[ENET_RAEM] = 0x00000004; 635 s->regs[ENET_RAFL] = 0x00000004; 636 s->regs[ENET_TAEM] = 0x00000004; 637 s->regs[ENET_TAFL] = 0x00000008; 638 s->regs[ENET_TIPG] = 0x0000000c; 639 s->regs[ENET_FTRL] = 0x000007ff; 640 s->regs[ENET_ATPER] = 0x3b9aca00; 641 } 642 643 s->rx_descriptor = 0; 644 memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); 645 646 /* We also reset the PHY */ 647 phy_reset(s); 648 } 649 650 static uint32_t imx_default_read(IMXFECState *s, uint32_t index) 651 { 652 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 653 PRIx32 "\n", TYPE_IMX_FEC, __func__, index * 4); 654 return 0; 655 } 656 657 static uint32_t imx_fec_read(IMXFECState *s, uint32_t index) 658 { 659 switch (index) { 660 case ENET_FRBR: 661 case ENET_FRSR: 662 case ENET_MIIGSK_CFGR: 663 case ENET_MIIGSK_ENR: 664 return s->regs[index]; 665 default: 666 return imx_default_read(s, index); 667 } 668 } 669 670 static uint32_t imx_enet_read(IMXFECState *s, uint32_t index) 671 { 672 switch (index) { 673 case ENET_RSFL: 674 case ENET_RSEM: 675 case ENET_RAEM: 676 case ENET_RAFL: 677 case ENET_TSEM: 678 case ENET_TAEM: 679 case ENET_TAFL: 680 case ENET_TIPG: 681 case ENET_FTRL: 682 case ENET_TACC: 683 case ENET_RACC: 684 case ENET_ATCR: 685 case ENET_ATVR: 686 case ENET_ATOFF: 687 case ENET_ATPER: 688 case ENET_ATCOR: 689 case ENET_ATINC: 690 case ENET_ATSTMP: 691 case ENET_TGSR: 692 case ENET_TCSR0: 693 case ENET_TCCR0: 694 case ENET_TCSR1: 695 case ENET_TCCR1: 696 case ENET_TCSR2: 697 case ENET_TCCR2: 698 case ENET_TCSR3: 699 case ENET_TCCR3: 700 return s->regs[index]; 701 default: 702 return imx_default_read(s, index); 703 } 704 } 705 706 static uint64_t imx_eth_read(void *opaque, hwaddr offset, unsigned size) 707 { 708 uint32_t value = 0; 709 IMXFECState *s = IMX_FEC(opaque); 710 uint32_t index = offset >> 2; 711 712 switch (index) { 713 case ENET_EIR: 714 case ENET_EIMR: 715 case ENET_RDAR: 716 case ENET_TDAR: 717 case ENET_ECR: 718 case ENET_MMFR: 719 case ENET_MSCR: 720 case ENET_MIBC: 721 case ENET_RCR: 722 case ENET_TCR: 723 case ENET_PALR: 724 case ENET_PAUR: 725 case ENET_OPD: 726 case ENET_IAUR: 727 case ENET_IALR: 728 case ENET_GAUR: 729 case ENET_GALR: 730 case ENET_TFWR: 731 case ENET_RDSR: 732 case ENET_TDSR: 733 case ENET_MRBR: 734 value = s->regs[index]; 735 break; 736 default: 737 if (s->is_fec) { 738 value = imx_fec_read(s, index); 739 } else { 740 value = imx_enet_read(s, index); 741 } 742 break; 743 } 744 745 FEC_PRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), 746 value); 747 748 return value; 749 } 750 751 static void imx_default_write(IMXFECState *s, uint32_t index, uint32_t value) 752 { 753 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" 754 PRIx32 "\n", TYPE_IMX_FEC, __func__, index * 4); 755 return; 756 } 757 758 static void imx_fec_write(IMXFECState *s, uint32_t index, uint32_t value) 759 { 760 switch (index) { 761 case ENET_FRBR: 762 /* FRBR is read only */ 763 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Register FRBR is read only\n", 764 TYPE_IMX_FEC, __func__); 765 break; 766 case ENET_FRSR: 767 s->regs[index] = (value & 0x000003fc) | 0x00000400; 768 break; 769 case ENET_MIIGSK_CFGR: 770 s->regs[index] = value & 0x00000053; 771 break; 772 case ENET_MIIGSK_ENR: 773 s->regs[index] = (value & 0x00000002) ? 0x00000006 : 0; 774 break; 775 default: 776 imx_default_write(s, index, value); 777 break; 778 } 779 } 780 781 static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value) 782 { 783 switch (index) { 784 case ENET_RSFL: 785 case ENET_RSEM: 786 case ENET_RAEM: 787 case ENET_RAFL: 788 case ENET_TSEM: 789 case ENET_TAEM: 790 case ENET_TAFL: 791 s->regs[index] = value & 0x000001ff; 792 break; 793 case ENET_TIPG: 794 s->regs[index] = value & 0x0000001f; 795 break; 796 case ENET_FTRL: 797 s->regs[index] = value & 0x00003fff; 798 break; 799 case ENET_TACC: 800 s->regs[index] = value & 0x00000019; 801 break; 802 case ENET_RACC: 803 s->regs[index] = value & 0x000000C7; 804 break; 805 case ENET_ATCR: 806 s->regs[index] = value & 0x00002a9d; 807 break; 808 case ENET_ATVR: 809 case ENET_ATOFF: 810 case ENET_ATPER: 811 s->regs[index] = value; 812 break; 813 case ENET_ATSTMP: 814 /* ATSTMP is read only */ 815 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Register ATSTMP is read only\n", 816 TYPE_IMX_FEC, __func__); 817 break; 818 case ENET_ATCOR: 819 s->regs[index] = value & 0x7fffffff; 820 break; 821 case ENET_ATINC: 822 s->regs[index] = value & 0x00007f7f; 823 break; 824 case ENET_TGSR: 825 /* implement clear timer flag */ 826 value = value & 0x0000000f; 827 break; 828 case ENET_TCSR0: 829 case ENET_TCSR1: 830 case ENET_TCSR2: 831 case ENET_TCSR3: 832 value = value & 0x000000fd; 833 break; 834 case ENET_TCCR0: 835 case ENET_TCCR1: 836 case ENET_TCCR2: 837 case ENET_TCCR3: 838 s->regs[index] = value; 839 break; 840 default: 841 imx_default_write(s, index, value); 842 break; 843 } 844 } 845 846 static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, 847 unsigned size) 848 { 849 IMXFECState *s = IMX_FEC(opaque); 850 const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s); 851 uint32_t index = offset >> 2; 852 853 FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), 854 (uint32_t)value); 855 856 switch (index) { 857 case ENET_EIR: 858 s->regs[index] &= ~value; 859 break; 860 case ENET_EIMR: 861 s->regs[index] = value; 862 break; 863 case ENET_RDAR: 864 if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { 865 if (!s->regs[index]) { 866 imx_eth_enable_rx(s, true); 867 } 868 } else { 869 s->regs[index] = 0; 870 } 871 break; 872 case ENET_TDAR1: /* FALLTHROUGH */ 873 case ENET_TDAR2: /* FALLTHROUGH */ 874 if (unlikely(single_tx_ring)) { 875 qemu_log_mask(LOG_GUEST_ERROR, 876 "[%s]%s: trying to access TDAR2 or TDAR1\n", 877 TYPE_IMX_FEC, __func__); 878 return; 879 } 880 case ENET_TDAR: /* FALLTHROUGH */ 881 if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { 882 s->regs[index] = ENET_TDAR_TDAR; 883 imx_eth_do_tx(s, index); 884 } 885 s->regs[index] = 0; 886 break; 887 case ENET_ECR: 888 if (value & ENET_ECR_RESET) { 889 return imx_eth_reset(DEVICE(s)); 890 } 891 s->regs[index] = value; 892 if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) { 893 s->regs[ENET_RDAR] = 0; 894 s->rx_descriptor = s->regs[ENET_RDSR]; 895 s->regs[ENET_TDAR] = 0; 896 s->regs[ENET_TDAR1] = 0; 897 s->regs[ENET_TDAR2] = 0; 898 s->tx_descriptor[0] = s->regs[ENET_TDSR]; 899 s->tx_descriptor[1] = s->regs[ENET_TDSR1]; 900 s->tx_descriptor[2] = s->regs[ENET_TDSR2]; 901 } 902 break; 903 case ENET_MMFR: 904 s->regs[index] = value; 905 if (extract32(value, 29, 1)) { 906 /* This is a read operation */ 907 s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16, 908 do_phy_read(s, 909 extract32(value, 910 18, 10))); 911 } else { 912 /* This a write operation */ 913 do_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); 914 } 915 /* raise the interrupt as the PHY operation is done */ 916 s->regs[ENET_EIR] |= ENET_INT_MII; 917 break; 918 case ENET_MSCR: 919 s->regs[index] = value & 0xfe; 920 break; 921 case ENET_MIBC: 922 /* TODO: Implement MIB. */ 923 s->regs[index] = (value & 0x80000000) ? 0xc0000000 : 0; 924 break; 925 case ENET_RCR: 926 s->regs[index] = value & 0x07ff003f; 927 /* TODO: Implement LOOP mode. */ 928 break; 929 case ENET_TCR: 930 /* We transmit immediately, so raise GRA immediately. */ 931 s->regs[index] = value; 932 if (value & 1) { 933 s->regs[ENET_EIR] |= ENET_INT_GRA; 934 } 935 break; 936 case ENET_PALR: 937 s->regs[index] = value; 938 s->conf.macaddr.a[0] = value >> 24; 939 s->conf.macaddr.a[1] = value >> 16; 940 s->conf.macaddr.a[2] = value >> 8; 941 s->conf.macaddr.a[3] = value; 942 break; 943 case ENET_PAUR: 944 s->regs[index] = (value | 0x0000ffff) & 0xffff8808; 945 s->conf.macaddr.a[4] = value >> 24; 946 s->conf.macaddr.a[5] = value >> 16; 947 break; 948 case ENET_OPD: 949 s->regs[index] = (value & 0x0000ffff) | 0x00010000; 950 break; 951 case ENET_IAUR: 952 case ENET_IALR: 953 case ENET_GAUR: 954 case ENET_GALR: 955 /* TODO: implement MAC hash filtering. */ 956 break; 957 case ENET_TFWR: 958 if (s->is_fec) { 959 s->regs[index] = value & 0x3; 960 } else { 961 s->regs[index] = value & 0x13f; 962 } 963 break; 964 case ENET_RDSR: 965 if (s->is_fec) { 966 s->regs[index] = value & ~3; 967 } else { 968 s->regs[index] = value & ~7; 969 } 970 s->rx_descriptor = s->regs[index]; 971 break; 972 case ENET_TDSR: 973 if (s->is_fec) { 974 s->regs[index] = value & ~3; 975 } else { 976 s->regs[index] = value & ~7; 977 } 978 s->tx_descriptor[0] = s->regs[index]; 979 break; 980 case ENET_TDSR1: 981 if (unlikely(single_tx_ring)) { 982 qemu_log_mask(LOG_GUEST_ERROR, 983 "[%s]%s: trying to access TDSR1\n", 984 TYPE_IMX_FEC, __func__); 985 return; 986 } 987 988 s->regs[index] = value & ~7; 989 s->tx_descriptor[1] = s->regs[index]; 990 break; 991 case ENET_TDSR2: 992 if (unlikely(single_tx_ring)) { 993 qemu_log_mask(LOG_GUEST_ERROR, 994 "[%s]%s: trying to access TDSR2\n", 995 TYPE_IMX_FEC, __func__); 996 return; 997 } 998 999 s->regs[index] = value & ~7; 1000 s->tx_descriptor[2] = s->regs[index]; 1001 break; 1002 case ENET_MRBR: 1003 s->regs[index] = value & 0x00003ff0; 1004 break; 1005 default: 1006 if (s->is_fec) { 1007 imx_fec_write(s, index, value); 1008 } else { 1009 imx_enet_write(s, index, value); 1010 } 1011 return; 1012 } 1013 1014 imx_eth_update(s); 1015 } 1016 1017 static int imx_eth_can_receive(NetClientState *nc) 1018 { 1019 IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1020 1021 FEC_PRINTF("\n"); 1022 1023 return !!s->regs[ENET_RDAR]; 1024 } 1025 1026 static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, 1027 size_t len) 1028 { 1029 IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1030 IMXFECBufDesc bd; 1031 uint32_t flags = 0; 1032 uint32_t addr; 1033 uint32_t crc; 1034 uint32_t buf_addr; 1035 uint8_t *crc_ptr; 1036 unsigned int buf_len; 1037 size_t size = len; 1038 1039 FEC_PRINTF("len %d\n", (int)size); 1040 1041 if (!s->regs[ENET_RDAR]) { 1042 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", 1043 TYPE_IMX_FEC, __func__); 1044 return 0; 1045 } 1046 1047 /* 4 bytes for the CRC. */ 1048 size += 4; 1049 crc = cpu_to_be32(crc32(~0, buf, size)); 1050 crc_ptr = (uint8_t *) &crc; 1051 1052 /* Huge frames are truncated. */ 1053 if (size > ENET_MAX_FRAME_SIZE) { 1054 size = ENET_MAX_FRAME_SIZE; 1055 flags |= ENET_BD_TR | ENET_BD_LG; 1056 } 1057 1058 /* Frames larger than the user limit just set error flags. */ 1059 if (size > (s->regs[ENET_RCR] >> 16)) { 1060 flags |= ENET_BD_LG; 1061 } 1062 1063 addr = s->rx_descriptor; 1064 while (size > 0) { 1065 imx_fec_read_bd(&bd, addr); 1066 if ((bd.flags & ENET_BD_E) == 0) { 1067 /* No descriptors available. Bail out. */ 1068 /* 1069 * FIXME: This is wrong. We should probably either 1070 * save the remainder for when more RX buffers are 1071 * available, or flag an error. 1072 */ 1073 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Lost end of frame\n", 1074 TYPE_IMX_FEC, __func__); 1075 break; 1076 } 1077 buf_len = (size <= s->regs[ENET_MRBR]) ? size : s->regs[ENET_MRBR]; 1078 bd.length = buf_len; 1079 size -= buf_len; 1080 1081 FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); 1082 1083 /* The last 4 bytes are the CRC. */ 1084 if (size < 4) { 1085 buf_len += size - 4; 1086 } 1087 buf_addr = bd.data; 1088 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); 1089 buf += buf_len; 1090 if (size < 4) { 1091 dma_memory_write(&address_space_memory, buf_addr + buf_len, 1092 crc_ptr, 4 - size); 1093 crc_ptr += 4 - size; 1094 } 1095 bd.flags &= ~ENET_BD_E; 1096 if (size == 0) { 1097 /* Last buffer in frame. */ 1098 bd.flags |= flags | ENET_BD_L; 1099 FEC_PRINTF("rx frame flags %04x\n", bd.flags); 1100 s->regs[ENET_EIR] |= ENET_INT_RXF; 1101 } else { 1102 s->regs[ENET_EIR] |= ENET_INT_RXB; 1103 } 1104 imx_fec_write_bd(&bd, addr); 1105 /* Advance to the next descriptor. */ 1106 if ((bd.flags & ENET_BD_W) != 0) { 1107 addr = s->regs[ENET_RDSR]; 1108 } else { 1109 addr += sizeof(bd); 1110 } 1111 } 1112 s->rx_descriptor = addr; 1113 imx_eth_enable_rx(s, false); 1114 imx_eth_update(s); 1115 return len; 1116 } 1117 1118 static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, 1119 size_t len) 1120 { 1121 IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1122 IMXENETBufDesc bd; 1123 uint32_t flags = 0; 1124 uint32_t addr; 1125 uint32_t crc; 1126 uint32_t buf_addr; 1127 uint8_t *crc_ptr; 1128 unsigned int buf_len; 1129 size_t size = len; 1130 bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; 1131 1132 FEC_PRINTF("len %d\n", (int)size); 1133 1134 if (!s->regs[ENET_RDAR]) { 1135 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", 1136 TYPE_IMX_FEC, __func__); 1137 return 0; 1138 } 1139 1140 /* 4 bytes for the CRC. */ 1141 size += 4; 1142 crc = cpu_to_be32(crc32(~0, buf, size)); 1143 crc_ptr = (uint8_t *) &crc; 1144 1145 if (shift16) { 1146 size += 2; 1147 } 1148 1149 /* Huge frames are truncated. */ 1150 if (size > s->regs[ENET_FTRL]) { 1151 size = s->regs[ENET_FTRL]; 1152 flags |= ENET_BD_TR | ENET_BD_LG; 1153 } 1154 1155 /* Frames larger than the user limit just set error flags. */ 1156 if (size > (s->regs[ENET_RCR] >> 16)) { 1157 flags |= ENET_BD_LG; 1158 } 1159 1160 addr = s->rx_descriptor; 1161 while (size > 0) { 1162 imx_enet_read_bd(&bd, addr); 1163 if ((bd.flags & ENET_BD_E) == 0) { 1164 /* No descriptors available. Bail out. */ 1165 /* 1166 * FIXME: This is wrong. We should probably either 1167 * save the remainder for when more RX buffers are 1168 * available, or flag an error. 1169 */ 1170 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Lost end of frame\n", 1171 TYPE_IMX_FEC, __func__); 1172 break; 1173 } 1174 buf_len = MIN(size, s->regs[ENET_MRBR]); 1175 bd.length = buf_len; 1176 size -= buf_len; 1177 1178 FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); 1179 1180 /* The last 4 bytes are the CRC. */ 1181 if (size < 4) { 1182 buf_len += size - 4; 1183 } 1184 buf_addr = bd.data; 1185 1186 if (shift16) { 1187 /* 1188 * If SHIFT16 bit of ENETx_RACC register is set we need to 1189 * align the payload to 4-byte boundary. 1190 */ 1191 const uint8_t zeros[2] = { 0 }; 1192 1193 dma_memory_write(&address_space_memory, buf_addr, 1194 zeros, sizeof(zeros)); 1195 1196 buf_addr += sizeof(zeros); 1197 buf_len -= sizeof(zeros); 1198 1199 /* We only do this once per Ethernet frame */ 1200 shift16 = false; 1201 } 1202 1203 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); 1204 buf += buf_len; 1205 if (size < 4) { 1206 dma_memory_write(&address_space_memory, buf_addr + buf_len, 1207 crc_ptr, 4 - size); 1208 crc_ptr += 4 - size; 1209 } 1210 bd.flags &= ~ENET_BD_E; 1211 if (size == 0) { 1212 /* Last buffer in frame. */ 1213 bd.flags |= flags | ENET_BD_L; 1214 FEC_PRINTF("rx frame flags %04x\n", bd.flags); 1215 if (bd.option & ENET_BD_RX_INT) { 1216 s->regs[ENET_EIR] |= ENET_INT_RXF; 1217 } 1218 } else { 1219 if (bd.option & ENET_BD_RX_INT) { 1220 s->regs[ENET_EIR] |= ENET_INT_RXB; 1221 } 1222 } 1223 imx_enet_write_bd(&bd, addr); 1224 /* Advance to the next descriptor. */ 1225 if ((bd.flags & ENET_BD_W) != 0) { 1226 addr = s->regs[ENET_RDSR]; 1227 } else { 1228 addr += sizeof(bd); 1229 } 1230 } 1231 s->rx_descriptor = addr; 1232 imx_eth_enable_rx(s, false); 1233 imx_eth_update(s); 1234 return len; 1235 } 1236 1237 static ssize_t imx_eth_receive(NetClientState *nc, const uint8_t *buf, 1238 size_t len) 1239 { 1240 IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1241 1242 if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) { 1243 return imx_enet_receive(nc, buf, len); 1244 } else { 1245 return imx_fec_receive(nc, buf, len); 1246 } 1247 } 1248 1249 static const MemoryRegionOps imx_eth_ops = { 1250 .read = imx_eth_read, 1251 .write = imx_eth_write, 1252 .valid.min_access_size = 4, 1253 .valid.max_access_size = 4, 1254 .endianness = DEVICE_NATIVE_ENDIAN, 1255 }; 1256 1257 static void imx_eth_cleanup(NetClientState *nc) 1258 { 1259 IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1260 1261 s->nic = NULL; 1262 } 1263 1264 static NetClientInfo imx_eth_net_info = { 1265 .type = NET_CLIENT_DRIVER_NIC, 1266 .size = sizeof(NICState), 1267 .can_receive = imx_eth_can_receive, 1268 .receive = imx_eth_receive, 1269 .cleanup = imx_eth_cleanup, 1270 .link_status_changed = imx_eth_set_link, 1271 }; 1272 1273 1274 static void imx_eth_realize(DeviceState *dev, Error **errp) 1275 { 1276 IMXFECState *s = IMX_FEC(dev); 1277 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1278 1279 memory_region_init_io(&s->iomem, OBJECT(dev), &imx_eth_ops, s, 1280 TYPE_IMX_FEC, FSL_IMX25_FEC_SIZE); 1281 sysbus_init_mmio(sbd, &s->iomem); 1282 sysbus_init_irq(sbd, &s->irq[0]); 1283 sysbus_init_irq(sbd, &s->irq[1]); 1284 1285 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1286 1287 s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, 1288 object_get_typename(OBJECT(dev)), 1289 DEVICE(dev)->id, s); 1290 1291 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 1292 } 1293 1294 static Property imx_eth_properties[] = { 1295 DEFINE_NIC_PROPERTIES(IMXFECState, conf), 1296 DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1), 1297 DEFINE_PROP_END_OF_LIST(), 1298 }; 1299 1300 static void imx_eth_class_init(ObjectClass *klass, void *data) 1301 { 1302 DeviceClass *dc = DEVICE_CLASS(klass); 1303 1304 dc->vmsd = &vmstate_imx_eth; 1305 dc->reset = imx_eth_reset; 1306 dc->props = imx_eth_properties; 1307 dc->realize = imx_eth_realize; 1308 dc->desc = "i.MX FEC/ENET Ethernet Controller"; 1309 } 1310 1311 static void imx_fec_init(Object *obj) 1312 { 1313 IMXFECState *s = IMX_FEC(obj); 1314 1315 s->is_fec = true; 1316 } 1317 1318 static void imx_enet_init(Object *obj) 1319 { 1320 IMXFECState *s = IMX_FEC(obj); 1321 1322 s->is_fec = false; 1323 } 1324 1325 static const TypeInfo imx_fec_info = { 1326 .name = TYPE_IMX_FEC, 1327 .parent = TYPE_SYS_BUS_DEVICE, 1328 .instance_size = sizeof(IMXFECState), 1329 .instance_init = imx_fec_init, 1330 .class_init = imx_eth_class_init, 1331 }; 1332 1333 static const TypeInfo imx_enet_info = { 1334 .name = TYPE_IMX_ENET, 1335 .parent = TYPE_IMX_FEC, 1336 .instance_init = imx_enet_init, 1337 }; 1338 1339 static void imx_eth_register_types(void) 1340 { 1341 type_register_static(&imx_fec_info); 1342 type_register_static(&imx_enet_info); 1343 } 1344 1345 type_init(imx_eth_register_types) 1346