1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This is copied + edited from kernel header files in 4 * drivers/net/ethernet/intel/igb 5 */ 6 7 #ifndef HW_IGB_REGS_H_ 8 #define HW_IGB_REGS_H_ 9 10 #include "e1000x_regs.h" 11 12 /* from igb/e1000_hw.h */ 13 14 #define E1000_DEV_ID_82576 0x10C9 15 #define E1000_DEV_ID_82576_FIBER 0x10E6 16 #define E1000_DEV_ID_82576_SERDES 0x10E7 17 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 18 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 19 #define E1000_DEV_ID_82576_NS 0x150A 20 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 21 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 22 23 /* Context Descriptor */ 24 struct e1000_adv_tx_context_desc { 25 uint32_t vlan_macip_lens; 26 uint32_t seqnum_seed; 27 uint32_t type_tucmd_mlhl; 28 uint32_t mss_l4len_idx; 29 }; 30 31 /* Advanced Transmit Descriptor */ 32 union e1000_adv_tx_desc { 33 struct { 34 uint64_t buffer_addr; /* Address of descriptor's data buffer */ 35 uint32_t cmd_type_len; 36 uint32_t olinfo_status; 37 } read; 38 struct { 39 uint64_t rsvd; /* Reserved */ 40 uint32_t nxtseq_seed; 41 uint32_t status; 42 } wb; 43 }; 44 45 #define E1000_ADVTXD_POTS_IXSM 0x00000100 /* Insert TCP/UDP Checksum */ 46 #define E1000_ADVTXD_POTS_TXSM 0x00000200 /* Insert TCP/UDP Checksum */ 47 48 #define E1000_TXD_POPTS_IXSM 0x00000001 /* Insert IP checksum */ 49 #define E1000_TXD_POPTS_TXSM 0x00000002 /* Insert TCP/UDP checksum */ 50 51 /* Receive Descriptor - Advanced */ 52 union e1000_adv_rx_desc { 53 struct { 54 uint64_t pkt_addr; /* Packet Buffer Address */ 55 uint64_t hdr_addr; /* Header Buffer Address */ 56 } read; 57 struct { 58 struct { 59 struct { 60 uint16_t pkt_info; /* RSS Type, Packet Type */ 61 uint16_t hdr_info; /* Split Head, Buffer Length */ 62 } lo_dword; 63 union { 64 uint32_t rss; /* RSS Hash */ 65 struct { 66 uint16_t ip_id; /* IP Id */ 67 uint16_t csum; /* Packet Checksum */ 68 } csum_ip; 69 } hi_dword; 70 } lower; 71 struct { 72 uint32_t status_error; /* Ext Status/Error */ 73 uint16_t length; /* Packet Length */ 74 uint16_t vlan; /* VLAN tag */ 75 } upper; 76 } wb; /* writeback */ 77 }; 78 79 /* from igb/e1000_phy.h */ 80 81 /* IGP01E1000 Specific Registers */ 82 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 83 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 84 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 85 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 86 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 87 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 88 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 89 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 90 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 91 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 92 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 93 94 /* Enable flexible speed on link-up */ 95 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 96 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 97 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 98 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 99 #define IGP01E1000_PSSR_MDIX 0x0800 100 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 101 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 102 #define IGP02E1000_PHY_CHANNEL_NUM 4 103 #define IGP02E1000_PHY_AGC_A 0x11B1 104 #define IGP02E1000_PHY_AGC_B 0x12B1 105 #define IGP02E1000_PHY_AGC_C 0x14B1 106 #define IGP02E1000_PHY_AGC_D 0x18B1 107 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ 108 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 109 #define IGP02E1000_AGC_RANGE 15 110 111 /* from igb/igb.h */ 112 113 #define E1000_PCS_CFG_IGN_SD 1 114 115 /* Interrupt defines */ 116 #define IGB_START_ITR 648 /* ~6000 ints/sec */ 117 #define IGB_4K_ITR 980 118 #define IGB_20K_ITR 196 119 #define IGB_70K_ITR 56 120 121 /* TX/RX descriptor defines */ 122 #define IGB_DEFAULT_TXD 256 123 #define IGB_DEFAULT_TX_WORK 128 124 #define IGB_MIN_TXD 80 125 #define IGB_MAX_TXD 4096 126 127 #define IGB_DEFAULT_RXD 256 128 #define IGB_MIN_RXD 80 129 #define IGB_MAX_RXD 4096 130 131 #define IGB_DEFAULT_ITR 3 /* dynamic */ 132 #define IGB_MAX_ITR_USECS 10000 133 #define IGB_MIN_ITR_USECS 10 134 #define NON_Q_VECTORS 1 135 #define MAX_Q_VECTORS 8 136 #define MAX_MSIX_ENTRIES 10 137 138 /* Transmit and receive queues */ 139 #define IGB_MAX_RX_QUEUES 8 140 #define IGB_MAX_RX_QUEUES_82575 4 141 #define IGB_MAX_RX_QUEUES_I211 2 142 #define IGB_MAX_TX_QUEUES 8 143 #define IGB_MAX_VF_MC_ENTRIES 30 144 #define IGB_MAX_VF_FUNCTIONS 8 145 #define IGB_MAX_VFTA_ENTRIES 128 146 #define IGB_82576_VF_DEV_ID 0x10CA 147 #define IGB_I350_VF_DEV_ID 0x1520 148 149 /* VLAN info */ 150 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 151 #define IGB_TX_FLAGS_VLAN_SHIFT 16 152 153 /* from igb/e1000_82575.h */ 154 155 #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002 156 #define E1000_MRQC_ENABLE_VMDQ 0x00000003 157 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 158 #define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005 159 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 160 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 161 162 /* Adv Transmit Descriptor Config Masks */ 163 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ 164 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 165 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 166 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 167 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 168 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 169 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 170 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 171 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 172 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 173 174 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 175 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 176 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 177 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 178 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */ 179 /* IPSec Encrypt Enable for ESP */ 180 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 181 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 182 /* Adv ctxt IPSec SA IDX mask */ 183 /* Adv ctxt IPSec ESP len mask */ 184 185 /* Additional Transmit Descriptor Control definitions */ 186 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 187 188 /* Additional Receive Descriptor Control definitions */ 189 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 190 191 /* Direct Cache Access (DCA) definitions */ 192 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */ 193 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 194 195 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 196 #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */ 197 #define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */ 198 #define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */ 199 #define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */ 200 201 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 202 #define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ 203 #define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ 204 #define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ 205 #define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ 206 207 /* Additional DCA related definitions, note change in position of CPUID */ 208 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ 209 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ 210 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */ 211 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */ 212 213 /* ETQF register bit definitions */ 214 #define E1000_ETQF_FILTER_ENABLE BIT(26) 215 #define E1000_ETQF_1588 BIT(30) 216 #define E1000_ETQF_IMM_INT BIT(29) 217 #define E1000_ETQF_QUEUE_ENABLE BIT(31) 218 #define E1000_ETQF_QUEUE_SHIFT 16 219 #define E1000_ETQF_QUEUE_MASK 0x00070000 220 #define E1000_ETQF_ETYPE_MASK 0x0000FFFF 221 222 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */ 223 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */ 224 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ 225 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 226 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */ 227 228 /* Easy defines for setting default pool, would normally be left a zero */ 229 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 230 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) 231 232 /* Other useful VMD_CTL register defines */ 233 #define E1000_VT_CTL_IGNORE_MAC BIT(28) 234 #define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29) 235 #define E1000_VT_CTL_VM_REPL_EN BIT(30) 236 237 /* Per VM Offload register setup */ 238 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ 239 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ 240 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ 241 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ 242 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ 243 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ 244 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ 245 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ 246 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 247 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 248 249 #define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */ 250 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ 251 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */ 252 253 #define E1000_VLVF_ARRAY_SIZE 32 254 #define E1000_VLVF_VLANID_MASK 0x00000FFF 255 #define E1000_VLVF_POOLSEL_SHIFT 12 256 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) 257 #define E1000_VLVF_LVLAN 0x00100000 258 #define E1000_VLVF_VLANID_ENABLE 0x80000000 259 260 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 261 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 262 263 #define E1000_IOVCTL 0x05BBC 264 #define E1000_IOVCTL_REUSE_VFQ 0x00000001 265 266 #define E1000_RPLOLR_STRVLAN 0x40000000 267 #define E1000_RPLOLR_STRCRC 0x80000000 268 269 #define E1000_DTXCTL_8023LL 0x0004 270 #define E1000_DTXCTL_VLAN_ADDED 0x0008 271 #define E1000_DTXCTL_OOS_ENABLE 0x0010 272 #define E1000_DTXCTL_MDP_EN 0x0020 273 #define E1000_DTXCTL_SPOOF_INT 0x0040 274 275 /* from igb/e1000_defines.h */ 276 277 /* Physical Func Reset Done Indication */ 278 #define E1000_CTRL_EXT_PFRSTD 0x00004000 279 280 #define E1000_IVAR_VALID 0x80 281 #define E1000_GPIE_NSICR 0x00000001 282 #define E1000_GPIE_MSIX_MODE 0x00000010 283 #define E1000_GPIE_EIAME 0x40000000 284 #define E1000_GPIE_PBA 0x80000000 285 286 /* Transmit Control */ 287 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 288 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 289 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 290 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 291 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 292 293 /* Collision related configuration parameters */ 294 #define E1000_COLLISION_THRESHOLD 15 295 #define E1000_CT_SHIFT 4 296 #define E1000_COLLISION_DISTANCE 63 297 #define E1000_COLD_SHIFT 12 298 299 #define E1000_RAH_POOL_MASK 0x03FC0000 300 #define E1000_RAH_POOL_1 0x00040000 301 302 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 303 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 304 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 305 /* If this bit asserted, the driver should claim the interrupt */ 306 #define E1000_ICR_INT_ASSERTED 0x80000000 307 /* LAN connected device generates an interrupt */ 308 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 309 310 /* Extended Interrupt Cause Read */ 311 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 312 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 313 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 314 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 315 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 316 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 317 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 318 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 319 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 320 321 /* Extended Interrupt Cause Set */ 322 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 323 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 324 325 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 326 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 327 328 /* PCI Express Control */ 329 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 330 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 331 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 332 #define E1000_GCR_CAP_VER2 0x00040000 333 334 #define PHY_REVISION_MASK 0xFFFFFFF0 335 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 336 #define MAX_PHY_MULTI_PAGE_REG 0xF 337 338 #define IGP03E1000_E_PHY_ID 0x02A80390 339 340 /* from igb/e1000_mbox.h */ 341 342 #define E1000_P2VMAILBOX_STS 0x00000001 /* Initiate message send to VF */ 343 #define E1000_P2VMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */ 344 #define E1000_P2VMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */ 345 #define E1000_P2VMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ 346 #define E1000_P2VMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */ 347 348 #define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */ 349 #define E1000_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */ 350 #define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */ 351 #define E1000_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */ 352 353 #define E1000_V2PMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */ 354 355 /* 356 * If it's a E1000_VF_* msg then it originates in the VF and is sent to the 357 * PF. The reverse is true if it is E1000_PF_*. 358 * Message ACK's are the value or'd with 0xF0000000 359 */ 360 /* Messages below or'd with this are the ACK */ 361 #define E1000_VT_MSGTYPE_ACK 0x80000000 362 /* Messages below or'd with this are the NACK */ 363 #define E1000_VT_MSGTYPE_NACK 0x40000000 364 /* Indicates that VF is still clear to send requests */ 365 #define E1000_VT_MSGTYPE_CTS 0x20000000 366 #define E1000_VT_MSGINFO_SHIFT 16 367 /* bits 23:16 are used for extra info for certain messages */ 368 #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT) 369 370 #define E1000_VF_RESET 0x01 /* VF requests reset */ 371 #define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests to set MAC addr */ 372 /* VF requests to clear all unicast MAC filters */ 373 #define E1000_VF_MAC_FILTER_CLR (0x01 << E1000_VT_MSGINFO_SHIFT) 374 /* VF requests to add unicast MAC filter */ 375 #define E1000_VF_MAC_FILTER_ADD (0x02 << E1000_VT_MSGINFO_SHIFT) 376 #define E1000_VF_SET_MULTICAST 0x03 /* VF requests to set MC addr */ 377 #define E1000_VF_SET_VLAN 0x04 /* VF requests to set VLAN */ 378 #define E1000_VF_SET_LPE 0x05 /* VF requests to set VMOLR.LPE */ 379 #define E1000_VF_SET_PROMISC 0x06 /*VF requests to clear VMOLR.ROPE/MPME*/ 380 #define E1000_VF_SET_PROMISC_MULTICAST (0x02 << E1000_VT_MSGINFO_SHIFT) 381 382 #define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */ 383 384 /* from igb/e1000_regs.h */ 385 386 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 387 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 388 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 389 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 390 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 391 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 392 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 393 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable; RW */ 394 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation Register - RW */ 395 #define E1000_IVAR_MISC 0x01740 /* Interrupt Vector Allocation Register (last) - RW */ 396 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */ 397 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ 398 399 #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ 400 401 /* Filtering Registers */ 402 #define E1000_SAQF(_n) (0x5980 + 4 * (_n)) 403 #define E1000_DAQF(_n) (0x59A0 + 4 * (_n)) 404 #define E1000_SPQF(_n) (0x59C0 + 4 * (_n)) 405 #define E1000_FTQF(_n) (0x59E0 + 4 * (_n)) 406 #define E1000_SAQF0 E1000_SAQF(0) 407 #define E1000_DAQF0 E1000_DAQF(0) 408 #define E1000_SPQF0 E1000_SPQF(0) 409 #define E1000_FTQF0 E1000_FTQF(0) 410 #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ 411 #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ 412 413 #define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40)) 414 415 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ 416 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */ 417 418 #define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */ 419 420 #define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */ 421 #define E1000_RLPML 0x05004 /* RX Long Packet Max Length */ 422 #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */ 423 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4)) 424 #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */ 425 426 /* VT Registers */ 427 #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */ 428 #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */ 429 #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */ 430 #define E1000_VFRE 0x00C8C /* VF Receive Enables */ 431 #define E1000_VFTE 0x00C90 /* VF Transmit Enables */ 432 #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */ 433 #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */ 434 #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */ 435 #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */ 436 #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */ 437 #define E1000_IOVTCL 0x05BBC /* IOV Control Register */ 438 #define E1000_TXSWC 0x05ACC /* Tx Switch Control */ 439 #define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */ 440 /* These act per VF so an array friendly macro is used */ 441 #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n))) 442 #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 443 #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n))) 444 #define E1000_DVMOLR(_n) (0x0C038 + (64 * (_n))) 445 #define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN VM Filter */ 446 #define E1000_VMVIR(_n) (0x03700 + (4 * (_n))) 447 448 /* from igbvf/defines.h */ 449 450 /* SRRCTL bit definitions */ 451 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 452 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 453 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 454 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 455 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 456 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 457 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 458 #define E1000_SRRCTL_DROP_EN 0x80000000 459 460 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 461 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 462 463 /* from igbvf/mbox.h */ 464 465 #define E1000_V2PMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */ 466 #define E1000_V2PMAILBOX_ACK 0x00000002 /* Ack PF message received */ 467 #define E1000_V2PMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */ 468 #define E1000_V2PMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ 469 #define E1000_V2PMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */ 470 #define E1000_V2PMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */ 471 #define E1000_V2PMAILBOX_RSTI 0x00000040 /* PF has reset indication */ 472 #define E1000_V2PMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */ 473 #define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */ 474 475 #define E1000_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */ 476 477 /* 478 * If it's a E1000_VF_* msg then it originates in the VF and is sent to the 479 * PF. The reverse is true if it is E1000_PF_*. 480 * Message ACK's are the value or'd with 0xF0000000 481 */ 482 /* Messages below or'd with this are the ACK */ 483 #define E1000_VT_MSGTYPE_ACK 0x80000000 484 /* Messages below or'd with this are the NACK */ 485 #define E1000_VT_MSGTYPE_NACK 0x40000000 486 /* Indicates that VF is still clear to send requests */ 487 #define E1000_VT_MSGTYPE_CTS 0x20000000 488 489 /* We have a total wait time of 1s for vf mailbox posted messages */ 490 #define E1000_VF_MBX_INIT_TIMEOUT 2000 /* retry count for mbx timeout */ 491 #define E1000_VF_MBX_INIT_DELAY 500 /* usec delay between retries */ 492 493 #define E1000_VT_MSGINFO_SHIFT 16 494 /* bits 23:16 are used for extra info for certain messages */ 495 #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT) 496 497 #define E1000_VF_RESET 0x01 /* VF requests reset */ 498 #define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */ 499 /* VF requests PF to clear all unicast MAC filters */ 500 #define E1000_VF_MAC_FILTER_CLR (0x01 << E1000_VT_MSGINFO_SHIFT) 501 /* VF requests PF to add unicast MAC filter */ 502 #define E1000_VF_MAC_FILTER_ADD (0x02 << E1000_VT_MSGINFO_SHIFT) 503 #define E1000_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */ 504 #define E1000_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */ 505 #define E1000_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */ 506 507 #define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */ 508 509 /* from igbvf/regs.h */ 510 511 /* Statistics registers */ 512 #define E1000_VFGPRC 0x00F10 513 #define E1000_VFGORC 0x00F18 514 #define E1000_VFMPRC 0x00F3C 515 #define E1000_VFGPTC 0x00F14 516 #define E1000_VFGOTC 0x00F34 517 #define E1000_VFGOTLBC 0x00F50 518 #define E1000_VFGPTLBC 0x00F44 519 #define E1000_VFGORLBC 0x00F48 520 #define E1000_VFGPRLBC 0x00F40 521 522 /* These act per VF so an array friendly macro is used */ 523 #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n))) 524 #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n))) 525 526 /* from igbvf/vf.h */ 527 528 #define E1000_DEV_ID_82576_VF 0x10CA 529 530 /* new */ 531 532 /* Receive Registers */ 533 534 /* RX Descriptor Base Low; RW */ 535 #define E1000_RDBAL(_n) (0x0C000 + (0x40 * (_n))) 536 #define E1000_RDBAL_A(_n) (0x02800 + (0x100 * (_n))) 537 538 /* RX Descriptor Base High; RW */ 539 #define E1000_RDBAH(_n) (0x0C004 + (0x40 * (_n))) 540 #define E1000_RDBAH_A(_n) (0x02804 + (0x100 * (_n))) 541 542 /* RX Descriptor Ring Length; RW */ 543 #define E1000_RDLEN(_n) (0x0C008 + (0x40 * (_n))) 544 #define E1000_RDLEN_A(_n) (0x02808 + (0x100 * (_n))) 545 546 /* Split and Replication Receive Control; RW */ 547 #define E1000_SRRCTL(_n) (0x0C00C + (0x40 * (_n))) 548 #define E1000_SRRCTL_A(_n) (0x0280C + (0x100 * (_n))) 549 550 /* RX Descriptor Head; RW */ 551 #define E1000_RDH(_n) (0x0C010 + (0x40 * (_n))) 552 #define E1000_RDH_A(_n) (0x02810 + (0x100 * (_n))) 553 554 /* RX DCA Control; RW */ 555 #define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n))) 556 #define E1000_RXCTL_A(_n) (0x02814 + (0x100 * (_n))) 557 558 /* RX Descriptor Tail; RW */ 559 #define E1000_RDT(_n) (0x0C018 + (0x40 * (_n))) 560 #define E1000_RDT_A(_n) (0x02818 + (0x100 * (_n))) 561 562 /* RX Descriptor Control; RW */ 563 #define E1000_RXDCTL(_n) (0x0C028 + (0x40 * (_n))) 564 #define E1000_RXDCTL_A(_n) (0x02828 + (0x100 * (_n))) 565 566 /* RX Queue Drop Packet Count; RC */ 567 #define E1000_RQDPC_A(_n) (0x02830 + (0x100 * (_n))) 568 569 /* Transmit Registers */ 570 571 /* TX Descriptor Base Low; RW */ 572 #define E1000_TDBAL(_n) (0x0E000 + (0x40 * (_n))) 573 #define E1000_TDBAL_A(_n) (0x03800 + (0x100 * (_n))) 574 575 /* TX Descriptor Base High; RW */ 576 #define E1000_TDBAH(_n) (0x0E004 + (0x40 * (_n))) 577 #define E1000_TDBAH_A(_n) (0x03804 + (0x100 * (_n))) 578 579 /* TX Descriptor Ring Length; RW */ 580 #define E1000_TDLEN(_n) (0x0E008 + (0x40 * (_n))) 581 #define E1000_TDLEN_A(_n) (0x03808 + (0x100 * (_n))) 582 583 /* TX Descriptor Head; RW */ 584 #define E1000_TDH(_n) (0x0E010 + (0x40 * (_n))) 585 #define E1000_TDH_A(_n) (0x03810 + (0x100 * (_n))) 586 587 /* TX DCA Control; RW */ 588 #define E1000_TXCTL(_n) (0x0E014 + (0x40 * (_n))) 589 #define E1000_TXCTL_A(_n) (0x03814 + (0x100 * (_n))) 590 591 /* TX Descriptor Tail; RW */ 592 #define E1000_TDT(_n) (0x0E018 + (0x40 * (_n))) 593 #define E1000_TDT_A(_n) (0x03818 + (0x100 * (_n))) 594 595 /* TX Descriptor Control; RW */ 596 #define E1000_TXDCTL(_n) (0x0E028 + (0x40 * (_n))) 597 #define E1000_TXDCTL_A(_n) (0x03828 + (0x100 * (_n))) 598 599 /* TX Descriptor Completion Write–Back Address Low; RW */ 600 #define E1000_TDWBAL(_n) (0x0E038 + (0x40 * (_n))) 601 #define E1000_TDWBAL_A(_n) (0x03838 + (0x100 * (_n))) 602 603 /* TX Descriptor Completion Write–Back Address High; RW */ 604 #define E1000_TDWBAH(_n) (0x0E03C + (0x40 * (_n))) 605 #define E1000_TDWBAH_A(_n) (0x0383C + (0x100 * (_n))) 606 607 #define E1000_MTA_A 0x0200 608 609 #define E1000_XDBAL_MASK (~(BIT(5) - 1)) /* TDBAL and RDBAL Registers Mask */ 610 611 #define E1000_ICR_MACSEC 0x00000020 /* MACSec */ 612 #define E1000_ICR_RX0 0x00000040 /* Receiver Overrun */ 613 #define E1000_ICR_GPI_SDP0 0x00000800 /* General Purpose, SDP0 pin */ 614 #define E1000_ICR_GPI_SDP1 0x00001000 /* General Purpose, SDP1 pin */ 615 #define E1000_ICR_GPI_SDP2 0x00002000 /* General Purpose, SDP2 pin */ 616 #define E1000_ICR_GPI_SDP3 0x00004000 /* General Purpose, SDP3 pin */ 617 #define E1000_ICR_PTRAP 0x00008000 /* Probe Trap */ 618 #define E1000_ICR_MNG 0x00040000 /* Management Event */ 619 #define E1000_ICR_OMED 0x00100000 /* Other Media Energy Detected */ 620 #define E1000_ICR_FER 0x00400000 /* Fatal Error */ 621 #define E1000_ICR_NFER 0x00800000 /* Non Fatal Error */ 622 #define E1000_ICR_CSRTO 0x01000000 /* CSR access Time Out Indication */ 623 #define E1000_ICR_SCE 0x02000000 /* Storm Control Event */ 624 #define E1000_ICR_SW_WD 0x04000000 /* Software Watchdog */ 625 626 /* Extended Interrupts */ 627 628 #define E1000_EICR_MSIX_MASK 0x01FFFFFF /* Bits used in MSI-X mode */ 629 #define E1000_EICR_LEGACY_MASK 0x4000FFFF /* Bits used in non MSI-X mode */ 630 631 /* Mirror VF Control (only RST bit); RW */ 632 #define E1000_PVTCTRL(_n) (0x10000 + (_n) * 0x100) 633 634 /* Mirror Good Packets Received Count; RO */ 635 #define E1000_PVFGPRC(_n) (0x10010 + (_n) * 0x100) 636 637 /* Mirror Good Packets Transmitted Count; RO */ 638 #define E1000_PVFGPTC(_n) (0x10014 + (_n) * 0x100) 639 640 /* Mirror Good Octets Received Count; RO */ 641 #define E1000_PVFGORC(_n) (0x10018 + (_n) * 0x100) 642 643 /* Mirror Extended Interrupt Cause Set; WO */ 644 #define E1000_PVTEICS(_n) (0x10020 + (_n) * 0x100) 645 646 /* Mirror Extended Interrupt Mask Set/Read; RW */ 647 #define E1000_PVTEIMS(_n) (0x10024 + (_n) * 0x100) 648 649 /* Mirror Extended Interrupt Mask Clear; WO */ 650 #define E1000_PVTEIMC(_n) (0x10028 + (_n) * 0x100) 651 652 /* Mirror Extended Interrupt Auto Clear; RW */ 653 #define E1000_PVTEIAC(_n) (0x1002C + (_n) * 0x100) 654 655 /* Mirror Extended Interrupt Auto Mask Enable; RW */ 656 #define E1000_PVTEIAM(_n) (0x10030 + (_n) * 0x100) 657 658 /* Mirror Good Octets Transmitted Count; RO */ 659 #define E1000_PVFGOTC(_n) (0x10034 + (_n) * 0x100) 660 661 /* Mirror Multicast Packets Received Count; RO */ 662 #define E1000_PVFMPRC(_n) (0x1003C + (_n) * 0x100) 663 664 /* Mirror Good RX Packets loopback Count; RO */ 665 #define E1000_PVFGPRLBC(_n) (0x10040 + (_n) * 0x100) 666 667 /* Mirror Good TX packets loopback Count; RO */ 668 #define E1000_PVFGPTLBC(_n) (0x10044 + (_n) * 0x100) 669 670 /* Mirror Good RX Octets loopback Count; RO */ 671 #define E1000_PVFGORLBC(_n) (0x10048 + (_n) * 0x100) 672 673 /* Mirror Good TX Octets loopback Count; RO */ 674 #define E1000_PVFGOTLBC(_n) (0x10050 + (_n) * 0x100) 675 676 /* Mirror Extended Interrupt Cause Set; RC/W1C */ 677 #define E1000_PVTEICR(_n) (0x10080 + (_n) * 0x100) 678 679 /* 680 * These are fake addresses that, according to the specification, the device 681 * is not using. They are used to distinguish between the PF and the VFs 682 * accessing their VTIVAR register (which is the same address, 0x1700) 683 */ 684 #define E1000_VTIVAR 0x11700 685 #define E1000_VTIVAR_MISC 0x11720 686 687 #define E1000_RSS_QUEUE(reta, hash) (E1000_RETA_VAL(reta, hash) & 0x0F) 688 689 #define E1000_MRQ_RSS_TYPE_IPV4UDP 7 690 #define E1000_MRQ_RSS_TYPE_IPV6UDP 8 691 692 #define E1000_STATUS_IOV_MODE 0x00040000 693 694 #define E1000_STATUS_NUM_VFS_SHIFT 14 695 696 #define E1000_ADVRXD_PKT_IP4 BIT(0) 697 #define E1000_ADVRXD_PKT_IP6 BIT(2) 698 #define E1000_ADVRXD_PKT_IP6E BIT(3) 699 #define E1000_ADVRXD_PKT_TCP BIT(4) 700 #define E1000_ADVRXD_PKT_UDP BIT(5) 701 #define E1000_ADVRXD_PKT_SCTP BIT(6) 702 703 #define IGB_MAX_PS_BUFFERS 2 704 705 #define E1000_ADVRXD_HDR_LEN_OFFSET (21 - 16) 706 #define E1000_ADVRXD_ADV_HDR_LEN_MASK ((BIT(10) - 1) << \ 707 E1000_ADVRXD_HDR_LEN_OFFSET) 708 #define E1000_ADVRXD_HDR_SPH BIT(15) 709 #define E1000_ADVRXD_ST_ERR_HBO_OFFSET BIT(3 + 20) 710 711 static inline uint8_t igb_ivar_entry_rx(uint8_t i) 712 { 713 return i < 8 ? i * 4 : (i - 8) * 4 + 2; 714 } 715 716 static inline uint8_t igb_ivar_entry_tx(uint8_t i) 717 { 718 return i < 8 ? i * 4 + 1 : (i - 8) * 4 + 3; 719 } 720 721 #endif 722