1 /* 2 * Core code for QEMU igb emulation 3 * 4 * Datasheet: 5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf 6 * 7 * Copyright (c) 2020-2023 Red Hat, Inc. 8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 9 * Developed by Daynix Computing LTD (http://www.daynix.com) 10 * 11 * Authors: 12 * Akihiko Odaki <akihiko.odaki@daynix.com> 13 * Gal Hammmer <gal.hammer@sap.com> 14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com> 15 * Dmitry Fleytman <dmitry@daynix.com> 16 * Leonid Bloch <leonid@daynix.com> 17 * Yan Vugenfirer <yan@daynix.com> 18 * 19 * Based on work done by: 20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 21 * Copyright (c) 2008 Qumranet 22 * Based on work done by: 23 * Copyright (c) 2007 Dan Aloni 24 * Copyright (c) 2004 Antony T Curtis 25 * 26 * This library is free software; you can redistribute it and/or 27 * modify it under the terms of the GNU Lesser General Public 28 * License as published by the Free Software Foundation; either 29 * version 2.1 of the License, or (at your option) any later version. 30 * 31 * This library is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 34 * Lesser General Public License for more details. 35 * 36 * You should have received a copy of the GNU Lesser General Public 37 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/log.h" 42 #include "net/net.h" 43 #include "net/tap.h" 44 #include "hw/net/mii.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "sysemu/runstate.h" 48 49 #include "net_tx_pkt.h" 50 #include "net_rx_pkt.h" 51 52 #include "igb_common.h" 53 #include "e1000x_common.h" 54 #include "igb_core.h" 55 56 #include "trace.h" 57 58 #define E1000E_MAX_TX_FRAGS (64) 59 60 union e1000_rx_desc_union { 61 struct e1000_rx_desc legacy; 62 union e1000_adv_rx_desc adv; 63 }; 64 65 typedef struct IGBTxPktVmdqCallbackContext { 66 IGBCore *core; 67 NetClientState *nc; 68 } IGBTxPktVmdqCallbackContext; 69 70 static ssize_t 71 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 72 bool has_vnet, bool *external_tx); 73 74 static inline void 75 igb_set_interrupt_cause(IGBCore *core, uint32_t val); 76 77 static void igb_update_interrupt_state(IGBCore *core); 78 static void igb_reset(IGBCore *core, bool sw); 79 80 static inline void 81 igb_raise_legacy_irq(IGBCore *core) 82 { 83 trace_e1000e_irq_legacy_notify(true); 84 e1000x_inc_reg_if_not_full(core->mac, IAC); 85 pci_set_irq(core->owner, 1); 86 } 87 88 static inline void 89 igb_lower_legacy_irq(IGBCore *core) 90 { 91 trace_e1000e_irq_legacy_notify(false); 92 pci_set_irq(core->owner, 0); 93 } 94 95 static void igb_msix_notify(IGBCore *core, unsigned int vector) 96 { 97 PCIDevice *dev = core->owner; 98 uint16_t vfn; 99 100 vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM; 101 if (vfn < pcie_sriov_num_vfs(core->owner)) { 102 dev = pcie_sriov_get_vf_at_index(core->owner, vfn); 103 assert(dev); 104 vector = (vector + 2) % IGBVF_MSIX_VEC_NUM; 105 } else if (vector >= IGB_MSIX_VEC_NUM) { 106 qemu_log_mask(LOG_GUEST_ERROR, 107 "igb: Tried to use vector unavailable for PF"); 108 return; 109 } 110 111 msix_notify(dev, vector); 112 } 113 114 static inline void 115 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) 116 { 117 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 118 timer->delay_resolution_ns; 119 120 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 121 122 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 123 124 timer->running = true; 125 } 126 127 static void 128 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer) 129 { 130 if (timer->running) { 131 igb_intrmgr_rearm_timer(timer); 132 } 133 } 134 135 static void 136 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer) 137 { 138 if (timer->running) { 139 timer_del(timer->timer); 140 } 141 } 142 143 static void 144 igb_intrmgr_on_msix_throttling_timer(void *opaque) 145 { 146 IGBIntrDelayTimer *timer = opaque; 147 int idx = timer - &timer->core->eitr[0]; 148 149 timer->running = false; 150 151 trace_e1000e_irq_msix_notify_postponed_vec(idx); 152 igb_msix_notify(timer->core, idx); 153 } 154 155 static void 156 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create) 157 { 158 int i; 159 160 for (i = 0; i < IGB_INTR_NUM; i++) { 161 core->eitr[i].core = core; 162 core->eitr[i].delay_reg = EITR0 + i; 163 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 164 } 165 166 if (!create) { 167 return; 168 } 169 170 for (i = 0; i < IGB_INTR_NUM; i++) { 171 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 172 igb_intrmgr_on_msix_throttling_timer, 173 &core->eitr[i]); 174 } 175 } 176 177 static void 178 igb_intrmgr_resume(IGBCore *core) 179 { 180 int i; 181 182 for (i = 0; i < IGB_INTR_NUM; i++) { 183 igb_intmgr_timer_resume(&core->eitr[i]); 184 } 185 } 186 187 static void 188 igb_intrmgr_pause(IGBCore *core) 189 { 190 int i; 191 192 for (i = 0; i < IGB_INTR_NUM; i++) { 193 igb_intmgr_timer_pause(&core->eitr[i]); 194 } 195 } 196 197 static void 198 igb_intrmgr_reset(IGBCore *core) 199 { 200 int i; 201 202 for (i = 0; i < IGB_INTR_NUM; i++) { 203 if (core->eitr[i].running) { 204 timer_del(core->eitr[i].timer); 205 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 206 } 207 } 208 } 209 210 static void 211 igb_intrmgr_pci_unint(IGBCore *core) 212 { 213 int i; 214 215 for (i = 0; i < IGB_INTR_NUM; i++) { 216 timer_free(core->eitr[i].timer); 217 } 218 } 219 220 static void 221 igb_intrmgr_pci_realize(IGBCore *core) 222 { 223 igb_intrmgr_initialize_all_timers(core, true); 224 } 225 226 static inline bool 227 igb_rx_csum_enabled(IGBCore *core) 228 { 229 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 230 } 231 232 static inline bool 233 igb_rx_use_legacy_descriptor(IGBCore *core) 234 { 235 /* 236 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx 237 * descriptor. 238 */ 239 return false; 240 } 241 242 static inline bool 243 igb_rss_enabled(IGBCore *core) 244 { 245 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ && 246 !igb_rx_csum_enabled(core) && 247 !igb_rx_use_legacy_descriptor(core); 248 } 249 250 typedef struct E1000E_RSSInfo_st { 251 bool enabled; 252 uint32_t hash; 253 uint32_t queue; 254 uint32_t type; 255 } E1000E_RSSInfo; 256 257 static uint32_t 258 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt) 259 { 260 bool hasip4, hasip6; 261 EthL4HdrProto l4hdr_proto; 262 263 assert(igb_rss_enabled(core)); 264 265 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 266 267 if (hasip4) { 268 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 269 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 270 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 271 272 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 273 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 274 return E1000_MRQ_RSS_TYPE_IPV4TCP; 275 } 276 277 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 278 return E1000_MRQ_RSS_TYPE_IPV4; 279 } 280 } else if (hasip6) { 281 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 282 283 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 284 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 285 286 /* 287 * Following two traces must not be combined because resulting 288 * event will have 11 arguments totally and some trace backends 289 * (at least "ust") have limitation of maximum 10 arguments per 290 * event. Events with more arguments fail to compile for 291 * backends like these. 292 */ 293 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 294 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 295 ip6info->has_ext_hdrs, 296 ip6info->rss_ex_dst_valid, 297 ip6info->rss_ex_src_valid, 298 core->mac[MRQC], 299 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 300 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 301 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 302 303 if ((!ex_dis || !ip6info->has_ext_hdrs) && 304 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 305 ip6info->rss_ex_src_valid))) { 306 307 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 308 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 309 return E1000_MRQ_RSS_TYPE_IPV6TCP; 310 } 311 312 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 313 return E1000_MRQ_RSS_TYPE_IPV6EX; 314 } 315 316 } 317 318 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 319 return E1000_MRQ_RSS_TYPE_IPV6; 320 } 321 322 } 323 324 return E1000_MRQ_RSS_TYPE_NONE; 325 } 326 327 static uint32_t 328 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info) 329 { 330 NetRxPktRssType type; 331 332 assert(igb_rss_enabled(core)); 333 334 switch (info->type) { 335 case E1000_MRQ_RSS_TYPE_IPV4: 336 type = NetPktRssIpV4; 337 break; 338 case E1000_MRQ_RSS_TYPE_IPV4TCP: 339 type = NetPktRssIpV4Tcp; 340 break; 341 case E1000_MRQ_RSS_TYPE_IPV6TCP: 342 type = NetPktRssIpV6TcpEx; 343 break; 344 case E1000_MRQ_RSS_TYPE_IPV6: 345 type = NetPktRssIpV6; 346 break; 347 case E1000_MRQ_RSS_TYPE_IPV6EX: 348 type = NetPktRssIpV6Ex; 349 break; 350 default: 351 assert(false); 352 return 0; 353 } 354 355 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 356 } 357 358 static void 359 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx, 360 E1000E_RSSInfo *info) 361 { 362 trace_e1000e_rx_rss_started(); 363 364 if (tx || !igb_rss_enabled(core)) { 365 info->enabled = false; 366 info->hash = 0; 367 info->queue = 0; 368 info->type = 0; 369 trace_e1000e_rx_rss_disabled(); 370 return; 371 } 372 373 info->enabled = true; 374 375 info->type = igb_rss_get_hash_type(core, pkt); 376 377 trace_e1000e_rx_rss_type(info->type); 378 379 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 380 info->hash = 0; 381 info->queue = 0; 382 return; 383 } 384 385 info->hash = igb_rss_calc_hash(core, pkt, info); 386 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 387 } 388 389 static bool 390 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx) 391 { 392 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) { 393 uint32_t idx = (tx->first_olinfo_status >> 4) & 1; 394 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> 16; 395 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) { 396 return false; 397 } 398 399 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 400 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 401 return true; 402 } 403 404 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) { 405 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 406 return false; 407 } 408 } 409 410 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) { 411 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 412 } 413 414 return true; 415 } 416 417 static void igb_tx_pkt_mac_callback(void *core, 418 const struct iovec *iov, 419 int iovcnt, 420 const struct iovec *virt_iov, 421 int virt_iovcnt) 422 { 423 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL); 424 } 425 426 static void igb_tx_pkt_vmdq_callback(void *opaque, 427 const struct iovec *iov, 428 int iovcnt, 429 const struct iovec *virt_iov, 430 int virt_iovcnt) 431 { 432 IGBTxPktVmdqCallbackContext *context = opaque; 433 bool external_tx; 434 435 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true, 436 &external_tx); 437 438 if (external_tx) { 439 if (context->core->has_vnet) { 440 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt); 441 } else { 442 qemu_sendv_packet(context->nc, iov, iovcnt); 443 } 444 } 445 } 446 447 /* TX Packets Switching (7.10.3.6) */ 448 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx, 449 NetClientState *nc) 450 { 451 IGBTxPktVmdqCallbackContext context; 452 453 /* TX switching is only used to serve VM to VM traffic. */ 454 if (!(core->mac[MRQC] & 1)) { 455 goto send_out; 456 } 457 458 /* TX switching requires DTXSWC.Loopback_en bit enabled. */ 459 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) { 460 goto send_out; 461 } 462 463 context.core = core; 464 context.nc = nc; 465 466 return net_tx_pkt_send_custom(tx->tx_pkt, false, 467 igb_tx_pkt_vmdq_callback, &context); 468 469 send_out: 470 return net_tx_pkt_send(tx->tx_pkt, nc); 471 } 472 473 static bool 474 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index) 475 { 476 int target_queue = MIN(core->max_queue_num, queue_index); 477 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 478 479 if (!igb_setup_tx_offloads(core, tx)) { 480 return false; 481 } 482 483 net_tx_pkt_dump(tx->tx_pkt); 484 485 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) || 486 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 487 return net_tx_pkt_send_custom(tx->tx_pkt, false, 488 igb_tx_pkt_mac_callback, core); 489 } else { 490 return igb_tx_pkt_switch(core, tx, queue); 491 } 492 } 493 494 static void 495 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt, int qn) 496 { 497 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 498 PTC1023, PTC1522 }; 499 500 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 501 502 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 503 e1000x_inc_reg_if_not_full(core->mac, TPT); 504 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 505 506 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 507 case ETH_PKT_BCAST: 508 e1000x_inc_reg_if_not_full(core->mac, BPTC); 509 break; 510 case ETH_PKT_MCAST: 511 e1000x_inc_reg_if_not_full(core->mac, MPTC); 512 break; 513 case ETH_PKT_UCAST: 514 break; 515 default: 516 g_assert_not_reached(); 517 } 518 519 core->mac[GPTC] = core->mac[TPT]; 520 core->mac[GOTCL] = core->mac[TOTL]; 521 core->mac[GOTCH] = core->mac[TOTH]; 522 523 if (core->mac[MRQC] & 1) { 524 uint16_t pool = qn % IGB_NUM_VM_POOLS; 525 526 core->mac[PVFGOTC0 + (pool * 64)] += tot_len; 527 core->mac[PVFGPTC0 + (pool * 64)]++; 528 } 529 } 530 531 static void 532 igb_process_tx_desc(IGBCore *core, 533 PCIDevice *dev, 534 struct igb_tx *tx, 535 union e1000_adv_tx_desc *tx_desc, 536 int queue_index) 537 { 538 struct e1000_adv_tx_context_desc *tx_ctx_desc; 539 uint32_t cmd_type_len; 540 uint32_t idx; 541 uint64_t buffer_addr; 542 uint16_t length; 543 544 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 545 546 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) { 547 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) == 548 E1000_ADVTXD_DTYP_DATA) { 549 /* advanced transmit data descriptor */ 550 if (tx->first) { 551 tx->first_cmd_type_len = cmd_type_len; 552 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status); 553 tx->first = false; 554 } 555 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) == 556 E1000_ADVTXD_DTYP_CTXT) { 557 /* advanced transmit context descriptor */ 558 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc; 559 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1; 560 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens); 561 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed); 562 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl); 563 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx); 564 return; 565 } else { 566 /* unknown descriptor type */ 567 return; 568 } 569 } else { 570 /* legacy descriptor */ 571 572 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */ 573 } 574 575 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr); 576 length = cmd_type_len & 0xFFFF; 577 578 if (!tx->skip_cp) { 579 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, buffer_addr, length)) { 580 tx->skip_cp = true; 581 } 582 } 583 584 if (cmd_type_len & E1000_TXD_CMD_EOP) { 585 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 586 if (cmd_type_len & E1000_TXD_CMD_VLE) { 587 idx = (tx->first_olinfo_status >> 4) & 1; 588 uint16_t vlan = tx->ctx[idx].vlan_macip_lens >> 16; 589 uint16_t vet = core->mac[VET] & 0xffff; 590 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan, vet); 591 } 592 if (igb_tx_pkt_send(core, tx, queue_index)) { 593 igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index); 594 } 595 } 596 597 tx->first = true; 598 tx->skip_cp = false; 599 net_tx_pkt_reset(tx->tx_pkt, dev); 600 } 601 } 602 603 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx) 604 { 605 uint32_t n, ent = 0; 606 607 n = igb_ivar_entry_tx(queue_idx); 608 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 609 610 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 611 } 612 613 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx) 614 { 615 uint32_t n, ent = 0; 616 617 n = igb_ivar_entry_rx(queue_idx); 618 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 619 620 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 621 } 622 623 typedef struct E1000E_RingInfo_st { 624 int dbah; 625 int dbal; 626 int dlen; 627 int dh; 628 int dt; 629 int idx; 630 } E1000E_RingInfo; 631 632 static inline bool 633 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r) 634 { 635 return core->mac[r->dh] == core->mac[r->dt] || 636 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 637 } 638 639 static inline uint64_t 640 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r) 641 { 642 uint64_t bah = core->mac[r->dbah]; 643 uint64_t bal = core->mac[r->dbal]; 644 645 return (bah << 32) + bal; 646 } 647 648 static inline uint64_t 649 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r) 650 { 651 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 652 } 653 654 static inline void 655 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count) 656 { 657 core->mac[r->dh] += count; 658 659 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 660 core->mac[r->dh] = 0; 661 } 662 } 663 664 static inline uint32_t 665 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r) 666 { 667 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 668 core->mac[r->dh], core->mac[r->dt]); 669 670 if (core->mac[r->dh] <= core->mac[r->dt]) { 671 return core->mac[r->dt] - core->mac[r->dh]; 672 } 673 674 if (core->mac[r->dh] > core->mac[r->dt]) { 675 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 676 core->mac[r->dt] - core->mac[r->dh]; 677 } 678 679 g_assert_not_reached(); 680 return 0; 681 } 682 683 static inline bool 684 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r) 685 { 686 return core->mac[r->dlen] > 0; 687 } 688 689 typedef struct IGB_TxRing_st { 690 const E1000E_RingInfo *i; 691 struct igb_tx *tx; 692 } IGB_TxRing; 693 694 static inline int 695 igb_mq_queue_idx(int base_reg_idx, int reg_idx) 696 { 697 return (reg_idx - base_reg_idx) / 16; 698 } 699 700 static inline void 701 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx) 702 { 703 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 704 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 }, 705 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }, 706 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 }, 707 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 }, 708 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 }, 709 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 }, 710 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 }, 711 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 }, 712 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 }, 713 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 }, 714 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 }, 715 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 }, 716 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 }, 717 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 }, 718 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 }, 719 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 } 720 }; 721 722 assert(idx < ARRAY_SIZE(i)); 723 724 txr->i = &i[idx]; 725 txr->tx = &core->tx[idx]; 726 } 727 728 typedef struct E1000E_RxRing_st { 729 const E1000E_RingInfo *i; 730 } E1000E_RxRing; 731 732 static inline void 733 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx) 734 { 735 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 736 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 737 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }, 738 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 }, 739 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 }, 740 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 }, 741 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 }, 742 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 }, 743 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 }, 744 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 }, 745 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 }, 746 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 }, 747 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 }, 748 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 }, 749 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 }, 750 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 }, 751 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 } 752 }; 753 754 assert(idx < ARRAY_SIZE(i)); 755 756 rxr->i = &i[idx]; 757 } 758 759 static uint32_t 760 igb_txdesc_writeback(IGBCore *core, dma_addr_t base, 761 union e1000_adv_tx_desc *tx_desc, 762 const E1000E_RingInfo *txi) 763 { 764 PCIDevice *d; 765 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 766 uint64_t tdwba; 767 768 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2]; 769 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32; 770 771 if (!(cmd_type_len & E1000_TXD_CMD_RS)) { 772 return 0; 773 } 774 775 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 776 if (!d) { 777 d = core->owner; 778 } 779 780 if (tdwba & 1) { 781 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]); 782 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer)); 783 } else { 784 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD; 785 786 tx_desc->wb.status = cpu_to_le32(status); 787 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb), 788 &tx_desc->wb, sizeof(tx_desc->wb)); 789 } 790 791 return igb_tx_wb_eic(core, txi->idx); 792 } 793 794 static inline bool 795 igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi) 796 { 797 bool vmdq = core->mac[MRQC] & 1; 798 uint16_t qn = txi->idx; 799 uint16_t pool = qn % IGB_NUM_VM_POOLS; 800 801 return (core->mac[TCTL] & E1000_TCTL_EN) && 802 (!vmdq || core->mac[VFTE] & BIT(pool)) && 803 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE); 804 } 805 806 static void 807 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr) 808 { 809 PCIDevice *d; 810 dma_addr_t base; 811 union e1000_adv_tx_desc desc; 812 const E1000E_RingInfo *txi = txr->i; 813 uint32_t eic = 0; 814 815 if (!igb_tx_enabled(core, txi)) { 816 trace_e1000e_tx_disabled(); 817 return; 818 } 819 820 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 821 if (!d) { 822 d = core->owner; 823 } 824 825 net_tx_pkt_reset(txr->tx->tx_pkt, d); 826 827 while (!igb_ring_empty(core, txi)) { 828 base = igb_ring_head_descr(core, txi); 829 830 pci_dma_read(d, base, &desc, sizeof(desc)); 831 832 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr, 833 desc.read.cmd_type_len, desc.wb.status); 834 835 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx); 836 igb_ring_advance(core, txi, 1); 837 eic |= igb_txdesc_writeback(core, base, &desc, txi); 838 } 839 840 if (eic) { 841 core->mac[EICR] |= eic; 842 igb_set_interrupt_cause(core, E1000_ICR_TXDW); 843 } 844 } 845 846 static uint32_t 847 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r) 848 { 849 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2]; 850 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK; 851 if (bsizepkt) { 852 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT; 853 } 854 855 return e1000x_rxbufsize(core->mac[RCTL]); 856 } 857 858 static bool 859 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size) 860 { 861 uint32_t bufs = igb_ring_free_descr_num(core, r); 862 uint32_t bufsize = igb_rxbufsize(core, r); 863 864 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize); 865 866 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 867 bufsize; 868 } 869 870 void 871 igb_start_recv(IGBCore *core) 872 { 873 int i; 874 875 trace_e1000e_rx_start_recv(); 876 877 for (i = 0; i <= core->max_queue_num; i++) { 878 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 879 } 880 } 881 882 bool 883 igb_can_receive(IGBCore *core) 884 { 885 int i; 886 887 if (!e1000x_rx_ready(core->owner, core->mac)) { 888 return false; 889 } 890 891 for (i = 0; i < IGB_NUM_QUEUES; i++) { 892 E1000E_RxRing rxr; 893 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { 894 continue; 895 } 896 897 igb_rx_ring_init(core, &rxr, i); 898 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) { 899 trace_e1000e_rx_can_recv(); 900 return true; 901 } 902 } 903 904 trace_e1000e_rx_can_recv_rings_full(); 905 return false; 906 } 907 908 ssize_t 909 igb_receive(IGBCore *core, const uint8_t *buf, size_t size) 910 { 911 const struct iovec iov = { 912 .iov_base = (uint8_t *)buf, 913 .iov_len = size 914 }; 915 916 return igb_receive_iov(core, &iov, 1); 917 } 918 919 static inline bool 920 igb_rx_l3_cso_enabled(IGBCore *core) 921 { 922 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 923 } 924 925 static inline bool 926 igb_rx_l4_cso_enabled(IGBCore *core) 927 { 928 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 929 } 930 931 static bool 932 igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size) 933 { 934 uint16_t pool = qn % IGB_NUM_VM_POOLS; 935 bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE); 936 int max_ethernet_lpe_size = 937 core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK; 938 int max_ethernet_vlan_size = 1522; 939 940 return size > (lpe ? max_ethernet_lpe_size : max_ethernet_vlan_size); 941 } 942 943 static uint16_t igb_receive_assign(IGBCore *core, const struct eth_header *ehdr, 944 size_t size, E1000E_RSSInfo *rss_info, 945 bool *external_tx) 946 { 947 static const int ta_shift[] = { 4, 3, 2, 0 }; 948 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL]; 949 uint16_t queues = 0; 950 uint16_t oversized = 0; 951 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(ehdr)->h_tci) & VLAN_VID_MASK; 952 bool accepted = false; 953 int i; 954 955 memset(rss_info, 0, sizeof(E1000E_RSSInfo)); 956 957 if (external_tx) { 958 *external_tx = true; 959 } 960 961 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) && 962 e1000x_vlan_rx_filter_enabled(core->mac)) { 963 uint32_t vfta = 964 ldl_le_p((uint32_t *)(core->mac + VFTA) + 965 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK)); 966 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) { 967 trace_e1000e_rx_flt_vlan_mismatch(vid); 968 return queues; 969 } else { 970 trace_e1000e_rx_flt_vlan_match(vid); 971 } 972 } 973 974 if (core->mac[MRQC] & 1) { 975 if (is_broadcast_ether_addr(ehdr->h_dest)) { 976 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 977 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) { 978 queues |= BIT(i); 979 } 980 } 981 } else { 982 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) { 983 if (!(macp[1] & E1000_RAH_AV)) { 984 continue; 985 } 986 ra[0] = cpu_to_le32(macp[0]); 987 ra[1] = cpu_to_le32(macp[1]); 988 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 989 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 990 } 991 } 992 993 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 994 if (!(macp[1] & E1000_RAH_AV)) { 995 continue; 996 } 997 ra[0] = cpu_to_le32(macp[0]); 998 ra[1] = cpu_to_le32(macp[1]); 999 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 1000 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 1001 } 1002 } 1003 1004 if (!queues) { 1005 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA); 1006 1007 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; 1008 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff; 1009 if (macp[f >> 5] & (1 << (f & 0x1f))) { 1010 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1011 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) { 1012 queues |= BIT(i); 1013 } 1014 } 1015 } 1016 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) { 1017 *external_tx = false; 1018 } 1019 } 1020 1021 if (e1000x_vlan_rx_filter_enabled(core->mac)) { 1022 uint16_t mask = 0; 1023 1024 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) { 1025 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 1026 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid && 1027 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) { 1028 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK; 1029 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT; 1030 } 1031 } 1032 } else { 1033 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1034 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) { 1035 mask |= BIT(i); 1036 } 1037 } 1038 } 1039 1040 queues &= mask; 1041 } 1042 1043 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx && 1044 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) { 1045 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK; 1046 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT); 1047 } 1048 1049 queues &= core->mac[VFRE]; 1050 if (queues) { 1051 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1052 if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) { 1053 oversized |= BIT(i); 1054 } 1055 } 1056 /* 8.19.37 increment ROC if packet is oversized for all queues */ 1057 if (oversized == queues) { 1058 trace_e1000x_rx_oversized(size); 1059 e1000x_inc_reg_if_not_full(core->mac, ROC); 1060 } 1061 queues &= ~oversized; 1062 } 1063 1064 if (queues) { 1065 igb_rss_parse_packet(core, core->rx_pkt, 1066 external_tx != NULL, rss_info); 1067 /* Sec 8.26.1: PQn = VFn + VQn*8 */ 1068 if (rss_info->queue & 1) { 1069 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1070 if ((queues & BIT(i)) && 1071 (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) { 1072 queues |= BIT(i + IGB_NUM_VM_POOLS); 1073 queues &= ~BIT(i); 1074 } 1075 } 1076 } 1077 } 1078 } else { 1079 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1080 case ETH_PKT_UCAST: 1081 if (rctl & E1000_RCTL_UPE) { 1082 accepted = true; /* promiscuous ucast */ 1083 } 1084 break; 1085 1086 case ETH_PKT_BCAST: 1087 if (rctl & E1000_RCTL_BAM) { 1088 accepted = true; /* broadcast enabled */ 1089 } 1090 break; 1091 1092 case ETH_PKT_MCAST: 1093 if (rctl & E1000_RCTL_MPE) { 1094 accepted = true; /* promiscuous mcast */ 1095 } 1096 break; 1097 1098 default: 1099 g_assert_not_reached(); 1100 } 1101 1102 if (!accepted) { 1103 accepted = e1000x_rx_group_filter(core->mac, ehdr->h_dest); 1104 } 1105 1106 if (!accepted) { 1107 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 1108 if (!(macp[1] & E1000_RAH_AV)) { 1109 continue; 1110 } 1111 ra[0] = cpu_to_le32(macp[0]); 1112 ra[1] = cpu_to_le32(macp[1]); 1113 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 1114 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2, 1115 MAC_ARG(ehdr->h_dest)); 1116 1117 accepted = true; 1118 break; 1119 } 1120 } 1121 } 1122 1123 if (accepted) { 1124 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info); 1125 queues = BIT(rss_info->queue); 1126 } 1127 } 1128 1129 return queues; 1130 } 1131 1132 static inline void 1133 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1134 hwaddr *buff_addr) 1135 { 1136 *buff_addr = le64_to_cpu(desc->buffer_addr); 1137 } 1138 1139 static inline void 1140 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1141 hwaddr *buff_addr) 1142 { 1143 *buff_addr = le64_to_cpu(desc->read.pkt_addr); 1144 } 1145 1146 static inline void 1147 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1148 hwaddr *buff_addr) 1149 { 1150 if (igb_rx_use_legacy_descriptor(core)) { 1151 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr); 1152 } else { 1153 igb_read_adv_rx_descr(core, &desc->adv, buff_addr); 1154 } 1155 } 1156 1157 static void 1158 igb_verify_csum_in_sw(IGBCore *core, 1159 struct NetRxPkt *pkt, 1160 uint32_t *status_flags, 1161 EthL4HdrProto l4hdr_proto) 1162 { 1163 bool csum_valid; 1164 uint32_t csum_error; 1165 1166 if (igb_rx_l3_cso_enabled(core)) { 1167 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1168 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1169 } else { 1170 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1171 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1172 } 1173 } else { 1174 trace_e1000e_rx_metadata_l3_cso_disabled(); 1175 } 1176 1177 if (!igb_rx_l4_cso_enabled(core)) { 1178 trace_e1000e_rx_metadata_l4_cso_disabled(); 1179 return; 1180 } 1181 1182 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1183 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1184 return; 1185 } 1186 1187 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1188 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1189 1190 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1191 *status_flags |= E1000_RXD_STAT_UDPCS; 1192 } 1193 } 1194 1195 static void 1196 igb_build_rx_metadata(IGBCore *core, 1197 struct NetRxPkt *pkt, 1198 bool is_eop, 1199 const E1000E_RSSInfo *rss_info, 1200 uint16_t *pkt_info, uint16_t *hdr_info, 1201 uint32_t *rss, 1202 uint32_t *status_flags, 1203 uint16_t *ip_id, 1204 uint16_t *vlan_tag) 1205 { 1206 struct virtio_net_hdr *vhdr; 1207 bool hasip4, hasip6; 1208 EthL4HdrProto l4hdr_proto; 1209 uint32_t pkt_type; 1210 1211 *status_flags = E1000_RXD_STAT_DD; 1212 1213 /* No additional metadata needed for non-EOP descriptors */ 1214 /* TODO: EOP apply only to status so don't skip whole function. */ 1215 if (!is_eop) { 1216 goto func_exit; 1217 } 1218 1219 *status_flags |= E1000_RXD_STAT_EOP; 1220 1221 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1222 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1223 1224 /* VLAN state */ 1225 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1226 *status_flags |= E1000_RXD_STAT_VP; 1227 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1228 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1229 } 1230 1231 /* Packet parsing results */ 1232 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1233 if (rss_info->enabled) { 1234 *rss = cpu_to_le32(rss_info->hash); 1235 trace_igb_rx_metadata_rss(*rss); 1236 } 1237 } else if (hasip4) { 1238 *status_flags |= E1000_RXD_STAT_IPIDV; 1239 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1240 trace_e1000e_rx_metadata_ip_id(*ip_id); 1241 } 1242 1243 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) { 1244 *status_flags |= E1000_RXD_STAT_ACK; 1245 trace_e1000e_rx_metadata_ack(); 1246 } 1247 1248 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1249 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1250 pkt_type = E1000_RXD_PKT_MAC; 1251 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1252 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1253 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1254 } else if (hasip4 || hasip6) { 1255 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1256 } else { 1257 pkt_type = E1000_RXD_PKT_MAC; 1258 } 1259 1260 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1261 1262 if (pkt_info) { 1263 if (rss_info->enabled) { 1264 *pkt_info = rss_info->type; 1265 } 1266 1267 *pkt_info |= (pkt_type << 4); 1268 } else { 1269 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1270 } 1271 1272 if (hdr_info) { 1273 *hdr_info = 0; 1274 } 1275 1276 /* RX CSO information */ 1277 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1278 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1279 goto func_exit; 1280 } 1281 1282 vhdr = net_rx_pkt_get_vhdr(pkt); 1283 1284 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1285 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1286 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1287 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1288 goto func_exit; 1289 } 1290 1291 if (igb_rx_l3_cso_enabled(core)) { 1292 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1293 } else { 1294 trace_e1000e_rx_metadata_l3_cso_disabled(); 1295 } 1296 1297 if (igb_rx_l4_cso_enabled(core)) { 1298 switch (l4hdr_proto) { 1299 case ETH_L4_HDR_PROTO_TCP: 1300 *status_flags |= E1000_RXD_STAT_TCPCS; 1301 break; 1302 1303 case ETH_L4_HDR_PROTO_UDP: 1304 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1305 break; 1306 1307 default: 1308 goto func_exit; 1309 } 1310 } else { 1311 trace_e1000e_rx_metadata_l4_cso_disabled(); 1312 } 1313 1314 trace_e1000e_rx_metadata_status_flags(*status_flags); 1315 1316 func_exit: 1317 *status_flags = cpu_to_le32(*status_flags); 1318 } 1319 1320 static inline void 1321 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1322 struct NetRxPkt *pkt, 1323 const E1000E_RSSInfo *rss_info, 1324 uint16_t length) 1325 { 1326 uint32_t status_flags, rss; 1327 uint16_t ip_id; 1328 1329 assert(!rss_info->enabled); 1330 desc->length = cpu_to_le16(length); 1331 desc->csum = 0; 1332 1333 igb_build_rx_metadata(core, pkt, pkt != NULL, 1334 rss_info, 1335 NULL, NULL, &rss, 1336 &status_flags, &ip_id, 1337 &desc->special); 1338 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1339 desc->status = (uint8_t) le32_to_cpu(status_flags); 1340 } 1341 1342 static inline void 1343 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1344 struct NetRxPkt *pkt, 1345 const E1000E_RSSInfo *rss_info, 1346 uint16_t length) 1347 { 1348 memset(&desc->wb, 0, sizeof(desc->wb)); 1349 1350 desc->wb.upper.length = cpu_to_le16(length); 1351 1352 igb_build_rx_metadata(core, pkt, pkt != NULL, 1353 rss_info, 1354 &desc->wb.lower.lo_dword.pkt_info, 1355 &desc->wb.lower.lo_dword.hdr_info, 1356 &desc->wb.lower.hi_dword.rss, 1357 &desc->wb.upper.status_error, 1358 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1359 &desc->wb.upper.vlan); 1360 } 1361 1362 static inline void 1363 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1364 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length) 1365 { 1366 if (igb_rx_use_legacy_descriptor(core)) { 1367 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length); 1368 } else { 1369 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length); 1370 } 1371 } 1372 1373 static inline void 1374 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr, 1375 union e1000_rx_desc_union *desc, dma_addr_t len) 1376 { 1377 if (igb_rx_use_legacy_descriptor(core)) { 1378 struct e1000_rx_desc *d = &desc->legacy; 1379 size_t offset = offsetof(struct e1000_rx_desc, status); 1380 uint8_t status = d->status; 1381 1382 d->status &= ~E1000_RXD_STAT_DD; 1383 pci_dma_write(dev, addr, desc, len); 1384 1385 if (status & E1000_RXD_STAT_DD) { 1386 d->status = status; 1387 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1388 } 1389 } else { 1390 union e1000_adv_rx_desc *d = &desc->adv; 1391 size_t offset = 1392 offsetof(union e1000_adv_rx_desc, wb.upper.status_error); 1393 uint32_t status = d->wb.upper.status_error; 1394 1395 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1396 pci_dma_write(dev, addr, desc, len); 1397 1398 if (status & E1000_RXD_STAT_DD) { 1399 d->wb.upper.status_error = status; 1400 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1401 } 1402 } 1403 } 1404 1405 static void 1406 igb_write_to_rx_buffers(IGBCore *core, 1407 PCIDevice *d, 1408 hwaddr ba, 1409 uint16_t *written, 1410 const char *data, 1411 dma_addr_t data_len) 1412 { 1413 trace_igb_rx_desc_buff_write(ba, *written, data, data_len); 1414 pci_dma_write(d, ba + *written, data, data_len); 1415 *written += data_len; 1416 } 1417 1418 static void 1419 igb_update_rx_stats(IGBCore *core, const E1000E_RingInfo *rxi, 1420 size_t data_size, size_t data_fcs_size) 1421 { 1422 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1423 1424 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1425 case ETH_PKT_BCAST: 1426 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1427 break; 1428 1429 case ETH_PKT_MCAST: 1430 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1431 break; 1432 1433 default: 1434 break; 1435 } 1436 1437 if (core->mac[MRQC] & 1) { 1438 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS; 1439 1440 core->mac[PVFGORC0 + (pool * 64)] += data_size + 4; 1441 core->mac[PVFGPRC0 + (pool * 64)]++; 1442 if (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) { 1443 core->mac[PVFMPRC0 + (pool * 64)]++; 1444 } 1445 } 1446 } 1447 1448 static inline bool 1449 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi) 1450 { 1451 return igb_ring_free_descr_num(core, rxi) == 1452 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16; 1453 } 1454 1455 static void 1456 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt, 1457 const E1000E_RxRing *rxr, 1458 const E1000E_RSSInfo *rss_info) 1459 { 1460 PCIDevice *d; 1461 dma_addr_t base; 1462 union e1000_rx_desc_union desc; 1463 size_t desc_size; 1464 size_t desc_offset = 0; 1465 size_t iov_ofs = 0; 1466 1467 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1468 size_t size = net_rx_pkt_get_total_len(pkt); 1469 size_t total_size = size + e1000x_fcs_len(core->mac); 1470 const E1000E_RingInfo *rxi = rxr->i; 1471 size_t bufsize = igb_rxbufsize(core, rxi); 1472 1473 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8); 1474 if (!d) { 1475 d = core->owner; 1476 } 1477 1478 do { 1479 hwaddr ba; 1480 uint16_t written = 0; 1481 bool is_last = false; 1482 1483 desc_size = total_size - desc_offset; 1484 1485 if (desc_size > bufsize) { 1486 desc_size = bufsize; 1487 } 1488 1489 if (igb_ring_empty(core, rxi)) { 1490 return; 1491 } 1492 1493 base = igb_ring_head_descr(core, rxi); 1494 1495 pci_dma_read(d, base, &desc, core->rx_desc_len); 1496 1497 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1498 1499 igb_read_rx_descr(core, &desc, &ba); 1500 1501 if (ba) { 1502 if (desc_offset < size) { 1503 static const uint32_t fcs_pad; 1504 size_t iov_copy; 1505 size_t copy_size = size - desc_offset; 1506 if (copy_size > bufsize) { 1507 copy_size = bufsize; 1508 } 1509 1510 /* Copy packet payload */ 1511 while (copy_size) { 1512 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1513 1514 igb_write_to_rx_buffers(core, d, ba, &written, 1515 iov->iov_base + iov_ofs, iov_copy); 1516 1517 copy_size -= iov_copy; 1518 iov_ofs += iov_copy; 1519 if (iov_ofs == iov->iov_len) { 1520 iov++; 1521 iov_ofs = 0; 1522 } 1523 } 1524 1525 if (desc_offset + desc_size >= total_size) { 1526 /* Simulate FCS checksum presence in the last descriptor */ 1527 igb_write_to_rx_buffers(core, d, ba, &written, 1528 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1529 } 1530 } 1531 } else { /* as per intel docs; skip descriptors with null buf addr */ 1532 trace_e1000e_rx_null_descriptor(); 1533 } 1534 desc_offset += desc_size; 1535 if (desc_offset >= total_size) { 1536 is_last = true; 1537 } 1538 1539 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1540 rss_info, written); 1541 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len); 1542 1543 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1544 1545 } while (desc_offset < total_size); 1546 1547 igb_update_rx_stats(core, rxi, size, total_size); 1548 } 1549 1550 static inline void 1551 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt) 1552 { 1553 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1554 1555 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1556 net_rx_pkt_fix_l4_csum(pkt); 1557 } 1558 } 1559 1560 ssize_t 1561 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt) 1562 { 1563 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL); 1564 } 1565 1566 static ssize_t 1567 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 1568 bool has_vnet, bool *external_tx) 1569 { 1570 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4); 1571 1572 uint16_t queues = 0; 1573 uint32_t n = 0; 1574 uint8_t min_buf[ETH_ZLEN]; 1575 struct iovec min_iov; 1576 struct eth_header *ehdr; 1577 uint8_t *filter_buf; 1578 size_t size, orig_size; 1579 size_t iov_ofs = 0; 1580 E1000E_RxRing rxr; 1581 E1000E_RSSInfo rss_info; 1582 size_t total_size; 1583 int i; 1584 1585 trace_e1000e_rx_receive_iov(iovcnt); 1586 1587 if (external_tx) { 1588 *external_tx = true; 1589 } 1590 1591 if (!e1000x_hw_rx_enabled(core->mac)) { 1592 return -1; 1593 } 1594 1595 /* Pull virtio header in */ 1596 if (has_vnet) { 1597 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1598 iov_ofs = sizeof(struct virtio_net_hdr); 1599 } else { 1600 net_rx_pkt_unset_vhdr(core->rx_pkt); 1601 } 1602 1603 filter_buf = iov->iov_base + iov_ofs; 1604 orig_size = iov_size(iov, iovcnt); 1605 size = orig_size - iov_ofs; 1606 1607 /* Pad to minimum Ethernet frame length */ 1608 if (size < sizeof(min_buf)) { 1609 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1610 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1611 e1000x_inc_reg_if_not_full(core->mac, RUC); 1612 min_iov.iov_base = filter_buf = min_buf; 1613 min_iov.iov_len = size = sizeof(min_buf); 1614 iovcnt = 1; 1615 iov = &min_iov; 1616 iov_ofs = 0; 1617 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1618 /* This is very unlikely, but may happen. */ 1619 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1620 filter_buf = min_buf; 1621 } 1622 1623 /* Discard oversized packets if !LPE and !SBP. */ 1624 if (e1000x_is_oversized(core->mac, size)) { 1625 return orig_size; 1626 } 1627 1628 ehdr = PKT_GET_ETH_HDR(filter_buf); 1629 net_rx_pkt_set_packet_type(core->rx_pkt, get_eth_packet_type(ehdr)); 1630 1631 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1632 e1000x_vlan_enabled(core->mac), 1633 core->mac[VET] & 0xffff); 1634 1635 queues = igb_receive_assign(core, ehdr, size, &rss_info, external_tx); 1636 if (!queues) { 1637 trace_e1000e_rx_flt_dropped(); 1638 return orig_size; 1639 } 1640 1641 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1642 e1000x_fcs_len(core->mac); 1643 1644 for (i = 0; i < IGB_NUM_QUEUES; i++) { 1645 if (!(queues & BIT(i)) || 1646 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { 1647 continue; 1648 } 1649 1650 igb_rx_ring_init(core, &rxr, i); 1651 1652 if (!igb_has_rxbufs(core, rxr.i, total_size)) { 1653 n |= E1000_ICS_RXO; 1654 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1655 continue; 1656 } 1657 1658 n |= E1000_ICR_RXDW; 1659 1660 igb_rx_fix_l4_csum(core, core->rx_pkt); 1661 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1662 1663 /* Check if receive descriptor minimum threshold hit */ 1664 if (igb_rx_descr_threshold_hit(core, rxr.i)) { 1665 n |= E1000_ICS_RXDMT0; 1666 } 1667 1668 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx); 1669 1670 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1671 } 1672 1673 trace_e1000e_rx_interrupt_set(n); 1674 igb_set_interrupt_cause(core, n); 1675 1676 return orig_size; 1677 } 1678 1679 static inline bool 1680 igb_have_autoneg(IGBCore *core) 1681 { 1682 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN; 1683 } 1684 1685 static void igb_update_flowctl_status(IGBCore *core) 1686 { 1687 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) { 1688 trace_e1000e_link_autoneg_flowctl(true); 1689 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1690 } else { 1691 trace_e1000e_link_autoneg_flowctl(false); 1692 } 1693 } 1694 1695 static inline void 1696 igb_link_down(IGBCore *core) 1697 { 1698 e1000x_update_regs_on_link_down(core->mac, core->phy); 1699 igb_update_flowctl_status(core); 1700 } 1701 1702 static inline void 1703 igb_set_phy_ctrl(IGBCore *core, uint16_t val) 1704 { 1705 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1706 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART); 1707 1708 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) { 1709 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer); 1710 } 1711 } 1712 1713 void igb_core_set_link_status(IGBCore *core) 1714 { 1715 NetClientState *nc = qemu_get_queue(core->owner_nic); 1716 uint32_t old_status = core->mac[STATUS]; 1717 1718 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1719 1720 if (nc->link_down) { 1721 e1000x_update_regs_on_link_down(core->mac, core->phy); 1722 } else { 1723 if (igb_have_autoneg(core) && 1724 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 1725 e1000x_restart_autoneg(core->mac, core->phy, 1726 core->autoneg_timer); 1727 } else { 1728 e1000x_update_regs_on_link_up(core->mac, core->phy); 1729 igb_start_recv(core); 1730 } 1731 } 1732 1733 if (core->mac[STATUS] != old_status) { 1734 igb_set_interrupt_cause(core, E1000_ICR_LSC); 1735 } 1736 } 1737 1738 static void 1739 igb_set_ctrl(IGBCore *core, int index, uint32_t val) 1740 { 1741 trace_e1000e_core_ctrl_write(index, val); 1742 1743 /* RST is self clearing */ 1744 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1745 core->mac[CTRL_DUP] = core->mac[CTRL]; 1746 1747 trace_e1000e_link_set_params( 1748 !!(val & E1000_CTRL_ASDE), 1749 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1750 !!(val & E1000_CTRL_FRCSPD), 1751 !!(val & E1000_CTRL_FRCDPX), 1752 !!(val & E1000_CTRL_RFCE), 1753 !!(val & E1000_CTRL_TFCE)); 1754 1755 if (val & E1000_CTRL_RST) { 1756 trace_e1000e_core_ctrl_sw_reset(); 1757 igb_reset(core, true); 1758 } 1759 1760 if (val & E1000_CTRL_PHY_RST) { 1761 trace_e1000e_core_ctrl_phy_reset(); 1762 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1763 } 1764 } 1765 1766 static void 1767 igb_set_rfctl(IGBCore *core, int index, uint32_t val) 1768 { 1769 trace_e1000e_rx_set_rfctl(val); 1770 1771 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1772 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1773 } 1774 1775 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1776 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1777 } 1778 1779 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1780 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1781 } 1782 1783 core->mac[RFCTL] = val; 1784 } 1785 1786 static void 1787 igb_calc_rxdesclen(IGBCore *core) 1788 { 1789 if (igb_rx_use_legacy_descriptor(core)) { 1790 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1791 } else { 1792 core->rx_desc_len = sizeof(union e1000_adv_rx_desc); 1793 } 1794 trace_e1000e_rx_desc_len(core->rx_desc_len); 1795 } 1796 1797 static void 1798 igb_set_rx_control(IGBCore *core, int index, uint32_t val) 1799 { 1800 core->mac[RCTL] = val; 1801 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1802 1803 if (val & E1000_RCTL_DTYP_MASK) { 1804 qemu_log_mask(LOG_GUEST_ERROR, 1805 "igb: RCTL.DTYP must be zero for compatibility"); 1806 } 1807 1808 if (val & E1000_RCTL_EN) { 1809 igb_calc_rxdesclen(core); 1810 igb_start_recv(core); 1811 } 1812 } 1813 1814 static inline void 1815 igb_clear_ims_bits(IGBCore *core, uint32_t bits) 1816 { 1817 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1818 core->mac[IMS] &= ~bits; 1819 } 1820 1821 static inline bool 1822 igb_postpone_interrupt(IGBIntrDelayTimer *timer) 1823 { 1824 if (timer->running) { 1825 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1826 1827 return true; 1828 } 1829 1830 if (timer->core->mac[timer->delay_reg] != 0) { 1831 igb_intrmgr_rearm_timer(timer); 1832 } 1833 1834 return false; 1835 } 1836 1837 static inline bool 1838 igb_eitr_should_postpone(IGBCore *core, int idx) 1839 { 1840 return igb_postpone_interrupt(&core->eitr[idx]); 1841 } 1842 1843 static void igb_send_msix(IGBCore *core) 1844 { 1845 uint32_t causes = core->mac[EICR] & core->mac[EIMS]; 1846 uint32_t effective_eiac; 1847 int vector; 1848 1849 for (vector = 0; vector < IGB_INTR_NUM; ++vector) { 1850 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) { 1851 1852 trace_e1000e_irq_msix_notify_vec(vector); 1853 igb_msix_notify(core, vector); 1854 1855 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]); 1856 effective_eiac = core->mac[EIAC] & BIT(vector); 1857 core->mac[EICR] &= ~effective_eiac; 1858 } 1859 } 1860 } 1861 1862 static inline void 1863 igb_fix_icr_asserted(IGBCore *core) 1864 { 1865 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 1866 if (core->mac[ICR]) { 1867 core->mac[ICR] |= E1000_ICR_ASSERTED; 1868 } 1869 1870 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 1871 } 1872 1873 static void 1874 igb_update_interrupt_state(IGBCore *core) 1875 { 1876 uint32_t icr; 1877 uint32_t causes; 1878 uint32_t int_alloc; 1879 1880 icr = core->mac[ICR] & core->mac[IMS]; 1881 1882 if (msix_enabled(core->owner)) { 1883 if (icr) { 1884 causes = 0; 1885 if (icr & E1000_ICR_DRSTA) { 1886 int_alloc = core->mac[IVAR_MISC] & 0xff; 1887 if (int_alloc & E1000_IVAR_VALID) { 1888 causes |= BIT(int_alloc & 0x1f); 1889 } 1890 } 1891 /* Check if other bits (excluding the TCP Timer) are enabled. */ 1892 if (icr & ~E1000_ICR_DRSTA) { 1893 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff; 1894 if (int_alloc & E1000_IVAR_VALID) { 1895 causes |= BIT(int_alloc & 0x1f); 1896 } 1897 trace_e1000e_irq_add_msi_other(core->mac[EICR]); 1898 } 1899 core->mac[EICR] |= causes; 1900 } 1901 1902 if ((core->mac[EICR] & core->mac[EIMS])) { 1903 igb_send_msix(core); 1904 } 1905 } else { 1906 igb_fix_icr_asserted(core); 1907 1908 if (icr) { 1909 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER; 1910 } else { 1911 core->mac[EICR] &= ~E1000_EICR_OTHER; 1912 } 1913 1914 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 1915 core->mac[ICR], core->mac[IMS]); 1916 1917 if (msi_enabled(core->owner)) { 1918 if (icr) { 1919 msi_notify(core->owner, 0); 1920 } 1921 } else { 1922 if (icr) { 1923 igb_raise_legacy_irq(core); 1924 } else { 1925 igb_lower_legacy_irq(core); 1926 } 1927 } 1928 } 1929 } 1930 1931 static void 1932 igb_set_interrupt_cause(IGBCore *core, uint32_t val) 1933 { 1934 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 1935 1936 core->mac[ICR] |= val; 1937 1938 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 1939 1940 igb_update_interrupt_state(core); 1941 } 1942 1943 static void igb_set_eics(IGBCore *core, int index, uint32_t val) 1944 { 1945 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1946 1947 trace_igb_irq_write_eics(val, msix); 1948 1949 core->mac[EICS] |= 1950 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1951 1952 /* 1953 * TODO: Move to igb_update_interrupt_state if EICS is modified in other 1954 * places. 1955 */ 1956 core->mac[EICR] = core->mac[EICS]; 1957 1958 igb_update_interrupt_state(core); 1959 } 1960 1961 static void igb_set_eims(IGBCore *core, int index, uint32_t val) 1962 { 1963 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1964 1965 trace_igb_irq_write_eims(val, msix); 1966 1967 core->mac[EIMS] |= 1968 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1969 1970 igb_update_interrupt_state(core); 1971 } 1972 1973 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) 1974 { 1975 uint32_t ent = core->mac[VTIVAR_MISC + vfn]; 1976 1977 if ((ent & E1000_IVAR_VALID)) { 1978 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM); 1979 igb_update_interrupt_state(core); 1980 } 1981 } 1982 1983 static void mailbox_interrupt_to_pf(IGBCore *core) 1984 { 1985 igb_set_interrupt_cause(core, E1000_ICR_VMMB); 1986 } 1987 1988 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val) 1989 { 1990 uint16_t vfn = index - P2VMAILBOX0; 1991 1992 trace_igb_set_pfmailbox(vfn, val); 1993 1994 if (val & E1000_P2VMAILBOX_STS) { 1995 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS; 1996 mailbox_interrupt_to_vf(core, vfn); 1997 } 1998 1999 if (val & E1000_P2VMAILBOX_ACK) { 2000 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK; 2001 mailbox_interrupt_to_vf(core, vfn); 2002 } 2003 2004 /* Buffer Taken by PF (can be set only if the VFU is cleared). */ 2005 if (val & E1000_P2VMAILBOX_PFU) { 2006 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) { 2007 core->mac[index] |= E1000_P2VMAILBOX_PFU; 2008 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU; 2009 } 2010 } else { 2011 core->mac[index] &= ~E1000_P2VMAILBOX_PFU; 2012 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU; 2013 } 2014 2015 if (val & E1000_P2VMAILBOX_RVFU) { 2016 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU; 2017 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) | 2018 (E1000_MBVFICR_VFREQ_VF1 << vfn)); 2019 } 2020 } 2021 2022 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) 2023 { 2024 uint16_t vfn = index - V2PMAILBOX0; 2025 2026 trace_igb_set_vfmailbox(vfn, val); 2027 2028 if (val & E1000_V2PMAILBOX_REQ) { 2029 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn; 2030 mailbox_interrupt_to_pf(core); 2031 } 2032 2033 if (val & E1000_V2PMAILBOX_ACK) { 2034 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn; 2035 mailbox_interrupt_to_pf(core); 2036 } 2037 2038 /* Buffer Taken by VF (can be set only if the PFU is cleared). */ 2039 if (val & E1000_V2PMAILBOX_VFU) { 2040 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) { 2041 core->mac[index] |= E1000_V2PMAILBOX_VFU; 2042 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU; 2043 } 2044 } else { 2045 core->mac[index] &= ~E1000_V2PMAILBOX_VFU; 2046 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU; 2047 } 2048 } 2049 2050 static void igb_vf_reset(IGBCore *core, uint16_t vfn) 2051 { 2052 uint16_t qn0 = vfn; 2053 uint16_t qn1 = vfn + IGB_NUM_VM_POOLS; 2054 2055 /* disable Rx and Tx for the VF*/ 2056 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; 2057 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; 2058 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; 2059 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; 2060 core->mac[VFRE] &= ~BIT(vfn); 2061 core->mac[VFTE] &= ~BIT(vfn); 2062 /* indicate VF reset to PF */ 2063 core->mac[VFLRE] |= BIT(vfn); 2064 /* VFLRE and mailbox use the same interrupt cause */ 2065 mailbox_interrupt_to_pf(core); 2066 } 2067 2068 static void igb_w1c(IGBCore *core, int index, uint32_t val) 2069 { 2070 core->mac[index] &= ~val; 2071 } 2072 2073 static void igb_set_eimc(IGBCore *core, int index, uint32_t val) 2074 { 2075 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2076 2077 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */ 2078 core->mac[EIMS] &= 2079 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2080 2081 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix); 2082 igb_update_interrupt_state(core); 2083 } 2084 2085 static void igb_set_eiac(IGBCore *core, int index, uint32_t val) 2086 { 2087 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2088 2089 if (msix) { 2090 trace_igb_irq_write_eiac(val); 2091 2092 /* 2093 * TODO: When using IOV, the bits that correspond to MSI-X vectors 2094 * that are assigned to a VF are read-only. 2095 */ 2096 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK); 2097 } 2098 } 2099 2100 static void igb_set_eiam(IGBCore *core, int index, uint32_t val) 2101 { 2102 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2103 2104 /* 2105 * TODO: When using IOV, the bits that correspond to MSI-X vectors that 2106 * are assigned to a VF are read-only. 2107 */ 2108 core->mac[EIAM] |= 2109 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2110 2111 trace_igb_irq_write_eiam(val, msix); 2112 } 2113 2114 static void igb_set_eicr(IGBCore *core, int index, uint32_t val) 2115 { 2116 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2117 2118 /* 2119 * TODO: In IOV mode, only bit zero of this vector is available for the PF 2120 * function. 2121 */ 2122 core->mac[EICR] &= 2123 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2124 2125 trace_igb_irq_write_eicr(val, msix); 2126 igb_update_interrupt_state(core); 2127 } 2128 2129 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val) 2130 { 2131 uint16_t vfn; 2132 2133 if (val & E1000_CTRL_RST) { 2134 vfn = (index - PVTCTRL0) / 0x40; 2135 igb_vf_reset(core, vfn); 2136 } 2137 } 2138 2139 static void igb_set_vteics(IGBCore *core, int index, uint32_t val) 2140 { 2141 uint16_t vfn = (index - PVTEICS0) / 0x40; 2142 2143 core->mac[index] = val; 2144 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2145 } 2146 2147 static void igb_set_vteims(IGBCore *core, int index, uint32_t val) 2148 { 2149 uint16_t vfn = (index - PVTEIMS0) / 0x40; 2150 2151 core->mac[index] = val; 2152 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2153 } 2154 2155 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val) 2156 { 2157 uint16_t vfn = (index - PVTEIMC0) / 0x40; 2158 2159 core->mac[index] = val; 2160 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2161 } 2162 2163 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val) 2164 { 2165 uint16_t vfn = (index - PVTEIAC0) / 0x40; 2166 2167 core->mac[index] = val; 2168 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2169 } 2170 2171 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val) 2172 { 2173 uint16_t vfn = (index - PVTEIAM0) / 0x40; 2174 2175 core->mac[index] = val; 2176 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2177 } 2178 2179 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val) 2180 { 2181 uint16_t vfn = (index - PVTEICR0) / 0x40; 2182 2183 core->mac[index] = val; 2184 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2185 } 2186 2187 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val) 2188 { 2189 uint16_t vfn = (index - VTIVAR); 2190 uint16_t qn = vfn; 2191 uint8_t ent; 2192 int n; 2193 2194 core->mac[index] = val; 2195 2196 /* Get assigned vector associated with queue Rx#0. */ 2197 if ((val & E1000_IVAR_VALID)) { 2198 n = igb_ivar_entry_rx(qn); 2199 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7))); 2200 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2201 } 2202 2203 /* Get assigned vector associated with queue Tx#0 */ 2204 ent = val >> 8; 2205 if ((ent & E1000_IVAR_VALID)) { 2206 n = igb_ivar_entry_tx(qn); 2207 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7))); 2208 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2209 } 2210 2211 /* 2212 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now. 2213 */ 2214 } 2215 2216 static inline void 2217 igb_autoneg_timer(void *opaque) 2218 { 2219 IGBCore *core = opaque; 2220 if (!qemu_get_queue(core->owner_nic)->link_down) { 2221 e1000x_update_regs_on_autoneg_done(core->mac, core->phy); 2222 igb_start_recv(core); 2223 2224 igb_update_flowctl_status(core); 2225 /* signal link status change to the guest */ 2226 igb_set_interrupt_cause(core, E1000_ICR_LSC); 2227 } 2228 } 2229 2230 static inline uint16_t 2231 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2232 { 2233 uint16_t index = (addr & 0x1ffff) >> 2; 2234 return index + (mac_reg_access[index] & 0xfffe); 2235 } 2236 2237 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = { 2238 [MII_BMCR] = PHY_RW, 2239 [MII_BMSR] = PHY_R, 2240 [MII_PHYID1] = PHY_R, 2241 [MII_PHYID2] = PHY_R, 2242 [MII_ANAR] = PHY_RW, 2243 [MII_ANLPAR] = PHY_R, 2244 [MII_ANER] = PHY_R, 2245 [MII_ANNP] = PHY_RW, 2246 [MII_ANLPRNP] = PHY_R, 2247 [MII_CTRL1000] = PHY_RW, 2248 [MII_STAT1000] = PHY_R, 2249 [MII_EXTSTAT] = PHY_R, 2250 2251 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW, 2252 [IGP01E1000_PHY_PORT_STATUS] = PHY_R, 2253 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW, 2254 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R, 2255 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW, 2256 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W 2257 }; 2258 2259 static void 2260 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data) 2261 { 2262 assert(addr <= MAX_PHY_REG_ADDRESS); 2263 2264 if (addr == MII_BMCR) { 2265 igb_set_phy_ctrl(core, data); 2266 } else { 2267 core->phy[addr] = data; 2268 } 2269 } 2270 2271 static void 2272 igb_set_mdic(IGBCore *core, int index, uint32_t val) 2273 { 2274 uint32_t data = val & E1000_MDIC_DATA_MASK; 2275 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2276 2277 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2278 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2279 } else if (val & E1000_MDIC_OP_READ) { 2280 if (!(igb_phy_regcap[addr] & PHY_R)) { 2281 trace_igb_core_mdic_read_unhandled(addr); 2282 val |= E1000_MDIC_ERROR; 2283 } else { 2284 val = (val ^ data) | core->phy[addr]; 2285 trace_igb_core_mdic_read(addr, val); 2286 } 2287 } else if (val & E1000_MDIC_OP_WRITE) { 2288 if (!(igb_phy_regcap[addr] & PHY_W)) { 2289 trace_igb_core_mdic_write_unhandled(addr); 2290 val |= E1000_MDIC_ERROR; 2291 } else { 2292 trace_igb_core_mdic_write(addr, data); 2293 igb_phy_reg_write(core, addr, data); 2294 } 2295 } 2296 core->mac[MDIC] = val | E1000_MDIC_READY; 2297 2298 if (val & E1000_MDIC_INT_EN) { 2299 igb_set_interrupt_cause(core, E1000_ICR_MDAC); 2300 } 2301 } 2302 2303 static void 2304 igb_set_rdt(IGBCore *core, int index, uint32_t val) 2305 { 2306 core->mac[index] = val & 0xffff; 2307 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val); 2308 igb_start_recv(core); 2309 } 2310 2311 static void 2312 igb_set_status(IGBCore *core, int index, uint32_t val) 2313 { 2314 if ((val & E1000_STATUS_PHYRA) == 0) { 2315 core->mac[index] &= ~E1000_STATUS_PHYRA; 2316 } 2317 } 2318 2319 static void 2320 igb_set_ctrlext(IGBCore *core, int index, uint32_t val) 2321 { 2322 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2323 !!(val & E1000_CTRL_EXT_SPD_BYPS), 2324 !!(val & E1000_CTRL_EXT_PFRSTD)); 2325 2326 /* Zero self-clearing bits */ 2327 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2328 core->mac[CTRL_EXT] = val; 2329 2330 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) { 2331 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 2332 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; 2333 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD; 2334 } 2335 } 2336 } 2337 2338 static void 2339 igb_set_pbaclr(IGBCore *core, int index, uint32_t val) 2340 { 2341 int i; 2342 2343 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2344 2345 if (!msix_enabled(core->owner)) { 2346 return; 2347 } 2348 2349 for (i = 0; i < IGB_INTR_NUM; i++) { 2350 if (core->mac[PBACLR] & BIT(i)) { 2351 msix_clr_pending(core->owner, i); 2352 } 2353 } 2354 } 2355 2356 static void 2357 igb_set_fcrth(IGBCore *core, int index, uint32_t val) 2358 { 2359 core->mac[FCRTH] = val & 0xFFF8; 2360 } 2361 2362 static void 2363 igb_set_fcrtl(IGBCore *core, int index, uint32_t val) 2364 { 2365 core->mac[FCRTL] = val & 0x8000FFF8; 2366 } 2367 2368 #define IGB_LOW_BITS_SET_FUNC(num) \ 2369 static void \ 2370 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \ 2371 { \ 2372 core->mac[index] = val & (BIT(num) - 1); \ 2373 } 2374 2375 IGB_LOW_BITS_SET_FUNC(4) 2376 IGB_LOW_BITS_SET_FUNC(13) 2377 IGB_LOW_BITS_SET_FUNC(16) 2378 2379 static void 2380 igb_set_dlen(IGBCore *core, int index, uint32_t val) 2381 { 2382 core->mac[index] = val & 0xffff0; 2383 } 2384 2385 static void 2386 igb_set_dbal(IGBCore *core, int index, uint32_t val) 2387 { 2388 core->mac[index] = val & E1000_XDBAL_MASK; 2389 } 2390 2391 static void 2392 igb_set_tdt(IGBCore *core, int index, uint32_t val) 2393 { 2394 IGB_TxRing txr; 2395 int qn = igb_mq_queue_idx(TDT0, index); 2396 2397 core->mac[index] = val & 0xffff; 2398 2399 igb_tx_ring_init(core, &txr, qn); 2400 igb_start_xmit(core, &txr); 2401 } 2402 2403 static void 2404 igb_set_ics(IGBCore *core, int index, uint32_t val) 2405 { 2406 trace_e1000e_irq_write_ics(val); 2407 igb_set_interrupt_cause(core, val); 2408 } 2409 2410 static void 2411 igb_set_imc(IGBCore *core, int index, uint32_t val) 2412 { 2413 trace_e1000e_irq_ims_clear_set_imc(val); 2414 igb_clear_ims_bits(core, val); 2415 igb_update_interrupt_state(core); 2416 } 2417 2418 static void 2419 igb_set_ims(IGBCore *core, int index, uint32_t val) 2420 { 2421 uint32_t valid_val = val & 0x77D4FBFD; 2422 2423 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2424 core->mac[IMS] |= valid_val; 2425 igb_update_interrupt_state(core); 2426 } 2427 2428 static void igb_commit_icr(IGBCore *core) 2429 { 2430 /* 2431 * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at 2432 * least one bit is set in the IMS and there is a true interrupt as 2433 * reflected in ICR.INTA. 2434 */ 2435 if ((core->mac[GPIE] & E1000_GPIE_NSICR) || 2436 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) { 2437 igb_set_ims(core, IMS, core->mac[IAM]); 2438 } else { 2439 igb_update_interrupt_state(core); 2440 } 2441 } 2442 2443 static void igb_set_icr(IGBCore *core, int index, uint32_t val) 2444 { 2445 uint32_t icr = core->mac[ICR] & ~val; 2446 2447 trace_igb_irq_icr_write(val, core->mac[ICR], icr); 2448 core->mac[ICR] = icr; 2449 igb_commit_icr(core); 2450 } 2451 2452 static uint32_t 2453 igb_mac_readreg(IGBCore *core, int index) 2454 { 2455 return core->mac[index]; 2456 } 2457 2458 static uint32_t 2459 igb_mac_ics_read(IGBCore *core, int index) 2460 { 2461 trace_e1000e_irq_read_ics(core->mac[ICS]); 2462 return core->mac[ICS]; 2463 } 2464 2465 static uint32_t 2466 igb_mac_ims_read(IGBCore *core, int index) 2467 { 2468 trace_e1000e_irq_read_ims(core->mac[IMS]); 2469 return core->mac[IMS]; 2470 } 2471 2472 static uint32_t 2473 igb_mac_swsm_read(IGBCore *core, int index) 2474 { 2475 uint32_t val = core->mac[SWSM]; 2476 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2477 return val; 2478 } 2479 2480 static uint32_t 2481 igb_mac_eitr_read(IGBCore *core, int index) 2482 { 2483 return core->eitr_guest_value[index - EITR0]; 2484 } 2485 2486 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index) 2487 { 2488 uint32_t val = core->mac[index]; 2489 2490 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK | 2491 E1000_V2PMAILBOX_RSTD); 2492 2493 return val; 2494 } 2495 2496 static uint32_t 2497 igb_mac_icr_read(IGBCore *core, int index) 2498 { 2499 uint32_t ret = core->mac[ICR]; 2500 trace_e1000e_irq_icr_read_entry(ret); 2501 2502 if (core->mac[GPIE] & E1000_GPIE_NSICR) { 2503 trace_igb_irq_icr_clear_gpie_nsicr(); 2504 core->mac[ICR] = 0; 2505 } else if (core->mac[IMS] == 0) { 2506 trace_e1000e_irq_icr_clear_zero_ims(); 2507 core->mac[ICR] = 0; 2508 } else if (!msix_enabled(core->owner)) { 2509 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2510 core->mac[ICR] = 0; 2511 } 2512 2513 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2514 igb_commit_icr(core); 2515 return ret; 2516 } 2517 2518 static uint32_t 2519 igb_mac_read_clr4(IGBCore *core, int index) 2520 { 2521 uint32_t ret = core->mac[index]; 2522 2523 core->mac[index] = 0; 2524 return ret; 2525 } 2526 2527 static uint32_t 2528 igb_mac_read_clr8(IGBCore *core, int index) 2529 { 2530 uint32_t ret = core->mac[index]; 2531 2532 core->mac[index] = 0; 2533 core->mac[index - 1] = 0; 2534 return ret; 2535 } 2536 2537 static uint32_t 2538 igb_get_ctrl(IGBCore *core, int index) 2539 { 2540 uint32_t val = core->mac[CTRL]; 2541 2542 trace_e1000e_link_read_params( 2543 !!(val & E1000_CTRL_ASDE), 2544 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2545 !!(val & E1000_CTRL_FRCSPD), 2546 !!(val & E1000_CTRL_FRCDPX), 2547 !!(val & E1000_CTRL_RFCE), 2548 !!(val & E1000_CTRL_TFCE)); 2549 2550 return val; 2551 } 2552 2553 static uint32_t igb_get_status(IGBCore *core, int index) 2554 { 2555 uint32_t res = core->mac[STATUS]; 2556 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner); 2557 2558 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2559 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2560 } else { 2561 res |= E1000_STATUS_FD; 2562 } 2563 2564 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2565 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2566 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2567 case E1000_CTRL_SPD_10: 2568 res |= E1000_STATUS_SPEED_10; 2569 break; 2570 case E1000_CTRL_SPD_100: 2571 res |= E1000_STATUS_SPEED_100; 2572 break; 2573 case E1000_CTRL_SPD_1000: 2574 default: 2575 res |= E1000_STATUS_SPEED_1000; 2576 break; 2577 } 2578 } else { 2579 res |= E1000_STATUS_SPEED_1000; 2580 } 2581 2582 if (num_vfs) { 2583 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT; 2584 res |= E1000_STATUS_IOV_MODE; 2585 } 2586 2587 /* 2588 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is 2589 * left set after E1000_CTRL_LRST is set. 2590 */ 2591 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) && 2592 !(core->mac[CTRL] & E1000_CTRL_LRST)) { 2593 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2594 } 2595 2596 return res; 2597 } 2598 2599 static void 2600 igb_mac_writereg(IGBCore *core, int index, uint32_t val) 2601 { 2602 core->mac[index] = val; 2603 } 2604 2605 static void 2606 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val) 2607 { 2608 uint32_t macaddr[2]; 2609 2610 core->mac[index] = val; 2611 2612 macaddr[0] = cpu_to_le32(core->mac[RA]); 2613 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2614 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2615 (uint8_t *) macaddr); 2616 2617 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2618 } 2619 2620 static void 2621 igb_set_eecd(IGBCore *core, int index, uint32_t val) 2622 { 2623 static const uint32_t ro_bits = E1000_EECD_PRES | 2624 E1000_EECD_AUTO_RD | 2625 E1000_EECD_SIZE_EX_MASK; 2626 2627 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2628 } 2629 2630 static void 2631 igb_set_eerd(IGBCore *core, int index, uint32_t val) 2632 { 2633 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2634 uint32_t flags = 0; 2635 uint32_t data = 0; 2636 2637 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2638 data = core->eeprom[addr]; 2639 flags = E1000_EERW_DONE; 2640 } 2641 2642 core->mac[EERD] = flags | 2643 (addr << E1000_EERW_ADDR_SHIFT) | 2644 (data << E1000_EERW_DATA_SHIFT); 2645 } 2646 2647 static void 2648 igb_set_eitr(IGBCore *core, int index, uint32_t val) 2649 { 2650 uint32_t eitr_num = index - EITR0; 2651 2652 trace_igb_irq_eitr_set(eitr_num, val); 2653 2654 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR; 2655 core->mac[index] = val & 0x7FFE; 2656 } 2657 2658 static void 2659 igb_update_rx_offloads(IGBCore *core) 2660 { 2661 int cso_state = igb_rx_l4_cso_enabled(core); 2662 2663 trace_e1000e_rx_set_cso(cso_state); 2664 2665 if (core->has_vnet) { 2666 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2667 cso_state, 0, 0, 0, 0); 2668 } 2669 } 2670 2671 static void 2672 igb_set_rxcsum(IGBCore *core, int index, uint32_t val) 2673 { 2674 core->mac[RXCSUM] = val; 2675 igb_update_rx_offloads(core); 2676 } 2677 2678 static void 2679 igb_set_gcr(IGBCore *core, int index, uint32_t val) 2680 { 2681 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2682 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2683 } 2684 2685 static uint32_t igb_get_systiml(IGBCore *core, int index) 2686 { 2687 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2688 return core->mac[SYSTIML]; 2689 } 2690 2691 static uint32_t igb_get_rxsatrh(IGBCore *core, int index) 2692 { 2693 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2694 return core->mac[RXSATRH]; 2695 } 2696 2697 static uint32_t igb_get_txstmph(IGBCore *core, int index) 2698 { 2699 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2700 return core->mac[TXSTMPH]; 2701 } 2702 2703 static void igb_set_timinca(IGBCore *core, int index, uint32_t val) 2704 { 2705 e1000x_set_timinca(core->mac, &core->timadj, val); 2706 } 2707 2708 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val) 2709 { 2710 core->mac[TIMADJH] = val; 2711 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2712 } 2713 2714 #define igb_getreg(x) [x] = igb_mac_readreg 2715 typedef uint32_t (*readops)(IGBCore *, int); 2716 static const readops igb_macreg_readops[] = { 2717 igb_getreg(WUFC), 2718 igb_getreg(MANC), 2719 igb_getreg(TOTL), 2720 igb_getreg(RDT0), 2721 igb_getreg(RDT1), 2722 igb_getreg(RDT2), 2723 igb_getreg(RDT3), 2724 igb_getreg(RDT4), 2725 igb_getreg(RDT5), 2726 igb_getreg(RDT6), 2727 igb_getreg(RDT7), 2728 igb_getreg(RDT8), 2729 igb_getreg(RDT9), 2730 igb_getreg(RDT10), 2731 igb_getreg(RDT11), 2732 igb_getreg(RDT12), 2733 igb_getreg(RDT13), 2734 igb_getreg(RDT14), 2735 igb_getreg(RDT15), 2736 igb_getreg(RDBAH0), 2737 igb_getreg(RDBAH1), 2738 igb_getreg(RDBAH2), 2739 igb_getreg(RDBAH3), 2740 igb_getreg(RDBAH4), 2741 igb_getreg(RDBAH5), 2742 igb_getreg(RDBAH6), 2743 igb_getreg(RDBAH7), 2744 igb_getreg(RDBAH8), 2745 igb_getreg(RDBAH9), 2746 igb_getreg(RDBAH10), 2747 igb_getreg(RDBAH11), 2748 igb_getreg(RDBAH12), 2749 igb_getreg(RDBAH13), 2750 igb_getreg(RDBAH14), 2751 igb_getreg(RDBAH15), 2752 igb_getreg(TDBAL0), 2753 igb_getreg(TDBAL1), 2754 igb_getreg(TDBAL2), 2755 igb_getreg(TDBAL3), 2756 igb_getreg(TDBAL4), 2757 igb_getreg(TDBAL5), 2758 igb_getreg(TDBAL6), 2759 igb_getreg(TDBAL7), 2760 igb_getreg(TDBAL8), 2761 igb_getreg(TDBAL9), 2762 igb_getreg(TDBAL10), 2763 igb_getreg(TDBAL11), 2764 igb_getreg(TDBAL12), 2765 igb_getreg(TDBAL13), 2766 igb_getreg(TDBAL14), 2767 igb_getreg(TDBAL15), 2768 igb_getreg(RDLEN0), 2769 igb_getreg(RDLEN1), 2770 igb_getreg(RDLEN2), 2771 igb_getreg(RDLEN3), 2772 igb_getreg(RDLEN4), 2773 igb_getreg(RDLEN5), 2774 igb_getreg(RDLEN6), 2775 igb_getreg(RDLEN7), 2776 igb_getreg(RDLEN8), 2777 igb_getreg(RDLEN9), 2778 igb_getreg(RDLEN10), 2779 igb_getreg(RDLEN11), 2780 igb_getreg(RDLEN12), 2781 igb_getreg(RDLEN13), 2782 igb_getreg(RDLEN14), 2783 igb_getreg(RDLEN15), 2784 igb_getreg(SRRCTL0), 2785 igb_getreg(SRRCTL1), 2786 igb_getreg(SRRCTL2), 2787 igb_getreg(SRRCTL3), 2788 igb_getreg(SRRCTL4), 2789 igb_getreg(SRRCTL5), 2790 igb_getreg(SRRCTL6), 2791 igb_getreg(SRRCTL7), 2792 igb_getreg(SRRCTL8), 2793 igb_getreg(SRRCTL9), 2794 igb_getreg(SRRCTL10), 2795 igb_getreg(SRRCTL11), 2796 igb_getreg(SRRCTL12), 2797 igb_getreg(SRRCTL13), 2798 igb_getreg(SRRCTL14), 2799 igb_getreg(SRRCTL15), 2800 igb_getreg(LATECOL), 2801 igb_getreg(XONTXC), 2802 igb_getreg(TDFH), 2803 igb_getreg(TDFT), 2804 igb_getreg(TDFHS), 2805 igb_getreg(TDFTS), 2806 igb_getreg(TDFPC), 2807 igb_getreg(WUS), 2808 igb_getreg(RDFH), 2809 igb_getreg(RDFT), 2810 igb_getreg(RDFHS), 2811 igb_getreg(RDFTS), 2812 igb_getreg(RDFPC), 2813 igb_getreg(GORCL), 2814 igb_getreg(MGTPRC), 2815 igb_getreg(EERD), 2816 igb_getreg(EIAC), 2817 igb_getreg(MANC2H), 2818 igb_getreg(RXCSUM), 2819 igb_getreg(GSCL_3), 2820 igb_getreg(GSCN_2), 2821 igb_getreg(FCAH), 2822 igb_getreg(FCRTH), 2823 igb_getreg(FLOP), 2824 igb_getreg(RXSTMPH), 2825 igb_getreg(TXSTMPL), 2826 igb_getreg(TIMADJL), 2827 igb_getreg(RDH0), 2828 igb_getreg(RDH1), 2829 igb_getreg(RDH2), 2830 igb_getreg(RDH3), 2831 igb_getreg(RDH4), 2832 igb_getreg(RDH5), 2833 igb_getreg(RDH6), 2834 igb_getreg(RDH7), 2835 igb_getreg(RDH8), 2836 igb_getreg(RDH9), 2837 igb_getreg(RDH10), 2838 igb_getreg(RDH11), 2839 igb_getreg(RDH12), 2840 igb_getreg(RDH13), 2841 igb_getreg(RDH14), 2842 igb_getreg(RDH15), 2843 igb_getreg(TDT0), 2844 igb_getreg(TDT1), 2845 igb_getreg(TDT2), 2846 igb_getreg(TDT3), 2847 igb_getreg(TDT4), 2848 igb_getreg(TDT5), 2849 igb_getreg(TDT6), 2850 igb_getreg(TDT7), 2851 igb_getreg(TDT8), 2852 igb_getreg(TDT9), 2853 igb_getreg(TDT10), 2854 igb_getreg(TDT11), 2855 igb_getreg(TDT12), 2856 igb_getreg(TDT13), 2857 igb_getreg(TDT14), 2858 igb_getreg(TDT15), 2859 igb_getreg(TNCRS), 2860 igb_getreg(RJC), 2861 igb_getreg(IAM), 2862 igb_getreg(GSCL_2), 2863 igb_getreg(TIPG), 2864 igb_getreg(FLMNGCTL), 2865 igb_getreg(FLMNGCNT), 2866 igb_getreg(TSYNCTXCTL), 2867 igb_getreg(EEMNGDATA), 2868 igb_getreg(CTRL_EXT), 2869 igb_getreg(SYSTIMH), 2870 igb_getreg(EEMNGCTL), 2871 igb_getreg(FLMNGDATA), 2872 igb_getreg(TSYNCRXCTL), 2873 igb_getreg(LEDCTL), 2874 igb_getreg(TCTL), 2875 igb_getreg(TCTL_EXT), 2876 igb_getreg(DTXCTL), 2877 igb_getreg(RXPBS), 2878 igb_getreg(TDH0), 2879 igb_getreg(TDH1), 2880 igb_getreg(TDH2), 2881 igb_getreg(TDH3), 2882 igb_getreg(TDH4), 2883 igb_getreg(TDH5), 2884 igb_getreg(TDH6), 2885 igb_getreg(TDH7), 2886 igb_getreg(TDH8), 2887 igb_getreg(TDH9), 2888 igb_getreg(TDH10), 2889 igb_getreg(TDH11), 2890 igb_getreg(TDH12), 2891 igb_getreg(TDH13), 2892 igb_getreg(TDH14), 2893 igb_getreg(TDH15), 2894 igb_getreg(ECOL), 2895 igb_getreg(DC), 2896 igb_getreg(RLEC), 2897 igb_getreg(XOFFTXC), 2898 igb_getreg(RFC), 2899 igb_getreg(RNBC), 2900 igb_getreg(MGTPTC), 2901 igb_getreg(TIMINCA), 2902 igb_getreg(FACTPS), 2903 igb_getreg(GSCL_1), 2904 igb_getreg(GSCN_0), 2905 igb_getreg(PBACLR), 2906 igb_getreg(FCTTV), 2907 igb_getreg(RXSATRL), 2908 igb_getreg(TORL), 2909 igb_getreg(TDLEN0), 2910 igb_getreg(TDLEN1), 2911 igb_getreg(TDLEN2), 2912 igb_getreg(TDLEN3), 2913 igb_getreg(TDLEN4), 2914 igb_getreg(TDLEN5), 2915 igb_getreg(TDLEN6), 2916 igb_getreg(TDLEN7), 2917 igb_getreg(TDLEN8), 2918 igb_getreg(TDLEN9), 2919 igb_getreg(TDLEN10), 2920 igb_getreg(TDLEN11), 2921 igb_getreg(TDLEN12), 2922 igb_getreg(TDLEN13), 2923 igb_getreg(TDLEN14), 2924 igb_getreg(TDLEN15), 2925 igb_getreg(MCC), 2926 igb_getreg(WUC), 2927 igb_getreg(EECD), 2928 igb_getreg(FCRTV), 2929 igb_getreg(TXDCTL0), 2930 igb_getreg(TXDCTL1), 2931 igb_getreg(TXDCTL2), 2932 igb_getreg(TXDCTL3), 2933 igb_getreg(TXDCTL4), 2934 igb_getreg(TXDCTL5), 2935 igb_getreg(TXDCTL6), 2936 igb_getreg(TXDCTL7), 2937 igb_getreg(TXDCTL8), 2938 igb_getreg(TXDCTL9), 2939 igb_getreg(TXDCTL10), 2940 igb_getreg(TXDCTL11), 2941 igb_getreg(TXDCTL12), 2942 igb_getreg(TXDCTL13), 2943 igb_getreg(TXDCTL14), 2944 igb_getreg(TXDCTL15), 2945 igb_getreg(TXCTL0), 2946 igb_getreg(TXCTL1), 2947 igb_getreg(TXCTL2), 2948 igb_getreg(TXCTL3), 2949 igb_getreg(TXCTL4), 2950 igb_getreg(TXCTL5), 2951 igb_getreg(TXCTL6), 2952 igb_getreg(TXCTL7), 2953 igb_getreg(TXCTL8), 2954 igb_getreg(TXCTL9), 2955 igb_getreg(TXCTL10), 2956 igb_getreg(TXCTL11), 2957 igb_getreg(TXCTL12), 2958 igb_getreg(TXCTL13), 2959 igb_getreg(TXCTL14), 2960 igb_getreg(TXCTL15), 2961 igb_getreg(TDWBAL0), 2962 igb_getreg(TDWBAL1), 2963 igb_getreg(TDWBAL2), 2964 igb_getreg(TDWBAL3), 2965 igb_getreg(TDWBAL4), 2966 igb_getreg(TDWBAL5), 2967 igb_getreg(TDWBAL6), 2968 igb_getreg(TDWBAL7), 2969 igb_getreg(TDWBAL8), 2970 igb_getreg(TDWBAL9), 2971 igb_getreg(TDWBAL10), 2972 igb_getreg(TDWBAL11), 2973 igb_getreg(TDWBAL12), 2974 igb_getreg(TDWBAL13), 2975 igb_getreg(TDWBAL14), 2976 igb_getreg(TDWBAL15), 2977 igb_getreg(TDWBAH0), 2978 igb_getreg(TDWBAH1), 2979 igb_getreg(TDWBAH2), 2980 igb_getreg(TDWBAH3), 2981 igb_getreg(TDWBAH4), 2982 igb_getreg(TDWBAH5), 2983 igb_getreg(TDWBAH6), 2984 igb_getreg(TDWBAH7), 2985 igb_getreg(TDWBAH8), 2986 igb_getreg(TDWBAH9), 2987 igb_getreg(TDWBAH10), 2988 igb_getreg(TDWBAH11), 2989 igb_getreg(TDWBAH12), 2990 igb_getreg(TDWBAH13), 2991 igb_getreg(TDWBAH14), 2992 igb_getreg(TDWBAH15), 2993 igb_getreg(PVTCTRL0), 2994 igb_getreg(PVTCTRL1), 2995 igb_getreg(PVTCTRL2), 2996 igb_getreg(PVTCTRL3), 2997 igb_getreg(PVTCTRL4), 2998 igb_getreg(PVTCTRL5), 2999 igb_getreg(PVTCTRL6), 3000 igb_getreg(PVTCTRL7), 3001 igb_getreg(PVTEIMS0), 3002 igb_getreg(PVTEIMS1), 3003 igb_getreg(PVTEIMS2), 3004 igb_getreg(PVTEIMS3), 3005 igb_getreg(PVTEIMS4), 3006 igb_getreg(PVTEIMS5), 3007 igb_getreg(PVTEIMS6), 3008 igb_getreg(PVTEIMS7), 3009 igb_getreg(PVTEIAC0), 3010 igb_getreg(PVTEIAC1), 3011 igb_getreg(PVTEIAC2), 3012 igb_getreg(PVTEIAC3), 3013 igb_getreg(PVTEIAC4), 3014 igb_getreg(PVTEIAC5), 3015 igb_getreg(PVTEIAC6), 3016 igb_getreg(PVTEIAC7), 3017 igb_getreg(PVTEIAM0), 3018 igb_getreg(PVTEIAM1), 3019 igb_getreg(PVTEIAM2), 3020 igb_getreg(PVTEIAM3), 3021 igb_getreg(PVTEIAM4), 3022 igb_getreg(PVTEIAM5), 3023 igb_getreg(PVTEIAM6), 3024 igb_getreg(PVTEIAM7), 3025 igb_getreg(PVFGPRC0), 3026 igb_getreg(PVFGPRC1), 3027 igb_getreg(PVFGPRC2), 3028 igb_getreg(PVFGPRC3), 3029 igb_getreg(PVFGPRC4), 3030 igb_getreg(PVFGPRC5), 3031 igb_getreg(PVFGPRC6), 3032 igb_getreg(PVFGPRC7), 3033 igb_getreg(PVFGPTC0), 3034 igb_getreg(PVFGPTC1), 3035 igb_getreg(PVFGPTC2), 3036 igb_getreg(PVFGPTC3), 3037 igb_getreg(PVFGPTC4), 3038 igb_getreg(PVFGPTC5), 3039 igb_getreg(PVFGPTC6), 3040 igb_getreg(PVFGPTC7), 3041 igb_getreg(PVFGORC0), 3042 igb_getreg(PVFGORC1), 3043 igb_getreg(PVFGORC2), 3044 igb_getreg(PVFGORC3), 3045 igb_getreg(PVFGORC4), 3046 igb_getreg(PVFGORC5), 3047 igb_getreg(PVFGORC6), 3048 igb_getreg(PVFGORC7), 3049 igb_getreg(PVFGOTC0), 3050 igb_getreg(PVFGOTC1), 3051 igb_getreg(PVFGOTC2), 3052 igb_getreg(PVFGOTC3), 3053 igb_getreg(PVFGOTC4), 3054 igb_getreg(PVFGOTC5), 3055 igb_getreg(PVFGOTC6), 3056 igb_getreg(PVFGOTC7), 3057 igb_getreg(PVFMPRC0), 3058 igb_getreg(PVFMPRC1), 3059 igb_getreg(PVFMPRC2), 3060 igb_getreg(PVFMPRC3), 3061 igb_getreg(PVFMPRC4), 3062 igb_getreg(PVFMPRC5), 3063 igb_getreg(PVFMPRC6), 3064 igb_getreg(PVFMPRC7), 3065 igb_getreg(PVFGPRLBC0), 3066 igb_getreg(PVFGPRLBC1), 3067 igb_getreg(PVFGPRLBC2), 3068 igb_getreg(PVFGPRLBC3), 3069 igb_getreg(PVFGPRLBC4), 3070 igb_getreg(PVFGPRLBC5), 3071 igb_getreg(PVFGPRLBC6), 3072 igb_getreg(PVFGPRLBC7), 3073 igb_getreg(PVFGPTLBC0), 3074 igb_getreg(PVFGPTLBC1), 3075 igb_getreg(PVFGPTLBC2), 3076 igb_getreg(PVFGPTLBC3), 3077 igb_getreg(PVFGPTLBC4), 3078 igb_getreg(PVFGPTLBC5), 3079 igb_getreg(PVFGPTLBC6), 3080 igb_getreg(PVFGPTLBC7), 3081 igb_getreg(PVFGORLBC0), 3082 igb_getreg(PVFGORLBC1), 3083 igb_getreg(PVFGORLBC2), 3084 igb_getreg(PVFGORLBC3), 3085 igb_getreg(PVFGORLBC4), 3086 igb_getreg(PVFGORLBC5), 3087 igb_getreg(PVFGORLBC6), 3088 igb_getreg(PVFGORLBC7), 3089 igb_getreg(PVFGOTLBC0), 3090 igb_getreg(PVFGOTLBC1), 3091 igb_getreg(PVFGOTLBC2), 3092 igb_getreg(PVFGOTLBC3), 3093 igb_getreg(PVFGOTLBC4), 3094 igb_getreg(PVFGOTLBC5), 3095 igb_getreg(PVFGOTLBC6), 3096 igb_getreg(PVFGOTLBC7), 3097 igb_getreg(RCTL), 3098 igb_getreg(MDIC), 3099 igb_getreg(FCRUC), 3100 igb_getreg(VET), 3101 igb_getreg(RDBAL0), 3102 igb_getreg(RDBAL1), 3103 igb_getreg(RDBAL2), 3104 igb_getreg(RDBAL3), 3105 igb_getreg(RDBAL4), 3106 igb_getreg(RDBAL5), 3107 igb_getreg(RDBAL6), 3108 igb_getreg(RDBAL7), 3109 igb_getreg(RDBAL8), 3110 igb_getreg(RDBAL9), 3111 igb_getreg(RDBAL10), 3112 igb_getreg(RDBAL11), 3113 igb_getreg(RDBAL12), 3114 igb_getreg(RDBAL13), 3115 igb_getreg(RDBAL14), 3116 igb_getreg(RDBAL15), 3117 igb_getreg(TDBAH0), 3118 igb_getreg(TDBAH1), 3119 igb_getreg(TDBAH2), 3120 igb_getreg(TDBAH3), 3121 igb_getreg(TDBAH4), 3122 igb_getreg(TDBAH5), 3123 igb_getreg(TDBAH6), 3124 igb_getreg(TDBAH7), 3125 igb_getreg(TDBAH8), 3126 igb_getreg(TDBAH9), 3127 igb_getreg(TDBAH10), 3128 igb_getreg(TDBAH11), 3129 igb_getreg(TDBAH12), 3130 igb_getreg(TDBAH13), 3131 igb_getreg(TDBAH14), 3132 igb_getreg(TDBAH15), 3133 igb_getreg(SCC), 3134 igb_getreg(COLC), 3135 igb_getreg(XOFFRXC), 3136 igb_getreg(IPAV), 3137 igb_getreg(GOTCL), 3138 igb_getreg(MGTPDC), 3139 igb_getreg(GCR), 3140 igb_getreg(MFVAL), 3141 igb_getreg(FUNCTAG), 3142 igb_getreg(GSCL_4), 3143 igb_getreg(GSCN_3), 3144 igb_getreg(MRQC), 3145 igb_getreg(FCT), 3146 igb_getreg(FLA), 3147 igb_getreg(RXDCTL0), 3148 igb_getreg(RXDCTL1), 3149 igb_getreg(RXDCTL2), 3150 igb_getreg(RXDCTL3), 3151 igb_getreg(RXDCTL4), 3152 igb_getreg(RXDCTL5), 3153 igb_getreg(RXDCTL6), 3154 igb_getreg(RXDCTL7), 3155 igb_getreg(RXDCTL8), 3156 igb_getreg(RXDCTL9), 3157 igb_getreg(RXDCTL10), 3158 igb_getreg(RXDCTL11), 3159 igb_getreg(RXDCTL12), 3160 igb_getreg(RXDCTL13), 3161 igb_getreg(RXDCTL14), 3162 igb_getreg(RXDCTL15), 3163 igb_getreg(RXSTMPL), 3164 igb_getreg(TIMADJH), 3165 igb_getreg(FCRTL), 3166 igb_getreg(XONRXC), 3167 igb_getreg(RFCTL), 3168 igb_getreg(GSCN_1), 3169 igb_getreg(FCAL), 3170 igb_getreg(GPIE), 3171 igb_getreg(TXPBS), 3172 igb_getreg(RLPML), 3173 3174 [TOTH] = igb_mac_read_clr8, 3175 [GOTCH] = igb_mac_read_clr8, 3176 [PRC64] = igb_mac_read_clr4, 3177 [PRC255] = igb_mac_read_clr4, 3178 [PRC1023] = igb_mac_read_clr4, 3179 [PTC64] = igb_mac_read_clr4, 3180 [PTC255] = igb_mac_read_clr4, 3181 [PTC1023] = igb_mac_read_clr4, 3182 [GPRC] = igb_mac_read_clr4, 3183 [TPT] = igb_mac_read_clr4, 3184 [RUC] = igb_mac_read_clr4, 3185 [BPRC] = igb_mac_read_clr4, 3186 [MPTC] = igb_mac_read_clr4, 3187 [IAC] = igb_mac_read_clr4, 3188 [ICR] = igb_mac_icr_read, 3189 [STATUS] = igb_get_status, 3190 [ICS] = igb_mac_ics_read, 3191 /* 3192 * 8.8.10: Reading the IMC register returns the value of the IMS register. 3193 */ 3194 [IMC] = igb_mac_ims_read, 3195 [TORH] = igb_mac_read_clr8, 3196 [GORCH] = igb_mac_read_clr8, 3197 [PRC127] = igb_mac_read_clr4, 3198 [PRC511] = igb_mac_read_clr4, 3199 [PRC1522] = igb_mac_read_clr4, 3200 [PTC127] = igb_mac_read_clr4, 3201 [PTC511] = igb_mac_read_clr4, 3202 [PTC1522] = igb_mac_read_clr4, 3203 [GPTC] = igb_mac_read_clr4, 3204 [TPR] = igb_mac_read_clr4, 3205 [ROC] = igb_mac_read_clr4, 3206 [MPRC] = igb_mac_read_clr4, 3207 [BPTC] = igb_mac_read_clr4, 3208 [TSCTC] = igb_mac_read_clr4, 3209 [CTRL] = igb_get_ctrl, 3210 [SWSM] = igb_mac_swsm_read, 3211 [IMS] = igb_mac_ims_read, 3212 [SYSTIML] = igb_get_systiml, 3213 [RXSATRH] = igb_get_rxsatrh, 3214 [TXSTMPH] = igb_get_txstmph, 3215 3216 [CRCERRS ... MPC] = igb_mac_readreg, 3217 [IP6AT ... IP6AT + 3] = igb_mac_readreg, 3218 [IP4AT ... IP4AT + 6] = igb_mac_readreg, 3219 [RA ... RA + 31] = igb_mac_readreg, 3220 [RA2 ... RA2 + 31] = igb_mac_readreg, 3221 [WUPM ... WUPM + 31] = igb_mac_readreg, 3222 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg, 3223 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg, 3224 [FFMT ... FFMT + 254] = igb_mac_readreg, 3225 [MDEF ... MDEF + 7] = igb_mac_readreg, 3226 [FTFT ... FTFT + 254] = igb_mac_readreg, 3227 [RETA ... RETA + 31] = igb_mac_readreg, 3228 [RSSRK ... RSSRK + 9] = igb_mac_readreg, 3229 [MAVTV0 ... MAVTV3] = igb_mac_readreg, 3230 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read, 3231 [PVTEICR0] = igb_mac_read_clr4, 3232 [PVTEICR1] = igb_mac_read_clr4, 3233 [PVTEICR2] = igb_mac_read_clr4, 3234 [PVTEICR3] = igb_mac_read_clr4, 3235 [PVTEICR4] = igb_mac_read_clr4, 3236 [PVTEICR5] = igb_mac_read_clr4, 3237 [PVTEICR6] = igb_mac_read_clr4, 3238 [PVTEICR7] = igb_mac_read_clr4, 3239 3240 /* IGB specific: */ 3241 [FWSM] = igb_mac_readreg, 3242 [SW_FW_SYNC] = igb_mac_readreg, 3243 [HTCBDPC] = igb_mac_read_clr4, 3244 [EICR] = igb_mac_read_clr4, 3245 [EIMS] = igb_mac_readreg, 3246 [EIAM] = igb_mac_readreg, 3247 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg, 3248 igb_getreg(IVAR_MISC), 3249 igb_getreg(VT_CTL), 3250 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg, 3251 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read, 3252 igb_getreg(MBVFICR), 3253 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg, 3254 igb_getreg(MBVFIMR), 3255 igb_getreg(VFLRE), 3256 igb_getreg(VFRE), 3257 igb_getreg(VFTE), 3258 igb_getreg(QDE), 3259 igb_getreg(DTXSWC), 3260 igb_getreg(RPLOLR), 3261 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg, 3262 [VMVIR0 ... VMVIR7] = igb_mac_readreg, 3263 [VMOLR0 ... VMOLR7] = igb_mac_readreg, 3264 [WVBR] = igb_mac_read_clr4, 3265 [RQDPC0] = igb_mac_read_clr4, 3266 [RQDPC1] = igb_mac_read_clr4, 3267 [RQDPC2] = igb_mac_read_clr4, 3268 [RQDPC3] = igb_mac_read_clr4, 3269 [RQDPC4] = igb_mac_read_clr4, 3270 [RQDPC5] = igb_mac_read_clr4, 3271 [RQDPC6] = igb_mac_read_clr4, 3272 [RQDPC7] = igb_mac_read_clr4, 3273 [RQDPC8] = igb_mac_read_clr4, 3274 [RQDPC9] = igb_mac_read_clr4, 3275 [RQDPC10] = igb_mac_read_clr4, 3276 [RQDPC11] = igb_mac_read_clr4, 3277 [RQDPC12] = igb_mac_read_clr4, 3278 [RQDPC13] = igb_mac_read_clr4, 3279 [RQDPC14] = igb_mac_read_clr4, 3280 [RQDPC15] = igb_mac_read_clr4, 3281 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg, 3282 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg, 3283 }; 3284 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) }; 3285 3286 #define igb_putreg(x) [x] = igb_mac_writereg 3287 typedef void (*writeops)(IGBCore *, int, uint32_t); 3288 static const writeops igb_macreg_writeops[] = { 3289 igb_putreg(SWSM), 3290 igb_putreg(WUFC), 3291 igb_putreg(RDBAH0), 3292 igb_putreg(RDBAH1), 3293 igb_putreg(RDBAH2), 3294 igb_putreg(RDBAH3), 3295 igb_putreg(RDBAH4), 3296 igb_putreg(RDBAH5), 3297 igb_putreg(RDBAH6), 3298 igb_putreg(RDBAH7), 3299 igb_putreg(RDBAH8), 3300 igb_putreg(RDBAH9), 3301 igb_putreg(RDBAH10), 3302 igb_putreg(RDBAH11), 3303 igb_putreg(RDBAH12), 3304 igb_putreg(RDBAH13), 3305 igb_putreg(RDBAH14), 3306 igb_putreg(RDBAH15), 3307 igb_putreg(SRRCTL0), 3308 igb_putreg(SRRCTL1), 3309 igb_putreg(SRRCTL2), 3310 igb_putreg(SRRCTL3), 3311 igb_putreg(SRRCTL4), 3312 igb_putreg(SRRCTL5), 3313 igb_putreg(SRRCTL6), 3314 igb_putreg(SRRCTL7), 3315 igb_putreg(SRRCTL8), 3316 igb_putreg(SRRCTL9), 3317 igb_putreg(SRRCTL10), 3318 igb_putreg(SRRCTL11), 3319 igb_putreg(SRRCTL12), 3320 igb_putreg(SRRCTL13), 3321 igb_putreg(SRRCTL14), 3322 igb_putreg(SRRCTL15), 3323 igb_putreg(RXDCTL0), 3324 igb_putreg(RXDCTL1), 3325 igb_putreg(RXDCTL2), 3326 igb_putreg(RXDCTL3), 3327 igb_putreg(RXDCTL4), 3328 igb_putreg(RXDCTL5), 3329 igb_putreg(RXDCTL6), 3330 igb_putreg(RXDCTL7), 3331 igb_putreg(RXDCTL8), 3332 igb_putreg(RXDCTL9), 3333 igb_putreg(RXDCTL10), 3334 igb_putreg(RXDCTL11), 3335 igb_putreg(RXDCTL12), 3336 igb_putreg(RXDCTL13), 3337 igb_putreg(RXDCTL14), 3338 igb_putreg(RXDCTL15), 3339 igb_putreg(LEDCTL), 3340 igb_putreg(TCTL), 3341 igb_putreg(TCTL_EXT), 3342 igb_putreg(DTXCTL), 3343 igb_putreg(RXPBS), 3344 igb_putreg(RQDPC0), 3345 igb_putreg(FCAL), 3346 igb_putreg(FCRUC), 3347 igb_putreg(WUC), 3348 igb_putreg(WUS), 3349 igb_putreg(IPAV), 3350 igb_putreg(TDBAH0), 3351 igb_putreg(TDBAH1), 3352 igb_putreg(TDBAH2), 3353 igb_putreg(TDBAH3), 3354 igb_putreg(TDBAH4), 3355 igb_putreg(TDBAH5), 3356 igb_putreg(TDBAH6), 3357 igb_putreg(TDBAH7), 3358 igb_putreg(TDBAH8), 3359 igb_putreg(TDBAH9), 3360 igb_putreg(TDBAH10), 3361 igb_putreg(TDBAH11), 3362 igb_putreg(TDBAH12), 3363 igb_putreg(TDBAH13), 3364 igb_putreg(TDBAH14), 3365 igb_putreg(TDBAH15), 3366 igb_putreg(IAM), 3367 igb_putreg(MANC), 3368 igb_putreg(MANC2H), 3369 igb_putreg(MFVAL), 3370 igb_putreg(FACTPS), 3371 igb_putreg(FUNCTAG), 3372 igb_putreg(GSCL_1), 3373 igb_putreg(GSCL_2), 3374 igb_putreg(GSCL_3), 3375 igb_putreg(GSCL_4), 3376 igb_putreg(GSCN_0), 3377 igb_putreg(GSCN_1), 3378 igb_putreg(GSCN_2), 3379 igb_putreg(GSCN_3), 3380 igb_putreg(MRQC), 3381 igb_putreg(FLOP), 3382 igb_putreg(FLA), 3383 igb_putreg(TXDCTL0), 3384 igb_putreg(TXDCTL1), 3385 igb_putreg(TXDCTL2), 3386 igb_putreg(TXDCTL3), 3387 igb_putreg(TXDCTL4), 3388 igb_putreg(TXDCTL5), 3389 igb_putreg(TXDCTL6), 3390 igb_putreg(TXDCTL7), 3391 igb_putreg(TXDCTL8), 3392 igb_putreg(TXDCTL9), 3393 igb_putreg(TXDCTL10), 3394 igb_putreg(TXDCTL11), 3395 igb_putreg(TXDCTL12), 3396 igb_putreg(TXDCTL13), 3397 igb_putreg(TXDCTL14), 3398 igb_putreg(TXDCTL15), 3399 igb_putreg(TXCTL0), 3400 igb_putreg(TXCTL1), 3401 igb_putreg(TXCTL2), 3402 igb_putreg(TXCTL3), 3403 igb_putreg(TXCTL4), 3404 igb_putreg(TXCTL5), 3405 igb_putreg(TXCTL6), 3406 igb_putreg(TXCTL7), 3407 igb_putreg(TXCTL8), 3408 igb_putreg(TXCTL9), 3409 igb_putreg(TXCTL10), 3410 igb_putreg(TXCTL11), 3411 igb_putreg(TXCTL12), 3412 igb_putreg(TXCTL13), 3413 igb_putreg(TXCTL14), 3414 igb_putreg(TXCTL15), 3415 igb_putreg(TDWBAL0), 3416 igb_putreg(TDWBAL1), 3417 igb_putreg(TDWBAL2), 3418 igb_putreg(TDWBAL3), 3419 igb_putreg(TDWBAL4), 3420 igb_putreg(TDWBAL5), 3421 igb_putreg(TDWBAL6), 3422 igb_putreg(TDWBAL7), 3423 igb_putreg(TDWBAL8), 3424 igb_putreg(TDWBAL9), 3425 igb_putreg(TDWBAL10), 3426 igb_putreg(TDWBAL11), 3427 igb_putreg(TDWBAL12), 3428 igb_putreg(TDWBAL13), 3429 igb_putreg(TDWBAL14), 3430 igb_putreg(TDWBAL15), 3431 igb_putreg(TDWBAH0), 3432 igb_putreg(TDWBAH1), 3433 igb_putreg(TDWBAH2), 3434 igb_putreg(TDWBAH3), 3435 igb_putreg(TDWBAH4), 3436 igb_putreg(TDWBAH5), 3437 igb_putreg(TDWBAH6), 3438 igb_putreg(TDWBAH7), 3439 igb_putreg(TDWBAH8), 3440 igb_putreg(TDWBAH9), 3441 igb_putreg(TDWBAH10), 3442 igb_putreg(TDWBAH11), 3443 igb_putreg(TDWBAH12), 3444 igb_putreg(TDWBAH13), 3445 igb_putreg(TDWBAH14), 3446 igb_putreg(TDWBAH15), 3447 igb_putreg(TIPG), 3448 igb_putreg(RXSTMPH), 3449 igb_putreg(RXSTMPL), 3450 igb_putreg(RXSATRL), 3451 igb_putreg(RXSATRH), 3452 igb_putreg(TXSTMPL), 3453 igb_putreg(TXSTMPH), 3454 igb_putreg(SYSTIML), 3455 igb_putreg(SYSTIMH), 3456 igb_putreg(TIMADJL), 3457 igb_putreg(TSYNCRXCTL), 3458 igb_putreg(TSYNCTXCTL), 3459 igb_putreg(EEMNGCTL), 3460 igb_putreg(GPIE), 3461 igb_putreg(TXPBS), 3462 igb_putreg(RLPML), 3463 igb_putreg(VET), 3464 3465 [TDH0] = igb_set_16bit, 3466 [TDH1] = igb_set_16bit, 3467 [TDH2] = igb_set_16bit, 3468 [TDH3] = igb_set_16bit, 3469 [TDH4] = igb_set_16bit, 3470 [TDH5] = igb_set_16bit, 3471 [TDH6] = igb_set_16bit, 3472 [TDH7] = igb_set_16bit, 3473 [TDH8] = igb_set_16bit, 3474 [TDH9] = igb_set_16bit, 3475 [TDH10] = igb_set_16bit, 3476 [TDH11] = igb_set_16bit, 3477 [TDH12] = igb_set_16bit, 3478 [TDH13] = igb_set_16bit, 3479 [TDH14] = igb_set_16bit, 3480 [TDH15] = igb_set_16bit, 3481 [TDT0] = igb_set_tdt, 3482 [TDT1] = igb_set_tdt, 3483 [TDT2] = igb_set_tdt, 3484 [TDT3] = igb_set_tdt, 3485 [TDT4] = igb_set_tdt, 3486 [TDT5] = igb_set_tdt, 3487 [TDT6] = igb_set_tdt, 3488 [TDT7] = igb_set_tdt, 3489 [TDT8] = igb_set_tdt, 3490 [TDT9] = igb_set_tdt, 3491 [TDT10] = igb_set_tdt, 3492 [TDT11] = igb_set_tdt, 3493 [TDT12] = igb_set_tdt, 3494 [TDT13] = igb_set_tdt, 3495 [TDT14] = igb_set_tdt, 3496 [TDT15] = igb_set_tdt, 3497 [MDIC] = igb_set_mdic, 3498 [ICS] = igb_set_ics, 3499 [RDH0] = igb_set_16bit, 3500 [RDH1] = igb_set_16bit, 3501 [RDH2] = igb_set_16bit, 3502 [RDH3] = igb_set_16bit, 3503 [RDH4] = igb_set_16bit, 3504 [RDH5] = igb_set_16bit, 3505 [RDH6] = igb_set_16bit, 3506 [RDH7] = igb_set_16bit, 3507 [RDH8] = igb_set_16bit, 3508 [RDH9] = igb_set_16bit, 3509 [RDH10] = igb_set_16bit, 3510 [RDH11] = igb_set_16bit, 3511 [RDH12] = igb_set_16bit, 3512 [RDH13] = igb_set_16bit, 3513 [RDH14] = igb_set_16bit, 3514 [RDH15] = igb_set_16bit, 3515 [RDT0] = igb_set_rdt, 3516 [RDT1] = igb_set_rdt, 3517 [RDT2] = igb_set_rdt, 3518 [RDT3] = igb_set_rdt, 3519 [RDT4] = igb_set_rdt, 3520 [RDT5] = igb_set_rdt, 3521 [RDT6] = igb_set_rdt, 3522 [RDT7] = igb_set_rdt, 3523 [RDT8] = igb_set_rdt, 3524 [RDT9] = igb_set_rdt, 3525 [RDT10] = igb_set_rdt, 3526 [RDT11] = igb_set_rdt, 3527 [RDT12] = igb_set_rdt, 3528 [RDT13] = igb_set_rdt, 3529 [RDT14] = igb_set_rdt, 3530 [RDT15] = igb_set_rdt, 3531 [IMC] = igb_set_imc, 3532 [IMS] = igb_set_ims, 3533 [ICR] = igb_set_icr, 3534 [EECD] = igb_set_eecd, 3535 [RCTL] = igb_set_rx_control, 3536 [CTRL] = igb_set_ctrl, 3537 [EERD] = igb_set_eerd, 3538 [TDFH] = igb_set_13bit, 3539 [TDFT] = igb_set_13bit, 3540 [TDFHS] = igb_set_13bit, 3541 [TDFTS] = igb_set_13bit, 3542 [TDFPC] = igb_set_13bit, 3543 [RDFH] = igb_set_13bit, 3544 [RDFT] = igb_set_13bit, 3545 [RDFHS] = igb_set_13bit, 3546 [RDFTS] = igb_set_13bit, 3547 [RDFPC] = igb_set_13bit, 3548 [GCR] = igb_set_gcr, 3549 [RXCSUM] = igb_set_rxcsum, 3550 [TDLEN0] = igb_set_dlen, 3551 [TDLEN1] = igb_set_dlen, 3552 [TDLEN2] = igb_set_dlen, 3553 [TDLEN3] = igb_set_dlen, 3554 [TDLEN4] = igb_set_dlen, 3555 [TDLEN5] = igb_set_dlen, 3556 [TDLEN6] = igb_set_dlen, 3557 [TDLEN7] = igb_set_dlen, 3558 [TDLEN8] = igb_set_dlen, 3559 [TDLEN9] = igb_set_dlen, 3560 [TDLEN10] = igb_set_dlen, 3561 [TDLEN11] = igb_set_dlen, 3562 [TDLEN12] = igb_set_dlen, 3563 [TDLEN13] = igb_set_dlen, 3564 [TDLEN14] = igb_set_dlen, 3565 [TDLEN15] = igb_set_dlen, 3566 [RDLEN0] = igb_set_dlen, 3567 [RDLEN1] = igb_set_dlen, 3568 [RDLEN2] = igb_set_dlen, 3569 [RDLEN3] = igb_set_dlen, 3570 [RDLEN4] = igb_set_dlen, 3571 [RDLEN5] = igb_set_dlen, 3572 [RDLEN6] = igb_set_dlen, 3573 [RDLEN7] = igb_set_dlen, 3574 [RDLEN8] = igb_set_dlen, 3575 [RDLEN9] = igb_set_dlen, 3576 [RDLEN10] = igb_set_dlen, 3577 [RDLEN11] = igb_set_dlen, 3578 [RDLEN12] = igb_set_dlen, 3579 [RDLEN13] = igb_set_dlen, 3580 [RDLEN14] = igb_set_dlen, 3581 [RDLEN15] = igb_set_dlen, 3582 [TDBAL0] = igb_set_dbal, 3583 [TDBAL1] = igb_set_dbal, 3584 [TDBAL2] = igb_set_dbal, 3585 [TDBAL3] = igb_set_dbal, 3586 [TDBAL4] = igb_set_dbal, 3587 [TDBAL5] = igb_set_dbal, 3588 [TDBAL6] = igb_set_dbal, 3589 [TDBAL7] = igb_set_dbal, 3590 [TDBAL8] = igb_set_dbal, 3591 [TDBAL9] = igb_set_dbal, 3592 [TDBAL10] = igb_set_dbal, 3593 [TDBAL11] = igb_set_dbal, 3594 [TDBAL12] = igb_set_dbal, 3595 [TDBAL13] = igb_set_dbal, 3596 [TDBAL14] = igb_set_dbal, 3597 [TDBAL15] = igb_set_dbal, 3598 [RDBAL0] = igb_set_dbal, 3599 [RDBAL1] = igb_set_dbal, 3600 [RDBAL2] = igb_set_dbal, 3601 [RDBAL3] = igb_set_dbal, 3602 [RDBAL4] = igb_set_dbal, 3603 [RDBAL5] = igb_set_dbal, 3604 [RDBAL6] = igb_set_dbal, 3605 [RDBAL7] = igb_set_dbal, 3606 [RDBAL8] = igb_set_dbal, 3607 [RDBAL9] = igb_set_dbal, 3608 [RDBAL10] = igb_set_dbal, 3609 [RDBAL11] = igb_set_dbal, 3610 [RDBAL12] = igb_set_dbal, 3611 [RDBAL13] = igb_set_dbal, 3612 [RDBAL14] = igb_set_dbal, 3613 [RDBAL15] = igb_set_dbal, 3614 [STATUS] = igb_set_status, 3615 [PBACLR] = igb_set_pbaclr, 3616 [CTRL_EXT] = igb_set_ctrlext, 3617 [FCAH] = igb_set_16bit, 3618 [FCT] = igb_set_16bit, 3619 [FCTTV] = igb_set_16bit, 3620 [FCRTV] = igb_set_16bit, 3621 [FCRTH] = igb_set_fcrth, 3622 [FCRTL] = igb_set_fcrtl, 3623 [CTRL_DUP] = igb_set_ctrl, 3624 [RFCTL] = igb_set_rfctl, 3625 [TIMINCA] = igb_set_timinca, 3626 [TIMADJH] = igb_set_timadjh, 3627 3628 [IP6AT ... IP6AT + 3] = igb_mac_writereg, 3629 [IP4AT ... IP4AT + 6] = igb_mac_writereg, 3630 [RA] = igb_mac_writereg, 3631 [RA + 1] = igb_mac_setmacaddr, 3632 [RA + 2 ... RA + 31] = igb_mac_writereg, 3633 [RA2 ... RA2 + 31] = igb_mac_writereg, 3634 [WUPM ... WUPM + 31] = igb_mac_writereg, 3635 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3636 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg, 3637 [FFMT ... FFMT + 254] = igb_set_4bit, 3638 [MDEF ... MDEF + 7] = igb_mac_writereg, 3639 [FTFT ... FTFT + 254] = igb_mac_writereg, 3640 [RETA ... RETA + 31] = igb_mac_writereg, 3641 [RSSRK ... RSSRK + 9] = igb_mac_writereg, 3642 [MAVTV0 ... MAVTV3] = igb_mac_writereg, 3643 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr, 3644 3645 /* IGB specific: */ 3646 [FWSM] = igb_mac_writereg, 3647 [SW_FW_SYNC] = igb_mac_writereg, 3648 [EICR] = igb_set_eicr, 3649 [EICS] = igb_set_eics, 3650 [EIAC] = igb_set_eiac, 3651 [EIAM] = igb_set_eiam, 3652 [EIMC] = igb_set_eimc, 3653 [EIMS] = igb_set_eims, 3654 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg, 3655 igb_putreg(IVAR_MISC), 3656 igb_putreg(VT_CTL), 3657 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox, 3658 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox, 3659 [MBVFICR] = igb_w1c, 3660 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg, 3661 igb_putreg(MBVFIMR), 3662 [VFLRE] = igb_w1c, 3663 igb_putreg(VFRE), 3664 igb_putreg(VFTE), 3665 igb_putreg(QDE), 3666 igb_putreg(DTXSWC), 3667 igb_putreg(RPLOLR), 3668 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg, 3669 [VMVIR0 ... VMVIR7] = igb_mac_writereg, 3670 [VMOLR0 ... VMOLR7] = igb_mac_writereg, 3671 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3672 [PVTCTRL0] = igb_set_vtctrl, 3673 [PVTCTRL1] = igb_set_vtctrl, 3674 [PVTCTRL2] = igb_set_vtctrl, 3675 [PVTCTRL3] = igb_set_vtctrl, 3676 [PVTCTRL4] = igb_set_vtctrl, 3677 [PVTCTRL5] = igb_set_vtctrl, 3678 [PVTCTRL6] = igb_set_vtctrl, 3679 [PVTCTRL7] = igb_set_vtctrl, 3680 [PVTEICS0] = igb_set_vteics, 3681 [PVTEICS1] = igb_set_vteics, 3682 [PVTEICS2] = igb_set_vteics, 3683 [PVTEICS3] = igb_set_vteics, 3684 [PVTEICS4] = igb_set_vteics, 3685 [PVTEICS5] = igb_set_vteics, 3686 [PVTEICS6] = igb_set_vteics, 3687 [PVTEICS7] = igb_set_vteics, 3688 [PVTEIMS0] = igb_set_vteims, 3689 [PVTEIMS1] = igb_set_vteims, 3690 [PVTEIMS2] = igb_set_vteims, 3691 [PVTEIMS3] = igb_set_vteims, 3692 [PVTEIMS4] = igb_set_vteims, 3693 [PVTEIMS5] = igb_set_vteims, 3694 [PVTEIMS6] = igb_set_vteims, 3695 [PVTEIMS7] = igb_set_vteims, 3696 [PVTEIMC0] = igb_set_vteimc, 3697 [PVTEIMC1] = igb_set_vteimc, 3698 [PVTEIMC2] = igb_set_vteimc, 3699 [PVTEIMC3] = igb_set_vteimc, 3700 [PVTEIMC4] = igb_set_vteimc, 3701 [PVTEIMC5] = igb_set_vteimc, 3702 [PVTEIMC6] = igb_set_vteimc, 3703 [PVTEIMC7] = igb_set_vteimc, 3704 [PVTEIAC0] = igb_set_vteiac, 3705 [PVTEIAC1] = igb_set_vteiac, 3706 [PVTEIAC2] = igb_set_vteiac, 3707 [PVTEIAC3] = igb_set_vteiac, 3708 [PVTEIAC4] = igb_set_vteiac, 3709 [PVTEIAC5] = igb_set_vteiac, 3710 [PVTEIAC6] = igb_set_vteiac, 3711 [PVTEIAC7] = igb_set_vteiac, 3712 [PVTEIAM0] = igb_set_vteiam, 3713 [PVTEIAM1] = igb_set_vteiam, 3714 [PVTEIAM2] = igb_set_vteiam, 3715 [PVTEIAM3] = igb_set_vteiam, 3716 [PVTEIAM4] = igb_set_vteiam, 3717 [PVTEIAM5] = igb_set_vteiam, 3718 [PVTEIAM6] = igb_set_vteiam, 3719 [PVTEIAM7] = igb_set_vteiam, 3720 [PVTEICR0] = igb_set_vteicr, 3721 [PVTEICR1] = igb_set_vteicr, 3722 [PVTEICR2] = igb_set_vteicr, 3723 [PVTEICR3] = igb_set_vteicr, 3724 [PVTEICR4] = igb_set_vteicr, 3725 [PVTEICR5] = igb_set_vteicr, 3726 [PVTEICR6] = igb_set_vteicr, 3727 [PVTEICR7] = igb_set_vteicr, 3728 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar, 3729 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg 3730 }; 3731 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) }; 3732 3733 enum { MAC_ACCESS_PARTIAL = 1 }; 3734 3735 /* 3736 * The array below combines alias offsets of the index values for the 3737 * MAC registers that have aliases, with the indication of not fully 3738 * implemented registers (lowest bit). This combination is possible 3739 * because all of the offsets are even. 3740 */ 3741 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3742 /* Alias index offsets */ 3743 [FCRTL_A] = 0x07fe, 3744 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3745 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3746 [RA_A ... RA_A + 31] = 0x14f0, 3747 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3748 3749 [RDBAL0_A] = 0x2600, 3750 [RDBAH0_A] = 0x2600, 3751 [RDLEN0_A] = 0x2600, 3752 [SRRCTL0_A] = 0x2600, 3753 [RDH0_A] = 0x2600, 3754 [RDT0_A] = 0x2600, 3755 [RXDCTL0_A] = 0x2600, 3756 [RXCTL0_A] = 0x2600, 3757 [RQDPC0_A] = 0x2600, 3758 [RDBAL1_A] = 0x25D0, 3759 [RDBAL2_A] = 0x25A0, 3760 [RDBAL3_A] = 0x2570, 3761 [RDBAH1_A] = 0x25D0, 3762 [RDBAH2_A] = 0x25A0, 3763 [RDBAH3_A] = 0x2570, 3764 [RDLEN1_A] = 0x25D0, 3765 [RDLEN2_A] = 0x25A0, 3766 [RDLEN3_A] = 0x2570, 3767 [SRRCTL1_A] = 0x25D0, 3768 [SRRCTL2_A] = 0x25A0, 3769 [SRRCTL3_A] = 0x2570, 3770 [RDH1_A] = 0x25D0, 3771 [RDH2_A] = 0x25A0, 3772 [RDH3_A] = 0x2570, 3773 [RDT1_A] = 0x25D0, 3774 [RDT2_A] = 0x25A0, 3775 [RDT3_A] = 0x2570, 3776 [RXDCTL1_A] = 0x25D0, 3777 [RXDCTL2_A] = 0x25A0, 3778 [RXDCTL3_A] = 0x2570, 3779 [RXCTL1_A] = 0x25D0, 3780 [RXCTL2_A] = 0x25A0, 3781 [RXCTL3_A] = 0x2570, 3782 [RQDPC1_A] = 0x25D0, 3783 [RQDPC2_A] = 0x25A0, 3784 [RQDPC3_A] = 0x2570, 3785 [TDBAL0_A] = 0x2A00, 3786 [TDBAH0_A] = 0x2A00, 3787 [TDLEN0_A] = 0x2A00, 3788 [TDH0_A] = 0x2A00, 3789 [TDT0_A] = 0x2A00, 3790 [TXCTL0_A] = 0x2A00, 3791 [TDWBAL0_A] = 0x2A00, 3792 [TDWBAH0_A] = 0x2A00, 3793 [TDBAL1_A] = 0x29D0, 3794 [TDBAL2_A] = 0x29A0, 3795 [TDBAL3_A] = 0x2970, 3796 [TDBAH1_A] = 0x29D0, 3797 [TDBAH2_A] = 0x29A0, 3798 [TDBAH3_A] = 0x2970, 3799 [TDLEN1_A] = 0x29D0, 3800 [TDLEN2_A] = 0x29A0, 3801 [TDLEN3_A] = 0x2970, 3802 [TDH1_A] = 0x29D0, 3803 [TDH2_A] = 0x29A0, 3804 [TDH3_A] = 0x2970, 3805 [TDT1_A] = 0x29D0, 3806 [TDT2_A] = 0x29A0, 3807 [TDT3_A] = 0x2970, 3808 [TXDCTL0_A] = 0x2A00, 3809 [TXDCTL1_A] = 0x29D0, 3810 [TXDCTL2_A] = 0x29A0, 3811 [TXDCTL3_A] = 0x2970, 3812 [TXCTL1_A] = 0x29D0, 3813 [TXCTL2_A] = 0x29A0, 3814 [TXCTL3_A] = 0x29D0, 3815 [TDWBAL1_A] = 0x29D0, 3816 [TDWBAL2_A] = 0x29A0, 3817 [TDWBAL3_A] = 0x2970, 3818 [TDWBAH1_A] = 0x29D0, 3819 [TDWBAH2_A] = 0x29A0, 3820 [TDWBAH3_A] = 0x2970, 3821 3822 /* Access options */ 3823 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3824 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3825 [RDFPC] = MAC_ACCESS_PARTIAL, 3826 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3827 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3828 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3829 [FLA] = MAC_ACCESS_PARTIAL, 3830 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3831 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3832 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3833 [FCRTH] = MAC_ACCESS_PARTIAL, 3834 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3835 }; 3836 3837 void 3838 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size) 3839 { 3840 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3841 3842 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) { 3843 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3844 trace_e1000e_wrn_regs_write_trivial(index << 2); 3845 } 3846 trace_e1000e_core_write(index << 2, size, val); 3847 igb_macreg_writeops[index](core, index, val); 3848 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3849 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3850 } else { 3851 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3852 } 3853 } 3854 3855 uint64_t 3856 igb_core_read(IGBCore *core, hwaddr addr, unsigned size) 3857 { 3858 uint64_t val; 3859 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3860 3861 if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3862 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3863 trace_e1000e_wrn_regs_read_trivial(index << 2); 3864 } 3865 val = igb_macreg_readops[index](core, index); 3866 trace_e1000e_core_read(index << 2, size, val); 3867 return val; 3868 } else { 3869 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3870 } 3871 return 0; 3872 } 3873 3874 static inline void 3875 igb_autoneg_pause(IGBCore *core) 3876 { 3877 timer_del(core->autoneg_timer); 3878 } 3879 3880 static void 3881 igb_autoneg_resume(IGBCore *core) 3882 { 3883 if (igb_have_autoneg(core) && 3884 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 3885 qemu_get_queue(core->owner_nic)->link_down = false; 3886 timer_mod(core->autoneg_timer, 3887 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3888 } 3889 } 3890 3891 static void 3892 igb_vm_state_change(void *opaque, bool running, RunState state) 3893 { 3894 IGBCore *core = opaque; 3895 3896 if (running) { 3897 trace_e1000e_vm_state_running(); 3898 igb_intrmgr_resume(core); 3899 igb_autoneg_resume(core); 3900 } else { 3901 trace_e1000e_vm_state_stopped(); 3902 igb_autoneg_pause(core); 3903 igb_intrmgr_pause(core); 3904 } 3905 } 3906 3907 void 3908 igb_core_pci_realize(IGBCore *core, 3909 const uint16_t *eeprom_templ, 3910 uint32_t eeprom_size, 3911 const uint8_t *macaddr) 3912 { 3913 int i; 3914 3915 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3916 igb_autoneg_timer, core); 3917 igb_intrmgr_pci_realize(core); 3918 3919 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core); 3920 3921 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3922 net_tx_pkt_init(&core->tx[i].tx_pkt, NULL, E1000E_MAX_TX_FRAGS); 3923 } 3924 3925 net_rx_pkt_init(&core->rx_pkt); 3926 3927 e1000x_core_prepare_eeprom(core->eeprom, 3928 eeprom_templ, 3929 eeprom_size, 3930 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3931 macaddr); 3932 igb_update_rx_offloads(core); 3933 } 3934 3935 void 3936 igb_core_pci_uninit(IGBCore *core) 3937 { 3938 int i; 3939 3940 timer_free(core->autoneg_timer); 3941 3942 igb_intrmgr_pci_unint(core); 3943 3944 qemu_del_vm_change_state_handler(core->vmstate); 3945 3946 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3947 net_tx_pkt_reset(core->tx[i].tx_pkt, NULL); 3948 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3949 } 3950 3951 net_rx_pkt_uninit(core->rx_pkt); 3952 } 3953 3954 static const uint16_t 3955 igb_phy_reg_init[] = { 3956 [MII_BMCR] = MII_BMCR_SPEED1000 | 3957 MII_BMCR_FD | 3958 MII_BMCR_AUTOEN, 3959 3960 [MII_BMSR] = MII_BMSR_EXTCAP | 3961 MII_BMSR_LINK_ST | 3962 MII_BMSR_AUTONEG | 3963 MII_BMSR_MFPS | 3964 MII_BMSR_EXTSTAT | 3965 MII_BMSR_10T_HD | 3966 MII_BMSR_10T_FD | 3967 MII_BMSR_100TX_HD | 3968 MII_BMSR_100TX_FD, 3969 3970 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16, 3971 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1, 3972 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3973 MII_ANAR_10FD | MII_ANAR_TX | 3974 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3975 MII_ANAR_PAUSE_ASYM, 3976 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3977 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3978 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3979 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3980 [MII_ANNP] = 0x1 | MII_ANNP_MP, 3981 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3982 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3983 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3984 MII_STAT1000_ROK | MII_STAT1000_LOK, 3985 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3986 3987 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8), 3988 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS, 3989 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU | 3990 IGP01E1000_PSCFR_SMART_SPEED 3991 }; 3992 3993 static const uint32_t igb_mac_reg_init[] = { 3994 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24), 3995 [EEMNGCTL] = BIT(31), 3996 [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE, 3997 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16), 3998 [RXDCTL1] = 1 << 16, 3999 [RXDCTL2] = 1 << 16, 4000 [RXDCTL3] = 1 << 16, 4001 [RXDCTL4] = 1 << 16, 4002 [RXDCTL5] = 1 << 16, 4003 [RXDCTL6] = 1 << 16, 4004 [RXDCTL7] = 1 << 16, 4005 [RXDCTL8] = 1 << 16, 4006 [RXDCTL9] = 1 << 16, 4007 [RXDCTL10] = 1 << 16, 4008 [RXDCTL11] = 1 << 16, 4009 [RXDCTL12] = 1 << 16, 4010 [RXDCTL13] = 1 << 16, 4011 [RXDCTL14] = 1 << 16, 4012 [RXDCTL15] = 1 << 16, 4013 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20), 4014 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 | 4015 E1000_CTRL_ADVD3WUC, 4016 [STATUS] = E1000_STATUS_PHYRA | BIT(31), 4017 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES | 4018 (2 << E1000_EECD_SIZE_EX_SHIFT), 4019 [GCR] = E1000_L0S_ADJUST | 4020 E1000_GCR_CMPL_TMOUT_RESEND | 4021 E1000_GCR_CAP_VER2 | 4022 E1000_L1_ENTRY_LATENCY_MSB | 4023 E1000_L1_ENTRY_LATENCY_LSB, 4024 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 4025 [TXPBS] = 0x28, 4026 [RXPBS] = 0x40, 4027 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) | 4028 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28), 4029 [TCTL_EXT] = 0x40 | (0x42 << 10), 4030 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT, 4031 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16), 4032 4033 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI, 4034 [MBVFIMR] = 0xFF, 4035 [VFRE] = 0xFF, 4036 [VFTE] = 0xFF, 4037 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC, 4038 [RPLOLR] = E1000_RPLOLR_STRCRC, 4039 [RLPML] = 0x2600, 4040 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4041 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4042 E1000_DCA_TXCTRL_DESC_RRO_EN, 4043 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4044 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4045 E1000_DCA_TXCTRL_DESC_RRO_EN, 4046 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4047 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4048 E1000_DCA_TXCTRL_DESC_RRO_EN, 4049 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4050 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4051 E1000_DCA_TXCTRL_DESC_RRO_EN, 4052 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4053 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4054 E1000_DCA_TXCTRL_DESC_RRO_EN, 4055 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4056 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4057 E1000_DCA_TXCTRL_DESC_RRO_EN, 4058 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4059 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4060 E1000_DCA_TXCTRL_DESC_RRO_EN, 4061 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4062 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4063 E1000_DCA_TXCTRL_DESC_RRO_EN, 4064 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4065 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4066 E1000_DCA_TXCTRL_DESC_RRO_EN, 4067 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4068 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4069 E1000_DCA_TXCTRL_DESC_RRO_EN, 4070 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4071 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4072 E1000_DCA_TXCTRL_DESC_RRO_EN, 4073 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4074 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4075 E1000_DCA_TXCTRL_DESC_RRO_EN, 4076 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4077 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4078 E1000_DCA_TXCTRL_DESC_RRO_EN, 4079 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4080 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4081 E1000_DCA_TXCTRL_DESC_RRO_EN, 4082 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4083 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4084 E1000_DCA_TXCTRL_DESC_RRO_EN, 4085 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4086 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4087 E1000_DCA_TXCTRL_DESC_RRO_EN, 4088 }; 4089 4090 static void igb_reset(IGBCore *core, bool sw) 4091 { 4092 struct igb_tx *tx; 4093 int i; 4094 4095 timer_del(core->autoneg_timer); 4096 4097 igb_intrmgr_reset(core); 4098 4099 memset(core->phy, 0, sizeof core->phy); 4100 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init); 4101 4102 for (i = 0; i < E1000E_MAC_SIZE; i++) { 4103 if (sw && 4104 (i == RXPBS || i == TXPBS || 4105 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) { 4106 continue; 4107 } 4108 4109 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ? 4110 igb_mac_reg_init[i] : 0; 4111 } 4112 4113 if (qemu_get_queue(core->owner_nic)->link_down) { 4114 igb_link_down(core); 4115 } 4116 4117 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 4118 4119 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 4120 /* Set RSTI, so VF can identify a PF reset is in progress */ 4121 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI; 4122 } 4123 4124 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4125 tx = &core->tx[i]; 4126 net_tx_pkt_reset(tx->tx_pkt, NULL); 4127 memset(tx->ctx, 0, sizeof(tx->ctx)); 4128 tx->first = true; 4129 tx->skip_cp = false; 4130 } 4131 } 4132 4133 void 4134 igb_core_reset(IGBCore *core) 4135 { 4136 igb_reset(core, false); 4137 } 4138 4139 void igb_core_pre_save(IGBCore *core) 4140 { 4141 int i; 4142 NetClientState *nc = qemu_get_queue(core->owner_nic); 4143 4144 /* 4145 * If link is down and auto-negotiation is supported and ongoing, 4146 * complete auto-negotiation immediately. This allows us to look 4147 * at MII_BMSR_AN_COMP to infer link status on load. 4148 */ 4149 if (nc->link_down && igb_have_autoneg(core)) { 4150 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP; 4151 igb_update_flowctl_status(core); 4152 } 4153 4154 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4155 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 4156 core->tx[i].skip_cp = true; 4157 } 4158 } 4159 } 4160 4161 int 4162 igb_core_post_load(IGBCore *core) 4163 { 4164 NetClientState *nc = qemu_get_queue(core->owner_nic); 4165 4166 /* 4167 * nc.link_down can't be migrated, so infer link_down according 4168 * to link status bit in core.mac[STATUS]. 4169 */ 4170 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 4171 4172 return 0; 4173 } 4174