1 /* 2 * Core code for QEMU igb emulation 3 * 4 * Datasheet: 5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf 6 * 7 * Copyright (c) 2020-2023 Red Hat, Inc. 8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 9 * Developed by Daynix Computing LTD (http://www.daynix.com) 10 * 11 * Authors: 12 * Akihiko Odaki <akihiko.odaki@daynix.com> 13 * Gal Hammmer <gal.hammer@sap.com> 14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com> 15 * Dmitry Fleytman <dmitry@daynix.com> 16 * Leonid Bloch <leonid@daynix.com> 17 * Yan Vugenfirer <yan@daynix.com> 18 * 19 * Based on work done by: 20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 21 * Copyright (c) 2008 Qumranet 22 * Based on work done by: 23 * Copyright (c) 2007 Dan Aloni 24 * Copyright (c) 2004 Antony T Curtis 25 * 26 * This library is free software; you can redistribute it and/or 27 * modify it under the terms of the GNU Lesser General Public 28 * License as published by the Free Software Foundation; either 29 * version 2.1 of the License, or (at your option) any later version. 30 * 31 * This library is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 34 * Lesser General Public License for more details. 35 * 36 * You should have received a copy of the GNU Lesser General Public 37 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/log.h" 42 #include "net/net.h" 43 #include "net/tap.h" 44 #include "hw/net/mii.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "sysemu/runstate.h" 48 49 #include "net_tx_pkt.h" 50 #include "net_rx_pkt.h" 51 52 #include "igb_common.h" 53 #include "e1000x_common.h" 54 #include "igb_core.h" 55 56 #include "trace.h" 57 58 #define E1000E_MAX_TX_FRAGS (64) 59 60 union e1000_rx_desc_union { 61 struct e1000_rx_desc legacy; 62 union e1000_adv_rx_desc adv; 63 }; 64 65 typedef struct IGBTxPktVmdqCallbackContext { 66 IGBCore *core; 67 NetClientState *nc; 68 } IGBTxPktVmdqCallbackContext; 69 70 static ssize_t 71 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 72 bool has_vnet, bool *external_tx); 73 74 static inline void 75 igb_set_interrupt_cause(IGBCore *core, uint32_t val); 76 77 static void igb_update_interrupt_state(IGBCore *core); 78 static void igb_reset(IGBCore *core, bool sw); 79 80 static inline void 81 igb_raise_legacy_irq(IGBCore *core) 82 { 83 trace_e1000e_irq_legacy_notify(true); 84 e1000x_inc_reg_if_not_full(core->mac, IAC); 85 pci_set_irq(core->owner, 1); 86 } 87 88 static inline void 89 igb_lower_legacy_irq(IGBCore *core) 90 { 91 trace_e1000e_irq_legacy_notify(false); 92 pci_set_irq(core->owner, 0); 93 } 94 95 static void igb_msix_notify(IGBCore *core, unsigned int vector) 96 { 97 PCIDevice *dev = core->owner; 98 uint16_t vfn; 99 100 vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM; 101 if (vfn < pcie_sriov_num_vfs(core->owner)) { 102 dev = pcie_sriov_get_vf_at_index(core->owner, vfn); 103 assert(dev); 104 vector = (vector + 2) % IGBVF_MSIX_VEC_NUM; 105 } else if (vector >= IGB_MSIX_VEC_NUM) { 106 qemu_log_mask(LOG_GUEST_ERROR, 107 "igb: Tried to use vector unavailable for PF"); 108 return; 109 } 110 111 msix_notify(dev, vector); 112 } 113 114 static inline void 115 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) 116 { 117 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 118 timer->delay_resolution_ns; 119 120 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 121 122 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 123 124 timer->running = true; 125 } 126 127 static void 128 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer) 129 { 130 if (timer->running) { 131 igb_intrmgr_rearm_timer(timer); 132 } 133 } 134 135 static void 136 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer) 137 { 138 if (timer->running) { 139 timer_del(timer->timer); 140 } 141 } 142 143 static void 144 igb_intrmgr_on_msix_throttling_timer(void *opaque) 145 { 146 IGBIntrDelayTimer *timer = opaque; 147 int idx = timer - &timer->core->eitr[0]; 148 149 timer->running = false; 150 151 trace_e1000e_irq_msix_notify_postponed_vec(idx); 152 igb_msix_notify(timer->core, idx); 153 } 154 155 static void 156 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create) 157 { 158 int i; 159 160 for (i = 0; i < IGB_INTR_NUM; i++) { 161 core->eitr[i].core = core; 162 core->eitr[i].delay_reg = EITR0 + i; 163 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 164 } 165 166 if (!create) { 167 return; 168 } 169 170 for (i = 0; i < IGB_INTR_NUM; i++) { 171 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 172 igb_intrmgr_on_msix_throttling_timer, 173 &core->eitr[i]); 174 } 175 } 176 177 static void 178 igb_intrmgr_resume(IGBCore *core) 179 { 180 int i; 181 182 for (i = 0; i < IGB_INTR_NUM; i++) { 183 igb_intmgr_timer_resume(&core->eitr[i]); 184 } 185 } 186 187 static void 188 igb_intrmgr_pause(IGBCore *core) 189 { 190 int i; 191 192 for (i = 0; i < IGB_INTR_NUM; i++) { 193 igb_intmgr_timer_pause(&core->eitr[i]); 194 } 195 } 196 197 static void 198 igb_intrmgr_reset(IGBCore *core) 199 { 200 int i; 201 202 for (i = 0; i < IGB_INTR_NUM; i++) { 203 if (core->eitr[i].running) { 204 timer_del(core->eitr[i].timer); 205 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 206 } 207 } 208 } 209 210 static void 211 igb_intrmgr_pci_unint(IGBCore *core) 212 { 213 int i; 214 215 for (i = 0; i < IGB_INTR_NUM; i++) { 216 timer_free(core->eitr[i].timer); 217 } 218 } 219 220 static void 221 igb_intrmgr_pci_realize(IGBCore *core) 222 { 223 igb_intrmgr_initialize_all_timers(core, true); 224 } 225 226 static inline bool 227 igb_rx_csum_enabled(IGBCore *core) 228 { 229 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 230 } 231 232 static inline bool 233 igb_rx_use_legacy_descriptor(IGBCore *core) 234 { 235 /* 236 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx 237 * descriptor. 238 */ 239 return false; 240 } 241 242 static inline bool 243 igb_rss_enabled(IGBCore *core) 244 { 245 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ && 246 !igb_rx_csum_enabled(core) && 247 !igb_rx_use_legacy_descriptor(core); 248 } 249 250 typedef struct E1000E_RSSInfo_st { 251 bool enabled; 252 uint32_t hash; 253 uint32_t queue; 254 uint32_t type; 255 } E1000E_RSSInfo; 256 257 static uint32_t 258 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt) 259 { 260 bool hasip4, hasip6; 261 EthL4HdrProto l4hdr_proto; 262 263 assert(igb_rss_enabled(core)); 264 265 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 266 267 if (hasip4) { 268 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 269 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 270 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 271 272 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 273 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 274 return E1000_MRQ_RSS_TYPE_IPV4TCP; 275 } 276 277 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 278 return E1000_MRQ_RSS_TYPE_IPV4; 279 } 280 } else if (hasip6) { 281 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 282 283 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 284 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 285 286 /* 287 * Following two traces must not be combined because resulting 288 * event will have 11 arguments totally and some trace backends 289 * (at least "ust") have limitation of maximum 10 arguments per 290 * event. Events with more arguments fail to compile for 291 * backends like these. 292 */ 293 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 294 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 295 ip6info->has_ext_hdrs, 296 ip6info->rss_ex_dst_valid, 297 ip6info->rss_ex_src_valid, 298 core->mac[MRQC], 299 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 300 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 301 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 302 303 if ((!ex_dis || !ip6info->has_ext_hdrs) && 304 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 305 ip6info->rss_ex_src_valid))) { 306 307 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 308 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 309 return E1000_MRQ_RSS_TYPE_IPV6TCP; 310 } 311 312 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 313 return E1000_MRQ_RSS_TYPE_IPV6EX; 314 } 315 316 } 317 318 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 319 return E1000_MRQ_RSS_TYPE_IPV6; 320 } 321 322 } 323 324 return E1000_MRQ_RSS_TYPE_NONE; 325 } 326 327 static uint32_t 328 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info) 329 { 330 NetRxPktRssType type; 331 332 assert(igb_rss_enabled(core)); 333 334 switch (info->type) { 335 case E1000_MRQ_RSS_TYPE_IPV4: 336 type = NetPktRssIpV4; 337 break; 338 case E1000_MRQ_RSS_TYPE_IPV4TCP: 339 type = NetPktRssIpV4Tcp; 340 break; 341 case E1000_MRQ_RSS_TYPE_IPV6TCP: 342 type = NetPktRssIpV6TcpEx; 343 break; 344 case E1000_MRQ_RSS_TYPE_IPV6: 345 type = NetPktRssIpV6; 346 break; 347 case E1000_MRQ_RSS_TYPE_IPV6EX: 348 type = NetPktRssIpV6Ex; 349 break; 350 default: 351 assert(false); 352 return 0; 353 } 354 355 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 356 } 357 358 static void 359 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx, 360 E1000E_RSSInfo *info) 361 { 362 trace_e1000e_rx_rss_started(); 363 364 if (tx || !igb_rss_enabled(core)) { 365 info->enabled = false; 366 info->hash = 0; 367 info->queue = 0; 368 info->type = 0; 369 trace_e1000e_rx_rss_disabled(); 370 return; 371 } 372 373 info->enabled = true; 374 375 info->type = igb_rss_get_hash_type(core, pkt); 376 377 trace_e1000e_rx_rss_type(info->type); 378 379 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 380 info->hash = 0; 381 info->queue = 0; 382 return; 383 } 384 385 info->hash = igb_rss_calc_hash(core, pkt, info); 386 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 387 } 388 389 static bool 390 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx) 391 { 392 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) { 393 uint32_t idx = (tx->first_olinfo_status >> 4) & 1; 394 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> 16; 395 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) { 396 return false; 397 } 398 399 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 400 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 401 return true; 402 } 403 404 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) { 405 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 406 return false; 407 } 408 } 409 410 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) { 411 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 412 } 413 414 return true; 415 } 416 417 static void igb_tx_pkt_mac_callback(void *core, 418 const struct iovec *iov, 419 int iovcnt, 420 const struct iovec *virt_iov, 421 int virt_iovcnt) 422 { 423 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL); 424 } 425 426 static void igb_tx_pkt_vmdq_callback(void *opaque, 427 const struct iovec *iov, 428 int iovcnt, 429 const struct iovec *virt_iov, 430 int virt_iovcnt) 431 { 432 IGBTxPktVmdqCallbackContext *context = opaque; 433 bool external_tx; 434 435 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true, 436 &external_tx); 437 438 if (external_tx) { 439 if (context->core->has_vnet) { 440 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt); 441 } else { 442 qemu_sendv_packet(context->nc, iov, iovcnt); 443 } 444 } 445 } 446 447 /* TX Packets Switching (7.10.3.6) */ 448 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx, 449 NetClientState *nc) 450 { 451 IGBTxPktVmdqCallbackContext context; 452 453 /* TX switching is only used to serve VM to VM traffic. */ 454 if (!(core->mac[MRQC] & 1)) { 455 goto send_out; 456 } 457 458 /* TX switching requires DTXSWC.Loopback_en bit enabled. */ 459 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) { 460 goto send_out; 461 } 462 463 context.core = core; 464 context.nc = nc; 465 466 return net_tx_pkt_send_custom(tx->tx_pkt, false, 467 igb_tx_pkt_vmdq_callback, &context); 468 469 send_out: 470 return net_tx_pkt_send(tx->tx_pkt, nc); 471 } 472 473 static bool 474 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index) 475 { 476 int target_queue = MIN(core->max_queue_num, queue_index); 477 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 478 479 if (!igb_setup_tx_offloads(core, tx)) { 480 return false; 481 } 482 483 net_tx_pkt_dump(tx->tx_pkt); 484 485 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) || 486 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 487 return net_tx_pkt_send_custom(tx->tx_pkt, false, 488 igb_tx_pkt_mac_callback, core); 489 } else { 490 return igb_tx_pkt_switch(core, tx, queue); 491 } 492 } 493 494 static void 495 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt) 496 { 497 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 498 PTC1023, PTC1522 }; 499 500 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 501 502 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 503 e1000x_inc_reg_if_not_full(core->mac, TPT); 504 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 505 506 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 507 case ETH_PKT_BCAST: 508 e1000x_inc_reg_if_not_full(core->mac, BPTC); 509 break; 510 case ETH_PKT_MCAST: 511 e1000x_inc_reg_if_not_full(core->mac, MPTC); 512 break; 513 case ETH_PKT_UCAST: 514 break; 515 default: 516 g_assert_not_reached(); 517 } 518 519 core->mac[GPTC] = core->mac[TPT]; 520 core->mac[GOTCL] = core->mac[TOTL]; 521 core->mac[GOTCH] = core->mac[TOTH]; 522 } 523 524 static void 525 igb_process_tx_desc(IGBCore *core, 526 PCIDevice *dev, 527 struct igb_tx *tx, 528 union e1000_adv_tx_desc *tx_desc, 529 int queue_index) 530 { 531 struct e1000_adv_tx_context_desc *tx_ctx_desc; 532 uint32_t cmd_type_len; 533 uint32_t idx; 534 uint64_t buffer_addr; 535 uint16_t length; 536 537 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 538 539 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) { 540 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) == 541 E1000_ADVTXD_DTYP_DATA) { 542 /* advanced transmit data descriptor */ 543 if (tx->first) { 544 tx->first_cmd_type_len = cmd_type_len; 545 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status); 546 tx->first = false; 547 } 548 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) == 549 E1000_ADVTXD_DTYP_CTXT) { 550 /* advanced transmit context descriptor */ 551 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc; 552 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1; 553 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens); 554 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed); 555 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl); 556 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx); 557 return; 558 } else { 559 /* unknown descriptor type */ 560 return; 561 } 562 } else { 563 /* legacy descriptor */ 564 565 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */ 566 } 567 568 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr); 569 length = cmd_type_len & 0xFFFF; 570 571 if (!tx->skip_cp) { 572 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, buffer_addr, length)) { 573 tx->skip_cp = true; 574 } 575 } 576 577 if (cmd_type_len & E1000_TXD_CMD_EOP) { 578 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 579 if (cmd_type_len & E1000_TXD_CMD_VLE) { 580 idx = (tx->first_olinfo_status >> 4) & 1; 581 uint16_t vlan = tx->ctx[idx].vlan_macip_lens >> 16; 582 uint16_t vet = core->mac[VET] & 0xffff; 583 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan, vet); 584 } 585 if (igb_tx_pkt_send(core, tx, queue_index)) { 586 igb_on_tx_done_update_stats(core, tx->tx_pkt); 587 } 588 } 589 590 tx->first = true; 591 tx->skip_cp = false; 592 net_tx_pkt_reset(tx->tx_pkt, dev); 593 } 594 } 595 596 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx) 597 { 598 uint32_t n, ent = 0; 599 600 n = igb_ivar_entry_tx(queue_idx); 601 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 602 603 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 604 } 605 606 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx) 607 { 608 uint32_t n, ent = 0; 609 610 n = igb_ivar_entry_rx(queue_idx); 611 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 612 613 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 614 } 615 616 typedef struct E1000E_RingInfo_st { 617 int dbah; 618 int dbal; 619 int dlen; 620 int dh; 621 int dt; 622 int idx; 623 } E1000E_RingInfo; 624 625 static inline bool 626 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r) 627 { 628 return core->mac[r->dh] == core->mac[r->dt] || 629 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 630 } 631 632 static inline uint64_t 633 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r) 634 { 635 uint64_t bah = core->mac[r->dbah]; 636 uint64_t bal = core->mac[r->dbal]; 637 638 return (bah << 32) + bal; 639 } 640 641 static inline uint64_t 642 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r) 643 { 644 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 645 } 646 647 static inline void 648 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count) 649 { 650 core->mac[r->dh] += count; 651 652 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 653 core->mac[r->dh] = 0; 654 } 655 } 656 657 static inline uint32_t 658 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r) 659 { 660 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 661 core->mac[r->dh], core->mac[r->dt]); 662 663 if (core->mac[r->dh] <= core->mac[r->dt]) { 664 return core->mac[r->dt] - core->mac[r->dh]; 665 } 666 667 if (core->mac[r->dh] > core->mac[r->dt]) { 668 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 669 core->mac[r->dt] - core->mac[r->dh]; 670 } 671 672 g_assert_not_reached(); 673 return 0; 674 } 675 676 static inline bool 677 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r) 678 { 679 return core->mac[r->dlen] > 0; 680 } 681 682 typedef struct IGB_TxRing_st { 683 const E1000E_RingInfo *i; 684 struct igb_tx *tx; 685 } IGB_TxRing; 686 687 static inline int 688 igb_mq_queue_idx(int base_reg_idx, int reg_idx) 689 { 690 return (reg_idx - base_reg_idx) / 16; 691 } 692 693 static inline void 694 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx) 695 { 696 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 697 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 }, 698 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }, 699 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 }, 700 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 }, 701 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 }, 702 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 }, 703 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 }, 704 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 }, 705 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 }, 706 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 }, 707 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 }, 708 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 }, 709 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 }, 710 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 }, 711 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 }, 712 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 } 713 }; 714 715 assert(idx < ARRAY_SIZE(i)); 716 717 txr->i = &i[idx]; 718 txr->tx = &core->tx[idx]; 719 } 720 721 typedef struct E1000E_RxRing_st { 722 const E1000E_RingInfo *i; 723 } E1000E_RxRing; 724 725 static inline void 726 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx) 727 { 728 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 729 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 730 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }, 731 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 }, 732 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 }, 733 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 }, 734 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 }, 735 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 }, 736 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 }, 737 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 }, 738 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 }, 739 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 }, 740 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 }, 741 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 }, 742 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 }, 743 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 }, 744 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 } 745 }; 746 747 assert(idx < ARRAY_SIZE(i)); 748 749 rxr->i = &i[idx]; 750 } 751 752 static uint32_t 753 igb_txdesc_writeback(IGBCore *core, dma_addr_t base, 754 union e1000_adv_tx_desc *tx_desc, 755 const E1000E_RingInfo *txi) 756 { 757 PCIDevice *d; 758 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 759 uint64_t tdwba; 760 761 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2]; 762 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32; 763 764 if (!(cmd_type_len & E1000_TXD_CMD_RS)) { 765 return 0; 766 } 767 768 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 769 if (!d) { 770 d = core->owner; 771 } 772 773 if (tdwba & 1) { 774 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]); 775 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer)); 776 } else { 777 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD; 778 779 tx_desc->wb.status = cpu_to_le32(status); 780 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb), 781 &tx_desc->wb, sizeof(tx_desc->wb)); 782 } 783 784 return igb_tx_wb_eic(core, txi->idx); 785 } 786 787 static inline bool 788 igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi) 789 { 790 bool vmdq = core->mac[MRQC] & 1; 791 uint16_t qn = txi->idx; 792 uint16_t pool = qn % IGB_NUM_VM_POOLS; 793 794 return (core->mac[TCTL] & E1000_TCTL_EN) && 795 (!vmdq || core->mac[VFTE] & BIT(pool)) && 796 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE); 797 } 798 799 static void 800 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr) 801 { 802 PCIDevice *d; 803 dma_addr_t base; 804 union e1000_adv_tx_desc desc; 805 const E1000E_RingInfo *txi = txr->i; 806 uint32_t eic = 0; 807 808 if (!igb_tx_enabled(core, txi)) { 809 trace_e1000e_tx_disabled(); 810 return; 811 } 812 813 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 814 if (!d) { 815 d = core->owner; 816 } 817 818 net_tx_pkt_reset(txr->tx->tx_pkt, d); 819 820 while (!igb_ring_empty(core, txi)) { 821 base = igb_ring_head_descr(core, txi); 822 823 pci_dma_read(d, base, &desc, sizeof(desc)); 824 825 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr, 826 desc.read.cmd_type_len, desc.wb.status); 827 828 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx); 829 igb_ring_advance(core, txi, 1); 830 eic |= igb_txdesc_writeback(core, base, &desc, txi); 831 } 832 833 if (eic) { 834 core->mac[EICR] |= eic; 835 igb_set_interrupt_cause(core, E1000_ICR_TXDW); 836 } 837 } 838 839 static uint32_t 840 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r) 841 { 842 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2]; 843 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK; 844 if (bsizepkt) { 845 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT; 846 } 847 848 return e1000x_rxbufsize(core->mac[RCTL]); 849 } 850 851 static bool 852 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size) 853 { 854 uint32_t bufs = igb_ring_free_descr_num(core, r); 855 uint32_t bufsize = igb_rxbufsize(core, r); 856 857 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize); 858 859 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 860 bufsize; 861 } 862 863 void 864 igb_start_recv(IGBCore *core) 865 { 866 int i; 867 868 trace_e1000e_rx_start_recv(); 869 870 for (i = 0; i <= core->max_queue_num; i++) { 871 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 872 } 873 } 874 875 bool 876 igb_can_receive(IGBCore *core) 877 { 878 int i; 879 880 if (!e1000x_rx_ready(core->owner, core->mac)) { 881 return false; 882 } 883 884 for (i = 0; i < IGB_NUM_QUEUES; i++) { 885 E1000E_RxRing rxr; 886 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { 887 continue; 888 } 889 890 igb_rx_ring_init(core, &rxr, i); 891 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) { 892 trace_e1000e_rx_can_recv(); 893 return true; 894 } 895 } 896 897 trace_e1000e_rx_can_recv_rings_full(); 898 return false; 899 } 900 901 ssize_t 902 igb_receive(IGBCore *core, const uint8_t *buf, size_t size) 903 { 904 const struct iovec iov = { 905 .iov_base = (uint8_t *)buf, 906 .iov_len = size 907 }; 908 909 return igb_receive_iov(core, &iov, 1); 910 } 911 912 static inline bool 913 igb_rx_l3_cso_enabled(IGBCore *core) 914 { 915 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 916 } 917 918 static inline bool 919 igb_rx_l4_cso_enabled(IGBCore *core) 920 { 921 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 922 } 923 924 static bool 925 igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size) 926 { 927 uint16_t pool = qn % IGB_NUM_VM_POOLS; 928 bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE); 929 int max_ethernet_lpe_size = 930 core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK; 931 int max_ethernet_vlan_size = 1522; 932 933 return size > (lpe ? max_ethernet_lpe_size : max_ethernet_vlan_size); 934 } 935 936 static uint16_t igb_receive_assign(IGBCore *core, const struct eth_header *ehdr, 937 size_t size, E1000E_RSSInfo *rss_info, 938 bool *external_tx) 939 { 940 static const int ta_shift[] = { 4, 3, 2, 0 }; 941 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL]; 942 uint16_t queues = 0; 943 uint16_t oversized = 0; 944 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(ehdr)->h_tci) & VLAN_VID_MASK; 945 bool accepted = false; 946 int i; 947 948 memset(rss_info, 0, sizeof(E1000E_RSSInfo)); 949 950 if (external_tx) { 951 *external_tx = true; 952 } 953 954 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) && 955 e1000x_vlan_rx_filter_enabled(core->mac)) { 956 uint32_t vfta = 957 ldl_le_p((uint32_t *)(core->mac + VFTA) + 958 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK)); 959 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) { 960 trace_e1000e_rx_flt_vlan_mismatch(vid); 961 return queues; 962 } else { 963 trace_e1000e_rx_flt_vlan_match(vid); 964 } 965 } 966 967 if (core->mac[MRQC] & 1) { 968 if (is_broadcast_ether_addr(ehdr->h_dest)) { 969 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 970 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) { 971 queues |= BIT(i); 972 } 973 } 974 } else { 975 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) { 976 if (!(macp[1] & E1000_RAH_AV)) { 977 continue; 978 } 979 ra[0] = cpu_to_le32(macp[0]); 980 ra[1] = cpu_to_le32(macp[1]); 981 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 982 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 983 } 984 } 985 986 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 987 if (!(macp[1] & E1000_RAH_AV)) { 988 continue; 989 } 990 ra[0] = cpu_to_le32(macp[0]); 991 ra[1] = cpu_to_le32(macp[1]); 992 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 993 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 994 } 995 } 996 997 if (!queues) { 998 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA); 999 1000 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; 1001 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff; 1002 if (macp[f >> 5] & (1 << (f & 0x1f))) { 1003 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1004 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) { 1005 queues |= BIT(i); 1006 } 1007 } 1008 } 1009 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) { 1010 *external_tx = false; 1011 } 1012 } 1013 1014 if (e1000x_vlan_rx_filter_enabled(core->mac)) { 1015 uint16_t mask = 0; 1016 1017 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) { 1018 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 1019 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid && 1020 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) { 1021 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK; 1022 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT; 1023 } 1024 } 1025 } else { 1026 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1027 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) { 1028 mask |= BIT(i); 1029 } 1030 } 1031 } 1032 1033 queues &= mask; 1034 } 1035 1036 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx && 1037 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) { 1038 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK; 1039 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT); 1040 } 1041 1042 queues &= core->mac[VFRE]; 1043 if (queues) { 1044 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1045 if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) { 1046 oversized |= BIT(i); 1047 } 1048 } 1049 /* 8.19.37 increment ROC if packet is oversized for all queues */ 1050 if (oversized == queues) { 1051 trace_e1000x_rx_oversized(size); 1052 e1000x_inc_reg_if_not_full(core->mac, ROC); 1053 } 1054 queues &= ~oversized; 1055 } 1056 1057 if (queues) { 1058 igb_rss_parse_packet(core, core->rx_pkt, 1059 external_tx != NULL, rss_info); 1060 /* Sec 8.26.1: PQn = VFn + VQn*8 */ 1061 if (rss_info->queue & 1) { 1062 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1063 if ((queues & BIT(i)) && 1064 (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) { 1065 queues |= BIT(i + IGB_NUM_VM_POOLS); 1066 queues &= ~BIT(i); 1067 } 1068 } 1069 } 1070 } 1071 } else { 1072 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1073 case ETH_PKT_UCAST: 1074 if (rctl & E1000_RCTL_UPE) { 1075 accepted = true; /* promiscuous ucast */ 1076 } 1077 break; 1078 1079 case ETH_PKT_BCAST: 1080 if (rctl & E1000_RCTL_BAM) { 1081 accepted = true; /* broadcast enabled */ 1082 } 1083 break; 1084 1085 case ETH_PKT_MCAST: 1086 if (rctl & E1000_RCTL_MPE) { 1087 accepted = true; /* promiscuous mcast */ 1088 } 1089 break; 1090 1091 default: 1092 g_assert_not_reached(); 1093 } 1094 1095 if (!accepted) { 1096 accepted = e1000x_rx_group_filter(core->mac, ehdr->h_dest); 1097 } 1098 1099 if (!accepted) { 1100 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 1101 if (!(macp[1] & E1000_RAH_AV)) { 1102 continue; 1103 } 1104 ra[0] = cpu_to_le32(macp[0]); 1105 ra[1] = cpu_to_le32(macp[1]); 1106 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 1107 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2, 1108 MAC_ARG(ehdr->h_dest)); 1109 1110 accepted = true; 1111 break; 1112 } 1113 } 1114 } 1115 1116 if (accepted) { 1117 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info); 1118 queues = BIT(rss_info->queue); 1119 } 1120 } 1121 1122 return queues; 1123 } 1124 1125 static inline void 1126 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1127 hwaddr *buff_addr) 1128 { 1129 *buff_addr = le64_to_cpu(desc->buffer_addr); 1130 } 1131 1132 static inline void 1133 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1134 hwaddr *buff_addr) 1135 { 1136 *buff_addr = le64_to_cpu(desc->read.pkt_addr); 1137 } 1138 1139 static inline void 1140 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1141 hwaddr *buff_addr) 1142 { 1143 if (igb_rx_use_legacy_descriptor(core)) { 1144 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr); 1145 } else { 1146 igb_read_adv_rx_descr(core, &desc->adv, buff_addr); 1147 } 1148 } 1149 1150 static void 1151 igb_verify_csum_in_sw(IGBCore *core, 1152 struct NetRxPkt *pkt, 1153 uint32_t *status_flags, 1154 EthL4HdrProto l4hdr_proto) 1155 { 1156 bool csum_valid; 1157 uint32_t csum_error; 1158 1159 if (igb_rx_l3_cso_enabled(core)) { 1160 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1161 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1162 } else { 1163 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1164 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1165 } 1166 } else { 1167 trace_e1000e_rx_metadata_l3_cso_disabled(); 1168 } 1169 1170 if (!igb_rx_l4_cso_enabled(core)) { 1171 trace_e1000e_rx_metadata_l4_cso_disabled(); 1172 return; 1173 } 1174 1175 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1176 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1177 return; 1178 } 1179 1180 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1181 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1182 1183 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1184 *status_flags |= E1000_RXD_STAT_UDPCS; 1185 } 1186 } 1187 1188 static void 1189 igb_build_rx_metadata(IGBCore *core, 1190 struct NetRxPkt *pkt, 1191 bool is_eop, 1192 const E1000E_RSSInfo *rss_info, 1193 uint16_t *pkt_info, uint16_t *hdr_info, 1194 uint32_t *rss, 1195 uint32_t *status_flags, 1196 uint16_t *ip_id, 1197 uint16_t *vlan_tag) 1198 { 1199 struct virtio_net_hdr *vhdr; 1200 bool hasip4, hasip6; 1201 EthL4HdrProto l4hdr_proto; 1202 uint32_t pkt_type; 1203 1204 *status_flags = E1000_RXD_STAT_DD; 1205 1206 /* No additional metadata needed for non-EOP descriptors */ 1207 /* TODO: EOP apply only to status so don't skip whole function. */ 1208 if (!is_eop) { 1209 goto func_exit; 1210 } 1211 1212 *status_flags |= E1000_RXD_STAT_EOP; 1213 1214 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1215 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1216 1217 /* VLAN state */ 1218 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1219 *status_flags |= E1000_RXD_STAT_VP; 1220 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1221 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1222 } 1223 1224 /* Packet parsing results */ 1225 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1226 if (rss_info->enabled) { 1227 *rss = cpu_to_le32(rss_info->hash); 1228 trace_igb_rx_metadata_rss(*rss); 1229 } 1230 } else if (hasip4) { 1231 *status_flags |= E1000_RXD_STAT_IPIDV; 1232 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1233 trace_e1000e_rx_metadata_ip_id(*ip_id); 1234 } 1235 1236 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) { 1237 *status_flags |= E1000_RXD_STAT_ACK; 1238 trace_e1000e_rx_metadata_ack(); 1239 } 1240 1241 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1242 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1243 pkt_type = E1000_RXD_PKT_MAC; 1244 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1245 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1246 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1247 } else if (hasip4 || hasip6) { 1248 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1249 } else { 1250 pkt_type = E1000_RXD_PKT_MAC; 1251 } 1252 1253 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1254 1255 if (pkt_info) { 1256 if (rss_info->enabled) { 1257 *pkt_info = rss_info->type; 1258 } 1259 1260 *pkt_info |= (pkt_type << 4); 1261 } else { 1262 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1263 } 1264 1265 if (hdr_info) { 1266 *hdr_info = 0; 1267 } 1268 1269 /* RX CSO information */ 1270 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1271 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1272 goto func_exit; 1273 } 1274 1275 vhdr = net_rx_pkt_get_vhdr(pkt); 1276 1277 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1278 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1279 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1280 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1281 goto func_exit; 1282 } 1283 1284 if (igb_rx_l3_cso_enabled(core)) { 1285 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1286 } else { 1287 trace_e1000e_rx_metadata_l3_cso_disabled(); 1288 } 1289 1290 if (igb_rx_l4_cso_enabled(core)) { 1291 switch (l4hdr_proto) { 1292 case ETH_L4_HDR_PROTO_TCP: 1293 *status_flags |= E1000_RXD_STAT_TCPCS; 1294 break; 1295 1296 case ETH_L4_HDR_PROTO_UDP: 1297 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1298 break; 1299 1300 default: 1301 goto func_exit; 1302 } 1303 } else { 1304 trace_e1000e_rx_metadata_l4_cso_disabled(); 1305 } 1306 1307 trace_e1000e_rx_metadata_status_flags(*status_flags); 1308 1309 func_exit: 1310 *status_flags = cpu_to_le32(*status_flags); 1311 } 1312 1313 static inline void 1314 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1315 struct NetRxPkt *pkt, 1316 const E1000E_RSSInfo *rss_info, 1317 uint16_t length) 1318 { 1319 uint32_t status_flags, rss; 1320 uint16_t ip_id; 1321 1322 assert(!rss_info->enabled); 1323 desc->length = cpu_to_le16(length); 1324 desc->csum = 0; 1325 1326 igb_build_rx_metadata(core, pkt, pkt != NULL, 1327 rss_info, 1328 NULL, NULL, &rss, 1329 &status_flags, &ip_id, 1330 &desc->special); 1331 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1332 desc->status = (uint8_t) le32_to_cpu(status_flags); 1333 } 1334 1335 static inline void 1336 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1337 struct NetRxPkt *pkt, 1338 const E1000E_RSSInfo *rss_info, 1339 uint16_t length) 1340 { 1341 memset(&desc->wb, 0, sizeof(desc->wb)); 1342 1343 desc->wb.upper.length = cpu_to_le16(length); 1344 1345 igb_build_rx_metadata(core, pkt, pkt != NULL, 1346 rss_info, 1347 &desc->wb.lower.lo_dword.pkt_info, 1348 &desc->wb.lower.lo_dword.hdr_info, 1349 &desc->wb.lower.hi_dword.rss, 1350 &desc->wb.upper.status_error, 1351 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1352 &desc->wb.upper.vlan); 1353 } 1354 1355 static inline void 1356 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1357 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length) 1358 { 1359 if (igb_rx_use_legacy_descriptor(core)) { 1360 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length); 1361 } else { 1362 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length); 1363 } 1364 } 1365 1366 static inline void 1367 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr, 1368 union e1000_rx_desc_union *desc, dma_addr_t len) 1369 { 1370 if (igb_rx_use_legacy_descriptor(core)) { 1371 struct e1000_rx_desc *d = &desc->legacy; 1372 size_t offset = offsetof(struct e1000_rx_desc, status); 1373 uint8_t status = d->status; 1374 1375 d->status &= ~E1000_RXD_STAT_DD; 1376 pci_dma_write(dev, addr, desc, len); 1377 1378 if (status & E1000_RXD_STAT_DD) { 1379 d->status = status; 1380 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1381 } 1382 } else { 1383 union e1000_adv_rx_desc *d = &desc->adv; 1384 size_t offset = 1385 offsetof(union e1000_adv_rx_desc, wb.upper.status_error); 1386 uint32_t status = d->wb.upper.status_error; 1387 1388 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1389 pci_dma_write(dev, addr, desc, len); 1390 1391 if (status & E1000_RXD_STAT_DD) { 1392 d->wb.upper.status_error = status; 1393 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1394 } 1395 } 1396 } 1397 1398 static void 1399 igb_write_to_rx_buffers(IGBCore *core, 1400 PCIDevice *d, 1401 hwaddr ba, 1402 uint16_t *written, 1403 const char *data, 1404 dma_addr_t data_len) 1405 { 1406 trace_igb_rx_desc_buff_write(ba, *written, data, data_len); 1407 pci_dma_write(d, ba + *written, data, data_len); 1408 *written += data_len; 1409 } 1410 1411 static void 1412 igb_update_rx_stats(IGBCore *core, size_t data_size, size_t data_fcs_size) 1413 { 1414 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1415 1416 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1417 case ETH_PKT_BCAST: 1418 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1419 break; 1420 1421 case ETH_PKT_MCAST: 1422 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1423 break; 1424 1425 default: 1426 break; 1427 } 1428 } 1429 1430 static inline bool 1431 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi) 1432 { 1433 return igb_ring_free_descr_num(core, rxi) == 1434 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16; 1435 } 1436 1437 static void 1438 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt, 1439 const E1000E_RxRing *rxr, 1440 const E1000E_RSSInfo *rss_info) 1441 { 1442 PCIDevice *d; 1443 dma_addr_t base; 1444 union e1000_rx_desc_union desc; 1445 size_t desc_size; 1446 size_t desc_offset = 0; 1447 size_t iov_ofs = 0; 1448 1449 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1450 size_t size = net_rx_pkt_get_total_len(pkt); 1451 size_t total_size = size + e1000x_fcs_len(core->mac); 1452 const E1000E_RingInfo *rxi = rxr->i; 1453 size_t bufsize = igb_rxbufsize(core, rxi); 1454 1455 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8); 1456 if (!d) { 1457 d = core->owner; 1458 } 1459 1460 do { 1461 hwaddr ba; 1462 uint16_t written = 0; 1463 bool is_last = false; 1464 1465 desc_size = total_size - desc_offset; 1466 1467 if (desc_size > bufsize) { 1468 desc_size = bufsize; 1469 } 1470 1471 if (igb_ring_empty(core, rxi)) { 1472 return; 1473 } 1474 1475 base = igb_ring_head_descr(core, rxi); 1476 1477 pci_dma_read(d, base, &desc, core->rx_desc_len); 1478 1479 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1480 1481 igb_read_rx_descr(core, &desc, &ba); 1482 1483 if (ba) { 1484 if (desc_offset < size) { 1485 static const uint32_t fcs_pad; 1486 size_t iov_copy; 1487 size_t copy_size = size - desc_offset; 1488 if (copy_size > bufsize) { 1489 copy_size = bufsize; 1490 } 1491 1492 /* Copy packet payload */ 1493 while (copy_size) { 1494 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1495 1496 igb_write_to_rx_buffers(core, d, ba, &written, 1497 iov->iov_base + iov_ofs, iov_copy); 1498 1499 copy_size -= iov_copy; 1500 iov_ofs += iov_copy; 1501 if (iov_ofs == iov->iov_len) { 1502 iov++; 1503 iov_ofs = 0; 1504 } 1505 } 1506 1507 if (desc_offset + desc_size >= total_size) { 1508 /* Simulate FCS checksum presence in the last descriptor */ 1509 igb_write_to_rx_buffers(core, d, ba, &written, 1510 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1511 } 1512 } 1513 } else { /* as per intel docs; skip descriptors with null buf addr */ 1514 trace_e1000e_rx_null_descriptor(); 1515 } 1516 desc_offset += desc_size; 1517 if (desc_offset >= total_size) { 1518 is_last = true; 1519 } 1520 1521 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1522 rss_info, written); 1523 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len); 1524 1525 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1526 1527 } while (desc_offset < total_size); 1528 1529 igb_update_rx_stats(core, size, total_size); 1530 } 1531 1532 static inline void 1533 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt) 1534 { 1535 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1536 1537 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1538 net_rx_pkt_fix_l4_csum(pkt); 1539 } 1540 } 1541 1542 ssize_t 1543 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt) 1544 { 1545 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL); 1546 } 1547 1548 static ssize_t 1549 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 1550 bool has_vnet, bool *external_tx) 1551 { 1552 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4); 1553 1554 uint16_t queues = 0; 1555 uint32_t n = 0; 1556 uint8_t min_buf[ETH_ZLEN]; 1557 struct iovec min_iov; 1558 struct eth_header *ehdr; 1559 uint8_t *filter_buf; 1560 size_t size, orig_size; 1561 size_t iov_ofs = 0; 1562 E1000E_RxRing rxr; 1563 E1000E_RSSInfo rss_info; 1564 size_t total_size; 1565 int i; 1566 1567 trace_e1000e_rx_receive_iov(iovcnt); 1568 1569 if (external_tx) { 1570 *external_tx = true; 1571 } 1572 1573 if (!e1000x_hw_rx_enabled(core->mac)) { 1574 return -1; 1575 } 1576 1577 /* Pull virtio header in */ 1578 if (has_vnet) { 1579 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1580 iov_ofs = sizeof(struct virtio_net_hdr); 1581 } else { 1582 net_rx_pkt_unset_vhdr(core->rx_pkt); 1583 } 1584 1585 filter_buf = iov->iov_base + iov_ofs; 1586 orig_size = iov_size(iov, iovcnt); 1587 size = orig_size - iov_ofs; 1588 1589 /* Pad to minimum Ethernet frame length */ 1590 if (size < sizeof(min_buf)) { 1591 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1592 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1593 e1000x_inc_reg_if_not_full(core->mac, RUC); 1594 min_iov.iov_base = filter_buf = min_buf; 1595 min_iov.iov_len = size = sizeof(min_buf); 1596 iovcnt = 1; 1597 iov = &min_iov; 1598 iov_ofs = 0; 1599 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1600 /* This is very unlikely, but may happen. */ 1601 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1602 filter_buf = min_buf; 1603 } 1604 1605 /* Discard oversized packets if !LPE and !SBP. */ 1606 if (e1000x_is_oversized(core->mac, size)) { 1607 return orig_size; 1608 } 1609 1610 ehdr = PKT_GET_ETH_HDR(filter_buf); 1611 net_rx_pkt_set_packet_type(core->rx_pkt, get_eth_packet_type(ehdr)); 1612 1613 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1614 e1000x_vlan_enabled(core->mac), 1615 core->mac[VET] & 0xffff); 1616 1617 queues = igb_receive_assign(core, ehdr, size, &rss_info, external_tx); 1618 if (!queues) { 1619 trace_e1000e_rx_flt_dropped(); 1620 return orig_size; 1621 } 1622 1623 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1624 e1000x_fcs_len(core->mac); 1625 1626 for (i = 0; i < IGB_NUM_QUEUES; i++) { 1627 if (!(queues & BIT(i)) || 1628 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { 1629 continue; 1630 } 1631 1632 igb_rx_ring_init(core, &rxr, i); 1633 1634 if (!igb_has_rxbufs(core, rxr.i, total_size)) { 1635 n |= E1000_ICS_RXO; 1636 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1637 continue; 1638 } 1639 1640 n |= E1000_ICR_RXDW; 1641 1642 igb_rx_fix_l4_csum(core, core->rx_pkt); 1643 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1644 1645 /* Check if receive descriptor minimum threshold hit */ 1646 if (igb_rx_descr_threshold_hit(core, rxr.i)) { 1647 n |= E1000_ICS_RXDMT0; 1648 } 1649 1650 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx); 1651 1652 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1653 } 1654 1655 trace_e1000e_rx_interrupt_set(n); 1656 igb_set_interrupt_cause(core, n); 1657 1658 return orig_size; 1659 } 1660 1661 static inline bool 1662 igb_have_autoneg(IGBCore *core) 1663 { 1664 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN; 1665 } 1666 1667 static void igb_update_flowctl_status(IGBCore *core) 1668 { 1669 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) { 1670 trace_e1000e_link_autoneg_flowctl(true); 1671 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1672 } else { 1673 trace_e1000e_link_autoneg_flowctl(false); 1674 } 1675 } 1676 1677 static inline void 1678 igb_link_down(IGBCore *core) 1679 { 1680 e1000x_update_regs_on_link_down(core->mac, core->phy); 1681 igb_update_flowctl_status(core); 1682 } 1683 1684 static inline void 1685 igb_set_phy_ctrl(IGBCore *core, uint16_t val) 1686 { 1687 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1688 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART); 1689 1690 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) { 1691 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer); 1692 } 1693 } 1694 1695 void igb_core_set_link_status(IGBCore *core) 1696 { 1697 NetClientState *nc = qemu_get_queue(core->owner_nic); 1698 uint32_t old_status = core->mac[STATUS]; 1699 1700 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1701 1702 if (nc->link_down) { 1703 e1000x_update_regs_on_link_down(core->mac, core->phy); 1704 } else { 1705 if (igb_have_autoneg(core) && 1706 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 1707 e1000x_restart_autoneg(core->mac, core->phy, 1708 core->autoneg_timer); 1709 } else { 1710 e1000x_update_regs_on_link_up(core->mac, core->phy); 1711 igb_start_recv(core); 1712 } 1713 } 1714 1715 if (core->mac[STATUS] != old_status) { 1716 igb_set_interrupt_cause(core, E1000_ICR_LSC); 1717 } 1718 } 1719 1720 static void 1721 igb_set_ctrl(IGBCore *core, int index, uint32_t val) 1722 { 1723 trace_e1000e_core_ctrl_write(index, val); 1724 1725 /* RST is self clearing */ 1726 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1727 core->mac[CTRL_DUP] = core->mac[CTRL]; 1728 1729 trace_e1000e_link_set_params( 1730 !!(val & E1000_CTRL_ASDE), 1731 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1732 !!(val & E1000_CTRL_FRCSPD), 1733 !!(val & E1000_CTRL_FRCDPX), 1734 !!(val & E1000_CTRL_RFCE), 1735 !!(val & E1000_CTRL_TFCE)); 1736 1737 if (val & E1000_CTRL_RST) { 1738 trace_e1000e_core_ctrl_sw_reset(); 1739 igb_reset(core, true); 1740 } 1741 1742 if (val & E1000_CTRL_PHY_RST) { 1743 trace_e1000e_core_ctrl_phy_reset(); 1744 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1745 } 1746 } 1747 1748 static void 1749 igb_set_rfctl(IGBCore *core, int index, uint32_t val) 1750 { 1751 trace_e1000e_rx_set_rfctl(val); 1752 1753 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1754 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1755 } 1756 1757 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1758 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1759 } 1760 1761 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1762 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1763 } 1764 1765 core->mac[RFCTL] = val; 1766 } 1767 1768 static void 1769 igb_calc_rxdesclen(IGBCore *core) 1770 { 1771 if (igb_rx_use_legacy_descriptor(core)) { 1772 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1773 } else { 1774 core->rx_desc_len = sizeof(union e1000_adv_rx_desc); 1775 } 1776 trace_e1000e_rx_desc_len(core->rx_desc_len); 1777 } 1778 1779 static void 1780 igb_set_rx_control(IGBCore *core, int index, uint32_t val) 1781 { 1782 core->mac[RCTL] = val; 1783 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1784 1785 if (val & E1000_RCTL_DTYP_MASK) { 1786 qemu_log_mask(LOG_GUEST_ERROR, 1787 "igb: RCTL.DTYP must be zero for compatibility"); 1788 } 1789 1790 if (val & E1000_RCTL_EN) { 1791 igb_calc_rxdesclen(core); 1792 igb_start_recv(core); 1793 } 1794 } 1795 1796 static inline void 1797 igb_clear_ims_bits(IGBCore *core, uint32_t bits) 1798 { 1799 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1800 core->mac[IMS] &= ~bits; 1801 } 1802 1803 static inline bool 1804 igb_postpone_interrupt(IGBIntrDelayTimer *timer) 1805 { 1806 if (timer->running) { 1807 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1808 1809 return true; 1810 } 1811 1812 if (timer->core->mac[timer->delay_reg] != 0) { 1813 igb_intrmgr_rearm_timer(timer); 1814 } 1815 1816 return false; 1817 } 1818 1819 static inline bool 1820 igb_eitr_should_postpone(IGBCore *core, int idx) 1821 { 1822 return igb_postpone_interrupt(&core->eitr[idx]); 1823 } 1824 1825 static void igb_send_msix(IGBCore *core) 1826 { 1827 uint32_t causes = core->mac[EICR] & core->mac[EIMS]; 1828 uint32_t effective_eiac; 1829 int vector; 1830 1831 for (vector = 0; vector < IGB_INTR_NUM; ++vector) { 1832 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) { 1833 1834 trace_e1000e_irq_msix_notify_vec(vector); 1835 igb_msix_notify(core, vector); 1836 1837 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]); 1838 effective_eiac = core->mac[EIAC] & BIT(vector); 1839 core->mac[EICR] &= ~effective_eiac; 1840 } 1841 } 1842 } 1843 1844 static inline void 1845 igb_fix_icr_asserted(IGBCore *core) 1846 { 1847 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 1848 if (core->mac[ICR]) { 1849 core->mac[ICR] |= E1000_ICR_ASSERTED; 1850 } 1851 1852 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 1853 } 1854 1855 static void 1856 igb_update_interrupt_state(IGBCore *core) 1857 { 1858 uint32_t icr; 1859 uint32_t causes; 1860 uint32_t int_alloc; 1861 1862 icr = core->mac[ICR] & core->mac[IMS]; 1863 1864 if (msix_enabled(core->owner)) { 1865 if (icr) { 1866 causes = 0; 1867 if (icr & E1000_ICR_DRSTA) { 1868 int_alloc = core->mac[IVAR_MISC] & 0xff; 1869 if (int_alloc & E1000_IVAR_VALID) { 1870 causes |= BIT(int_alloc & 0x1f); 1871 } 1872 } 1873 /* Check if other bits (excluding the TCP Timer) are enabled. */ 1874 if (icr & ~E1000_ICR_DRSTA) { 1875 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff; 1876 if (int_alloc & E1000_IVAR_VALID) { 1877 causes |= BIT(int_alloc & 0x1f); 1878 } 1879 trace_e1000e_irq_add_msi_other(core->mac[EICR]); 1880 } 1881 core->mac[EICR] |= causes; 1882 } 1883 1884 if ((core->mac[EICR] & core->mac[EIMS])) { 1885 igb_send_msix(core); 1886 } 1887 } else { 1888 igb_fix_icr_asserted(core); 1889 1890 if (icr) { 1891 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER; 1892 } else { 1893 core->mac[EICR] &= ~E1000_EICR_OTHER; 1894 } 1895 1896 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 1897 core->mac[ICR], core->mac[IMS]); 1898 1899 if (msi_enabled(core->owner)) { 1900 if (icr) { 1901 msi_notify(core->owner, 0); 1902 } 1903 } else { 1904 if (icr) { 1905 igb_raise_legacy_irq(core); 1906 } else { 1907 igb_lower_legacy_irq(core); 1908 } 1909 } 1910 } 1911 } 1912 1913 static void 1914 igb_set_interrupt_cause(IGBCore *core, uint32_t val) 1915 { 1916 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 1917 1918 core->mac[ICR] |= val; 1919 1920 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 1921 1922 igb_update_interrupt_state(core); 1923 } 1924 1925 static void igb_set_eics(IGBCore *core, int index, uint32_t val) 1926 { 1927 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1928 1929 trace_igb_irq_write_eics(val, msix); 1930 1931 core->mac[EICS] |= 1932 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1933 1934 /* 1935 * TODO: Move to igb_update_interrupt_state if EICS is modified in other 1936 * places. 1937 */ 1938 core->mac[EICR] = core->mac[EICS]; 1939 1940 igb_update_interrupt_state(core); 1941 } 1942 1943 static void igb_set_eims(IGBCore *core, int index, uint32_t val) 1944 { 1945 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1946 1947 trace_igb_irq_write_eims(val, msix); 1948 1949 core->mac[EIMS] |= 1950 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1951 1952 igb_update_interrupt_state(core); 1953 } 1954 1955 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) 1956 { 1957 uint32_t ent = core->mac[VTIVAR_MISC + vfn]; 1958 1959 if ((ent & E1000_IVAR_VALID)) { 1960 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM); 1961 igb_update_interrupt_state(core); 1962 } 1963 } 1964 1965 static void mailbox_interrupt_to_pf(IGBCore *core) 1966 { 1967 igb_set_interrupt_cause(core, E1000_ICR_VMMB); 1968 } 1969 1970 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val) 1971 { 1972 uint16_t vfn = index - P2VMAILBOX0; 1973 1974 trace_igb_set_pfmailbox(vfn, val); 1975 1976 if (val & E1000_P2VMAILBOX_STS) { 1977 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS; 1978 mailbox_interrupt_to_vf(core, vfn); 1979 } 1980 1981 if (val & E1000_P2VMAILBOX_ACK) { 1982 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK; 1983 mailbox_interrupt_to_vf(core, vfn); 1984 } 1985 1986 /* Buffer Taken by PF (can be set only if the VFU is cleared). */ 1987 if (val & E1000_P2VMAILBOX_PFU) { 1988 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) { 1989 core->mac[index] |= E1000_P2VMAILBOX_PFU; 1990 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU; 1991 } 1992 } else { 1993 core->mac[index] &= ~E1000_P2VMAILBOX_PFU; 1994 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU; 1995 } 1996 1997 if (val & E1000_P2VMAILBOX_RVFU) { 1998 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU; 1999 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) | 2000 (E1000_MBVFICR_VFREQ_VF1 << vfn)); 2001 } 2002 } 2003 2004 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) 2005 { 2006 uint16_t vfn = index - V2PMAILBOX0; 2007 2008 trace_igb_set_vfmailbox(vfn, val); 2009 2010 if (val & E1000_V2PMAILBOX_REQ) { 2011 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn; 2012 mailbox_interrupt_to_pf(core); 2013 } 2014 2015 if (val & E1000_V2PMAILBOX_ACK) { 2016 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn; 2017 mailbox_interrupt_to_pf(core); 2018 } 2019 2020 /* Buffer Taken by VF (can be set only if the PFU is cleared). */ 2021 if (val & E1000_V2PMAILBOX_VFU) { 2022 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) { 2023 core->mac[index] |= E1000_V2PMAILBOX_VFU; 2024 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU; 2025 } 2026 } else { 2027 core->mac[index] &= ~E1000_V2PMAILBOX_VFU; 2028 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU; 2029 } 2030 } 2031 2032 static void igb_vf_reset(IGBCore *core, uint16_t vfn) 2033 { 2034 uint16_t qn0 = vfn; 2035 uint16_t qn1 = vfn + IGB_NUM_VM_POOLS; 2036 2037 /* disable Rx and Tx for the VF*/ 2038 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; 2039 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; 2040 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; 2041 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; 2042 core->mac[VFRE] &= ~BIT(vfn); 2043 core->mac[VFTE] &= ~BIT(vfn); 2044 /* indicate VF reset to PF */ 2045 core->mac[VFLRE] |= BIT(vfn); 2046 /* VFLRE and mailbox use the same interrupt cause */ 2047 mailbox_interrupt_to_pf(core); 2048 } 2049 2050 static void igb_w1c(IGBCore *core, int index, uint32_t val) 2051 { 2052 core->mac[index] &= ~val; 2053 } 2054 2055 static void igb_set_eimc(IGBCore *core, int index, uint32_t val) 2056 { 2057 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2058 2059 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */ 2060 core->mac[EIMS] &= 2061 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2062 2063 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix); 2064 igb_update_interrupt_state(core); 2065 } 2066 2067 static void igb_set_eiac(IGBCore *core, int index, uint32_t val) 2068 { 2069 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2070 2071 if (msix) { 2072 trace_igb_irq_write_eiac(val); 2073 2074 /* 2075 * TODO: When using IOV, the bits that correspond to MSI-X vectors 2076 * that are assigned to a VF are read-only. 2077 */ 2078 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK); 2079 } 2080 } 2081 2082 static void igb_set_eiam(IGBCore *core, int index, uint32_t val) 2083 { 2084 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2085 2086 /* 2087 * TODO: When using IOV, the bits that correspond to MSI-X vectors that 2088 * are assigned to a VF are read-only. 2089 */ 2090 core->mac[EIAM] |= 2091 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2092 2093 trace_igb_irq_write_eiam(val, msix); 2094 } 2095 2096 static void igb_set_eicr(IGBCore *core, int index, uint32_t val) 2097 { 2098 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2099 2100 /* 2101 * TODO: In IOV mode, only bit zero of this vector is available for the PF 2102 * function. 2103 */ 2104 core->mac[EICR] &= 2105 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2106 2107 trace_igb_irq_write_eicr(val, msix); 2108 igb_update_interrupt_state(core); 2109 } 2110 2111 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val) 2112 { 2113 uint16_t vfn; 2114 2115 if (val & E1000_CTRL_RST) { 2116 vfn = (index - PVTCTRL0) / 0x40; 2117 igb_vf_reset(core, vfn); 2118 } 2119 } 2120 2121 static void igb_set_vteics(IGBCore *core, int index, uint32_t val) 2122 { 2123 uint16_t vfn = (index - PVTEICS0) / 0x40; 2124 2125 core->mac[index] = val; 2126 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2127 } 2128 2129 static void igb_set_vteims(IGBCore *core, int index, uint32_t val) 2130 { 2131 uint16_t vfn = (index - PVTEIMS0) / 0x40; 2132 2133 core->mac[index] = val; 2134 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2135 } 2136 2137 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val) 2138 { 2139 uint16_t vfn = (index - PVTEIMC0) / 0x40; 2140 2141 core->mac[index] = val; 2142 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2143 } 2144 2145 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val) 2146 { 2147 uint16_t vfn = (index - PVTEIAC0) / 0x40; 2148 2149 core->mac[index] = val; 2150 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2151 } 2152 2153 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val) 2154 { 2155 uint16_t vfn = (index - PVTEIAM0) / 0x40; 2156 2157 core->mac[index] = val; 2158 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2159 } 2160 2161 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val) 2162 { 2163 uint16_t vfn = (index - PVTEICR0) / 0x40; 2164 2165 core->mac[index] = val; 2166 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2167 } 2168 2169 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val) 2170 { 2171 uint16_t vfn = (index - VTIVAR); 2172 uint16_t qn = vfn; 2173 uint8_t ent; 2174 int n; 2175 2176 core->mac[index] = val; 2177 2178 /* Get assigned vector associated with queue Rx#0. */ 2179 if ((val & E1000_IVAR_VALID)) { 2180 n = igb_ivar_entry_rx(qn); 2181 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7))); 2182 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2183 } 2184 2185 /* Get assigned vector associated with queue Tx#0 */ 2186 ent = val >> 8; 2187 if ((ent & E1000_IVAR_VALID)) { 2188 n = igb_ivar_entry_tx(qn); 2189 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7))); 2190 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2191 } 2192 2193 /* 2194 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now. 2195 */ 2196 } 2197 2198 static inline void 2199 igb_autoneg_timer(void *opaque) 2200 { 2201 IGBCore *core = opaque; 2202 if (!qemu_get_queue(core->owner_nic)->link_down) { 2203 e1000x_update_regs_on_autoneg_done(core->mac, core->phy); 2204 igb_start_recv(core); 2205 2206 igb_update_flowctl_status(core); 2207 /* signal link status change to the guest */ 2208 igb_set_interrupt_cause(core, E1000_ICR_LSC); 2209 } 2210 } 2211 2212 static inline uint16_t 2213 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2214 { 2215 uint16_t index = (addr & 0x1ffff) >> 2; 2216 return index + (mac_reg_access[index] & 0xfffe); 2217 } 2218 2219 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = { 2220 [MII_BMCR] = PHY_RW, 2221 [MII_BMSR] = PHY_R, 2222 [MII_PHYID1] = PHY_R, 2223 [MII_PHYID2] = PHY_R, 2224 [MII_ANAR] = PHY_RW, 2225 [MII_ANLPAR] = PHY_R, 2226 [MII_ANER] = PHY_R, 2227 [MII_ANNP] = PHY_RW, 2228 [MII_ANLPRNP] = PHY_R, 2229 [MII_CTRL1000] = PHY_RW, 2230 [MII_STAT1000] = PHY_R, 2231 [MII_EXTSTAT] = PHY_R, 2232 2233 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW, 2234 [IGP01E1000_PHY_PORT_STATUS] = PHY_R, 2235 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW, 2236 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R, 2237 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW, 2238 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W 2239 }; 2240 2241 static void 2242 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data) 2243 { 2244 assert(addr <= MAX_PHY_REG_ADDRESS); 2245 2246 if (addr == MII_BMCR) { 2247 igb_set_phy_ctrl(core, data); 2248 } else { 2249 core->phy[addr] = data; 2250 } 2251 } 2252 2253 static void 2254 igb_set_mdic(IGBCore *core, int index, uint32_t val) 2255 { 2256 uint32_t data = val & E1000_MDIC_DATA_MASK; 2257 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2258 2259 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2260 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2261 } else if (val & E1000_MDIC_OP_READ) { 2262 if (!(igb_phy_regcap[addr] & PHY_R)) { 2263 trace_igb_core_mdic_read_unhandled(addr); 2264 val |= E1000_MDIC_ERROR; 2265 } else { 2266 val = (val ^ data) | core->phy[addr]; 2267 trace_igb_core_mdic_read(addr, val); 2268 } 2269 } else if (val & E1000_MDIC_OP_WRITE) { 2270 if (!(igb_phy_regcap[addr] & PHY_W)) { 2271 trace_igb_core_mdic_write_unhandled(addr); 2272 val |= E1000_MDIC_ERROR; 2273 } else { 2274 trace_igb_core_mdic_write(addr, data); 2275 igb_phy_reg_write(core, addr, data); 2276 } 2277 } 2278 core->mac[MDIC] = val | E1000_MDIC_READY; 2279 2280 if (val & E1000_MDIC_INT_EN) { 2281 igb_set_interrupt_cause(core, E1000_ICR_MDAC); 2282 } 2283 } 2284 2285 static void 2286 igb_set_rdt(IGBCore *core, int index, uint32_t val) 2287 { 2288 core->mac[index] = val & 0xffff; 2289 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val); 2290 igb_start_recv(core); 2291 } 2292 2293 static void 2294 igb_set_status(IGBCore *core, int index, uint32_t val) 2295 { 2296 if ((val & E1000_STATUS_PHYRA) == 0) { 2297 core->mac[index] &= ~E1000_STATUS_PHYRA; 2298 } 2299 } 2300 2301 static void 2302 igb_set_ctrlext(IGBCore *core, int index, uint32_t val) 2303 { 2304 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2305 !!(val & E1000_CTRL_EXT_SPD_BYPS), 2306 !!(val & E1000_CTRL_EXT_PFRSTD)); 2307 2308 /* Zero self-clearing bits */ 2309 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2310 core->mac[CTRL_EXT] = val; 2311 2312 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) { 2313 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 2314 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; 2315 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD; 2316 } 2317 } 2318 } 2319 2320 static void 2321 igb_set_pbaclr(IGBCore *core, int index, uint32_t val) 2322 { 2323 int i; 2324 2325 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2326 2327 if (!msix_enabled(core->owner)) { 2328 return; 2329 } 2330 2331 for (i = 0; i < IGB_INTR_NUM; i++) { 2332 if (core->mac[PBACLR] & BIT(i)) { 2333 msix_clr_pending(core->owner, i); 2334 } 2335 } 2336 } 2337 2338 static void 2339 igb_set_fcrth(IGBCore *core, int index, uint32_t val) 2340 { 2341 core->mac[FCRTH] = val & 0xFFF8; 2342 } 2343 2344 static void 2345 igb_set_fcrtl(IGBCore *core, int index, uint32_t val) 2346 { 2347 core->mac[FCRTL] = val & 0x8000FFF8; 2348 } 2349 2350 #define IGB_LOW_BITS_SET_FUNC(num) \ 2351 static void \ 2352 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \ 2353 { \ 2354 core->mac[index] = val & (BIT(num) - 1); \ 2355 } 2356 2357 IGB_LOW_BITS_SET_FUNC(4) 2358 IGB_LOW_BITS_SET_FUNC(13) 2359 IGB_LOW_BITS_SET_FUNC(16) 2360 2361 static void 2362 igb_set_dlen(IGBCore *core, int index, uint32_t val) 2363 { 2364 core->mac[index] = val & 0xffff0; 2365 } 2366 2367 static void 2368 igb_set_dbal(IGBCore *core, int index, uint32_t val) 2369 { 2370 core->mac[index] = val & E1000_XDBAL_MASK; 2371 } 2372 2373 static void 2374 igb_set_tdt(IGBCore *core, int index, uint32_t val) 2375 { 2376 IGB_TxRing txr; 2377 int qn = igb_mq_queue_idx(TDT0, index); 2378 2379 core->mac[index] = val & 0xffff; 2380 2381 igb_tx_ring_init(core, &txr, qn); 2382 igb_start_xmit(core, &txr); 2383 } 2384 2385 static void 2386 igb_set_ics(IGBCore *core, int index, uint32_t val) 2387 { 2388 trace_e1000e_irq_write_ics(val); 2389 igb_set_interrupt_cause(core, val); 2390 } 2391 2392 static void 2393 igb_set_imc(IGBCore *core, int index, uint32_t val) 2394 { 2395 trace_e1000e_irq_ims_clear_set_imc(val); 2396 igb_clear_ims_bits(core, val); 2397 igb_update_interrupt_state(core); 2398 } 2399 2400 static void 2401 igb_set_ims(IGBCore *core, int index, uint32_t val) 2402 { 2403 uint32_t valid_val = val & 0x77D4FBFD; 2404 2405 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2406 core->mac[IMS] |= valid_val; 2407 igb_update_interrupt_state(core); 2408 } 2409 2410 static void igb_commit_icr(IGBCore *core) 2411 { 2412 /* 2413 * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at 2414 * least one bit is set in the IMS and there is a true interrupt as 2415 * reflected in ICR.INTA. 2416 */ 2417 if ((core->mac[GPIE] & E1000_GPIE_NSICR) || 2418 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) { 2419 igb_set_ims(core, IMS, core->mac[IAM]); 2420 } else { 2421 igb_update_interrupt_state(core); 2422 } 2423 } 2424 2425 static void igb_set_icr(IGBCore *core, int index, uint32_t val) 2426 { 2427 uint32_t icr = core->mac[ICR] & ~val; 2428 2429 trace_igb_irq_icr_write(val, core->mac[ICR], icr); 2430 core->mac[ICR] = icr; 2431 igb_commit_icr(core); 2432 } 2433 2434 static uint32_t 2435 igb_mac_readreg(IGBCore *core, int index) 2436 { 2437 return core->mac[index]; 2438 } 2439 2440 static uint32_t 2441 igb_mac_ics_read(IGBCore *core, int index) 2442 { 2443 trace_e1000e_irq_read_ics(core->mac[ICS]); 2444 return core->mac[ICS]; 2445 } 2446 2447 static uint32_t 2448 igb_mac_ims_read(IGBCore *core, int index) 2449 { 2450 trace_e1000e_irq_read_ims(core->mac[IMS]); 2451 return core->mac[IMS]; 2452 } 2453 2454 static uint32_t 2455 igb_mac_swsm_read(IGBCore *core, int index) 2456 { 2457 uint32_t val = core->mac[SWSM]; 2458 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2459 return val; 2460 } 2461 2462 static uint32_t 2463 igb_mac_eitr_read(IGBCore *core, int index) 2464 { 2465 return core->eitr_guest_value[index - EITR0]; 2466 } 2467 2468 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index) 2469 { 2470 uint32_t val = core->mac[index]; 2471 2472 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK | 2473 E1000_V2PMAILBOX_RSTD); 2474 2475 return val; 2476 } 2477 2478 static uint32_t 2479 igb_mac_icr_read(IGBCore *core, int index) 2480 { 2481 uint32_t ret = core->mac[ICR]; 2482 trace_e1000e_irq_icr_read_entry(ret); 2483 2484 if (core->mac[GPIE] & E1000_GPIE_NSICR) { 2485 trace_igb_irq_icr_clear_gpie_nsicr(); 2486 core->mac[ICR] = 0; 2487 } else if (core->mac[IMS] == 0) { 2488 trace_e1000e_irq_icr_clear_zero_ims(); 2489 core->mac[ICR] = 0; 2490 } else if (!msix_enabled(core->owner)) { 2491 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2492 core->mac[ICR] = 0; 2493 } 2494 2495 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2496 igb_commit_icr(core); 2497 return ret; 2498 } 2499 2500 static uint32_t 2501 igb_mac_read_clr4(IGBCore *core, int index) 2502 { 2503 uint32_t ret = core->mac[index]; 2504 2505 core->mac[index] = 0; 2506 return ret; 2507 } 2508 2509 static uint32_t 2510 igb_mac_read_clr8(IGBCore *core, int index) 2511 { 2512 uint32_t ret = core->mac[index]; 2513 2514 core->mac[index] = 0; 2515 core->mac[index - 1] = 0; 2516 return ret; 2517 } 2518 2519 static uint32_t 2520 igb_get_ctrl(IGBCore *core, int index) 2521 { 2522 uint32_t val = core->mac[CTRL]; 2523 2524 trace_e1000e_link_read_params( 2525 !!(val & E1000_CTRL_ASDE), 2526 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2527 !!(val & E1000_CTRL_FRCSPD), 2528 !!(val & E1000_CTRL_FRCDPX), 2529 !!(val & E1000_CTRL_RFCE), 2530 !!(val & E1000_CTRL_TFCE)); 2531 2532 return val; 2533 } 2534 2535 static uint32_t igb_get_status(IGBCore *core, int index) 2536 { 2537 uint32_t res = core->mac[STATUS]; 2538 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner); 2539 2540 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2541 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2542 } else { 2543 res |= E1000_STATUS_FD; 2544 } 2545 2546 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2547 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2548 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2549 case E1000_CTRL_SPD_10: 2550 res |= E1000_STATUS_SPEED_10; 2551 break; 2552 case E1000_CTRL_SPD_100: 2553 res |= E1000_STATUS_SPEED_100; 2554 break; 2555 case E1000_CTRL_SPD_1000: 2556 default: 2557 res |= E1000_STATUS_SPEED_1000; 2558 break; 2559 } 2560 } else { 2561 res |= E1000_STATUS_SPEED_1000; 2562 } 2563 2564 if (num_vfs) { 2565 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT; 2566 res |= E1000_STATUS_IOV_MODE; 2567 } 2568 2569 /* 2570 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is 2571 * left set after E1000_CTRL_LRST is set. 2572 */ 2573 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) && 2574 !(core->mac[CTRL] & E1000_CTRL_LRST)) { 2575 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2576 } 2577 2578 return res; 2579 } 2580 2581 static void 2582 igb_mac_writereg(IGBCore *core, int index, uint32_t val) 2583 { 2584 core->mac[index] = val; 2585 } 2586 2587 static void 2588 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val) 2589 { 2590 uint32_t macaddr[2]; 2591 2592 core->mac[index] = val; 2593 2594 macaddr[0] = cpu_to_le32(core->mac[RA]); 2595 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2596 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2597 (uint8_t *) macaddr); 2598 2599 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2600 } 2601 2602 static void 2603 igb_set_eecd(IGBCore *core, int index, uint32_t val) 2604 { 2605 static const uint32_t ro_bits = E1000_EECD_PRES | 2606 E1000_EECD_AUTO_RD | 2607 E1000_EECD_SIZE_EX_MASK; 2608 2609 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2610 } 2611 2612 static void 2613 igb_set_eerd(IGBCore *core, int index, uint32_t val) 2614 { 2615 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2616 uint32_t flags = 0; 2617 uint32_t data = 0; 2618 2619 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2620 data = core->eeprom[addr]; 2621 flags = E1000_EERW_DONE; 2622 } 2623 2624 core->mac[EERD] = flags | 2625 (addr << E1000_EERW_ADDR_SHIFT) | 2626 (data << E1000_EERW_DATA_SHIFT); 2627 } 2628 2629 static void 2630 igb_set_eitr(IGBCore *core, int index, uint32_t val) 2631 { 2632 uint32_t eitr_num = index - EITR0; 2633 2634 trace_igb_irq_eitr_set(eitr_num, val); 2635 2636 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR; 2637 core->mac[index] = val & 0x7FFE; 2638 } 2639 2640 static void 2641 igb_update_rx_offloads(IGBCore *core) 2642 { 2643 int cso_state = igb_rx_l4_cso_enabled(core); 2644 2645 trace_e1000e_rx_set_cso(cso_state); 2646 2647 if (core->has_vnet) { 2648 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2649 cso_state, 0, 0, 0, 0); 2650 } 2651 } 2652 2653 static void 2654 igb_set_rxcsum(IGBCore *core, int index, uint32_t val) 2655 { 2656 core->mac[RXCSUM] = val; 2657 igb_update_rx_offloads(core); 2658 } 2659 2660 static void 2661 igb_set_gcr(IGBCore *core, int index, uint32_t val) 2662 { 2663 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2664 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2665 } 2666 2667 static uint32_t igb_get_systiml(IGBCore *core, int index) 2668 { 2669 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2670 return core->mac[SYSTIML]; 2671 } 2672 2673 static uint32_t igb_get_rxsatrh(IGBCore *core, int index) 2674 { 2675 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2676 return core->mac[RXSATRH]; 2677 } 2678 2679 static uint32_t igb_get_txstmph(IGBCore *core, int index) 2680 { 2681 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2682 return core->mac[TXSTMPH]; 2683 } 2684 2685 static void igb_set_timinca(IGBCore *core, int index, uint32_t val) 2686 { 2687 e1000x_set_timinca(core->mac, &core->timadj, val); 2688 } 2689 2690 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val) 2691 { 2692 core->mac[TIMADJH] = val; 2693 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2694 } 2695 2696 #define igb_getreg(x) [x] = igb_mac_readreg 2697 typedef uint32_t (*readops)(IGBCore *, int); 2698 static const readops igb_macreg_readops[] = { 2699 igb_getreg(WUFC), 2700 igb_getreg(MANC), 2701 igb_getreg(TOTL), 2702 igb_getreg(RDT0), 2703 igb_getreg(RDT1), 2704 igb_getreg(RDT2), 2705 igb_getreg(RDT3), 2706 igb_getreg(RDT4), 2707 igb_getreg(RDT5), 2708 igb_getreg(RDT6), 2709 igb_getreg(RDT7), 2710 igb_getreg(RDT8), 2711 igb_getreg(RDT9), 2712 igb_getreg(RDT10), 2713 igb_getreg(RDT11), 2714 igb_getreg(RDT12), 2715 igb_getreg(RDT13), 2716 igb_getreg(RDT14), 2717 igb_getreg(RDT15), 2718 igb_getreg(RDBAH0), 2719 igb_getreg(RDBAH1), 2720 igb_getreg(RDBAH2), 2721 igb_getreg(RDBAH3), 2722 igb_getreg(RDBAH4), 2723 igb_getreg(RDBAH5), 2724 igb_getreg(RDBAH6), 2725 igb_getreg(RDBAH7), 2726 igb_getreg(RDBAH8), 2727 igb_getreg(RDBAH9), 2728 igb_getreg(RDBAH10), 2729 igb_getreg(RDBAH11), 2730 igb_getreg(RDBAH12), 2731 igb_getreg(RDBAH13), 2732 igb_getreg(RDBAH14), 2733 igb_getreg(RDBAH15), 2734 igb_getreg(TDBAL0), 2735 igb_getreg(TDBAL1), 2736 igb_getreg(TDBAL2), 2737 igb_getreg(TDBAL3), 2738 igb_getreg(TDBAL4), 2739 igb_getreg(TDBAL5), 2740 igb_getreg(TDBAL6), 2741 igb_getreg(TDBAL7), 2742 igb_getreg(TDBAL8), 2743 igb_getreg(TDBAL9), 2744 igb_getreg(TDBAL10), 2745 igb_getreg(TDBAL11), 2746 igb_getreg(TDBAL12), 2747 igb_getreg(TDBAL13), 2748 igb_getreg(TDBAL14), 2749 igb_getreg(TDBAL15), 2750 igb_getreg(RDLEN0), 2751 igb_getreg(RDLEN1), 2752 igb_getreg(RDLEN2), 2753 igb_getreg(RDLEN3), 2754 igb_getreg(RDLEN4), 2755 igb_getreg(RDLEN5), 2756 igb_getreg(RDLEN6), 2757 igb_getreg(RDLEN7), 2758 igb_getreg(RDLEN8), 2759 igb_getreg(RDLEN9), 2760 igb_getreg(RDLEN10), 2761 igb_getreg(RDLEN11), 2762 igb_getreg(RDLEN12), 2763 igb_getreg(RDLEN13), 2764 igb_getreg(RDLEN14), 2765 igb_getreg(RDLEN15), 2766 igb_getreg(SRRCTL0), 2767 igb_getreg(SRRCTL1), 2768 igb_getreg(SRRCTL2), 2769 igb_getreg(SRRCTL3), 2770 igb_getreg(SRRCTL4), 2771 igb_getreg(SRRCTL5), 2772 igb_getreg(SRRCTL6), 2773 igb_getreg(SRRCTL7), 2774 igb_getreg(SRRCTL8), 2775 igb_getreg(SRRCTL9), 2776 igb_getreg(SRRCTL10), 2777 igb_getreg(SRRCTL11), 2778 igb_getreg(SRRCTL12), 2779 igb_getreg(SRRCTL13), 2780 igb_getreg(SRRCTL14), 2781 igb_getreg(SRRCTL15), 2782 igb_getreg(LATECOL), 2783 igb_getreg(XONTXC), 2784 igb_getreg(TDFH), 2785 igb_getreg(TDFT), 2786 igb_getreg(TDFHS), 2787 igb_getreg(TDFTS), 2788 igb_getreg(TDFPC), 2789 igb_getreg(WUS), 2790 igb_getreg(RDFH), 2791 igb_getreg(RDFT), 2792 igb_getreg(RDFHS), 2793 igb_getreg(RDFTS), 2794 igb_getreg(RDFPC), 2795 igb_getreg(GORCL), 2796 igb_getreg(MGTPRC), 2797 igb_getreg(EERD), 2798 igb_getreg(EIAC), 2799 igb_getreg(MANC2H), 2800 igb_getreg(RXCSUM), 2801 igb_getreg(GSCL_3), 2802 igb_getreg(GSCN_2), 2803 igb_getreg(FCAH), 2804 igb_getreg(FCRTH), 2805 igb_getreg(FLOP), 2806 igb_getreg(RXSTMPH), 2807 igb_getreg(TXSTMPL), 2808 igb_getreg(TIMADJL), 2809 igb_getreg(RDH0), 2810 igb_getreg(RDH1), 2811 igb_getreg(RDH2), 2812 igb_getreg(RDH3), 2813 igb_getreg(RDH4), 2814 igb_getreg(RDH5), 2815 igb_getreg(RDH6), 2816 igb_getreg(RDH7), 2817 igb_getreg(RDH8), 2818 igb_getreg(RDH9), 2819 igb_getreg(RDH10), 2820 igb_getreg(RDH11), 2821 igb_getreg(RDH12), 2822 igb_getreg(RDH13), 2823 igb_getreg(RDH14), 2824 igb_getreg(RDH15), 2825 igb_getreg(TDT0), 2826 igb_getreg(TDT1), 2827 igb_getreg(TDT2), 2828 igb_getreg(TDT3), 2829 igb_getreg(TDT4), 2830 igb_getreg(TDT5), 2831 igb_getreg(TDT6), 2832 igb_getreg(TDT7), 2833 igb_getreg(TDT8), 2834 igb_getreg(TDT9), 2835 igb_getreg(TDT10), 2836 igb_getreg(TDT11), 2837 igb_getreg(TDT12), 2838 igb_getreg(TDT13), 2839 igb_getreg(TDT14), 2840 igb_getreg(TDT15), 2841 igb_getreg(TNCRS), 2842 igb_getreg(RJC), 2843 igb_getreg(IAM), 2844 igb_getreg(GSCL_2), 2845 igb_getreg(TIPG), 2846 igb_getreg(FLMNGCTL), 2847 igb_getreg(FLMNGCNT), 2848 igb_getreg(TSYNCTXCTL), 2849 igb_getreg(EEMNGDATA), 2850 igb_getreg(CTRL_EXT), 2851 igb_getreg(SYSTIMH), 2852 igb_getreg(EEMNGCTL), 2853 igb_getreg(FLMNGDATA), 2854 igb_getreg(TSYNCRXCTL), 2855 igb_getreg(LEDCTL), 2856 igb_getreg(TCTL), 2857 igb_getreg(TCTL_EXT), 2858 igb_getreg(DTXCTL), 2859 igb_getreg(RXPBS), 2860 igb_getreg(TDH0), 2861 igb_getreg(TDH1), 2862 igb_getreg(TDH2), 2863 igb_getreg(TDH3), 2864 igb_getreg(TDH4), 2865 igb_getreg(TDH5), 2866 igb_getreg(TDH6), 2867 igb_getreg(TDH7), 2868 igb_getreg(TDH8), 2869 igb_getreg(TDH9), 2870 igb_getreg(TDH10), 2871 igb_getreg(TDH11), 2872 igb_getreg(TDH12), 2873 igb_getreg(TDH13), 2874 igb_getreg(TDH14), 2875 igb_getreg(TDH15), 2876 igb_getreg(ECOL), 2877 igb_getreg(DC), 2878 igb_getreg(RLEC), 2879 igb_getreg(XOFFTXC), 2880 igb_getreg(RFC), 2881 igb_getreg(RNBC), 2882 igb_getreg(MGTPTC), 2883 igb_getreg(TIMINCA), 2884 igb_getreg(FACTPS), 2885 igb_getreg(GSCL_1), 2886 igb_getreg(GSCN_0), 2887 igb_getreg(PBACLR), 2888 igb_getreg(FCTTV), 2889 igb_getreg(RXSATRL), 2890 igb_getreg(TORL), 2891 igb_getreg(TDLEN0), 2892 igb_getreg(TDLEN1), 2893 igb_getreg(TDLEN2), 2894 igb_getreg(TDLEN3), 2895 igb_getreg(TDLEN4), 2896 igb_getreg(TDLEN5), 2897 igb_getreg(TDLEN6), 2898 igb_getreg(TDLEN7), 2899 igb_getreg(TDLEN8), 2900 igb_getreg(TDLEN9), 2901 igb_getreg(TDLEN10), 2902 igb_getreg(TDLEN11), 2903 igb_getreg(TDLEN12), 2904 igb_getreg(TDLEN13), 2905 igb_getreg(TDLEN14), 2906 igb_getreg(TDLEN15), 2907 igb_getreg(MCC), 2908 igb_getreg(WUC), 2909 igb_getreg(EECD), 2910 igb_getreg(FCRTV), 2911 igb_getreg(TXDCTL0), 2912 igb_getreg(TXDCTL1), 2913 igb_getreg(TXDCTL2), 2914 igb_getreg(TXDCTL3), 2915 igb_getreg(TXDCTL4), 2916 igb_getreg(TXDCTL5), 2917 igb_getreg(TXDCTL6), 2918 igb_getreg(TXDCTL7), 2919 igb_getreg(TXDCTL8), 2920 igb_getreg(TXDCTL9), 2921 igb_getreg(TXDCTL10), 2922 igb_getreg(TXDCTL11), 2923 igb_getreg(TXDCTL12), 2924 igb_getreg(TXDCTL13), 2925 igb_getreg(TXDCTL14), 2926 igb_getreg(TXDCTL15), 2927 igb_getreg(TXCTL0), 2928 igb_getreg(TXCTL1), 2929 igb_getreg(TXCTL2), 2930 igb_getreg(TXCTL3), 2931 igb_getreg(TXCTL4), 2932 igb_getreg(TXCTL5), 2933 igb_getreg(TXCTL6), 2934 igb_getreg(TXCTL7), 2935 igb_getreg(TXCTL8), 2936 igb_getreg(TXCTL9), 2937 igb_getreg(TXCTL10), 2938 igb_getreg(TXCTL11), 2939 igb_getreg(TXCTL12), 2940 igb_getreg(TXCTL13), 2941 igb_getreg(TXCTL14), 2942 igb_getreg(TXCTL15), 2943 igb_getreg(TDWBAL0), 2944 igb_getreg(TDWBAL1), 2945 igb_getreg(TDWBAL2), 2946 igb_getreg(TDWBAL3), 2947 igb_getreg(TDWBAL4), 2948 igb_getreg(TDWBAL5), 2949 igb_getreg(TDWBAL6), 2950 igb_getreg(TDWBAL7), 2951 igb_getreg(TDWBAL8), 2952 igb_getreg(TDWBAL9), 2953 igb_getreg(TDWBAL10), 2954 igb_getreg(TDWBAL11), 2955 igb_getreg(TDWBAL12), 2956 igb_getreg(TDWBAL13), 2957 igb_getreg(TDWBAL14), 2958 igb_getreg(TDWBAL15), 2959 igb_getreg(TDWBAH0), 2960 igb_getreg(TDWBAH1), 2961 igb_getreg(TDWBAH2), 2962 igb_getreg(TDWBAH3), 2963 igb_getreg(TDWBAH4), 2964 igb_getreg(TDWBAH5), 2965 igb_getreg(TDWBAH6), 2966 igb_getreg(TDWBAH7), 2967 igb_getreg(TDWBAH8), 2968 igb_getreg(TDWBAH9), 2969 igb_getreg(TDWBAH10), 2970 igb_getreg(TDWBAH11), 2971 igb_getreg(TDWBAH12), 2972 igb_getreg(TDWBAH13), 2973 igb_getreg(TDWBAH14), 2974 igb_getreg(TDWBAH15), 2975 igb_getreg(PVTCTRL0), 2976 igb_getreg(PVTCTRL1), 2977 igb_getreg(PVTCTRL2), 2978 igb_getreg(PVTCTRL3), 2979 igb_getreg(PVTCTRL4), 2980 igb_getreg(PVTCTRL5), 2981 igb_getreg(PVTCTRL6), 2982 igb_getreg(PVTCTRL7), 2983 igb_getreg(PVTEIMS0), 2984 igb_getreg(PVTEIMS1), 2985 igb_getreg(PVTEIMS2), 2986 igb_getreg(PVTEIMS3), 2987 igb_getreg(PVTEIMS4), 2988 igb_getreg(PVTEIMS5), 2989 igb_getreg(PVTEIMS6), 2990 igb_getreg(PVTEIMS7), 2991 igb_getreg(PVTEIAC0), 2992 igb_getreg(PVTEIAC1), 2993 igb_getreg(PVTEIAC2), 2994 igb_getreg(PVTEIAC3), 2995 igb_getreg(PVTEIAC4), 2996 igb_getreg(PVTEIAC5), 2997 igb_getreg(PVTEIAC6), 2998 igb_getreg(PVTEIAC7), 2999 igb_getreg(PVTEIAM0), 3000 igb_getreg(PVTEIAM1), 3001 igb_getreg(PVTEIAM2), 3002 igb_getreg(PVTEIAM3), 3003 igb_getreg(PVTEIAM4), 3004 igb_getreg(PVTEIAM5), 3005 igb_getreg(PVTEIAM6), 3006 igb_getreg(PVTEIAM7), 3007 igb_getreg(PVFGPRC0), 3008 igb_getreg(PVFGPRC1), 3009 igb_getreg(PVFGPRC2), 3010 igb_getreg(PVFGPRC3), 3011 igb_getreg(PVFGPRC4), 3012 igb_getreg(PVFGPRC5), 3013 igb_getreg(PVFGPRC6), 3014 igb_getreg(PVFGPRC7), 3015 igb_getreg(PVFGPTC0), 3016 igb_getreg(PVFGPTC1), 3017 igb_getreg(PVFGPTC2), 3018 igb_getreg(PVFGPTC3), 3019 igb_getreg(PVFGPTC4), 3020 igb_getreg(PVFGPTC5), 3021 igb_getreg(PVFGPTC6), 3022 igb_getreg(PVFGPTC7), 3023 igb_getreg(PVFGORC0), 3024 igb_getreg(PVFGORC1), 3025 igb_getreg(PVFGORC2), 3026 igb_getreg(PVFGORC3), 3027 igb_getreg(PVFGORC4), 3028 igb_getreg(PVFGORC5), 3029 igb_getreg(PVFGORC6), 3030 igb_getreg(PVFGORC7), 3031 igb_getreg(PVFGOTC0), 3032 igb_getreg(PVFGOTC1), 3033 igb_getreg(PVFGOTC2), 3034 igb_getreg(PVFGOTC3), 3035 igb_getreg(PVFGOTC4), 3036 igb_getreg(PVFGOTC5), 3037 igb_getreg(PVFGOTC6), 3038 igb_getreg(PVFGOTC7), 3039 igb_getreg(PVFMPRC0), 3040 igb_getreg(PVFMPRC1), 3041 igb_getreg(PVFMPRC2), 3042 igb_getreg(PVFMPRC3), 3043 igb_getreg(PVFMPRC4), 3044 igb_getreg(PVFMPRC5), 3045 igb_getreg(PVFMPRC6), 3046 igb_getreg(PVFMPRC7), 3047 igb_getreg(PVFGPRLBC0), 3048 igb_getreg(PVFGPRLBC1), 3049 igb_getreg(PVFGPRLBC2), 3050 igb_getreg(PVFGPRLBC3), 3051 igb_getreg(PVFGPRLBC4), 3052 igb_getreg(PVFGPRLBC5), 3053 igb_getreg(PVFGPRLBC6), 3054 igb_getreg(PVFGPRLBC7), 3055 igb_getreg(PVFGPTLBC0), 3056 igb_getreg(PVFGPTLBC1), 3057 igb_getreg(PVFGPTLBC2), 3058 igb_getreg(PVFGPTLBC3), 3059 igb_getreg(PVFGPTLBC4), 3060 igb_getreg(PVFGPTLBC5), 3061 igb_getreg(PVFGPTLBC6), 3062 igb_getreg(PVFGPTLBC7), 3063 igb_getreg(PVFGORLBC0), 3064 igb_getreg(PVFGORLBC1), 3065 igb_getreg(PVFGORLBC2), 3066 igb_getreg(PVFGORLBC3), 3067 igb_getreg(PVFGORLBC4), 3068 igb_getreg(PVFGORLBC5), 3069 igb_getreg(PVFGORLBC6), 3070 igb_getreg(PVFGORLBC7), 3071 igb_getreg(PVFGOTLBC0), 3072 igb_getreg(PVFGOTLBC1), 3073 igb_getreg(PVFGOTLBC2), 3074 igb_getreg(PVFGOTLBC3), 3075 igb_getreg(PVFGOTLBC4), 3076 igb_getreg(PVFGOTLBC5), 3077 igb_getreg(PVFGOTLBC6), 3078 igb_getreg(PVFGOTLBC7), 3079 igb_getreg(RCTL), 3080 igb_getreg(MDIC), 3081 igb_getreg(FCRUC), 3082 igb_getreg(VET), 3083 igb_getreg(RDBAL0), 3084 igb_getreg(RDBAL1), 3085 igb_getreg(RDBAL2), 3086 igb_getreg(RDBAL3), 3087 igb_getreg(RDBAL4), 3088 igb_getreg(RDBAL5), 3089 igb_getreg(RDBAL6), 3090 igb_getreg(RDBAL7), 3091 igb_getreg(RDBAL8), 3092 igb_getreg(RDBAL9), 3093 igb_getreg(RDBAL10), 3094 igb_getreg(RDBAL11), 3095 igb_getreg(RDBAL12), 3096 igb_getreg(RDBAL13), 3097 igb_getreg(RDBAL14), 3098 igb_getreg(RDBAL15), 3099 igb_getreg(TDBAH0), 3100 igb_getreg(TDBAH1), 3101 igb_getreg(TDBAH2), 3102 igb_getreg(TDBAH3), 3103 igb_getreg(TDBAH4), 3104 igb_getreg(TDBAH5), 3105 igb_getreg(TDBAH6), 3106 igb_getreg(TDBAH7), 3107 igb_getreg(TDBAH8), 3108 igb_getreg(TDBAH9), 3109 igb_getreg(TDBAH10), 3110 igb_getreg(TDBAH11), 3111 igb_getreg(TDBAH12), 3112 igb_getreg(TDBAH13), 3113 igb_getreg(TDBAH14), 3114 igb_getreg(TDBAH15), 3115 igb_getreg(SCC), 3116 igb_getreg(COLC), 3117 igb_getreg(XOFFRXC), 3118 igb_getreg(IPAV), 3119 igb_getreg(GOTCL), 3120 igb_getreg(MGTPDC), 3121 igb_getreg(GCR), 3122 igb_getreg(MFVAL), 3123 igb_getreg(FUNCTAG), 3124 igb_getreg(GSCL_4), 3125 igb_getreg(GSCN_3), 3126 igb_getreg(MRQC), 3127 igb_getreg(FCT), 3128 igb_getreg(FLA), 3129 igb_getreg(RXDCTL0), 3130 igb_getreg(RXDCTL1), 3131 igb_getreg(RXDCTL2), 3132 igb_getreg(RXDCTL3), 3133 igb_getreg(RXDCTL4), 3134 igb_getreg(RXDCTL5), 3135 igb_getreg(RXDCTL6), 3136 igb_getreg(RXDCTL7), 3137 igb_getreg(RXDCTL8), 3138 igb_getreg(RXDCTL9), 3139 igb_getreg(RXDCTL10), 3140 igb_getreg(RXDCTL11), 3141 igb_getreg(RXDCTL12), 3142 igb_getreg(RXDCTL13), 3143 igb_getreg(RXDCTL14), 3144 igb_getreg(RXDCTL15), 3145 igb_getreg(RXSTMPL), 3146 igb_getreg(TIMADJH), 3147 igb_getreg(FCRTL), 3148 igb_getreg(XONRXC), 3149 igb_getreg(RFCTL), 3150 igb_getreg(GSCN_1), 3151 igb_getreg(FCAL), 3152 igb_getreg(GPIE), 3153 igb_getreg(TXPBS), 3154 igb_getreg(RLPML), 3155 3156 [TOTH] = igb_mac_read_clr8, 3157 [GOTCH] = igb_mac_read_clr8, 3158 [PRC64] = igb_mac_read_clr4, 3159 [PRC255] = igb_mac_read_clr4, 3160 [PRC1023] = igb_mac_read_clr4, 3161 [PTC64] = igb_mac_read_clr4, 3162 [PTC255] = igb_mac_read_clr4, 3163 [PTC1023] = igb_mac_read_clr4, 3164 [GPRC] = igb_mac_read_clr4, 3165 [TPT] = igb_mac_read_clr4, 3166 [RUC] = igb_mac_read_clr4, 3167 [BPRC] = igb_mac_read_clr4, 3168 [MPTC] = igb_mac_read_clr4, 3169 [IAC] = igb_mac_read_clr4, 3170 [ICR] = igb_mac_icr_read, 3171 [STATUS] = igb_get_status, 3172 [ICS] = igb_mac_ics_read, 3173 /* 3174 * 8.8.10: Reading the IMC register returns the value of the IMS register. 3175 */ 3176 [IMC] = igb_mac_ims_read, 3177 [TORH] = igb_mac_read_clr8, 3178 [GORCH] = igb_mac_read_clr8, 3179 [PRC127] = igb_mac_read_clr4, 3180 [PRC511] = igb_mac_read_clr4, 3181 [PRC1522] = igb_mac_read_clr4, 3182 [PTC127] = igb_mac_read_clr4, 3183 [PTC511] = igb_mac_read_clr4, 3184 [PTC1522] = igb_mac_read_clr4, 3185 [GPTC] = igb_mac_read_clr4, 3186 [TPR] = igb_mac_read_clr4, 3187 [ROC] = igb_mac_read_clr4, 3188 [MPRC] = igb_mac_read_clr4, 3189 [BPTC] = igb_mac_read_clr4, 3190 [TSCTC] = igb_mac_read_clr4, 3191 [CTRL] = igb_get_ctrl, 3192 [SWSM] = igb_mac_swsm_read, 3193 [IMS] = igb_mac_ims_read, 3194 [SYSTIML] = igb_get_systiml, 3195 [RXSATRH] = igb_get_rxsatrh, 3196 [TXSTMPH] = igb_get_txstmph, 3197 3198 [CRCERRS ... MPC] = igb_mac_readreg, 3199 [IP6AT ... IP6AT + 3] = igb_mac_readreg, 3200 [IP4AT ... IP4AT + 6] = igb_mac_readreg, 3201 [RA ... RA + 31] = igb_mac_readreg, 3202 [RA2 ... RA2 + 31] = igb_mac_readreg, 3203 [WUPM ... WUPM + 31] = igb_mac_readreg, 3204 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg, 3205 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg, 3206 [FFMT ... FFMT + 254] = igb_mac_readreg, 3207 [MDEF ... MDEF + 7] = igb_mac_readreg, 3208 [FTFT ... FTFT + 254] = igb_mac_readreg, 3209 [RETA ... RETA + 31] = igb_mac_readreg, 3210 [RSSRK ... RSSRK + 9] = igb_mac_readreg, 3211 [MAVTV0 ... MAVTV3] = igb_mac_readreg, 3212 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read, 3213 [PVTEICR0] = igb_mac_read_clr4, 3214 [PVTEICR1] = igb_mac_read_clr4, 3215 [PVTEICR2] = igb_mac_read_clr4, 3216 [PVTEICR3] = igb_mac_read_clr4, 3217 [PVTEICR4] = igb_mac_read_clr4, 3218 [PVTEICR5] = igb_mac_read_clr4, 3219 [PVTEICR6] = igb_mac_read_clr4, 3220 [PVTEICR7] = igb_mac_read_clr4, 3221 3222 /* IGB specific: */ 3223 [FWSM] = igb_mac_readreg, 3224 [SW_FW_SYNC] = igb_mac_readreg, 3225 [HTCBDPC] = igb_mac_read_clr4, 3226 [EICR] = igb_mac_read_clr4, 3227 [EIMS] = igb_mac_readreg, 3228 [EIAM] = igb_mac_readreg, 3229 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg, 3230 igb_getreg(IVAR_MISC), 3231 igb_getreg(VT_CTL), 3232 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg, 3233 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read, 3234 igb_getreg(MBVFICR), 3235 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg, 3236 igb_getreg(MBVFIMR), 3237 igb_getreg(VFLRE), 3238 igb_getreg(VFRE), 3239 igb_getreg(VFTE), 3240 igb_getreg(QDE), 3241 igb_getreg(DTXSWC), 3242 igb_getreg(RPLOLR), 3243 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg, 3244 [VMVIR0 ... VMVIR7] = igb_mac_readreg, 3245 [VMOLR0 ... VMOLR7] = igb_mac_readreg, 3246 [WVBR] = igb_mac_read_clr4, 3247 [RQDPC0] = igb_mac_read_clr4, 3248 [RQDPC1] = igb_mac_read_clr4, 3249 [RQDPC2] = igb_mac_read_clr4, 3250 [RQDPC3] = igb_mac_read_clr4, 3251 [RQDPC4] = igb_mac_read_clr4, 3252 [RQDPC5] = igb_mac_read_clr4, 3253 [RQDPC6] = igb_mac_read_clr4, 3254 [RQDPC7] = igb_mac_read_clr4, 3255 [RQDPC8] = igb_mac_read_clr4, 3256 [RQDPC9] = igb_mac_read_clr4, 3257 [RQDPC10] = igb_mac_read_clr4, 3258 [RQDPC11] = igb_mac_read_clr4, 3259 [RQDPC12] = igb_mac_read_clr4, 3260 [RQDPC13] = igb_mac_read_clr4, 3261 [RQDPC14] = igb_mac_read_clr4, 3262 [RQDPC15] = igb_mac_read_clr4, 3263 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg, 3264 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg, 3265 }; 3266 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) }; 3267 3268 #define igb_putreg(x) [x] = igb_mac_writereg 3269 typedef void (*writeops)(IGBCore *, int, uint32_t); 3270 static const writeops igb_macreg_writeops[] = { 3271 igb_putreg(SWSM), 3272 igb_putreg(WUFC), 3273 igb_putreg(RDBAH0), 3274 igb_putreg(RDBAH1), 3275 igb_putreg(RDBAH2), 3276 igb_putreg(RDBAH3), 3277 igb_putreg(RDBAH4), 3278 igb_putreg(RDBAH5), 3279 igb_putreg(RDBAH6), 3280 igb_putreg(RDBAH7), 3281 igb_putreg(RDBAH8), 3282 igb_putreg(RDBAH9), 3283 igb_putreg(RDBAH10), 3284 igb_putreg(RDBAH11), 3285 igb_putreg(RDBAH12), 3286 igb_putreg(RDBAH13), 3287 igb_putreg(RDBAH14), 3288 igb_putreg(RDBAH15), 3289 igb_putreg(SRRCTL0), 3290 igb_putreg(SRRCTL1), 3291 igb_putreg(SRRCTL2), 3292 igb_putreg(SRRCTL3), 3293 igb_putreg(SRRCTL4), 3294 igb_putreg(SRRCTL5), 3295 igb_putreg(SRRCTL6), 3296 igb_putreg(SRRCTL7), 3297 igb_putreg(SRRCTL8), 3298 igb_putreg(SRRCTL9), 3299 igb_putreg(SRRCTL10), 3300 igb_putreg(SRRCTL11), 3301 igb_putreg(SRRCTL12), 3302 igb_putreg(SRRCTL13), 3303 igb_putreg(SRRCTL14), 3304 igb_putreg(SRRCTL15), 3305 igb_putreg(RXDCTL0), 3306 igb_putreg(RXDCTL1), 3307 igb_putreg(RXDCTL2), 3308 igb_putreg(RXDCTL3), 3309 igb_putreg(RXDCTL4), 3310 igb_putreg(RXDCTL5), 3311 igb_putreg(RXDCTL6), 3312 igb_putreg(RXDCTL7), 3313 igb_putreg(RXDCTL8), 3314 igb_putreg(RXDCTL9), 3315 igb_putreg(RXDCTL10), 3316 igb_putreg(RXDCTL11), 3317 igb_putreg(RXDCTL12), 3318 igb_putreg(RXDCTL13), 3319 igb_putreg(RXDCTL14), 3320 igb_putreg(RXDCTL15), 3321 igb_putreg(LEDCTL), 3322 igb_putreg(TCTL), 3323 igb_putreg(TCTL_EXT), 3324 igb_putreg(DTXCTL), 3325 igb_putreg(RXPBS), 3326 igb_putreg(RQDPC0), 3327 igb_putreg(FCAL), 3328 igb_putreg(FCRUC), 3329 igb_putreg(WUC), 3330 igb_putreg(WUS), 3331 igb_putreg(IPAV), 3332 igb_putreg(TDBAH0), 3333 igb_putreg(TDBAH1), 3334 igb_putreg(TDBAH2), 3335 igb_putreg(TDBAH3), 3336 igb_putreg(TDBAH4), 3337 igb_putreg(TDBAH5), 3338 igb_putreg(TDBAH6), 3339 igb_putreg(TDBAH7), 3340 igb_putreg(TDBAH8), 3341 igb_putreg(TDBAH9), 3342 igb_putreg(TDBAH10), 3343 igb_putreg(TDBAH11), 3344 igb_putreg(TDBAH12), 3345 igb_putreg(TDBAH13), 3346 igb_putreg(TDBAH14), 3347 igb_putreg(TDBAH15), 3348 igb_putreg(IAM), 3349 igb_putreg(MANC), 3350 igb_putreg(MANC2H), 3351 igb_putreg(MFVAL), 3352 igb_putreg(FACTPS), 3353 igb_putreg(FUNCTAG), 3354 igb_putreg(GSCL_1), 3355 igb_putreg(GSCL_2), 3356 igb_putreg(GSCL_3), 3357 igb_putreg(GSCL_4), 3358 igb_putreg(GSCN_0), 3359 igb_putreg(GSCN_1), 3360 igb_putreg(GSCN_2), 3361 igb_putreg(GSCN_3), 3362 igb_putreg(MRQC), 3363 igb_putreg(FLOP), 3364 igb_putreg(FLA), 3365 igb_putreg(TXDCTL0), 3366 igb_putreg(TXDCTL1), 3367 igb_putreg(TXDCTL2), 3368 igb_putreg(TXDCTL3), 3369 igb_putreg(TXDCTL4), 3370 igb_putreg(TXDCTL5), 3371 igb_putreg(TXDCTL6), 3372 igb_putreg(TXDCTL7), 3373 igb_putreg(TXDCTL8), 3374 igb_putreg(TXDCTL9), 3375 igb_putreg(TXDCTL10), 3376 igb_putreg(TXDCTL11), 3377 igb_putreg(TXDCTL12), 3378 igb_putreg(TXDCTL13), 3379 igb_putreg(TXDCTL14), 3380 igb_putreg(TXDCTL15), 3381 igb_putreg(TXCTL0), 3382 igb_putreg(TXCTL1), 3383 igb_putreg(TXCTL2), 3384 igb_putreg(TXCTL3), 3385 igb_putreg(TXCTL4), 3386 igb_putreg(TXCTL5), 3387 igb_putreg(TXCTL6), 3388 igb_putreg(TXCTL7), 3389 igb_putreg(TXCTL8), 3390 igb_putreg(TXCTL9), 3391 igb_putreg(TXCTL10), 3392 igb_putreg(TXCTL11), 3393 igb_putreg(TXCTL12), 3394 igb_putreg(TXCTL13), 3395 igb_putreg(TXCTL14), 3396 igb_putreg(TXCTL15), 3397 igb_putreg(TDWBAL0), 3398 igb_putreg(TDWBAL1), 3399 igb_putreg(TDWBAL2), 3400 igb_putreg(TDWBAL3), 3401 igb_putreg(TDWBAL4), 3402 igb_putreg(TDWBAL5), 3403 igb_putreg(TDWBAL6), 3404 igb_putreg(TDWBAL7), 3405 igb_putreg(TDWBAL8), 3406 igb_putreg(TDWBAL9), 3407 igb_putreg(TDWBAL10), 3408 igb_putreg(TDWBAL11), 3409 igb_putreg(TDWBAL12), 3410 igb_putreg(TDWBAL13), 3411 igb_putreg(TDWBAL14), 3412 igb_putreg(TDWBAL15), 3413 igb_putreg(TDWBAH0), 3414 igb_putreg(TDWBAH1), 3415 igb_putreg(TDWBAH2), 3416 igb_putreg(TDWBAH3), 3417 igb_putreg(TDWBAH4), 3418 igb_putreg(TDWBAH5), 3419 igb_putreg(TDWBAH6), 3420 igb_putreg(TDWBAH7), 3421 igb_putreg(TDWBAH8), 3422 igb_putreg(TDWBAH9), 3423 igb_putreg(TDWBAH10), 3424 igb_putreg(TDWBAH11), 3425 igb_putreg(TDWBAH12), 3426 igb_putreg(TDWBAH13), 3427 igb_putreg(TDWBAH14), 3428 igb_putreg(TDWBAH15), 3429 igb_putreg(TIPG), 3430 igb_putreg(RXSTMPH), 3431 igb_putreg(RXSTMPL), 3432 igb_putreg(RXSATRL), 3433 igb_putreg(RXSATRH), 3434 igb_putreg(TXSTMPL), 3435 igb_putreg(TXSTMPH), 3436 igb_putreg(SYSTIML), 3437 igb_putreg(SYSTIMH), 3438 igb_putreg(TIMADJL), 3439 igb_putreg(TSYNCRXCTL), 3440 igb_putreg(TSYNCTXCTL), 3441 igb_putreg(EEMNGCTL), 3442 igb_putreg(GPIE), 3443 igb_putreg(TXPBS), 3444 igb_putreg(RLPML), 3445 igb_putreg(VET), 3446 3447 [TDH0] = igb_set_16bit, 3448 [TDH1] = igb_set_16bit, 3449 [TDH2] = igb_set_16bit, 3450 [TDH3] = igb_set_16bit, 3451 [TDH4] = igb_set_16bit, 3452 [TDH5] = igb_set_16bit, 3453 [TDH6] = igb_set_16bit, 3454 [TDH7] = igb_set_16bit, 3455 [TDH8] = igb_set_16bit, 3456 [TDH9] = igb_set_16bit, 3457 [TDH10] = igb_set_16bit, 3458 [TDH11] = igb_set_16bit, 3459 [TDH12] = igb_set_16bit, 3460 [TDH13] = igb_set_16bit, 3461 [TDH14] = igb_set_16bit, 3462 [TDH15] = igb_set_16bit, 3463 [TDT0] = igb_set_tdt, 3464 [TDT1] = igb_set_tdt, 3465 [TDT2] = igb_set_tdt, 3466 [TDT3] = igb_set_tdt, 3467 [TDT4] = igb_set_tdt, 3468 [TDT5] = igb_set_tdt, 3469 [TDT6] = igb_set_tdt, 3470 [TDT7] = igb_set_tdt, 3471 [TDT8] = igb_set_tdt, 3472 [TDT9] = igb_set_tdt, 3473 [TDT10] = igb_set_tdt, 3474 [TDT11] = igb_set_tdt, 3475 [TDT12] = igb_set_tdt, 3476 [TDT13] = igb_set_tdt, 3477 [TDT14] = igb_set_tdt, 3478 [TDT15] = igb_set_tdt, 3479 [MDIC] = igb_set_mdic, 3480 [ICS] = igb_set_ics, 3481 [RDH0] = igb_set_16bit, 3482 [RDH1] = igb_set_16bit, 3483 [RDH2] = igb_set_16bit, 3484 [RDH3] = igb_set_16bit, 3485 [RDH4] = igb_set_16bit, 3486 [RDH5] = igb_set_16bit, 3487 [RDH6] = igb_set_16bit, 3488 [RDH7] = igb_set_16bit, 3489 [RDH8] = igb_set_16bit, 3490 [RDH9] = igb_set_16bit, 3491 [RDH10] = igb_set_16bit, 3492 [RDH11] = igb_set_16bit, 3493 [RDH12] = igb_set_16bit, 3494 [RDH13] = igb_set_16bit, 3495 [RDH14] = igb_set_16bit, 3496 [RDH15] = igb_set_16bit, 3497 [RDT0] = igb_set_rdt, 3498 [RDT1] = igb_set_rdt, 3499 [RDT2] = igb_set_rdt, 3500 [RDT3] = igb_set_rdt, 3501 [RDT4] = igb_set_rdt, 3502 [RDT5] = igb_set_rdt, 3503 [RDT6] = igb_set_rdt, 3504 [RDT7] = igb_set_rdt, 3505 [RDT8] = igb_set_rdt, 3506 [RDT9] = igb_set_rdt, 3507 [RDT10] = igb_set_rdt, 3508 [RDT11] = igb_set_rdt, 3509 [RDT12] = igb_set_rdt, 3510 [RDT13] = igb_set_rdt, 3511 [RDT14] = igb_set_rdt, 3512 [RDT15] = igb_set_rdt, 3513 [IMC] = igb_set_imc, 3514 [IMS] = igb_set_ims, 3515 [ICR] = igb_set_icr, 3516 [EECD] = igb_set_eecd, 3517 [RCTL] = igb_set_rx_control, 3518 [CTRL] = igb_set_ctrl, 3519 [EERD] = igb_set_eerd, 3520 [TDFH] = igb_set_13bit, 3521 [TDFT] = igb_set_13bit, 3522 [TDFHS] = igb_set_13bit, 3523 [TDFTS] = igb_set_13bit, 3524 [TDFPC] = igb_set_13bit, 3525 [RDFH] = igb_set_13bit, 3526 [RDFT] = igb_set_13bit, 3527 [RDFHS] = igb_set_13bit, 3528 [RDFTS] = igb_set_13bit, 3529 [RDFPC] = igb_set_13bit, 3530 [GCR] = igb_set_gcr, 3531 [RXCSUM] = igb_set_rxcsum, 3532 [TDLEN0] = igb_set_dlen, 3533 [TDLEN1] = igb_set_dlen, 3534 [TDLEN2] = igb_set_dlen, 3535 [TDLEN3] = igb_set_dlen, 3536 [TDLEN4] = igb_set_dlen, 3537 [TDLEN5] = igb_set_dlen, 3538 [TDLEN6] = igb_set_dlen, 3539 [TDLEN7] = igb_set_dlen, 3540 [TDLEN8] = igb_set_dlen, 3541 [TDLEN9] = igb_set_dlen, 3542 [TDLEN10] = igb_set_dlen, 3543 [TDLEN11] = igb_set_dlen, 3544 [TDLEN12] = igb_set_dlen, 3545 [TDLEN13] = igb_set_dlen, 3546 [TDLEN14] = igb_set_dlen, 3547 [TDLEN15] = igb_set_dlen, 3548 [RDLEN0] = igb_set_dlen, 3549 [RDLEN1] = igb_set_dlen, 3550 [RDLEN2] = igb_set_dlen, 3551 [RDLEN3] = igb_set_dlen, 3552 [RDLEN4] = igb_set_dlen, 3553 [RDLEN5] = igb_set_dlen, 3554 [RDLEN6] = igb_set_dlen, 3555 [RDLEN7] = igb_set_dlen, 3556 [RDLEN8] = igb_set_dlen, 3557 [RDLEN9] = igb_set_dlen, 3558 [RDLEN10] = igb_set_dlen, 3559 [RDLEN11] = igb_set_dlen, 3560 [RDLEN12] = igb_set_dlen, 3561 [RDLEN13] = igb_set_dlen, 3562 [RDLEN14] = igb_set_dlen, 3563 [RDLEN15] = igb_set_dlen, 3564 [TDBAL0] = igb_set_dbal, 3565 [TDBAL1] = igb_set_dbal, 3566 [TDBAL2] = igb_set_dbal, 3567 [TDBAL3] = igb_set_dbal, 3568 [TDBAL4] = igb_set_dbal, 3569 [TDBAL5] = igb_set_dbal, 3570 [TDBAL6] = igb_set_dbal, 3571 [TDBAL7] = igb_set_dbal, 3572 [TDBAL8] = igb_set_dbal, 3573 [TDBAL9] = igb_set_dbal, 3574 [TDBAL10] = igb_set_dbal, 3575 [TDBAL11] = igb_set_dbal, 3576 [TDBAL12] = igb_set_dbal, 3577 [TDBAL13] = igb_set_dbal, 3578 [TDBAL14] = igb_set_dbal, 3579 [TDBAL15] = igb_set_dbal, 3580 [RDBAL0] = igb_set_dbal, 3581 [RDBAL1] = igb_set_dbal, 3582 [RDBAL2] = igb_set_dbal, 3583 [RDBAL3] = igb_set_dbal, 3584 [RDBAL4] = igb_set_dbal, 3585 [RDBAL5] = igb_set_dbal, 3586 [RDBAL6] = igb_set_dbal, 3587 [RDBAL7] = igb_set_dbal, 3588 [RDBAL8] = igb_set_dbal, 3589 [RDBAL9] = igb_set_dbal, 3590 [RDBAL10] = igb_set_dbal, 3591 [RDBAL11] = igb_set_dbal, 3592 [RDBAL12] = igb_set_dbal, 3593 [RDBAL13] = igb_set_dbal, 3594 [RDBAL14] = igb_set_dbal, 3595 [RDBAL15] = igb_set_dbal, 3596 [STATUS] = igb_set_status, 3597 [PBACLR] = igb_set_pbaclr, 3598 [CTRL_EXT] = igb_set_ctrlext, 3599 [FCAH] = igb_set_16bit, 3600 [FCT] = igb_set_16bit, 3601 [FCTTV] = igb_set_16bit, 3602 [FCRTV] = igb_set_16bit, 3603 [FCRTH] = igb_set_fcrth, 3604 [FCRTL] = igb_set_fcrtl, 3605 [CTRL_DUP] = igb_set_ctrl, 3606 [RFCTL] = igb_set_rfctl, 3607 [TIMINCA] = igb_set_timinca, 3608 [TIMADJH] = igb_set_timadjh, 3609 3610 [IP6AT ... IP6AT + 3] = igb_mac_writereg, 3611 [IP4AT ... IP4AT + 6] = igb_mac_writereg, 3612 [RA] = igb_mac_writereg, 3613 [RA + 1] = igb_mac_setmacaddr, 3614 [RA + 2 ... RA + 31] = igb_mac_writereg, 3615 [RA2 ... RA2 + 31] = igb_mac_writereg, 3616 [WUPM ... WUPM + 31] = igb_mac_writereg, 3617 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3618 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg, 3619 [FFMT ... FFMT + 254] = igb_set_4bit, 3620 [MDEF ... MDEF + 7] = igb_mac_writereg, 3621 [FTFT ... FTFT + 254] = igb_mac_writereg, 3622 [RETA ... RETA + 31] = igb_mac_writereg, 3623 [RSSRK ... RSSRK + 9] = igb_mac_writereg, 3624 [MAVTV0 ... MAVTV3] = igb_mac_writereg, 3625 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr, 3626 3627 /* IGB specific: */ 3628 [FWSM] = igb_mac_writereg, 3629 [SW_FW_SYNC] = igb_mac_writereg, 3630 [EICR] = igb_set_eicr, 3631 [EICS] = igb_set_eics, 3632 [EIAC] = igb_set_eiac, 3633 [EIAM] = igb_set_eiam, 3634 [EIMC] = igb_set_eimc, 3635 [EIMS] = igb_set_eims, 3636 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg, 3637 igb_putreg(IVAR_MISC), 3638 igb_putreg(VT_CTL), 3639 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox, 3640 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox, 3641 [MBVFICR] = igb_w1c, 3642 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg, 3643 igb_putreg(MBVFIMR), 3644 [VFLRE] = igb_w1c, 3645 igb_putreg(VFRE), 3646 igb_putreg(VFTE), 3647 igb_putreg(QDE), 3648 igb_putreg(DTXSWC), 3649 igb_putreg(RPLOLR), 3650 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg, 3651 [VMVIR0 ... VMVIR7] = igb_mac_writereg, 3652 [VMOLR0 ... VMOLR7] = igb_mac_writereg, 3653 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3654 [PVTCTRL0] = igb_set_vtctrl, 3655 [PVTCTRL1] = igb_set_vtctrl, 3656 [PVTCTRL2] = igb_set_vtctrl, 3657 [PVTCTRL3] = igb_set_vtctrl, 3658 [PVTCTRL4] = igb_set_vtctrl, 3659 [PVTCTRL5] = igb_set_vtctrl, 3660 [PVTCTRL6] = igb_set_vtctrl, 3661 [PVTCTRL7] = igb_set_vtctrl, 3662 [PVTEICS0] = igb_set_vteics, 3663 [PVTEICS1] = igb_set_vteics, 3664 [PVTEICS2] = igb_set_vteics, 3665 [PVTEICS3] = igb_set_vteics, 3666 [PVTEICS4] = igb_set_vteics, 3667 [PVTEICS5] = igb_set_vteics, 3668 [PVTEICS6] = igb_set_vteics, 3669 [PVTEICS7] = igb_set_vteics, 3670 [PVTEIMS0] = igb_set_vteims, 3671 [PVTEIMS1] = igb_set_vteims, 3672 [PVTEIMS2] = igb_set_vteims, 3673 [PVTEIMS3] = igb_set_vteims, 3674 [PVTEIMS4] = igb_set_vteims, 3675 [PVTEIMS5] = igb_set_vteims, 3676 [PVTEIMS6] = igb_set_vteims, 3677 [PVTEIMS7] = igb_set_vteims, 3678 [PVTEIMC0] = igb_set_vteimc, 3679 [PVTEIMC1] = igb_set_vteimc, 3680 [PVTEIMC2] = igb_set_vteimc, 3681 [PVTEIMC3] = igb_set_vteimc, 3682 [PVTEIMC4] = igb_set_vteimc, 3683 [PVTEIMC5] = igb_set_vteimc, 3684 [PVTEIMC6] = igb_set_vteimc, 3685 [PVTEIMC7] = igb_set_vteimc, 3686 [PVTEIAC0] = igb_set_vteiac, 3687 [PVTEIAC1] = igb_set_vteiac, 3688 [PVTEIAC2] = igb_set_vteiac, 3689 [PVTEIAC3] = igb_set_vteiac, 3690 [PVTEIAC4] = igb_set_vteiac, 3691 [PVTEIAC5] = igb_set_vteiac, 3692 [PVTEIAC6] = igb_set_vteiac, 3693 [PVTEIAC7] = igb_set_vteiac, 3694 [PVTEIAM0] = igb_set_vteiam, 3695 [PVTEIAM1] = igb_set_vteiam, 3696 [PVTEIAM2] = igb_set_vteiam, 3697 [PVTEIAM3] = igb_set_vteiam, 3698 [PVTEIAM4] = igb_set_vteiam, 3699 [PVTEIAM5] = igb_set_vteiam, 3700 [PVTEIAM6] = igb_set_vteiam, 3701 [PVTEIAM7] = igb_set_vteiam, 3702 [PVTEICR0] = igb_set_vteicr, 3703 [PVTEICR1] = igb_set_vteicr, 3704 [PVTEICR2] = igb_set_vteicr, 3705 [PVTEICR3] = igb_set_vteicr, 3706 [PVTEICR4] = igb_set_vteicr, 3707 [PVTEICR5] = igb_set_vteicr, 3708 [PVTEICR6] = igb_set_vteicr, 3709 [PVTEICR7] = igb_set_vteicr, 3710 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar, 3711 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg 3712 }; 3713 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) }; 3714 3715 enum { MAC_ACCESS_PARTIAL = 1 }; 3716 3717 /* 3718 * The array below combines alias offsets of the index values for the 3719 * MAC registers that have aliases, with the indication of not fully 3720 * implemented registers (lowest bit). This combination is possible 3721 * because all of the offsets are even. 3722 */ 3723 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3724 /* Alias index offsets */ 3725 [FCRTL_A] = 0x07fe, 3726 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3727 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3728 [RA_A ... RA_A + 31] = 0x14f0, 3729 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3730 3731 [RDBAL0_A] = 0x2600, 3732 [RDBAH0_A] = 0x2600, 3733 [RDLEN0_A] = 0x2600, 3734 [SRRCTL0_A] = 0x2600, 3735 [RDH0_A] = 0x2600, 3736 [RDT0_A] = 0x2600, 3737 [RXDCTL0_A] = 0x2600, 3738 [RXCTL0_A] = 0x2600, 3739 [RQDPC0_A] = 0x2600, 3740 [RDBAL1_A] = 0x25D0, 3741 [RDBAL2_A] = 0x25A0, 3742 [RDBAL3_A] = 0x2570, 3743 [RDBAH1_A] = 0x25D0, 3744 [RDBAH2_A] = 0x25A0, 3745 [RDBAH3_A] = 0x2570, 3746 [RDLEN1_A] = 0x25D0, 3747 [RDLEN2_A] = 0x25A0, 3748 [RDLEN3_A] = 0x2570, 3749 [SRRCTL1_A] = 0x25D0, 3750 [SRRCTL2_A] = 0x25A0, 3751 [SRRCTL3_A] = 0x2570, 3752 [RDH1_A] = 0x25D0, 3753 [RDH2_A] = 0x25A0, 3754 [RDH3_A] = 0x2570, 3755 [RDT1_A] = 0x25D0, 3756 [RDT2_A] = 0x25A0, 3757 [RDT3_A] = 0x2570, 3758 [RXDCTL1_A] = 0x25D0, 3759 [RXDCTL2_A] = 0x25A0, 3760 [RXDCTL3_A] = 0x2570, 3761 [RXCTL1_A] = 0x25D0, 3762 [RXCTL2_A] = 0x25A0, 3763 [RXCTL3_A] = 0x2570, 3764 [RQDPC1_A] = 0x25D0, 3765 [RQDPC2_A] = 0x25A0, 3766 [RQDPC3_A] = 0x2570, 3767 [TDBAL0_A] = 0x2A00, 3768 [TDBAH0_A] = 0x2A00, 3769 [TDLEN0_A] = 0x2A00, 3770 [TDH0_A] = 0x2A00, 3771 [TDT0_A] = 0x2A00, 3772 [TXCTL0_A] = 0x2A00, 3773 [TDWBAL0_A] = 0x2A00, 3774 [TDWBAH0_A] = 0x2A00, 3775 [TDBAL1_A] = 0x29D0, 3776 [TDBAL2_A] = 0x29A0, 3777 [TDBAL3_A] = 0x2970, 3778 [TDBAH1_A] = 0x29D0, 3779 [TDBAH2_A] = 0x29A0, 3780 [TDBAH3_A] = 0x2970, 3781 [TDLEN1_A] = 0x29D0, 3782 [TDLEN2_A] = 0x29A0, 3783 [TDLEN3_A] = 0x2970, 3784 [TDH1_A] = 0x29D0, 3785 [TDH2_A] = 0x29A0, 3786 [TDH3_A] = 0x2970, 3787 [TDT1_A] = 0x29D0, 3788 [TDT2_A] = 0x29A0, 3789 [TDT3_A] = 0x2970, 3790 [TXDCTL0_A] = 0x2A00, 3791 [TXDCTL1_A] = 0x29D0, 3792 [TXDCTL2_A] = 0x29A0, 3793 [TXDCTL3_A] = 0x2970, 3794 [TXCTL1_A] = 0x29D0, 3795 [TXCTL2_A] = 0x29A0, 3796 [TXCTL3_A] = 0x29D0, 3797 [TDWBAL1_A] = 0x29D0, 3798 [TDWBAL2_A] = 0x29A0, 3799 [TDWBAL3_A] = 0x2970, 3800 [TDWBAH1_A] = 0x29D0, 3801 [TDWBAH2_A] = 0x29A0, 3802 [TDWBAH3_A] = 0x2970, 3803 3804 /* Access options */ 3805 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3806 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3807 [RDFPC] = MAC_ACCESS_PARTIAL, 3808 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3809 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3810 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3811 [FLA] = MAC_ACCESS_PARTIAL, 3812 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3813 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3814 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3815 [FCRTH] = MAC_ACCESS_PARTIAL, 3816 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3817 }; 3818 3819 void 3820 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size) 3821 { 3822 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3823 3824 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) { 3825 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3826 trace_e1000e_wrn_regs_write_trivial(index << 2); 3827 } 3828 trace_e1000e_core_write(index << 2, size, val); 3829 igb_macreg_writeops[index](core, index, val); 3830 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3831 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3832 } else { 3833 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3834 } 3835 } 3836 3837 uint64_t 3838 igb_core_read(IGBCore *core, hwaddr addr, unsigned size) 3839 { 3840 uint64_t val; 3841 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3842 3843 if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3844 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3845 trace_e1000e_wrn_regs_read_trivial(index << 2); 3846 } 3847 val = igb_macreg_readops[index](core, index); 3848 trace_e1000e_core_read(index << 2, size, val); 3849 return val; 3850 } else { 3851 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3852 } 3853 return 0; 3854 } 3855 3856 static inline void 3857 igb_autoneg_pause(IGBCore *core) 3858 { 3859 timer_del(core->autoneg_timer); 3860 } 3861 3862 static void 3863 igb_autoneg_resume(IGBCore *core) 3864 { 3865 if (igb_have_autoneg(core) && 3866 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 3867 qemu_get_queue(core->owner_nic)->link_down = false; 3868 timer_mod(core->autoneg_timer, 3869 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3870 } 3871 } 3872 3873 static void 3874 igb_vm_state_change(void *opaque, bool running, RunState state) 3875 { 3876 IGBCore *core = opaque; 3877 3878 if (running) { 3879 trace_e1000e_vm_state_running(); 3880 igb_intrmgr_resume(core); 3881 igb_autoneg_resume(core); 3882 } else { 3883 trace_e1000e_vm_state_stopped(); 3884 igb_autoneg_pause(core); 3885 igb_intrmgr_pause(core); 3886 } 3887 } 3888 3889 void 3890 igb_core_pci_realize(IGBCore *core, 3891 const uint16_t *eeprom_templ, 3892 uint32_t eeprom_size, 3893 const uint8_t *macaddr) 3894 { 3895 int i; 3896 3897 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3898 igb_autoneg_timer, core); 3899 igb_intrmgr_pci_realize(core); 3900 3901 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core); 3902 3903 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3904 net_tx_pkt_init(&core->tx[i].tx_pkt, NULL, E1000E_MAX_TX_FRAGS); 3905 } 3906 3907 net_rx_pkt_init(&core->rx_pkt); 3908 3909 e1000x_core_prepare_eeprom(core->eeprom, 3910 eeprom_templ, 3911 eeprom_size, 3912 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3913 macaddr); 3914 igb_update_rx_offloads(core); 3915 } 3916 3917 void 3918 igb_core_pci_uninit(IGBCore *core) 3919 { 3920 int i; 3921 3922 timer_free(core->autoneg_timer); 3923 3924 igb_intrmgr_pci_unint(core); 3925 3926 qemu_del_vm_change_state_handler(core->vmstate); 3927 3928 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3929 net_tx_pkt_reset(core->tx[i].tx_pkt, NULL); 3930 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3931 } 3932 3933 net_rx_pkt_uninit(core->rx_pkt); 3934 } 3935 3936 static const uint16_t 3937 igb_phy_reg_init[] = { 3938 [MII_BMCR] = MII_BMCR_SPEED1000 | 3939 MII_BMCR_FD | 3940 MII_BMCR_AUTOEN, 3941 3942 [MII_BMSR] = MII_BMSR_EXTCAP | 3943 MII_BMSR_LINK_ST | 3944 MII_BMSR_AUTONEG | 3945 MII_BMSR_MFPS | 3946 MII_BMSR_EXTSTAT | 3947 MII_BMSR_10T_HD | 3948 MII_BMSR_10T_FD | 3949 MII_BMSR_100TX_HD | 3950 MII_BMSR_100TX_FD, 3951 3952 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16, 3953 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1, 3954 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3955 MII_ANAR_10FD | MII_ANAR_TX | 3956 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3957 MII_ANAR_PAUSE_ASYM, 3958 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3959 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3960 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3961 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3962 [MII_ANNP] = 0x1 | MII_ANNP_MP, 3963 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3964 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3965 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3966 MII_STAT1000_ROK | MII_STAT1000_LOK, 3967 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3968 3969 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8), 3970 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS, 3971 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU | 3972 IGP01E1000_PSCFR_SMART_SPEED 3973 }; 3974 3975 static const uint32_t igb_mac_reg_init[] = { 3976 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24), 3977 [EEMNGCTL] = BIT(31), 3978 [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE, 3979 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16), 3980 [RXDCTL1] = 1 << 16, 3981 [RXDCTL2] = 1 << 16, 3982 [RXDCTL3] = 1 << 16, 3983 [RXDCTL4] = 1 << 16, 3984 [RXDCTL5] = 1 << 16, 3985 [RXDCTL6] = 1 << 16, 3986 [RXDCTL7] = 1 << 16, 3987 [RXDCTL8] = 1 << 16, 3988 [RXDCTL9] = 1 << 16, 3989 [RXDCTL10] = 1 << 16, 3990 [RXDCTL11] = 1 << 16, 3991 [RXDCTL12] = 1 << 16, 3992 [RXDCTL13] = 1 << 16, 3993 [RXDCTL14] = 1 << 16, 3994 [RXDCTL15] = 1 << 16, 3995 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20), 3996 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 | 3997 E1000_CTRL_ADVD3WUC, 3998 [STATUS] = E1000_STATUS_PHYRA | BIT(31), 3999 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES | 4000 (2 << E1000_EECD_SIZE_EX_SHIFT), 4001 [GCR] = E1000_L0S_ADJUST | 4002 E1000_GCR_CMPL_TMOUT_RESEND | 4003 E1000_GCR_CAP_VER2 | 4004 E1000_L1_ENTRY_LATENCY_MSB | 4005 E1000_L1_ENTRY_LATENCY_LSB, 4006 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 4007 [TXPBS] = 0x28, 4008 [RXPBS] = 0x40, 4009 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) | 4010 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28), 4011 [TCTL_EXT] = 0x40 | (0x42 << 10), 4012 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT, 4013 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16), 4014 4015 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI, 4016 [MBVFIMR] = 0xFF, 4017 [VFRE] = 0xFF, 4018 [VFTE] = 0xFF, 4019 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC, 4020 [RPLOLR] = E1000_RPLOLR_STRCRC, 4021 [RLPML] = 0x2600, 4022 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4023 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4024 E1000_DCA_TXCTRL_DESC_RRO_EN, 4025 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4026 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4027 E1000_DCA_TXCTRL_DESC_RRO_EN, 4028 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4029 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4030 E1000_DCA_TXCTRL_DESC_RRO_EN, 4031 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4032 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4033 E1000_DCA_TXCTRL_DESC_RRO_EN, 4034 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4035 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4036 E1000_DCA_TXCTRL_DESC_RRO_EN, 4037 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4038 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4039 E1000_DCA_TXCTRL_DESC_RRO_EN, 4040 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4041 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4042 E1000_DCA_TXCTRL_DESC_RRO_EN, 4043 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4044 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4045 E1000_DCA_TXCTRL_DESC_RRO_EN, 4046 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4047 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4048 E1000_DCA_TXCTRL_DESC_RRO_EN, 4049 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4050 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4051 E1000_DCA_TXCTRL_DESC_RRO_EN, 4052 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4053 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4054 E1000_DCA_TXCTRL_DESC_RRO_EN, 4055 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4056 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4057 E1000_DCA_TXCTRL_DESC_RRO_EN, 4058 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4059 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4060 E1000_DCA_TXCTRL_DESC_RRO_EN, 4061 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4062 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4063 E1000_DCA_TXCTRL_DESC_RRO_EN, 4064 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4065 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4066 E1000_DCA_TXCTRL_DESC_RRO_EN, 4067 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4068 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4069 E1000_DCA_TXCTRL_DESC_RRO_EN, 4070 }; 4071 4072 static void igb_reset(IGBCore *core, bool sw) 4073 { 4074 struct igb_tx *tx; 4075 int i; 4076 4077 timer_del(core->autoneg_timer); 4078 4079 igb_intrmgr_reset(core); 4080 4081 memset(core->phy, 0, sizeof core->phy); 4082 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init); 4083 4084 for (i = 0; i < E1000E_MAC_SIZE; i++) { 4085 if (sw && 4086 (i == RXPBS || i == TXPBS || 4087 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) { 4088 continue; 4089 } 4090 4091 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ? 4092 igb_mac_reg_init[i] : 0; 4093 } 4094 4095 if (qemu_get_queue(core->owner_nic)->link_down) { 4096 igb_link_down(core); 4097 } 4098 4099 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 4100 4101 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 4102 /* Set RSTI, so VF can identify a PF reset is in progress */ 4103 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI; 4104 } 4105 4106 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4107 tx = &core->tx[i]; 4108 net_tx_pkt_reset(tx->tx_pkt, NULL); 4109 memset(tx->ctx, 0, sizeof(tx->ctx)); 4110 tx->first = true; 4111 tx->skip_cp = false; 4112 } 4113 } 4114 4115 void 4116 igb_core_reset(IGBCore *core) 4117 { 4118 igb_reset(core, false); 4119 } 4120 4121 void igb_core_pre_save(IGBCore *core) 4122 { 4123 int i; 4124 NetClientState *nc = qemu_get_queue(core->owner_nic); 4125 4126 /* 4127 * If link is down and auto-negotiation is supported and ongoing, 4128 * complete auto-negotiation immediately. This allows us to look 4129 * at MII_BMSR_AN_COMP to infer link status on load. 4130 */ 4131 if (nc->link_down && igb_have_autoneg(core)) { 4132 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP; 4133 igb_update_flowctl_status(core); 4134 } 4135 4136 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4137 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 4138 core->tx[i].skip_cp = true; 4139 } 4140 } 4141 } 4142 4143 int 4144 igb_core_post_load(IGBCore *core) 4145 { 4146 NetClientState *nc = qemu_get_queue(core->owner_nic); 4147 4148 /* 4149 * nc.link_down can't be migrated, so infer link_down according 4150 * to link status bit in core.mac[STATUS]. 4151 */ 4152 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 4153 4154 return 0; 4155 } 4156