1 /* 2 * Core code for QEMU igb emulation 3 * 4 * Datasheet: 5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf 6 * 7 * Copyright (c) 2020-2023 Red Hat, Inc. 8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 9 * Developed by Daynix Computing LTD (http://www.daynix.com) 10 * 11 * Authors: 12 * Akihiko Odaki <akihiko.odaki@daynix.com> 13 * Gal Hammmer <gal.hammer@sap.com> 14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com> 15 * Dmitry Fleytman <dmitry@daynix.com> 16 * Leonid Bloch <leonid@daynix.com> 17 * Yan Vugenfirer <yan@daynix.com> 18 * 19 * Based on work done by: 20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 21 * Copyright (c) 2008 Qumranet 22 * Based on work done by: 23 * Copyright (c) 2007 Dan Aloni 24 * Copyright (c) 2004 Antony T Curtis 25 * 26 * This library is free software; you can redistribute it and/or 27 * modify it under the terms of the GNU Lesser General Public 28 * License as published by the Free Software Foundation; either 29 * version 2.1 of the License, or (at your option) any later version. 30 * 31 * This library is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 34 * Lesser General Public License for more details. 35 * 36 * You should have received a copy of the GNU Lesser General Public 37 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/log.h" 42 #include "net/net.h" 43 #include "net/tap.h" 44 #include "hw/net/mii.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "sysemu/runstate.h" 48 49 #include "net_tx_pkt.h" 50 #include "net_rx_pkt.h" 51 52 #include "igb_common.h" 53 #include "e1000x_common.h" 54 #include "igb_core.h" 55 56 #include "trace.h" 57 58 #define E1000E_MAX_TX_FRAGS (64) 59 60 union e1000_rx_desc_union { 61 struct e1000_rx_desc legacy; 62 union e1000_adv_rx_desc adv; 63 }; 64 65 typedef struct IGBTxPktVmdqCallbackContext { 66 IGBCore *core; 67 NetClientState *nc; 68 } IGBTxPktVmdqCallbackContext; 69 70 static ssize_t 71 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 72 bool has_vnet, bool *external_tx); 73 74 static inline void 75 igb_set_interrupt_cause(IGBCore *core, uint32_t val); 76 77 static void igb_update_interrupt_state(IGBCore *core); 78 static void igb_reset(IGBCore *core, bool sw); 79 80 static inline void 81 igb_raise_legacy_irq(IGBCore *core) 82 { 83 trace_e1000e_irq_legacy_notify(true); 84 e1000x_inc_reg_if_not_full(core->mac, IAC); 85 pci_set_irq(core->owner, 1); 86 } 87 88 static inline void 89 igb_lower_legacy_irq(IGBCore *core) 90 { 91 trace_e1000e_irq_legacy_notify(false); 92 pci_set_irq(core->owner, 0); 93 } 94 95 static void igb_msix_notify(IGBCore *core, unsigned int vector) 96 { 97 PCIDevice *dev = core->owner; 98 uint16_t vfn; 99 100 vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM; 101 if (vfn < pcie_sriov_num_vfs(core->owner)) { 102 dev = pcie_sriov_get_vf_at_index(core->owner, vfn); 103 assert(dev); 104 vector = (vector + 2) % IGBVF_MSIX_VEC_NUM; 105 } else if (vector >= IGB_MSIX_VEC_NUM) { 106 qemu_log_mask(LOG_GUEST_ERROR, 107 "igb: Tried to use vector unavailable for PF"); 108 return; 109 } 110 111 msix_notify(dev, vector); 112 } 113 114 static inline void 115 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) 116 { 117 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 118 timer->delay_resolution_ns; 119 120 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 121 122 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 123 124 timer->running = true; 125 } 126 127 static void 128 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer) 129 { 130 if (timer->running) { 131 igb_intrmgr_rearm_timer(timer); 132 } 133 } 134 135 static void 136 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer) 137 { 138 if (timer->running) { 139 timer_del(timer->timer); 140 } 141 } 142 143 static void 144 igb_intrmgr_on_msix_throttling_timer(void *opaque) 145 { 146 IGBIntrDelayTimer *timer = opaque; 147 int idx = timer - &timer->core->eitr[0]; 148 149 timer->running = false; 150 151 trace_e1000e_irq_msix_notify_postponed_vec(idx); 152 igb_msix_notify(timer->core, idx); 153 } 154 155 static void 156 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create) 157 { 158 int i; 159 160 for (i = 0; i < IGB_INTR_NUM; i++) { 161 core->eitr[i].core = core; 162 core->eitr[i].delay_reg = EITR0 + i; 163 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 164 } 165 166 if (!create) { 167 return; 168 } 169 170 for (i = 0; i < IGB_INTR_NUM; i++) { 171 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 172 igb_intrmgr_on_msix_throttling_timer, 173 &core->eitr[i]); 174 } 175 } 176 177 static void 178 igb_intrmgr_resume(IGBCore *core) 179 { 180 int i; 181 182 for (i = 0; i < IGB_INTR_NUM; i++) { 183 igb_intmgr_timer_resume(&core->eitr[i]); 184 } 185 } 186 187 static void 188 igb_intrmgr_pause(IGBCore *core) 189 { 190 int i; 191 192 for (i = 0; i < IGB_INTR_NUM; i++) { 193 igb_intmgr_timer_pause(&core->eitr[i]); 194 } 195 } 196 197 static void 198 igb_intrmgr_reset(IGBCore *core) 199 { 200 int i; 201 202 for (i = 0; i < IGB_INTR_NUM; i++) { 203 if (core->eitr[i].running) { 204 timer_del(core->eitr[i].timer); 205 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 206 } 207 } 208 } 209 210 static void 211 igb_intrmgr_pci_unint(IGBCore *core) 212 { 213 int i; 214 215 for (i = 0; i < IGB_INTR_NUM; i++) { 216 timer_free(core->eitr[i].timer); 217 } 218 } 219 220 static void 221 igb_intrmgr_pci_realize(IGBCore *core) 222 { 223 igb_intrmgr_initialize_all_timers(core, true); 224 } 225 226 static inline bool 227 igb_rx_csum_enabled(IGBCore *core) 228 { 229 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 230 } 231 232 static inline bool 233 igb_rx_use_legacy_descriptor(IGBCore *core) 234 { 235 /* 236 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx 237 * descriptor. 238 */ 239 return false; 240 } 241 242 static inline bool 243 igb_rss_enabled(IGBCore *core) 244 { 245 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ && 246 !igb_rx_csum_enabled(core) && 247 !igb_rx_use_legacy_descriptor(core); 248 } 249 250 typedef struct E1000E_RSSInfo_st { 251 bool enabled; 252 uint32_t hash; 253 uint32_t queue; 254 uint32_t type; 255 } E1000E_RSSInfo; 256 257 static uint32_t 258 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt) 259 { 260 bool hasip4, hasip6; 261 EthL4HdrProto l4hdr_proto; 262 263 assert(igb_rss_enabled(core)); 264 265 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 266 267 if (hasip4) { 268 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 269 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 270 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 271 272 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 273 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 274 return E1000_MRQ_RSS_TYPE_IPV4TCP; 275 } 276 277 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 278 return E1000_MRQ_RSS_TYPE_IPV4; 279 } 280 } else if (hasip6) { 281 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 282 283 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 284 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 285 286 /* 287 * Following two traces must not be combined because resulting 288 * event will have 11 arguments totally and some trace backends 289 * (at least "ust") have limitation of maximum 10 arguments per 290 * event. Events with more arguments fail to compile for 291 * backends like these. 292 */ 293 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 294 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 295 ip6info->has_ext_hdrs, 296 ip6info->rss_ex_dst_valid, 297 ip6info->rss_ex_src_valid, 298 core->mac[MRQC], 299 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 300 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 301 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 302 303 if ((!ex_dis || !ip6info->has_ext_hdrs) && 304 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 305 ip6info->rss_ex_src_valid))) { 306 307 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 308 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 309 return E1000_MRQ_RSS_TYPE_IPV6TCP; 310 } 311 312 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 313 return E1000_MRQ_RSS_TYPE_IPV6EX; 314 } 315 316 } 317 318 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 319 return E1000_MRQ_RSS_TYPE_IPV6; 320 } 321 322 } 323 324 return E1000_MRQ_RSS_TYPE_NONE; 325 } 326 327 static uint32_t 328 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info) 329 { 330 NetRxPktRssType type; 331 332 assert(igb_rss_enabled(core)); 333 334 switch (info->type) { 335 case E1000_MRQ_RSS_TYPE_IPV4: 336 type = NetPktRssIpV4; 337 break; 338 case E1000_MRQ_RSS_TYPE_IPV4TCP: 339 type = NetPktRssIpV4Tcp; 340 break; 341 case E1000_MRQ_RSS_TYPE_IPV6TCP: 342 type = NetPktRssIpV6TcpEx; 343 break; 344 case E1000_MRQ_RSS_TYPE_IPV6: 345 type = NetPktRssIpV6; 346 break; 347 case E1000_MRQ_RSS_TYPE_IPV6EX: 348 type = NetPktRssIpV6Ex; 349 break; 350 default: 351 assert(false); 352 return 0; 353 } 354 355 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 356 } 357 358 static void 359 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx, 360 E1000E_RSSInfo *info) 361 { 362 trace_e1000e_rx_rss_started(); 363 364 if (tx || !igb_rss_enabled(core)) { 365 info->enabled = false; 366 info->hash = 0; 367 info->queue = 0; 368 info->type = 0; 369 trace_e1000e_rx_rss_disabled(); 370 return; 371 } 372 373 info->enabled = true; 374 375 info->type = igb_rss_get_hash_type(core, pkt); 376 377 trace_e1000e_rx_rss_type(info->type); 378 379 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 380 info->hash = 0; 381 info->queue = 0; 382 return; 383 } 384 385 info->hash = igb_rss_calc_hash(core, pkt, info); 386 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 387 } 388 389 static bool 390 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx) 391 { 392 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) { 393 uint32_t idx = (tx->first_olinfo_status >> 4) & 1; 394 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> 16; 395 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) { 396 return false; 397 } 398 399 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 400 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 401 return true; 402 } 403 404 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) { 405 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 406 return false; 407 } 408 } 409 410 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) { 411 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 412 } 413 414 return true; 415 } 416 417 static void igb_tx_pkt_mac_callback(void *core, 418 const struct iovec *iov, 419 int iovcnt, 420 const struct iovec *virt_iov, 421 int virt_iovcnt) 422 { 423 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL); 424 } 425 426 static void igb_tx_pkt_vmdq_callback(void *opaque, 427 const struct iovec *iov, 428 int iovcnt, 429 const struct iovec *virt_iov, 430 int virt_iovcnt) 431 { 432 IGBTxPktVmdqCallbackContext *context = opaque; 433 bool external_tx; 434 435 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true, 436 &external_tx); 437 438 if (external_tx) { 439 if (context->core->has_vnet) { 440 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt); 441 } else { 442 qemu_sendv_packet(context->nc, iov, iovcnt); 443 } 444 } 445 } 446 447 /* TX Packets Switching (7.10.3.6) */ 448 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx, 449 NetClientState *nc) 450 { 451 IGBTxPktVmdqCallbackContext context; 452 453 /* TX switching is only used to serve VM to VM traffic. */ 454 if (!(core->mac[MRQC] & 1)) { 455 goto send_out; 456 } 457 458 /* TX switching requires DTXSWC.Loopback_en bit enabled. */ 459 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) { 460 goto send_out; 461 } 462 463 context.core = core; 464 context.nc = nc; 465 466 return net_tx_pkt_send_custom(tx->tx_pkt, false, 467 igb_tx_pkt_vmdq_callback, &context); 468 469 send_out: 470 return net_tx_pkt_send(tx->tx_pkt, nc); 471 } 472 473 static bool 474 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index) 475 { 476 int target_queue = MIN(core->max_queue_num, queue_index); 477 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 478 479 if (!igb_setup_tx_offloads(core, tx)) { 480 return false; 481 } 482 483 net_tx_pkt_dump(tx->tx_pkt); 484 485 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) || 486 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 487 return net_tx_pkt_send_custom(tx->tx_pkt, false, 488 igb_tx_pkt_mac_callback, core); 489 } else { 490 return igb_tx_pkt_switch(core, tx, queue); 491 } 492 } 493 494 static void 495 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt) 496 { 497 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 498 PTC1023, PTC1522 }; 499 500 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 501 502 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 503 e1000x_inc_reg_if_not_full(core->mac, TPT); 504 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 505 506 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 507 case ETH_PKT_BCAST: 508 e1000x_inc_reg_if_not_full(core->mac, BPTC); 509 break; 510 case ETH_PKT_MCAST: 511 e1000x_inc_reg_if_not_full(core->mac, MPTC); 512 break; 513 case ETH_PKT_UCAST: 514 break; 515 default: 516 g_assert_not_reached(); 517 } 518 519 core->mac[GPTC] = core->mac[TPT]; 520 core->mac[GOTCL] = core->mac[TOTL]; 521 core->mac[GOTCH] = core->mac[TOTH]; 522 } 523 524 static void 525 igb_process_tx_desc(IGBCore *core, 526 PCIDevice *dev, 527 struct igb_tx *tx, 528 union e1000_adv_tx_desc *tx_desc, 529 int queue_index) 530 { 531 struct e1000_adv_tx_context_desc *tx_ctx_desc; 532 uint32_t cmd_type_len; 533 uint32_t idx; 534 uint64_t buffer_addr; 535 uint16_t length; 536 537 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 538 539 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) { 540 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) == 541 E1000_ADVTXD_DTYP_DATA) { 542 /* advanced transmit data descriptor */ 543 if (tx->first) { 544 tx->first_cmd_type_len = cmd_type_len; 545 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status); 546 tx->first = false; 547 } 548 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) == 549 E1000_ADVTXD_DTYP_CTXT) { 550 /* advanced transmit context descriptor */ 551 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc; 552 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1; 553 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens); 554 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed); 555 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl); 556 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx); 557 return; 558 } else { 559 /* unknown descriptor type */ 560 return; 561 } 562 } else { 563 /* legacy descriptor */ 564 565 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */ 566 } 567 568 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr); 569 length = cmd_type_len & 0xFFFF; 570 571 if (!tx->skip_cp) { 572 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, buffer_addr, length)) { 573 tx->skip_cp = true; 574 } 575 } 576 577 if (cmd_type_len & E1000_TXD_CMD_EOP) { 578 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 579 if (cmd_type_len & E1000_TXD_CMD_VLE) { 580 idx = (tx->first_olinfo_status >> 4) & 1; 581 uint16_t vlan = tx->ctx[idx].vlan_macip_lens >> 16; 582 uint16_t vet = core->mac[VET] & 0xffff; 583 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan, vet); 584 } 585 if (igb_tx_pkt_send(core, tx, queue_index)) { 586 igb_on_tx_done_update_stats(core, tx->tx_pkt); 587 } 588 } 589 590 tx->first = true; 591 tx->skip_cp = false; 592 net_tx_pkt_reset(tx->tx_pkt, dev); 593 } 594 } 595 596 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx) 597 { 598 uint32_t n, ent = 0; 599 600 n = igb_ivar_entry_tx(queue_idx); 601 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 602 603 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 604 } 605 606 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx) 607 { 608 uint32_t n, ent = 0; 609 610 n = igb_ivar_entry_rx(queue_idx); 611 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 612 613 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 614 } 615 616 typedef struct E1000E_RingInfo_st { 617 int dbah; 618 int dbal; 619 int dlen; 620 int dh; 621 int dt; 622 int idx; 623 } E1000E_RingInfo; 624 625 static inline bool 626 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r) 627 { 628 return core->mac[r->dh] == core->mac[r->dt] || 629 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 630 } 631 632 static inline uint64_t 633 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r) 634 { 635 uint64_t bah = core->mac[r->dbah]; 636 uint64_t bal = core->mac[r->dbal]; 637 638 return (bah << 32) + bal; 639 } 640 641 static inline uint64_t 642 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r) 643 { 644 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 645 } 646 647 static inline void 648 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count) 649 { 650 core->mac[r->dh] += count; 651 652 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 653 core->mac[r->dh] = 0; 654 } 655 } 656 657 static inline uint32_t 658 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r) 659 { 660 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 661 core->mac[r->dh], core->mac[r->dt]); 662 663 if (core->mac[r->dh] <= core->mac[r->dt]) { 664 return core->mac[r->dt] - core->mac[r->dh]; 665 } 666 667 if (core->mac[r->dh] > core->mac[r->dt]) { 668 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 669 core->mac[r->dt] - core->mac[r->dh]; 670 } 671 672 g_assert_not_reached(); 673 return 0; 674 } 675 676 static inline bool 677 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r) 678 { 679 return core->mac[r->dlen] > 0; 680 } 681 682 typedef struct IGB_TxRing_st { 683 const E1000E_RingInfo *i; 684 struct igb_tx *tx; 685 } IGB_TxRing; 686 687 static inline int 688 igb_mq_queue_idx(int base_reg_idx, int reg_idx) 689 { 690 return (reg_idx - base_reg_idx) / 16; 691 } 692 693 static inline void 694 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx) 695 { 696 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 697 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 }, 698 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }, 699 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 }, 700 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 }, 701 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 }, 702 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 }, 703 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 }, 704 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 }, 705 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 }, 706 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 }, 707 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 }, 708 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 }, 709 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 }, 710 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 }, 711 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 }, 712 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 } 713 }; 714 715 assert(idx < ARRAY_SIZE(i)); 716 717 txr->i = &i[idx]; 718 txr->tx = &core->tx[idx]; 719 } 720 721 typedef struct E1000E_RxRing_st { 722 const E1000E_RingInfo *i; 723 } E1000E_RxRing; 724 725 static inline void 726 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx) 727 { 728 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 729 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 730 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }, 731 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 }, 732 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 }, 733 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 }, 734 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 }, 735 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 }, 736 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 }, 737 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 }, 738 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 }, 739 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 }, 740 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 }, 741 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 }, 742 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 }, 743 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 }, 744 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 } 745 }; 746 747 assert(idx < ARRAY_SIZE(i)); 748 749 rxr->i = &i[idx]; 750 } 751 752 static uint32_t 753 igb_txdesc_writeback(IGBCore *core, dma_addr_t base, 754 union e1000_adv_tx_desc *tx_desc, 755 const E1000E_RingInfo *txi) 756 { 757 PCIDevice *d; 758 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 759 uint64_t tdwba; 760 761 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2]; 762 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32; 763 764 if (!(cmd_type_len & E1000_TXD_CMD_RS)) { 765 return 0; 766 } 767 768 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 769 if (!d) { 770 d = core->owner; 771 } 772 773 if (tdwba & 1) { 774 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]); 775 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer)); 776 } else { 777 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD; 778 779 tx_desc->wb.status = cpu_to_le32(status); 780 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb), 781 &tx_desc->wb, sizeof(tx_desc->wb)); 782 } 783 784 return igb_tx_wb_eic(core, txi->idx); 785 } 786 787 static void 788 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr) 789 { 790 PCIDevice *d; 791 dma_addr_t base; 792 union e1000_adv_tx_desc desc; 793 const E1000E_RingInfo *txi = txr->i; 794 uint32_t eic = 0; 795 796 /* TODO: check if the queue itself is enabled too. */ 797 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 798 trace_e1000e_tx_disabled(); 799 return; 800 } 801 802 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 803 if (!d) { 804 d = core->owner; 805 } 806 807 net_tx_pkt_reset(txr->tx->tx_pkt, d); 808 809 while (!igb_ring_empty(core, txi)) { 810 base = igb_ring_head_descr(core, txi); 811 812 pci_dma_read(d, base, &desc, sizeof(desc)); 813 814 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr, 815 desc.read.cmd_type_len, desc.wb.status); 816 817 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx); 818 igb_ring_advance(core, txi, 1); 819 eic |= igb_txdesc_writeback(core, base, &desc, txi); 820 } 821 822 if (eic) { 823 core->mac[EICR] |= eic; 824 igb_set_interrupt_cause(core, E1000_ICR_TXDW); 825 } 826 } 827 828 static uint32_t 829 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r) 830 { 831 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2]; 832 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK; 833 if (bsizepkt) { 834 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT; 835 } 836 837 return e1000x_rxbufsize(core->mac[RCTL]); 838 } 839 840 static bool 841 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size) 842 { 843 uint32_t bufs = igb_ring_free_descr_num(core, r); 844 uint32_t bufsize = igb_rxbufsize(core, r); 845 846 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize); 847 848 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 849 bufsize; 850 } 851 852 void 853 igb_start_recv(IGBCore *core) 854 { 855 int i; 856 857 trace_e1000e_rx_start_recv(); 858 859 for (i = 0; i <= core->max_queue_num; i++) { 860 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 861 } 862 } 863 864 bool 865 igb_can_receive(IGBCore *core) 866 { 867 int i; 868 869 if (!e1000x_rx_ready(core->owner, core->mac)) { 870 return false; 871 } 872 873 for (i = 0; i < IGB_NUM_QUEUES; i++) { 874 E1000E_RxRing rxr; 875 876 igb_rx_ring_init(core, &rxr, i); 877 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) { 878 trace_e1000e_rx_can_recv(); 879 return true; 880 } 881 } 882 883 trace_e1000e_rx_can_recv_rings_full(); 884 return false; 885 } 886 887 ssize_t 888 igb_receive(IGBCore *core, const uint8_t *buf, size_t size) 889 { 890 const struct iovec iov = { 891 .iov_base = (uint8_t *)buf, 892 .iov_len = size 893 }; 894 895 return igb_receive_iov(core, &iov, 1); 896 } 897 898 static inline bool 899 igb_rx_l3_cso_enabled(IGBCore *core) 900 { 901 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 902 } 903 904 static inline bool 905 igb_rx_l4_cso_enabled(IGBCore *core) 906 { 907 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 908 } 909 910 static uint16_t igb_receive_assign(IGBCore *core, const struct eth_header *ehdr, 911 E1000E_RSSInfo *rss_info, bool *external_tx) 912 { 913 static const int ta_shift[] = { 4, 3, 2, 0 }; 914 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL]; 915 uint16_t queues = 0; 916 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(ehdr)->h_tci) & VLAN_VID_MASK; 917 bool accepted = false; 918 int i; 919 920 memset(rss_info, 0, sizeof(E1000E_RSSInfo)); 921 922 if (external_tx) { 923 *external_tx = true; 924 } 925 926 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) && 927 e1000x_vlan_rx_filter_enabled(core->mac)) { 928 uint32_t vfta = 929 ldl_le_p((uint32_t *)(core->mac + VFTA) + 930 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK)); 931 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) { 932 trace_e1000e_rx_flt_vlan_mismatch(vid); 933 return queues; 934 } else { 935 trace_e1000e_rx_flt_vlan_match(vid); 936 } 937 } 938 939 if (core->mac[MRQC] & 1) { 940 if (is_broadcast_ether_addr(ehdr->h_dest)) { 941 for (i = 0; i < 8; i++) { 942 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) { 943 queues |= BIT(i); 944 } 945 } 946 } else { 947 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) { 948 if (!(macp[1] & E1000_RAH_AV)) { 949 continue; 950 } 951 ra[0] = cpu_to_le32(macp[0]); 952 ra[1] = cpu_to_le32(macp[1]); 953 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 954 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 955 } 956 } 957 958 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 959 if (!(macp[1] & E1000_RAH_AV)) { 960 continue; 961 } 962 ra[0] = cpu_to_le32(macp[0]); 963 ra[1] = cpu_to_le32(macp[1]); 964 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 965 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 966 } 967 } 968 969 if (!queues) { 970 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA); 971 972 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; 973 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff; 974 if (macp[f >> 5] & (1 << (f & 0x1f))) { 975 for (i = 0; i < 8; i++) { 976 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) { 977 queues |= BIT(i); 978 } 979 } 980 } 981 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) { 982 *external_tx = false; 983 } 984 } 985 986 if (e1000x_vlan_rx_filter_enabled(core->mac)) { 987 uint16_t mask = 0; 988 989 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) { 990 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 991 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid && 992 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) { 993 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK; 994 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT; 995 } 996 } 997 } else { 998 for (i = 0; i < 8; i++) { 999 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) { 1000 mask |= BIT(i); 1001 } 1002 } 1003 } 1004 1005 queues &= mask; 1006 } 1007 1008 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx && 1009 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) { 1010 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK; 1011 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT); 1012 } 1013 1014 igb_rss_parse_packet(core, core->rx_pkt, external_tx != NULL, rss_info); 1015 if (rss_info->queue & 1) { 1016 queues <<= 8; 1017 } 1018 } else { 1019 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1020 case ETH_PKT_UCAST: 1021 if (rctl & E1000_RCTL_UPE) { 1022 accepted = true; /* promiscuous ucast */ 1023 } 1024 break; 1025 1026 case ETH_PKT_BCAST: 1027 if (rctl & E1000_RCTL_BAM) { 1028 accepted = true; /* broadcast enabled */ 1029 } 1030 break; 1031 1032 case ETH_PKT_MCAST: 1033 if (rctl & E1000_RCTL_MPE) { 1034 accepted = true; /* promiscuous mcast */ 1035 } 1036 break; 1037 1038 default: 1039 g_assert_not_reached(); 1040 } 1041 1042 if (!accepted) { 1043 accepted = e1000x_rx_group_filter(core->mac, ehdr->h_dest); 1044 } 1045 1046 if (!accepted) { 1047 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 1048 if (!(macp[1] & E1000_RAH_AV)) { 1049 continue; 1050 } 1051 ra[0] = cpu_to_le32(macp[0]); 1052 ra[1] = cpu_to_le32(macp[1]); 1053 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 1054 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2, 1055 MAC_ARG(ehdr->h_dest)); 1056 1057 accepted = true; 1058 break; 1059 } 1060 } 1061 } 1062 1063 if (accepted) { 1064 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info); 1065 queues = BIT(rss_info->queue); 1066 } 1067 } 1068 1069 return queues; 1070 } 1071 1072 static inline void 1073 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1074 hwaddr *buff_addr) 1075 { 1076 *buff_addr = le64_to_cpu(desc->buffer_addr); 1077 } 1078 1079 static inline void 1080 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1081 hwaddr *buff_addr) 1082 { 1083 *buff_addr = le64_to_cpu(desc->read.pkt_addr); 1084 } 1085 1086 static inline void 1087 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1088 hwaddr *buff_addr) 1089 { 1090 if (igb_rx_use_legacy_descriptor(core)) { 1091 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr); 1092 } else { 1093 igb_read_adv_rx_descr(core, &desc->adv, buff_addr); 1094 } 1095 } 1096 1097 static void 1098 igb_verify_csum_in_sw(IGBCore *core, 1099 struct NetRxPkt *pkt, 1100 uint32_t *status_flags, 1101 EthL4HdrProto l4hdr_proto) 1102 { 1103 bool csum_valid; 1104 uint32_t csum_error; 1105 1106 if (igb_rx_l3_cso_enabled(core)) { 1107 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1108 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1109 } else { 1110 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1111 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1112 } 1113 } else { 1114 trace_e1000e_rx_metadata_l3_cso_disabled(); 1115 } 1116 1117 if (!igb_rx_l4_cso_enabled(core)) { 1118 trace_e1000e_rx_metadata_l4_cso_disabled(); 1119 return; 1120 } 1121 1122 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1123 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1124 return; 1125 } 1126 1127 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1128 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1129 1130 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1131 *status_flags |= E1000_RXD_STAT_UDPCS; 1132 } 1133 } 1134 1135 static void 1136 igb_build_rx_metadata(IGBCore *core, 1137 struct NetRxPkt *pkt, 1138 bool is_eop, 1139 const E1000E_RSSInfo *rss_info, 1140 uint16_t *pkt_info, uint16_t *hdr_info, 1141 uint32_t *rss, 1142 uint32_t *status_flags, 1143 uint16_t *ip_id, 1144 uint16_t *vlan_tag) 1145 { 1146 struct virtio_net_hdr *vhdr; 1147 bool hasip4, hasip6; 1148 EthL4HdrProto l4hdr_proto; 1149 uint32_t pkt_type; 1150 1151 *status_flags = E1000_RXD_STAT_DD; 1152 1153 /* No additional metadata needed for non-EOP descriptors */ 1154 /* TODO: EOP apply only to status so don't skip whole function. */ 1155 if (!is_eop) { 1156 goto func_exit; 1157 } 1158 1159 *status_flags |= E1000_RXD_STAT_EOP; 1160 1161 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1162 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1163 1164 /* VLAN state */ 1165 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1166 *status_flags |= E1000_RXD_STAT_VP; 1167 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1168 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1169 } 1170 1171 /* Packet parsing results */ 1172 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1173 if (rss_info->enabled) { 1174 *rss = cpu_to_le32(rss_info->hash); 1175 trace_igb_rx_metadata_rss(*rss); 1176 } 1177 } else if (hasip4) { 1178 *status_flags |= E1000_RXD_STAT_IPIDV; 1179 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1180 trace_e1000e_rx_metadata_ip_id(*ip_id); 1181 } 1182 1183 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) { 1184 *status_flags |= E1000_RXD_STAT_ACK; 1185 trace_e1000e_rx_metadata_ack(); 1186 } 1187 1188 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1189 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1190 pkt_type = E1000_RXD_PKT_MAC; 1191 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1192 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1193 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1194 } else if (hasip4 || hasip6) { 1195 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1196 } else { 1197 pkt_type = E1000_RXD_PKT_MAC; 1198 } 1199 1200 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1201 1202 if (pkt_info) { 1203 if (rss_info->enabled) { 1204 *pkt_info = rss_info->type; 1205 } 1206 1207 *pkt_info |= (pkt_type << 4); 1208 } else { 1209 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1210 } 1211 1212 if (hdr_info) { 1213 *hdr_info = 0; 1214 } 1215 1216 /* RX CSO information */ 1217 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1218 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1219 goto func_exit; 1220 } 1221 1222 vhdr = net_rx_pkt_get_vhdr(pkt); 1223 1224 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1225 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1226 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1227 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1228 goto func_exit; 1229 } 1230 1231 if (igb_rx_l3_cso_enabled(core)) { 1232 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1233 } else { 1234 trace_e1000e_rx_metadata_l3_cso_disabled(); 1235 } 1236 1237 if (igb_rx_l4_cso_enabled(core)) { 1238 switch (l4hdr_proto) { 1239 case ETH_L4_HDR_PROTO_TCP: 1240 *status_flags |= E1000_RXD_STAT_TCPCS; 1241 break; 1242 1243 case ETH_L4_HDR_PROTO_UDP: 1244 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1245 break; 1246 1247 default: 1248 goto func_exit; 1249 } 1250 } else { 1251 trace_e1000e_rx_metadata_l4_cso_disabled(); 1252 } 1253 1254 trace_e1000e_rx_metadata_status_flags(*status_flags); 1255 1256 func_exit: 1257 *status_flags = cpu_to_le32(*status_flags); 1258 } 1259 1260 static inline void 1261 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1262 struct NetRxPkt *pkt, 1263 const E1000E_RSSInfo *rss_info, 1264 uint16_t length) 1265 { 1266 uint32_t status_flags, rss; 1267 uint16_t ip_id; 1268 1269 assert(!rss_info->enabled); 1270 desc->length = cpu_to_le16(length); 1271 desc->csum = 0; 1272 1273 igb_build_rx_metadata(core, pkt, pkt != NULL, 1274 rss_info, 1275 NULL, NULL, &rss, 1276 &status_flags, &ip_id, 1277 &desc->special); 1278 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1279 desc->status = (uint8_t) le32_to_cpu(status_flags); 1280 } 1281 1282 static inline void 1283 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1284 struct NetRxPkt *pkt, 1285 const E1000E_RSSInfo *rss_info, 1286 uint16_t length) 1287 { 1288 memset(&desc->wb, 0, sizeof(desc->wb)); 1289 1290 desc->wb.upper.length = cpu_to_le16(length); 1291 1292 igb_build_rx_metadata(core, pkt, pkt != NULL, 1293 rss_info, 1294 &desc->wb.lower.lo_dword.pkt_info, 1295 &desc->wb.lower.lo_dword.hdr_info, 1296 &desc->wb.lower.hi_dword.rss, 1297 &desc->wb.upper.status_error, 1298 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1299 &desc->wb.upper.vlan); 1300 } 1301 1302 static inline void 1303 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1304 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length) 1305 { 1306 if (igb_rx_use_legacy_descriptor(core)) { 1307 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length); 1308 } else { 1309 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length); 1310 } 1311 } 1312 1313 static inline void 1314 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr, 1315 union e1000_rx_desc_union *desc, dma_addr_t len) 1316 { 1317 if (igb_rx_use_legacy_descriptor(core)) { 1318 struct e1000_rx_desc *d = &desc->legacy; 1319 size_t offset = offsetof(struct e1000_rx_desc, status); 1320 uint8_t status = d->status; 1321 1322 d->status &= ~E1000_RXD_STAT_DD; 1323 pci_dma_write(dev, addr, desc, len); 1324 1325 if (status & E1000_RXD_STAT_DD) { 1326 d->status = status; 1327 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1328 } 1329 } else { 1330 union e1000_adv_rx_desc *d = &desc->adv; 1331 size_t offset = 1332 offsetof(union e1000_adv_rx_desc, wb.upper.status_error); 1333 uint32_t status = d->wb.upper.status_error; 1334 1335 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1336 pci_dma_write(dev, addr, desc, len); 1337 1338 if (status & E1000_RXD_STAT_DD) { 1339 d->wb.upper.status_error = status; 1340 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1341 } 1342 } 1343 } 1344 1345 static void 1346 igb_write_to_rx_buffers(IGBCore *core, 1347 PCIDevice *d, 1348 hwaddr ba, 1349 uint16_t *written, 1350 const char *data, 1351 dma_addr_t data_len) 1352 { 1353 trace_igb_rx_desc_buff_write(ba, *written, data, data_len); 1354 pci_dma_write(d, ba + *written, data, data_len); 1355 *written += data_len; 1356 } 1357 1358 static void 1359 igb_update_rx_stats(IGBCore *core, size_t data_size, size_t data_fcs_size) 1360 { 1361 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1362 1363 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1364 case ETH_PKT_BCAST: 1365 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1366 break; 1367 1368 case ETH_PKT_MCAST: 1369 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1370 break; 1371 1372 default: 1373 break; 1374 } 1375 } 1376 1377 static inline bool 1378 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi) 1379 { 1380 return igb_ring_free_descr_num(core, rxi) == 1381 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16; 1382 } 1383 1384 static void 1385 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt, 1386 const E1000E_RxRing *rxr, 1387 const E1000E_RSSInfo *rss_info) 1388 { 1389 PCIDevice *d; 1390 dma_addr_t base; 1391 union e1000_rx_desc_union desc; 1392 size_t desc_size; 1393 size_t desc_offset = 0; 1394 size_t iov_ofs = 0; 1395 1396 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1397 size_t size = net_rx_pkt_get_total_len(pkt); 1398 size_t total_size = size + e1000x_fcs_len(core->mac); 1399 const E1000E_RingInfo *rxi = rxr->i; 1400 size_t bufsize = igb_rxbufsize(core, rxi); 1401 1402 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8); 1403 if (!d) { 1404 d = core->owner; 1405 } 1406 1407 do { 1408 hwaddr ba; 1409 uint16_t written = 0; 1410 bool is_last = false; 1411 1412 desc_size = total_size - desc_offset; 1413 1414 if (desc_size > bufsize) { 1415 desc_size = bufsize; 1416 } 1417 1418 if (igb_ring_empty(core, rxi)) { 1419 return; 1420 } 1421 1422 base = igb_ring_head_descr(core, rxi); 1423 1424 pci_dma_read(d, base, &desc, core->rx_desc_len); 1425 1426 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1427 1428 igb_read_rx_descr(core, &desc, &ba); 1429 1430 if (ba) { 1431 if (desc_offset < size) { 1432 static const uint32_t fcs_pad; 1433 size_t iov_copy; 1434 size_t copy_size = size - desc_offset; 1435 if (copy_size > bufsize) { 1436 copy_size = bufsize; 1437 } 1438 1439 /* Copy packet payload */ 1440 while (copy_size) { 1441 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1442 1443 igb_write_to_rx_buffers(core, d, ba, &written, 1444 iov->iov_base + iov_ofs, iov_copy); 1445 1446 copy_size -= iov_copy; 1447 iov_ofs += iov_copy; 1448 if (iov_ofs == iov->iov_len) { 1449 iov++; 1450 iov_ofs = 0; 1451 } 1452 } 1453 1454 if (desc_offset + desc_size >= total_size) { 1455 /* Simulate FCS checksum presence in the last descriptor */ 1456 igb_write_to_rx_buffers(core, d, ba, &written, 1457 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1458 } 1459 } 1460 } else { /* as per intel docs; skip descriptors with null buf addr */ 1461 trace_e1000e_rx_null_descriptor(); 1462 } 1463 desc_offset += desc_size; 1464 if (desc_offset >= total_size) { 1465 is_last = true; 1466 } 1467 1468 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1469 rss_info, written); 1470 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len); 1471 1472 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1473 1474 } while (desc_offset < total_size); 1475 1476 igb_update_rx_stats(core, size, total_size); 1477 } 1478 1479 static inline void 1480 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt) 1481 { 1482 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1483 1484 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1485 net_rx_pkt_fix_l4_csum(pkt); 1486 } 1487 } 1488 1489 ssize_t 1490 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt) 1491 { 1492 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL); 1493 } 1494 1495 static ssize_t 1496 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 1497 bool has_vnet, bool *external_tx) 1498 { 1499 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4); 1500 1501 uint16_t queues = 0; 1502 uint32_t n = 0; 1503 uint8_t min_buf[ETH_ZLEN]; 1504 struct iovec min_iov; 1505 struct eth_header *ehdr; 1506 uint8_t *filter_buf; 1507 size_t size, orig_size; 1508 size_t iov_ofs = 0; 1509 E1000E_RxRing rxr; 1510 E1000E_RSSInfo rss_info; 1511 size_t total_size; 1512 int i; 1513 1514 trace_e1000e_rx_receive_iov(iovcnt); 1515 1516 if (external_tx) { 1517 *external_tx = true; 1518 } 1519 1520 if (!e1000x_hw_rx_enabled(core->mac)) { 1521 return -1; 1522 } 1523 1524 /* Pull virtio header in */ 1525 if (has_vnet) { 1526 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1527 iov_ofs = sizeof(struct virtio_net_hdr); 1528 } else { 1529 net_rx_pkt_unset_vhdr(core->rx_pkt); 1530 } 1531 1532 filter_buf = iov->iov_base + iov_ofs; 1533 orig_size = iov_size(iov, iovcnt); 1534 size = orig_size - iov_ofs; 1535 1536 /* Pad to minimum Ethernet frame length */ 1537 if (size < sizeof(min_buf)) { 1538 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1539 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1540 e1000x_inc_reg_if_not_full(core->mac, RUC); 1541 min_iov.iov_base = filter_buf = min_buf; 1542 min_iov.iov_len = size = sizeof(min_buf); 1543 iovcnt = 1; 1544 iov = &min_iov; 1545 iov_ofs = 0; 1546 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1547 /* This is very unlikely, but may happen. */ 1548 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1549 filter_buf = min_buf; 1550 } 1551 1552 /* Discard oversized packets if !LPE and !SBP. */ 1553 if (e1000x_is_oversized(core->mac, size)) { 1554 return orig_size; 1555 } 1556 1557 ehdr = PKT_GET_ETH_HDR(filter_buf); 1558 net_rx_pkt_set_packet_type(core->rx_pkt, get_eth_packet_type(ehdr)); 1559 1560 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1561 e1000x_vlan_enabled(core->mac), 1562 core->mac[VET] & 0xffff); 1563 1564 queues = igb_receive_assign(core, ehdr, &rss_info, external_tx); 1565 if (!queues) { 1566 trace_e1000e_rx_flt_dropped(); 1567 return orig_size; 1568 } 1569 1570 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1571 e1000x_fcs_len(core->mac); 1572 1573 for (i = 0; i < IGB_NUM_QUEUES; i++) { 1574 if (!(queues & BIT(i))) { 1575 continue; 1576 } 1577 1578 igb_rx_ring_init(core, &rxr, i); 1579 1580 if (!igb_has_rxbufs(core, rxr.i, total_size)) { 1581 n |= E1000_ICS_RXO; 1582 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1583 continue; 1584 } 1585 1586 n |= E1000_ICR_RXDW; 1587 1588 igb_rx_fix_l4_csum(core, core->rx_pkt); 1589 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1590 1591 /* Check if receive descriptor minimum threshold hit */ 1592 if (igb_rx_descr_threshold_hit(core, rxr.i)) { 1593 n |= E1000_ICS_RXDMT0; 1594 } 1595 1596 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx); 1597 1598 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1599 } 1600 1601 trace_e1000e_rx_interrupt_set(n); 1602 igb_set_interrupt_cause(core, n); 1603 1604 return orig_size; 1605 } 1606 1607 static inline bool 1608 igb_have_autoneg(IGBCore *core) 1609 { 1610 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN; 1611 } 1612 1613 static void igb_update_flowctl_status(IGBCore *core) 1614 { 1615 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) { 1616 trace_e1000e_link_autoneg_flowctl(true); 1617 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1618 } else { 1619 trace_e1000e_link_autoneg_flowctl(false); 1620 } 1621 } 1622 1623 static inline void 1624 igb_link_down(IGBCore *core) 1625 { 1626 e1000x_update_regs_on_link_down(core->mac, core->phy); 1627 igb_update_flowctl_status(core); 1628 } 1629 1630 static inline void 1631 igb_set_phy_ctrl(IGBCore *core, uint16_t val) 1632 { 1633 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1634 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART); 1635 1636 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) { 1637 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer); 1638 } 1639 } 1640 1641 void igb_core_set_link_status(IGBCore *core) 1642 { 1643 NetClientState *nc = qemu_get_queue(core->owner_nic); 1644 uint32_t old_status = core->mac[STATUS]; 1645 1646 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1647 1648 if (nc->link_down) { 1649 e1000x_update_regs_on_link_down(core->mac, core->phy); 1650 } else { 1651 if (igb_have_autoneg(core) && 1652 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 1653 e1000x_restart_autoneg(core->mac, core->phy, 1654 core->autoneg_timer); 1655 } else { 1656 e1000x_update_regs_on_link_up(core->mac, core->phy); 1657 igb_start_recv(core); 1658 } 1659 } 1660 1661 if (core->mac[STATUS] != old_status) { 1662 igb_set_interrupt_cause(core, E1000_ICR_LSC); 1663 } 1664 } 1665 1666 static void 1667 igb_set_ctrl(IGBCore *core, int index, uint32_t val) 1668 { 1669 trace_e1000e_core_ctrl_write(index, val); 1670 1671 /* RST is self clearing */ 1672 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1673 core->mac[CTRL_DUP] = core->mac[CTRL]; 1674 1675 trace_e1000e_link_set_params( 1676 !!(val & E1000_CTRL_ASDE), 1677 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1678 !!(val & E1000_CTRL_FRCSPD), 1679 !!(val & E1000_CTRL_FRCDPX), 1680 !!(val & E1000_CTRL_RFCE), 1681 !!(val & E1000_CTRL_TFCE)); 1682 1683 if (val & E1000_CTRL_RST) { 1684 trace_e1000e_core_ctrl_sw_reset(); 1685 igb_reset(core, true); 1686 } 1687 1688 if (val & E1000_CTRL_PHY_RST) { 1689 trace_e1000e_core_ctrl_phy_reset(); 1690 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1691 } 1692 } 1693 1694 static void 1695 igb_set_rfctl(IGBCore *core, int index, uint32_t val) 1696 { 1697 trace_e1000e_rx_set_rfctl(val); 1698 1699 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1700 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1701 } 1702 1703 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1704 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1705 } 1706 1707 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1708 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1709 } 1710 1711 core->mac[RFCTL] = val; 1712 } 1713 1714 static void 1715 igb_calc_rxdesclen(IGBCore *core) 1716 { 1717 if (igb_rx_use_legacy_descriptor(core)) { 1718 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1719 } else { 1720 core->rx_desc_len = sizeof(union e1000_adv_rx_desc); 1721 } 1722 trace_e1000e_rx_desc_len(core->rx_desc_len); 1723 } 1724 1725 static void 1726 igb_set_rx_control(IGBCore *core, int index, uint32_t val) 1727 { 1728 core->mac[RCTL] = val; 1729 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1730 1731 if (val & E1000_RCTL_DTYP_MASK) { 1732 qemu_log_mask(LOG_GUEST_ERROR, 1733 "igb: RCTL.DTYP must be zero for compatibility"); 1734 } 1735 1736 if (val & E1000_RCTL_EN) { 1737 igb_calc_rxdesclen(core); 1738 igb_start_recv(core); 1739 } 1740 } 1741 1742 static inline void 1743 igb_clear_ims_bits(IGBCore *core, uint32_t bits) 1744 { 1745 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1746 core->mac[IMS] &= ~bits; 1747 } 1748 1749 static inline bool 1750 igb_postpone_interrupt(IGBIntrDelayTimer *timer) 1751 { 1752 if (timer->running) { 1753 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1754 1755 return true; 1756 } 1757 1758 if (timer->core->mac[timer->delay_reg] != 0) { 1759 igb_intrmgr_rearm_timer(timer); 1760 } 1761 1762 return false; 1763 } 1764 1765 static inline bool 1766 igb_eitr_should_postpone(IGBCore *core, int idx) 1767 { 1768 return igb_postpone_interrupt(&core->eitr[idx]); 1769 } 1770 1771 static void igb_send_msix(IGBCore *core) 1772 { 1773 uint32_t causes = core->mac[EICR] & core->mac[EIMS]; 1774 uint32_t effective_eiac; 1775 int vector; 1776 1777 for (vector = 0; vector < IGB_INTR_NUM; ++vector) { 1778 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) { 1779 1780 trace_e1000e_irq_msix_notify_vec(vector); 1781 igb_msix_notify(core, vector); 1782 1783 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]); 1784 effective_eiac = core->mac[EIAC] & BIT(vector); 1785 core->mac[EICR] &= ~effective_eiac; 1786 } 1787 } 1788 } 1789 1790 static inline void 1791 igb_fix_icr_asserted(IGBCore *core) 1792 { 1793 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 1794 if (core->mac[ICR]) { 1795 core->mac[ICR] |= E1000_ICR_ASSERTED; 1796 } 1797 1798 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 1799 } 1800 1801 static void 1802 igb_update_interrupt_state(IGBCore *core) 1803 { 1804 uint32_t icr; 1805 uint32_t causes; 1806 uint32_t int_alloc; 1807 1808 icr = core->mac[ICR] & core->mac[IMS]; 1809 1810 if (msix_enabled(core->owner)) { 1811 if (icr) { 1812 causes = 0; 1813 if (icr & E1000_ICR_DRSTA) { 1814 int_alloc = core->mac[IVAR_MISC] & 0xff; 1815 if (int_alloc & E1000_IVAR_VALID) { 1816 causes |= BIT(int_alloc & 0x1f); 1817 } 1818 } 1819 /* Check if other bits (excluding the TCP Timer) are enabled. */ 1820 if (icr & ~E1000_ICR_DRSTA) { 1821 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff; 1822 if (int_alloc & E1000_IVAR_VALID) { 1823 causes |= BIT(int_alloc & 0x1f); 1824 } 1825 trace_e1000e_irq_add_msi_other(core->mac[EICR]); 1826 } 1827 core->mac[EICR] |= causes; 1828 } 1829 1830 if ((core->mac[EICR] & core->mac[EIMS])) { 1831 igb_send_msix(core); 1832 } 1833 } else { 1834 igb_fix_icr_asserted(core); 1835 1836 if (icr) { 1837 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER; 1838 } else { 1839 core->mac[EICR] &= ~E1000_EICR_OTHER; 1840 } 1841 1842 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 1843 core->mac[ICR], core->mac[IMS]); 1844 1845 if (msi_enabled(core->owner)) { 1846 if (icr) { 1847 msi_notify(core->owner, 0); 1848 } 1849 } else { 1850 if (icr) { 1851 igb_raise_legacy_irq(core); 1852 } else { 1853 igb_lower_legacy_irq(core); 1854 } 1855 } 1856 } 1857 } 1858 1859 static void 1860 igb_set_interrupt_cause(IGBCore *core, uint32_t val) 1861 { 1862 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 1863 1864 core->mac[ICR] |= val; 1865 1866 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 1867 1868 igb_update_interrupt_state(core); 1869 } 1870 1871 static void igb_set_eics(IGBCore *core, int index, uint32_t val) 1872 { 1873 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1874 1875 trace_igb_irq_write_eics(val, msix); 1876 1877 core->mac[EICS] |= 1878 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1879 1880 /* 1881 * TODO: Move to igb_update_interrupt_state if EICS is modified in other 1882 * places. 1883 */ 1884 core->mac[EICR] = core->mac[EICS]; 1885 1886 igb_update_interrupt_state(core); 1887 } 1888 1889 static void igb_set_eims(IGBCore *core, int index, uint32_t val) 1890 { 1891 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1892 1893 trace_igb_irq_write_eims(val, msix); 1894 1895 core->mac[EIMS] |= 1896 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1897 1898 igb_update_interrupt_state(core); 1899 } 1900 1901 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) 1902 { 1903 uint32_t ent = core->mac[VTIVAR_MISC + vfn]; 1904 1905 if ((ent & E1000_IVAR_VALID)) { 1906 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM); 1907 igb_update_interrupt_state(core); 1908 } 1909 } 1910 1911 static void mailbox_interrupt_to_pf(IGBCore *core) 1912 { 1913 igb_set_interrupt_cause(core, E1000_ICR_VMMB); 1914 } 1915 1916 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val) 1917 { 1918 uint16_t vfn = index - P2VMAILBOX0; 1919 1920 trace_igb_set_pfmailbox(vfn, val); 1921 1922 if (val & E1000_P2VMAILBOX_STS) { 1923 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS; 1924 mailbox_interrupt_to_vf(core, vfn); 1925 } 1926 1927 if (val & E1000_P2VMAILBOX_ACK) { 1928 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK; 1929 mailbox_interrupt_to_vf(core, vfn); 1930 } 1931 1932 /* Buffer Taken by PF (can be set only if the VFU is cleared). */ 1933 if (val & E1000_P2VMAILBOX_PFU) { 1934 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) { 1935 core->mac[index] |= E1000_P2VMAILBOX_PFU; 1936 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU; 1937 } 1938 } else { 1939 core->mac[index] &= ~E1000_P2VMAILBOX_PFU; 1940 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU; 1941 } 1942 1943 if (val & E1000_P2VMAILBOX_RVFU) { 1944 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU; 1945 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) | 1946 (E1000_MBVFICR_VFREQ_VF1 << vfn)); 1947 } 1948 } 1949 1950 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) 1951 { 1952 uint16_t vfn = index - V2PMAILBOX0; 1953 1954 trace_igb_set_vfmailbox(vfn, val); 1955 1956 if (val & E1000_V2PMAILBOX_REQ) { 1957 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn; 1958 mailbox_interrupt_to_pf(core); 1959 } 1960 1961 if (val & E1000_V2PMAILBOX_ACK) { 1962 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn; 1963 mailbox_interrupt_to_pf(core); 1964 } 1965 1966 /* Buffer Taken by VF (can be set only if the PFU is cleared). */ 1967 if (val & E1000_V2PMAILBOX_VFU) { 1968 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) { 1969 core->mac[index] |= E1000_V2PMAILBOX_VFU; 1970 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU; 1971 } 1972 } else { 1973 core->mac[index] &= ~E1000_V2PMAILBOX_VFU; 1974 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU; 1975 } 1976 } 1977 1978 static void igb_vf_reset(IGBCore *core, uint16_t vfn) 1979 { 1980 /* disable Rx and Tx for the VF*/ 1981 core->mac[VFTE] &= ~BIT(vfn); 1982 core->mac[VFRE] &= ~BIT(vfn); 1983 /* indicate VF reset to PF */ 1984 core->mac[VFLRE] |= BIT(vfn); 1985 /* VFLRE and mailbox use the same interrupt cause */ 1986 mailbox_interrupt_to_pf(core); 1987 } 1988 1989 static void igb_w1c(IGBCore *core, int index, uint32_t val) 1990 { 1991 core->mac[index] &= ~val; 1992 } 1993 1994 static void igb_set_eimc(IGBCore *core, int index, uint32_t val) 1995 { 1996 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1997 1998 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */ 1999 core->mac[EIMS] &= 2000 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2001 2002 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix); 2003 igb_update_interrupt_state(core); 2004 } 2005 2006 static void igb_set_eiac(IGBCore *core, int index, uint32_t val) 2007 { 2008 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2009 2010 if (msix) { 2011 trace_igb_irq_write_eiac(val); 2012 2013 /* 2014 * TODO: When using IOV, the bits that correspond to MSI-X vectors 2015 * that are assigned to a VF are read-only. 2016 */ 2017 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK); 2018 } 2019 } 2020 2021 static void igb_set_eiam(IGBCore *core, int index, uint32_t val) 2022 { 2023 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2024 2025 /* 2026 * TODO: When using IOV, the bits that correspond to MSI-X vectors that 2027 * are assigned to a VF are read-only. 2028 */ 2029 core->mac[EIAM] |= 2030 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2031 2032 trace_igb_irq_write_eiam(val, msix); 2033 } 2034 2035 static void igb_set_eicr(IGBCore *core, int index, uint32_t val) 2036 { 2037 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2038 2039 /* 2040 * TODO: In IOV mode, only bit zero of this vector is available for the PF 2041 * function. 2042 */ 2043 core->mac[EICR] &= 2044 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2045 2046 trace_igb_irq_write_eicr(val, msix); 2047 igb_update_interrupt_state(core); 2048 } 2049 2050 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val) 2051 { 2052 uint16_t vfn; 2053 2054 if (val & E1000_CTRL_RST) { 2055 vfn = (index - PVTCTRL0) / 0x40; 2056 igb_vf_reset(core, vfn); 2057 } 2058 } 2059 2060 static void igb_set_vteics(IGBCore *core, int index, uint32_t val) 2061 { 2062 uint16_t vfn = (index - PVTEICS0) / 0x40; 2063 2064 core->mac[index] = val; 2065 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2066 } 2067 2068 static void igb_set_vteims(IGBCore *core, int index, uint32_t val) 2069 { 2070 uint16_t vfn = (index - PVTEIMS0) / 0x40; 2071 2072 core->mac[index] = val; 2073 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2074 } 2075 2076 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val) 2077 { 2078 uint16_t vfn = (index - PVTEIMC0) / 0x40; 2079 2080 core->mac[index] = val; 2081 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2082 } 2083 2084 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val) 2085 { 2086 uint16_t vfn = (index - PVTEIAC0) / 0x40; 2087 2088 core->mac[index] = val; 2089 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2090 } 2091 2092 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val) 2093 { 2094 uint16_t vfn = (index - PVTEIAM0) / 0x40; 2095 2096 core->mac[index] = val; 2097 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2098 } 2099 2100 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val) 2101 { 2102 uint16_t vfn = (index - PVTEICR0) / 0x40; 2103 2104 core->mac[index] = val; 2105 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2106 } 2107 2108 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val) 2109 { 2110 uint16_t vfn = (index - VTIVAR); 2111 uint16_t qn = vfn; 2112 uint8_t ent; 2113 int n; 2114 2115 core->mac[index] = val; 2116 2117 /* Get assigned vector associated with queue Rx#0. */ 2118 if ((val & E1000_IVAR_VALID)) { 2119 n = igb_ivar_entry_rx(qn); 2120 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7))); 2121 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2122 } 2123 2124 /* Get assigned vector associated with queue Tx#0 */ 2125 ent = val >> 8; 2126 if ((ent & E1000_IVAR_VALID)) { 2127 n = igb_ivar_entry_tx(qn); 2128 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7))); 2129 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2130 } 2131 2132 /* 2133 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now. 2134 */ 2135 } 2136 2137 static inline void 2138 igb_autoneg_timer(void *opaque) 2139 { 2140 IGBCore *core = opaque; 2141 if (!qemu_get_queue(core->owner_nic)->link_down) { 2142 e1000x_update_regs_on_autoneg_done(core->mac, core->phy); 2143 igb_start_recv(core); 2144 2145 igb_update_flowctl_status(core); 2146 /* signal link status change to the guest */ 2147 igb_set_interrupt_cause(core, E1000_ICR_LSC); 2148 } 2149 } 2150 2151 static inline uint16_t 2152 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2153 { 2154 uint16_t index = (addr & 0x1ffff) >> 2; 2155 return index + (mac_reg_access[index] & 0xfffe); 2156 } 2157 2158 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = { 2159 [MII_BMCR] = PHY_RW, 2160 [MII_BMSR] = PHY_R, 2161 [MII_PHYID1] = PHY_R, 2162 [MII_PHYID2] = PHY_R, 2163 [MII_ANAR] = PHY_RW, 2164 [MII_ANLPAR] = PHY_R, 2165 [MII_ANER] = PHY_R, 2166 [MII_ANNP] = PHY_RW, 2167 [MII_ANLPRNP] = PHY_R, 2168 [MII_CTRL1000] = PHY_RW, 2169 [MII_STAT1000] = PHY_R, 2170 [MII_EXTSTAT] = PHY_R, 2171 2172 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW, 2173 [IGP01E1000_PHY_PORT_STATUS] = PHY_R, 2174 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW, 2175 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R, 2176 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW, 2177 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W 2178 }; 2179 2180 static void 2181 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data) 2182 { 2183 assert(addr <= MAX_PHY_REG_ADDRESS); 2184 2185 if (addr == MII_BMCR) { 2186 igb_set_phy_ctrl(core, data); 2187 } else { 2188 core->phy[addr] = data; 2189 } 2190 } 2191 2192 static void 2193 igb_set_mdic(IGBCore *core, int index, uint32_t val) 2194 { 2195 uint32_t data = val & E1000_MDIC_DATA_MASK; 2196 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2197 2198 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2199 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2200 } else if (val & E1000_MDIC_OP_READ) { 2201 if (!(igb_phy_regcap[addr] & PHY_R)) { 2202 trace_igb_core_mdic_read_unhandled(addr); 2203 val |= E1000_MDIC_ERROR; 2204 } else { 2205 val = (val ^ data) | core->phy[addr]; 2206 trace_igb_core_mdic_read(addr, val); 2207 } 2208 } else if (val & E1000_MDIC_OP_WRITE) { 2209 if (!(igb_phy_regcap[addr] & PHY_W)) { 2210 trace_igb_core_mdic_write_unhandled(addr); 2211 val |= E1000_MDIC_ERROR; 2212 } else { 2213 trace_igb_core_mdic_write(addr, data); 2214 igb_phy_reg_write(core, addr, data); 2215 } 2216 } 2217 core->mac[MDIC] = val | E1000_MDIC_READY; 2218 2219 if (val & E1000_MDIC_INT_EN) { 2220 igb_set_interrupt_cause(core, E1000_ICR_MDAC); 2221 } 2222 } 2223 2224 static void 2225 igb_set_rdt(IGBCore *core, int index, uint32_t val) 2226 { 2227 core->mac[index] = val & 0xffff; 2228 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val); 2229 igb_start_recv(core); 2230 } 2231 2232 static void 2233 igb_set_status(IGBCore *core, int index, uint32_t val) 2234 { 2235 if ((val & E1000_STATUS_PHYRA) == 0) { 2236 core->mac[index] &= ~E1000_STATUS_PHYRA; 2237 } 2238 } 2239 2240 static void 2241 igb_set_ctrlext(IGBCore *core, int index, uint32_t val) 2242 { 2243 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2244 !!(val & E1000_CTRL_EXT_SPD_BYPS), 2245 !!(val & E1000_CTRL_EXT_PFRSTD)); 2246 2247 /* Zero self-clearing bits */ 2248 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2249 core->mac[CTRL_EXT] = val; 2250 2251 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) { 2252 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 2253 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; 2254 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD; 2255 } 2256 } 2257 } 2258 2259 static void 2260 igb_set_pbaclr(IGBCore *core, int index, uint32_t val) 2261 { 2262 int i; 2263 2264 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2265 2266 if (!msix_enabled(core->owner)) { 2267 return; 2268 } 2269 2270 for (i = 0; i < IGB_INTR_NUM; i++) { 2271 if (core->mac[PBACLR] & BIT(i)) { 2272 msix_clr_pending(core->owner, i); 2273 } 2274 } 2275 } 2276 2277 static void 2278 igb_set_fcrth(IGBCore *core, int index, uint32_t val) 2279 { 2280 core->mac[FCRTH] = val & 0xFFF8; 2281 } 2282 2283 static void 2284 igb_set_fcrtl(IGBCore *core, int index, uint32_t val) 2285 { 2286 core->mac[FCRTL] = val & 0x8000FFF8; 2287 } 2288 2289 #define IGB_LOW_BITS_SET_FUNC(num) \ 2290 static void \ 2291 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \ 2292 { \ 2293 core->mac[index] = val & (BIT(num) - 1); \ 2294 } 2295 2296 IGB_LOW_BITS_SET_FUNC(4) 2297 IGB_LOW_BITS_SET_FUNC(13) 2298 IGB_LOW_BITS_SET_FUNC(16) 2299 2300 static void 2301 igb_set_dlen(IGBCore *core, int index, uint32_t val) 2302 { 2303 core->mac[index] = val & 0xffff0; 2304 } 2305 2306 static void 2307 igb_set_dbal(IGBCore *core, int index, uint32_t val) 2308 { 2309 core->mac[index] = val & E1000_XDBAL_MASK; 2310 } 2311 2312 static void 2313 igb_set_tdt(IGBCore *core, int index, uint32_t val) 2314 { 2315 IGB_TxRing txr; 2316 int qn = igb_mq_queue_idx(TDT0, index); 2317 2318 core->mac[index] = val & 0xffff; 2319 2320 igb_tx_ring_init(core, &txr, qn); 2321 igb_start_xmit(core, &txr); 2322 } 2323 2324 static void 2325 igb_set_ics(IGBCore *core, int index, uint32_t val) 2326 { 2327 trace_e1000e_irq_write_ics(val); 2328 igb_set_interrupt_cause(core, val); 2329 } 2330 2331 static void 2332 igb_set_imc(IGBCore *core, int index, uint32_t val) 2333 { 2334 trace_e1000e_irq_ims_clear_set_imc(val); 2335 igb_clear_ims_bits(core, val); 2336 igb_update_interrupt_state(core); 2337 } 2338 2339 static void 2340 igb_set_ims(IGBCore *core, int index, uint32_t val) 2341 { 2342 uint32_t valid_val = val & 0x77D4FBFD; 2343 2344 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2345 core->mac[IMS] |= valid_val; 2346 igb_update_interrupt_state(core); 2347 } 2348 2349 static void igb_commit_icr(IGBCore *core) 2350 { 2351 /* 2352 * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at 2353 * least one bit is set in the IMS and there is a true interrupt as 2354 * reflected in ICR.INTA. 2355 */ 2356 if ((core->mac[GPIE] & E1000_GPIE_NSICR) || 2357 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) { 2358 igb_set_ims(core, IMS, core->mac[IAM]); 2359 } else { 2360 igb_update_interrupt_state(core); 2361 } 2362 } 2363 2364 static void igb_set_icr(IGBCore *core, int index, uint32_t val) 2365 { 2366 uint32_t icr = core->mac[ICR] & ~val; 2367 2368 trace_igb_irq_icr_write(val, core->mac[ICR], icr); 2369 core->mac[ICR] = icr; 2370 igb_commit_icr(core); 2371 } 2372 2373 static uint32_t 2374 igb_mac_readreg(IGBCore *core, int index) 2375 { 2376 return core->mac[index]; 2377 } 2378 2379 static uint32_t 2380 igb_mac_ics_read(IGBCore *core, int index) 2381 { 2382 trace_e1000e_irq_read_ics(core->mac[ICS]); 2383 return core->mac[ICS]; 2384 } 2385 2386 static uint32_t 2387 igb_mac_ims_read(IGBCore *core, int index) 2388 { 2389 trace_e1000e_irq_read_ims(core->mac[IMS]); 2390 return core->mac[IMS]; 2391 } 2392 2393 static uint32_t 2394 igb_mac_swsm_read(IGBCore *core, int index) 2395 { 2396 uint32_t val = core->mac[SWSM]; 2397 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2398 return val; 2399 } 2400 2401 static uint32_t 2402 igb_mac_eitr_read(IGBCore *core, int index) 2403 { 2404 return core->eitr_guest_value[index - EITR0]; 2405 } 2406 2407 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index) 2408 { 2409 uint32_t val = core->mac[index]; 2410 2411 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK | 2412 E1000_V2PMAILBOX_RSTD); 2413 2414 return val; 2415 } 2416 2417 static uint32_t 2418 igb_mac_icr_read(IGBCore *core, int index) 2419 { 2420 uint32_t ret = core->mac[ICR]; 2421 trace_e1000e_irq_icr_read_entry(ret); 2422 2423 if (core->mac[GPIE] & E1000_GPIE_NSICR) { 2424 trace_igb_irq_icr_clear_gpie_nsicr(); 2425 core->mac[ICR] = 0; 2426 } else if (core->mac[IMS] == 0) { 2427 trace_e1000e_irq_icr_clear_zero_ims(); 2428 core->mac[ICR] = 0; 2429 } else if (!msix_enabled(core->owner)) { 2430 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2431 core->mac[ICR] = 0; 2432 } 2433 2434 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2435 igb_commit_icr(core); 2436 return ret; 2437 } 2438 2439 static uint32_t 2440 igb_mac_read_clr4(IGBCore *core, int index) 2441 { 2442 uint32_t ret = core->mac[index]; 2443 2444 core->mac[index] = 0; 2445 return ret; 2446 } 2447 2448 static uint32_t 2449 igb_mac_read_clr8(IGBCore *core, int index) 2450 { 2451 uint32_t ret = core->mac[index]; 2452 2453 core->mac[index] = 0; 2454 core->mac[index - 1] = 0; 2455 return ret; 2456 } 2457 2458 static uint32_t 2459 igb_get_ctrl(IGBCore *core, int index) 2460 { 2461 uint32_t val = core->mac[CTRL]; 2462 2463 trace_e1000e_link_read_params( 2464 !!(val & E1000_CTRL_ASDE), 2465 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2466 !!(val & E1000_CTRL_FRCSPD), 2467 !!(val & E1000_CTRL_FRCDPX), 2468 !!(val & E1000_CTRL_RFCE), 2469 !!(val & E1000_CTRL_TFCE)); 2470 2471 return val; 2472 } 2473 2474 static uint32_t igb_get_status(IGBCore *core, int index) 2475 { 2476 uint32_t res = core->mac[STATUS]; 2477 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner); 2478 2479 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2480 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2481 } else { 2482 res |= E1000_STATUS_FD; 2483 } 2484 2485 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2486 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2487 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2488 case E1000_CTRL_SPD_10: 2489 res |= E1000_STATUS_SPEED_10; 2490 break; 2491 case E1000_CTRL_SPD_100: 2492 res |= E1000_STATUS_SPEED_100; 2493 break; 2494 case E1000_CTRL_SPD_1000: 2495 default: 2496 res |= E1000_STATUS_SPEED_1000; 2497 break; 2498 } 2499 } else { 2500 res |= E1000_STATUS_SPEED_1000; 2501 } 2502 2503 if (num_vfs) { 2504 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT; 2505 res |= E1000_STATUS_IOV_MODE; 2506 } 2507 2508 /* 2509 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is 2510 * left set after E1000_CTRL_LRST is set. 2511 */ 2512 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) && 2513 !(core->mac[CTRL] & E1000_CTRL_LRST)) { 2514 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2515 } 2516 2517 return res; 2518 } 2519 2520 static void 2521 igb_mac_writereg(IGBCore *core, int index, uint32_t val) 2522 { 2523 core->mac[index] = val; 2524 } 2525 2526 static void 2527 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val) 2528 { 2529 uint32_t macaddr[2]; 2530 2531 core->mac[index] = val; 2532 2533 macaddr[0] = cpu_to_le32(core->mac[RA]); 2534 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2535 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2536 (uint8_t *) macaddr); 2537 2538 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2539 } 2540 2541 static void 2542 igb_set_eecd(IGBCore *core, int index, uint32_t val) 2543 { 2544 static const uint32_t ro_bits = E1000_EECD_PRES | 2545 E1000_EECD_AUTO_RD | 2546 E1000_EECD_SIZE_EX_MASK; 2547 2548 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2549 } 2550 2551 static void 2552 igb_set_eerd(IGBCore *core, int index, uint32_t val) 2553 { 2554 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2555 uint32_t flags = 0; 2556 uint32_t data = 0; 2557 2558 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2559 data = core->eeprom[addr]; 2560 flags = E1000_EERW_DONE; 2561 } 2562 2563 core->mac[EERD] = flags | 2564 (addr << E1000_EERW_ADDR_SHIFT) | 2565 (data << E1000_EERW_DATA_SHIFT); 2566 } 2567 2568 static void 2569 igb_set_eitr(IGBCore *core, int index, uint32_t val) 2570 { 2571 uint32_t eitr_num = index - EITR0; 2572 2573 trace_igb_irq_eitr_set(eitr_num, val); 2574 2575 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR; 2576 core->mac[index] = val & 0x7FFE; 2577 } 2578 2579 static void 2580 igb_update_rx_offloads(IGBCore *core) 2581 { 2582 int cso_state = igb_rx_l4_cso_enabled(core); 2583 2584 trace_e1000e_rx_set_cso(cso_state); 2585 2586 if (core->has_vnet) { 2587 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2588 cso_state, 0, 0, 0, 0); 2589 } 2590 } 2591 2592 static void 2593 igb_set_rxcsum(IGBCore *core, int index, uint32_t val) 2594 { 2595 core->mac[RXCSUM] = val; 2596 igb_update_rx_offloads(core); 2597 } 2598 2599 static void 2600 igb_set_gcr(IGBCore *core, int index, uint32_t val) 2601 { 2602 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2603 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2604 } 2605 2606 static uint32_t igb_get_systiml(IGBCore *core, int index) 2607 { 2608 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2609 return core->mac[SYSTIML]; 2610 } 2611 2612 static uint32_t igb_get_rxsatrh(IGBCore *core, int index) 2613 { 2614 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2615 return core->mac[RXSATRH]; 2616 } 2617 2618 static uint32_t igb_get_txstmph(IGBCore *core, int index) 2619 { 2620 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2621 return core->mac[TXSTMPH]; 2622 } 2623 2624 static void igb_set_timinca(IGBCore *core, int index, uint32_t val) 2625 { 2626 e1000x_set_timinca(core->mac, &core->timadj, val); 2627 } 2628 2629 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val) 2630 { 2631 core->mac[TIMADJH] = val; 2632 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2633 } 2634 2635 #define igb_getreg(x) [x] = igb_mac_readreg 2636 typedef uint32_t (*readops)(IGBCore *, int); 2637 static const readops igb_macreg_readops[] = { 2638 igb_getreg(WUFC), 2639 igb_getreg(MANC), 2640 igb_getreg(TOTL), 2641 igb_getreg(RDT0), 2642 igb_getreg(RDT1), 2643 igb_getreg(RDT2), 2644 igb_getreg(RDT3), 2645 igb_getreg(RDT4), 2646 igb_getreg(RDT5), 2647 igb_getreg(RDT6), 2648 igb_getreg(RDT7), 2649 igb_getreg(RDT8), 2650 igb_getreg(RDT9), 2651 igb_getreg(RDT10), 2652 igb_getreg(RDT11), 2653 igb_getreg(RDT12), 2654 igb_getreg(RDT13), 2655 igb_getreg(RDT14), 2656 igb_getreg(RDT15), 2657 igb_getreg(RDBAH0), 2658 igb_getreg(RDBAH1), 2659 igb_getreg(RDBAH2), 2660 igb_getreg(RDBAH3), 2661 igb_getreg(RDBAH4), 2662 igb_getreg(RDBAH5), 2663 igb_getreg(RDBAH6), 2664 igb_getreg(RDBAH7), 2665 igb_getreg(RDBAH8), 2666 igb_getreg(RDBAH9), 2667 igb_getreg(RDBAH10), 2668 igb_getreg(RDBAH11), 2669 igb_getreg(RDBAH12), 2670 igb_getreg(RDBAH13), 2671 igb_getreg(RDBAH14), 2672 igb_getreg(RDBAH15), 2673 igb_getreg(TDBAL0), 2674 igb_getreg(TDBAL1), 2675 igb_getreg(TDBAL2), 2676 igb_getreg(TDBAL3), 2677 igb_getreg(TDBAL4), 2678 igb_getreg(TDBAL5), 2679 igb_getreg(TDBAL6), 2680 igb_getreg(TDBAL7), 2681 igb_getreg(TDBAL8), 2682 igb_getreg(TDBAL9), 2683 igb_getreg(TDBAL10), 2684 igb_getreg(TDBAL11), 2685 igb_getreg(TDBAL12), 2686 igb_getreg(TDBAL13), 2687 igb_getreg(TDBAL14), 2688 igb_getreg(TDBAL15), 2689 igb_getreg(RDLEN0), 2690 igb_getreg(RDLEN1), 2691 igb_getreg(RDLEN2), 2692 igb_getreg(RDLEN3), 2693 igb_getreg(RDLEN4), 2694 igb_getreg(RDLEN5), 2695 igb_getreg(RDLEN6), 2696 igb_getreg(RDLEN7), 2697 igb_getreg(RDLEN8), 2698 igb_getreg(RDLEN9), 2699 igb_getreg(RDLEN10), 2700 igb_getreg(RDLEN11), 2701 igb_getreg(RDLEN12), 2702 igb_getreg(RDLEN13), 2703 igb_getreg(RDLEN14), 2704 igb_getreg(RDLEN15), 2705 igb_getreg(SRRCTL0), 2706 igb_getreg(SRRCTL1), 2707 igb_getreg(SRRCTL2), 2708 igb_getreg(SRRCTL3), 2709 igb_getreg(SRRCTL4), 2710 igb_getreg(SRRCTL5), 2711 igb_getreg(SRRCTL6), 2712 igb_getreg(SRRCTL7), 2713 igb_getreg(SRRCTL8), 2714 igb_getreg(SRRCTL9), 2715 igb_getreg(SRRCTL10), 2716 igb_getreg(SRRCTL11), 2717 igb_getreg(SRRCTL12), 2718 igb_getreg(SRRCTL13), 2719 igb_getreg(SRRCTL14), 2720 igb_getreg(SRRCTL15), 2721 igb_getreg(LATECOL), 2722 igb_getreg(XONTXC), 2723 igb_getreg(TDFH), 2724 igb_getreg(TDFT), 2725 igb_getreg(TDFHS), 2726 igb_getreg(TDFTS), 2727 igb_getreg(TDFPC), 2728 igb_getreg(WUS), 2729 igb_getreg(RDFH), 2730 igb_getreg(RDFT), 2731 igb_getreg(RDFHS), 2732 igb_getreg(RDFTS), 2733 igb_getreg(RDFPC), 2734 igb_getreg(GORCL), 2735 igb_getreg(MGTPRC), 2736 igb_getreg(EERD), 2737 igb_getreg(EIAC), 2738 igb_getreg(MANC2H), 2739 igb_getreg(RXCSUM), 2740 igb_getreg(GSCL_3), 2741 igb_getreg(GSCN_2), 2742 igb_getreg(FCAH), 2743 igb_getreg(FCRTH), 2744 igb_getreg(FLOP), 2745 igb_getreg(RXSTMPH), 2746 igb_getreg(TXSTMPL), 2747 igb_getreg(TIMADJL), 2748 igb_getreg(RDH0), 2749 igb_getreg(RDH1), 2750 igb_getreg(RDH2), 2751 igb_getreg(RDH3), 2752 igb_getreg(RDH4), 2753 igb_getreg(RDH5), 2754 igb_getreg(RDH6), 2755 igb_getreg(RDH7), 2756 igb_getreg(RDH8), 2757 igb_getreg(RDH9), 2758 igb_getreg(RDH10), 2759 igb_getreg(RDH11), 2760 igb_getreg(RDH12), 2761 igb_getreg(RDH13), 2762 igb_getreg(RDH14), 2763 igb_getreg(RDH15), 2764 igb_getreg(TDT0), 2765 igb_getreg(TDT1), 2766 igb_getreg(TDT2), 2767 igb_getreg(TDT3), 2768 igb_getreg(TDT4), 2769 igb_getreg(TDT5), 2770 igb_getreg(TDT6), 2771 igb_getreg(TDT7), 2772 igb_getreg(TDT8), 2773 igb_getreg(TDT9), 2774 igb_getreg(TDT10), 2775 igb_getreg(TDT11), 2776 igb_getreg(TDT12), 2777 igb_getreg(TDT13), 2778 igb_getreg(TDT14), 2779 igb_getreg(TDT15), 2780 igb_getreg(TNCRS), 2781 igb_getreg(RJC), 2782 igb_getreg(IAM), 2783 igb_getreg(GSCL_2), 2784 igb_getreg(TIPG), 2785 igb_getreg(FLMNGCTL), 2786 igb_getreg(FLMNGCNT), 2787 igb_getreg(TSYNCTXCTL), 2788 igb_getreg(EEMNGDATA), 2789 igb_getreg(CTRL_EXT), 2790 igb_getreg(SYSTIMH), 2791 igb_getreg(EEMNGCTL), 2792 igb_getreg(FLMNGDATA), 2793 igb_getreg(TSYNCRXCTL), 2794 igb_getreg(LEDCTL), 2795 igb_getreg(TCTL), 2796 igb_getreg(TCTL_EXT), 2797 igb_getreg(DTXCTL), 2798 igb_getreg(RXPBS), 2799 igb_getreg(TDH0), 2800 igb_getreg(TDH1), 2801 igb_getreg(TDH2), 2802 igb_getreg(TDH3), 2803 igb_getreg(TDH4), 2804 igb_getreg(TDH5), 2805 igb_getreg(TDH6), 2806 igb_getreg(TDH7), 2807 igb_getreg(TDH8), 2808 igb_getreg(TDH9), 2809 igb_getreg(TDH10), 2810 igb_getreg(TDH11), 2811 igb_getreg(TDH12), 2812 igb_getreg(TDH13), 2813 igb_getreg(TDH14), 2814 igb_getreg(TDH15), 2815 igb_getreg(ECOL), 2816 igb_getreg(DC), 2817 igb_getreg(RLEC), 2818 igb_getreg(XOFFTXC), 2819 igb_getreg(RFC), 2820 igb_getreg(RNBC), 2821 igb_getreg(MGTPTC), 2822 igb_getreg(TIMINCA), 2823 igb_getreg(FACTPS), 2824 igb_getreg(GSCL_1), 2825 igb_getreg(GSCN_0), 2826 igb_getreg(PBACLR), 2827 igb_getreg(FCTTV), 2828 igb_getreg(RXSATRL), 2829 igb_getreg(TORL), 2830 igb_getreg(TDLEN0), 2831 igb_getreg(TDLEN1), 2832 igb_getreg(TDLEN2), 2833 igb_getreg(TDLEN3), 2834 igb_getreg(TDLEN4), 2835 igb_getreg(TDLEN5), 2836 igb_getreg(TDLEN6), 2837 igb_getreg(TDLEN7), 2838 igb_getreg(TDLEN8), 2839 igb_getreg(TDLEN9), 2840 igb_getreg(TDLEN10), 2841 igb_getreg(TDLEN11), 2842 igb_getreg(TDLEN12), 2843 igb_getreg(TDLEN13), 2844 igb_getreg(TDLEN14), 2845 igb_getreg(TDLEN15), 2846 igb_getreg(MCC), 2847 igb_getreg(WUC), 2848 igb_getreg(EECD), 2849 igb_getreg(FCRTV), 2850 igb_getreg(TXDCTL0), 2851 igb_getreg(TXDCTL1), 2852 igb_getreg(TXDCTL2), 2853 igb_getreg(TXDCTL3), 2854 igb_getreg(TXDCTL4), 2855 igb_getreg(TXDCTL5), 2856 igb_getreg(TXDCTL6), 2857 igb_getreg(TXDCTL7), 2858 igb_getreg(TXDCTL8), 2859 igb_getreg(TXDCTL9), 2860 igb_getreg(TXDCTL10), 2861 igb_getreg(TXDCTL11), 2862 igb_getreg(TXDCTL12), 2863 igb_getreg(TXDCTL13), 2864 igb_getreg(TXDCTL14), 2865 igb_getreg(TXDCTL15), 2866 igb_getreg(TXCTL0), 2867 igb_getreg(TXCTL1), 2868 igb_getreg(TXCTL2), 2869 igb_getreg(TXCTL3), 2870 igb_getreg(TXCTL4), 2871 igb_getreg(TXCTL5), 2872 igb_getreg(TXCTL6), 2873 igb_getreg(TXCTL7), 2874 igb_getreg(TXCTL8), 2875 igb_getreg(TXCTL9), 2876 igb_getreg(TXCTL10), 2877 igb_getreg(TXCTL11), 2878 igb_getreg(TXCTL12), 2879 igb_getreg(TXCTL13), 2880 igb_getreg(TXCTL14), 2881 igb_getreg(TXCTL15), 2882 igb_getreg(TDWBAL0), 2883 igb_getreg(TDWBAL1), 2884 igb_getreg(TDWBAL2), 2885 igb_getreg(TDWBAL3), 2886 igb_getreg(TDWBAL4), 2887 igb_getreg(TDWBAL5), 2888 igb_getreg(TDWBAL6), 2889 igb_getreg(TDWBAL7), 2890 igb_getreg(TDWBAL8), 2891 igb_getreg(TDWBAL9), 2892 igb_getreg(TDWBAL10), 2893 igb_getreg(TDWBAL11), 2894 igb_getreg(TDWBAL12), 2895 igb_getreg(TDWBAL13), 2896 igb_getreg(TDWBAL14), 2897 igb_getreg(TDWBAL15), 2898 igb_getreg(TDWBAH0), 2899 igb_getreg(TDWBAH1), 2900 igb_getreg(TDWBAH2), 2901 igb_getreg(TDWBAH3), 2902 igb_getreg(TDWBAH4), 2903 igb_getreg(TDWBAH5), 2904 igb_getreg(TDWBAH6), 2905 igb_getreg(TDWBAH7), 2906 igb_getreg(TDWBAH8), 2907 igb_getreg(TDWBAH9), 2908 igb_getreg(TDWBAH10), 2909 igb_getreg(TDWBAH11), 2910 igb_getreg(TDWBAH12), 2911 igb_getreg(TDWBAH13), 2912 igb_getreg(TDWBAH14), 2913 igb_getreg(TDWBAH15), 2914 igb_getreg(PVTCTRL0), 2915 igb_getreg(PVTCTRL1), 2916 igb_getreg(PVTCTRL2), 2917 igb_getreg(PVTCTRL3), 2918 igb_getreg(PVTCTRL4), 2919 igb_getreg(PVTCTRL5), 2920 igb_getreg(PVTCTRL6), 2921 igb_getreg(PVTCTRL7), 2922 igb_getreg(PVTEIMS0), 2923 igb_getreg(PVTEIMS1), 2924 igb_getreg(PVTEIMS2), 2925 igb_getreg(PVTEIMS3), 2926 igb_getreg(PVTEIMS4), 2927 igb_getreg(PVTEIMS5), 2928 igb_getreg(PVTEIMS6), 2929 igb_getreg(PVTEIMS7), 2930 igb_getreg(PVTEIAC0), 2931 igb_getreg(PVTEIAC1), 2932 igb_getreg(PVTEIAC2), 2933 igb_getreg(PVTEIAC3), 2934 igb_getreg(PVTEIAC4), 2935 igb_getreg(PVTEIAC5), 2936 igb_getreg(PVTEIAC6), 2937 igb_getreg(PVTEIAC7), 2938 igb_getreg(PVTEIAM0), 2939 igb_getreg(PVTEIAM1), 2940 igb_getreg(PVTEIAM2), 2941 igb_getreg(PVTEIAM3), 2942 igb_getreg(PVTEIAM4), 2943 igb_getreg(PVTEIAM5), 2944 igb_getreg(PVTEIAM6), 2945 igb_getreg(PVTEIAM7), 2946 igb_getreg(PVFGPRC0), 2947 igb_getreg(PVFGPRC1), 2948 igb_getreg(PVFGPRC2), 2949 igb_getreg(PVFGPRC3), 2950 igb_getreg(PVFGPRC4), 2951 igb_getreg(PVFGPRC5), 2952 igb_getreg(PVFGPRC6), 2953 igb_getreg(PVFGPRC7), 2954 igb_getreg(PVFGPTC0), 2955 igb_getreg(PVFGPTC1), 2956 igb_getreg(PVFGPTC2), 2957 igb_getreg(PVFGPTC3), 2958 igb_getreg(PVFGPTC4), 2959 igb_getreg(PVFGPTC5), 2960 igb_getreg(PVFGPTC6), 2961 igb_getreg(PVFGPTC7), 2962 igb_getreg(PVFGORC0), 2963 igb_getreg(PVFGORC1), 2964 igb_getreg(PVFGORC2), 2965 igb_getreg(PVFGORC3), 2966 igb_getreg(PVFGORC4), 2967 igb_getreg(PVFGORC5), 2968 igb_getreg(PVFGORC6), 2969 igb_getreg(PVFGORC7), 2970 igb_getreg(PVFGOTC0), 2971 igb_getreg(PVFGOTC1), 2972 igb_getreg(PVFGOTC2), 2973 igb_getreg(PVFGOTC3), 2974 igb_getreg(PVFGOTC4), 2975 igb_getreg(PVFGOTC5), 2976 igb_getreg(PVFGOTC6), 2977 igb_getreg(PVFGOTC7), 2978 igb_getreg(PVFMPRC0), 2979 igb_getreg(PVFMPRC1), 2980 igb_getreg(PVFMPRC2), 2981 igb_getreg(PVFMPRC3), 2982 igb_getreg(PVFMPRC4), 2983 igb_getreg(PVFMPRC5), 2984 igb_getreg(PVFMPRC6), 2985 igb_getreg(PVFMPRC7), 2986 igb_getreg(PVFGPRLBC0), 2987 igb_getreg(PVFGPRLBC1), 2988 igb_getreg(PVFGPRLBC2), 2989 igb_getreg(PVFGPRLBC3), 2990 igb_getreg(PVFGPRLBC4), 2991 igb_getreg(PVFGPRLBC5), 2992 igb_getreg(PVFGPRLBC6), 2993 igb_getreg(PVFGPRLBC7), 2994 igb_getreg(PVFGPTLBC0), 2995 igb_getreg(PVFGPTLBC1), 2996 igb_getreg(PVFGPTLBC2), 2997 igb_getreg(PVFGPTLBC3), 2998 igb_getreg(PVFGPTLBC4), 2999 igb_getreg(PVFGPTLBC5), 3000 igb_getreg(PVFGPTLBC6), 3001 igb_getreg(PVFGPTLBC7), 3002 igb_getreg(PVFGORLBC0), 3003 igb_getreg(PVFGORLBC1), 3004 igb_getreg(PVFGORLBC2), 3005 igb_getreg(PVFGORLBC3), 3006 igb_getreg(PVFGORLBC4), 3007 igb_getreg(PVFGORLBC5), 3008 igb_getreg(PVFGORLBC6), 3009 igb_getreg(PVFGORLBC7), 3010 igb_getreg(PVFGOTLBC0), 3011 igb_getreg(PVFGOTLBC1), 3012 igb_getreg(PVFGOTLBC2), 3013 igb_getreg(PVFGOTLBC3), 3014 igb_getreg(PVFGOTLBC4), 3015 igb_getreg(PVFGOTLBC5), 3016 igb_getreg(PVFGOTLBC6), 3017 igb_getreg(PVFGOTLBC7), 3018 igb_getreg(RCTL), 3019 igb_getreg(MDIC), 3020 igb_getreg(FCRUC), 3021 igb_getreg(VET), 3022 igb_getreg(RDBAL0), 3023 igb_getreg(RDBAL1), 3024 igb_getreg(RDBAL2), 3025 igb_getreg(RDBAL3), 3026 igb_getreg(RDBAL4), 3027 igb_getreg(RDBAL5), 3028 igb_getreg(RDBAL6), 3029 igb_getreg(RDBAL7), 3030 igb_getreg(RDBAL8), 3031 igb_getreg(RDBAL9), 3032 igb_getreg(RDBAL10), 3033 igb_getreg(RDBAL11), 3034 igb_getreg(RDBAL12), 3035 igb_getreg(RDBAL13), 3036 igb_getreg(RDBAL14), 3037 igb_getreg(RDBAL15), 3038 igb_getreg(TDBAH0), 3039 igb_getreg(TDBAH1), 3040 igb_getreg(TDBAH2), 3041 igb_getreg(TDBAH3), 3042 igb_getreg(TDBAH4), 3043 igb_getreg(TDBAH5), 3044 igb_getreg(TDBAH6), 3045 igb_getreg(TDBAH7), 3046 igb_getreg(TDBAH8), 3047 igb_getreg(TDBAH9), 3048 igb_getreg(TDBAH10), 3049 igb_getreg(TDBAH11), 3050 igb_getreg(TDBAH12), 3051 igb_getreg(TDBAH13), 3052 igb_getreg(TDBAH14), 3053 igb_getreg(TDBAH15), 3054 igb_getreg(SCC), 3055 igb_getreg(COLC), 3056 igb_getreg(XOFFRXC), 3057 igb_getreg(IPAV), 3058 igb_getreg(GOTCL), 3059 igb_getreg(MGTPDC), 3060 igb_getreg(GCR), 3061 igb_getreg(MFVAL), 3062 igb_getreg(FUNCTAG), 3063 igb_getreg(GSCL_4), 3064 igb_getreg(GSCN_3), 3065 igb_getreg(MRQC), 3066 igb_getreg(FCT), 3067 igb_getreg(FLA), 3068 igb_getreg(RXDCTL0), 3069 igb_getreg(RXDCTL1), 3070 igb_getreg(RXDCTL2), 3071 igb_getreg(RXDCTL3), 3072 igb_getreg(RXDCTL4), 3073 igb_getreg(RXDCTL5), 3074 igb_getreg(RXDCTL6), 3075 igb_getreg(RXDCTL7), 3076 igb_getreg(RXDCTL8), 3077 igb_getreg(RXDCTL9), 3078 igb_getreg(RXDCTL10), 3079 igb_getreg(RXDCTL11), 3080 igb_getreg(RXDCTL12), 3081 igb_getreg(RXDCTL13), 3082 igb_getreg(RXDCTL14), 3083 igb_getreg(RXDCTL15), 3084 igb_getreg(RXSTMPL), 3085 igb_getreg(TIMADJH), 3086 igb_getreg(FCRTL), 3087 igb_getreg(XONRXC), 3088 igb_getreg(RFCTL), 3089 igb_getreg(GSCN_1), 3090 igb_getreg(FCAL), 3091 igb_getreg(GPIE), 3092 igb_getreg(TXPBS), 3093 igb_getreg(RLPML), 3094 3095 [TOTH] = igb_mac_read_clr8, 3096 [GOTCH] = igb_mac_read_clr8, 3097 [PRC64] = igb_mac_read_clr4, 3098 [PRC255] = igb_mac_read_clr4, 3099 [PRC1023] = igb_mac_read_clr4, 3100 [PTC64] = igb_mac_read_clr4, 3101 [PTC255] = igb_mac_read_clr4, 3102 [PTC1023] = igb_mac_read_clr4, 3103 [GPRC] = igb_mac_read_clr4, 3104 [TPT] = igb_mac_read_clr4, 3105 [RUC] = igb_mac_read_clr4, 3106 [BPRC] = igb_mac_read_clr4, 3107 [MPTC] = igb_mac_read_clr4, 3108 [IAC] = igb_mac_read_clr4, 3109 [ICR] = igb_mac_icr_read, 3110 [STATUS] = igb_get_status, 3111 [ICS] = igb_mac_ics_read, 3112 /* 3113 * 8.8.10: Reading the IMC register returns the value of the IMS register. 3114 */ 3115 [IMC] = igb_mac_ims_read, 3116 [TORH] = igb_mac_read_clr8, 3117 [GORCH] = igb_mac_read_clr8, 3118 [PRC127] = igb_mac_read_clr4, 3119 [PRC511] = igb_mac_read_clr4, 3120 [PRC1522] = igb_mac_read_clr4, 3121 [PTC127] = igb_mac_read_clr4, 3122 [PTC511] = igb_mac_read_clr4, 3123 [PTC1522] = igb_mac_read_clr4, 3124 [GPTC] = igb_mac_read_clr4, 3125 [TPR] = igb_mac_read_clr4, 3126 [ROC] = igb_mac_read_clr4, 3127 [MPRC] = igb_mac_read_clr4, 3128 [BPTC] = igb_mac_read_clr4, 3129 [TSCTC] = igb_mac_read_clr4, 3130 [CTRL] = igb_get_ctrl, 3131 [SWSM] = igb_mac_swsm_read, 3132 [IMS] = igb_mac_ims_read, 3133 [SYSTIML] = igb_get_systiml, 3134 [RXSATRH] = igb_get_rxsatrh, 3135 [TXSTMPH] = igb_get_txstmph, 3136 3137 [CRCERRS ... MPC] = igb_mac_readreg, 3138 [IP6AT ... IP6AT + 3] = igb_mac_readreg, 3139 [IP4AT ... IP4AT + 6] = igb_mac_readreg, 3140 [RA ... RA + 31] = igb_mac_readreg, 3141 [RA2 ... RA2 + 31] = igb_mac_readreg, 3142 [WUPM ... WUPM + 31] = igb_mac_readreg, 3143 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg, 3144 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg, 3145 [FFMT ... FFMT + 254] = igb_mac_readreg, 3146 [MDEF ... MDEF + 7] = igb_mac_readreg, 3147 [FTFT ... FTFT + 254] = igb_mac_readreg, 3148 [RETA ... RETA + 31] = igb_mac_readreg, 3149 [RSSRK ... RSSRK + 9] = igb_mac_readreg, 3150 [MAVTV0 ... MAVTV3] = igb_mac_readreg, 3151 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read, 3152 [PVTEICR0] = igb_mac_read_clr4, 3153 [PVTEICR1] = igb_mac_read_clr4, 3154 [PVTEICR2] = igb_mac_read_clr4, 3155 [PVTEICR3] = igb_mac_read_clr4, 3156 [PVTEICR4] = igb_mac_read_clr4, 3157 [PVTEICR5] = igb_mac_read_clr4, 3158 [PVTEICR6] = igb_mac_read_clr4, 3159 [PVTEICR7] = igb_mac_read_clr4, 3160 3161 /* IGB specific: */ 3162 [FWSM] = igb_mac_readreg, 3163 [SW_FW_SYNC] = igb_mac_readreg, 3164 [HTCBDPC] = igb_mac_read_clr4, 3165 [EICR] = igb_mac_read_clr4, 3166 [EIMS] = igb_mac_readreg, 3167 [EIAM] = igb_mac_readreg, 3168 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg, 3169 igb_getreg(IVAR_MISC), 3170 igb_getreg(VT_CTL), 3171 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg, 3172 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read, 3173 igb_getreg(MBVFICR), 3174 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg, 3175 igb_getreg(MBVFIMR), 3176 igb_getreg(VFLRE), 3177 igb_getreg(VFRE), 3178 igb_getreg(VFTE), 3179 igb_getreg(QDE), 3180 igb_getreg(DTXSWC), 3181 igb_getreg(RPLOLR), 3182 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg, 3183 [VMVIR0 ... VMVIR7] = igb_mac_readreg, 3184 [VMOLR0 ... VMOLR7] = igb_mac_readreg, 3185 [WVBR] = igb_mac_read_clr4, 3186 [RQDPC0] = igb_mac_read_clr4, 3187 [RQDPC1] = igb_mac_read_clr4, 3188 [RQDPC2] = igb_mac_read_clr4, 3189 [RQDPC3] = igb_mac_read_clr4, 3190 [RQDPC4] = igb_mac_read_clr4, 3191 [RQDPC5] = igb_mac_read_clr4, 3192 [RQDPC6] = igb_mac_read_clr4, 3193 [RQDPC7] = igb_mac_read_clr4, 3194 [RQDPC8] = igb_mac_read_clr4, 3195 [RQDPC9] = igb_mac_read_clr4, 3196 [RQDPC10] = igb_mac_read_clr4, 3197 [RQDPC11] = igb_mac_read_clr4, 3198 [RQDPC12] = igb_mac_read_clr4, 3199 [RQDPC13] = igb_mac_read_clr4, 3200 [RQDPC14] = igb_mac_read_clr4, 3201 [RQDPC15] = igb_mac_read_clr4, 3202 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg, 3203 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg, 3204 }; 3205 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) }; 3206 3207 #define igb_putreg(x) [x] = igb_mac_writereg 3208 typedef void (*writeops)(IGBCore *, int, uint32_t); 3209 static const writeops igb_macreg_writeops[] = { 3210 igb_putreg(SWSM), 3211 igb_putreg(WUFC), 3212 igb_putreg(RDBAH0), 3213 igb_putreg(RDBAH1), 3214 igb_putreg(RDBAH2), 3215 igb_putreg(RDBAH3), 3216 igb_putreg(RDBAH4), 3217 igb_putreg(RDBAH5), 3218 igb_putreg(RDBAH6), 3219 igb_putreg(RDBAH7), 3220 igb_putreg(RDBAH8), 3221 igb_putreg(RDBAH9), 3222 igb_putreg(RDBAH10), 3223 igb_putreg(RDBAH11), 3224 igb_putreg(RDBAH12), 3225 igb_putreg(RDBAH13), 3226 igb_putreg(RDBAH14), 3227 igb_putreg(RDBAH15), 3228 igb_putreg(SRRCTL0), 3229 igb_putreg(SRRCTL1), 3230 igb_putreg(SRRCTL2), 3231 igb_putreg(SRRCTL3), 3232 igb_putreg(SRRCTL4), 3233 igb_putreg(SRRCTL5), 3234 igb_putreg(SRRCTL6), 3235 igb_putreg(SRRCTL7), 3236 igb_putreg(SRRCTL8), 3237 igb_putreg(SRRCTL9), 3238 igb_putreg(SRRCTL10), 3239 igb_putreg(SRRCTL11), 3240 igb_putreg(SRRCTL12), 3241 igb_putreg(SRRCTL13), 3242 igb_putreg(SRRCTL14), 3243 igb_putreg(SRRCTL15), 3244 igb_putreg(RXDCTL0), 3245 igb_putreg(RXDCTL1), 3246 igb_putreg(RXDCTL2), 3247 igb_putreg(RXDCTL3), 3248 igb_putreg(RXDCTL4), 3249 igb_putreg(RXDCTL5), 3250 igb_putreg(RXDCTL6), 3251 igb_putreg(RXDCTL7), 3252 igb_putreg(RXDCTL8), 3253 igb_putreg(RXDCTL9), 3254 igb_putreg(RXDCTL10), 3255 igb_putreg(RXDCTL11), 3256 igb_putreg(RXDCTL12), 3257 igb_putreg(RXDCTL13), 3258 igb_putreg(RXDCTL14), 3259 igb_putreg(RXDCTL15), 3260 igb_putreg(LEDCTL), 3261 igb_putreg(TCTL), 3262 igb_putreg(TCTL_EXT), 3263 igb_putreg(DTXCTL), 3264 igb_putreg(RXPBS), 3265 igb_putreg(RQDPC0), 3266 igb_putreg(FCAL), 3267 igb_putreg(FCRUC), 3268 igb_putreg(WUC), 3269 igb_putreg(WUS), 3270 igb_putreg(IPAV), 3271 igb_putreg(TDBAH0), 3272 igb_putreg(TDBAH1), 3273 igb_putreg(TDBAH2), 3274 igb_putreg(TDBAH3), 3275 igb_putreg(TDBAH4), 3276 igb_putreg(TDBAH5), 3277 igb_putreg(TDBAH6), 3278 igb_putreg(TDBAH7), 3279 igb_putreg(TDBAH8), 3280 igb_putreg(TDBAH9), 3281 igb_putreg(TDBAH10), 3282 igb_putreg(TDBAH11), 3283 igb_putreg(TDBAH12), 3284 igb_putreg(TDBAH13), 3285 igb_putreg(TDBAH14), 3286 igb_putreg(TDBAH15), 3287 igb_putreg(IAM), 3288 igb_putreg(MANC), 3289 igb_putreg(MANC2H), 3290 igb_putreg(MFVAL), 3291 igb_putreg(FACTPS), 3292 igb_putreg(FUNCTAG), 3293 igb_putreg(GSCL_1), 3294 igb_putreg(GSCL_2), 3295 igb_putreg(GSCL_3), 3296 igb_putreg(GSCL_4), 3297 igb_putreg(GSCN_0), 3298 igb_putreg(GSCN_1), 3299 igb_putreg(GSCN_2), 3300 igb_putreg(GSCN_3), 3301 igb_putreg(MRQC), 3302 igb_putreg(FLOP), 3303 igb_putreg(FLA), 3304 igb_putreg(TXDCTL0), 3305 igb_putreg(TXDCTL1), 3306 igb_putreg(TXDCTL2), 3307 igb_putreg(TXDCTL3), 3308 igb_putreg(TXDCTL4), 3309 igb_putreg(TXDCTL5), 3310 igb_putreg(TXDCTL6), 3311 igb_putreg(TXDCTL7), 3312 igb_putreg(TXDCTL8), 3313 igb_putreg(TXDCTL9), 3314 igb_putreg(TXDCTL10), 3315 igb_putreg(TXDCTL11), 3316 igb_putreg(TXDCTL12), 3317 igb_putreg(TXDCTL13), 3318 igb_putreg(TXDCTL14), 3319 igb_putreg(TXDCTL15), 3320 igb_putreg(TXCTL0), 3321 igb_putreg(TXCTL1), 3322 igb_putreg(TXCTL2), 3323 igb_putreg(TXCTL3), 3324 igb_putreg(TXCTL4), 3325 igb_putreg(TXCTL5), 3326 igb_putreg(TXCTL6), 3327 igb_putreg(TXCTL7), 3328 igb_putreg(TXCTL8), 3329 igb_putreg(TXCTL9), 3330 igb_putreg(TXCTL10), 3331 igb_putreg(TXCTL11), 3332 igb_putreg(TXCTL12), 3333 igb_putreg(TXCTL13), 3334 igb_putreg(TXCTL14), 3335 igb_putreg(TXCTL15), 3336 igb_putreg(TDWBAL0), 3337 igb_putreg(TDWBAL1), 3338 igb_putreg(TDWBAL2), 3339 igb_putreg(TDWBAL3), 3340 igb_putreg(TDWBAL4), 3341 igb_putreg(TDWBAL5), 3342 igb_putreg(TDWBAL6), 3343 igb_putreg(TDWBAL7), 3344 igb_putreg(TDWBAL8), 3345 igb_putreg(TDWBAL9), 3346 igb_putreg(TDWBAL10), 3347 igb_putreg(TDWBAL11), 3348 igb_putreg(TDWBAL12), 3349 igb_putreg(TDWBAL13), 3350 igb_putreg(TDWBAL14), 3351 igb_putreg(TDWBAL15), 3352 igb_putreg(TDWBAH0), 3353 igb_putreg(TDWBAH1), 3354 igb_putreg(TDWBAH2), 3355 igb_putreg(TDWBAH3), 3356 igb_putreg(TDWBAH4), 3357 igb_putreg(TDWBAH5), 3358 igb_putreg(TDWBAH6), 3359 igb_putreg(TDWBAH7), 3360 igb_putreg(TDWBAH8), 3361 igb_putreg(TDWBAH9), 3362 igb_putreg(TDWBAH10), 3363 igb_putreg(TDWBAH11), 3364 igb_putreg(TDWBAH12), 3365 igb_putreg(TDWBAH13), 3366 igb_putreg(TDWBAH14), 3367 igb_putreg(TDWBAH15), 3368 igb_putreg(TIPG), 3369 igb_putreg(RXSTMPH), 3370 igb_putreg(RXSTMPL), 3371 igb_putreg(RXSATRL), 3372 igb_putreg(RXSATRH), 3373 igb_putreg(TXSTMPL), 3374 igb_putreg(TXSTMPH), 3375 igb_putreg(SYSTIML), 3376 igb_putreg(SYSTIMH), 3377 igb_putreg(TIMADJL), 3378 igb_putreg(TSYNCRXCTL), 3379 igb_putreg(TSYNCTXCTL), 3380 igb_putreg(EEMNGCTL), 3381 igb_putreg(GPIE), 3382 igb_putreg(TXPBS), 3383 igb_putreg(RLPML), 3384 igb_putreg(VET), 3385 3386 [TDH0] = igb_set_16bit, 3387 [TDH1] = igb_set_16bit, 3388 [TDH2] = igb_set_16bit, 3389 [TDH3] = igb_set_16bit, 3390 [TDH4] = igb_set_16bit, 3391 [TDH5] = igb_set_16bit, 3392 [TDH6] = igb_set_16bit, 3393 [TDH7] = igb_set_16bit, 3394 [TDH8] = igb_set_16bit, 3395 [TDH9] = igb_set_16bit, 3396 [TDH10] = igb_set_16bit, 3397 [TDH11] = igb_set_16bit, 3398 [TDH12] = igb_set_16bit, 3399 [TDH13] = igb_set_16bit, 3400 [TDH14] = igb_set_16bit, 3401 [TDH15] = igb_set_16bit, 3402 [TDT0] = igb_set_tdt, 3403 [TDT1] = igb_set_tdt, 3404 [TDT2] = igb_set_tdt, 3405 [TDT3] = igb_set_tdt, 3406 [TDT4] = igb_set_tdt, 3407 [TDT5] = igb_set_tdt, 3408 [TDT6] = igb_set_tdt, 3409 [TDT7] = igb_set_tdt, 3410 [TDT8] = igb_set_tdt, 3411 [TDT9] = igb_set_tdt, 3412 [TDT10] = igb_set_tdt, 3413 [TDT11] = igb_set_tdt, 3414 [TDT12] = igb_set_tdt, 3415 [TDT13] = igb_set_tdt, 3416 [TDT14] = igb_set_tdt, 3417 [TDT15] = igb_set_tdt, 3418 [MDIC] = igb_set_mdic, 3419 [ICS] = igb_set_ics, 3420 [RDH0] = igb_set_16bit, 3421 [RDH1] = igb_set_16bit, 3422 [RDH2] = igb_set_16bit, 3423 [RDH3] = igb_set_16bit, 3424 [RDH4] = igb_set_16bit, 3425 [RDH5] = igb_set_16bit, 3426 [RDH6] = igb_set_16bit, 3427 [RDH7] = igb_set_16bit, 3428 [RDH8] = igb_set_16bit, 3429 [RDH9] = igb_set_16bit, 3430 [RDH10] = igb_set_16bit, 3431 [RDH11] = igb_set_16bit, 3432 [RDH12] = igb_set_16bit, 3433 [RDH13] = igb_set_16bit, 3434 [RDH14] = igb_set_16bit, 3435 [RDH15] = igb_set_16bit, 3436 [RDT0] = igb_set_rdt, 3437 [RDT1] = igb_set_rdt, 3438 [RDT2] = igb_set_rdt, 3439 [RDT3] = igb_set_rdt, 3440 [RDT4] = igb_set_rdt, 3441 [RDT5] = igb_set_rdt, 3442 [RDT6] = igb_set_rdt, 3443 [RDT7] = igb_set_rdt, 3444 [RDT8] = igb_set_rdt, 3445 [RDT9] = igb_set_rdt, 3446 [RDT10] = igb_set_rdt, 3447 [RDT11] = igb_set_rdt, 3448 [RDT12] = igb_set_rdt, 3449 [RDT13] = igb_set_rdt, 3450 [RDT14] = igb_set_rdt, 3451 [RDT15] = igb_set_rdt, 3452 [IMC] = igb_set_imc, 3453 [IMS] = igb_set_ims, 3454 [ICR] = igb_set_icr, 3455 [EECD] = igb_set_eecd, 3456 [RCTL] = igb_set_rx_control, 3457 [CTRL] = igb_set_ctrl, 3458 [EERD] = igb_set_eerd, 3459 [TDFH] = igb_set_13bit, 3460 [TDFT] = igb_set_13bit, 3461 [TDFHS] = igb_set_13bit, 3462 [TDFTS] = igb_set_13bit, 3463 [TDFPC] = igb_set_13bit, 3464 [RDFH] = igb_set_13bit, 3465 [RDFT] = igb_set_13bit, 3466 [RDFHS] = igb_set_13bit, 3467 [RDFTS] = igb_set_13bit, 3468 [RDFPC] = igb_set_13bit, 3469 [GCR] = igb_set_gcr, 3470 [RXCSUM] = igb_set_rxcsum, 3471 [TDLEN0] = igb_set_dlen, 3472 [TDLEN1] = igb_set_dlen, 3473 [TDLEN2] = igb_set_dlen, 3474 [TDLEN3] = igb_set_dlen, 3475 [TDLEN4] = igb_set_dlen, 3476 [TDLEN5] = igb_set_dlen, 3477 [TDLEN6] = igb_set_dlen, 3478 [TDLEN7] = igb_set_dlen, 3479 [TDLEN8] = igb_set_dlen, 3480 [TDLEN9] = igb_set_dlen, 3481 [TDLEN10] = igb_set_dlen, 3482 [TDLEN11] = igb_set_dlen, 3483 [TDLEN12] = igb_set_dlen, 3484 [TDLEN13] = igb_set_dlen, 3485 [TDLEN14] = igb_set_dlen, 3486 [TDLEN15] = igb_set_dlen, 3487 [RDLEN0] = igb_set_dlen, 3488 [RDLEN1] = igb_set_dlen, 3489 [RDLEN2] = igb_set_dlen, 3490 [RDLEN3] = igb_set_dlen, 3491 [RDLEN4] = igb_set_dlen, 3492 [RDLEN5] = igb_set_dlen, 3493 [RDLEN6] = igb_set_dlen, 3494 [RDLEN7] = igb_set_dlen, 3495 [RDLEN8] = igb_set_dlen, 3496 [RDLEN9] = igb_set_dlen, 3497 [RDLEN10] = igb_set_dlen, 3498 [RDLEN11] = igb_set_dlen, 3499 [RDLEN12] = igb_set_dlen, 3500 [RDLEN13] = igb_set_dlen, 3501 [RDLEN14] = igb_set_dlen, 3502 [RDLEN15] = igb_set_dlen, 3503 [TDBAL0] = igb_set_dbal, 3504 [TDBAL1] = igb_set_dbal, 3505 [TDBAL2] = igb_set_dbal, 3506 [TDBAL3] = igb_set_dbal, 3507 [TDBAL4] = igb_set_dbal, 3508 [TDBAL5] = igb_set_dbal, 3509 [TDBAL6] = igb_set_dbal, 3510 [TDBAL7] = igb_set_dbal, 3511 [TDBAL8] = igb_set_dbal, 3512 [TDBAL9] = igb_set_dbal, 3513 [TDBAL10] = igb_set_dbal, 3514 [TDBAL11] = igb_set_dbal, 3515 [TDBAL12] = igb_set_dbal, 3516 [TDBAL13] = igb_set_dbal, 3517 [TDBAL14] = igb_set_dbal, 3518 [TDBAL15] = igb_set_dbal, 3519 [RDBAL0] = igb_set_dbal, 3520 [RDBAL1] = igb_set_dbal, 3521 [RDBAL2] = igb_set_dbal, 3522 [RDBAL3] = igb_set_dbal, 3523 [RDBAL4] = igb_set_dbal, 3524 [RDBAL5] = igb_set_dbal, 3525 [RDBAL6] = igb_set_dbal, 3526 [RDBAL7] = igb_set_dbal, 3527 [RDBAL8] = igb_set_dbal, 3528 [RDBAL9] = igb_set_dbal, 3529 [RDBAL10] = igb_set_dbal, 3530 [RDBAL11] = igb_set_dbal, 3531 [RDBAL12] = igb_set_dbal, 3532 [RDBAL13] = igb_set_dbal, 3533 [RDBAL14] = igb_set_dbal, 3534 [RDBAL15] = igb_set_dbal, 3535 [STATUS] = igb_set_status, 3536 [PBACLR] = igb_set_pbaclr, 3537 [CTRL_EXT] = igb_set_ctrlext, 3538 [FCAH] = igb_set_16bit, 3539 [FCT] = igb_set_16bit, 3540 [FCTTV] = igb_set_16bit, 3541 [FCRTV] = igb_set_16bit, 3542 [FCRTH] = igb_set_fcrth, 3543 [FCRTL] = igb_set_fcrtl, 3544 [CTRL_DUP] = igb_set_ctrl, 3545 [RFCTL] = igb_set_rfctl, 3546 [TIMINCA] = igb_set_timinca, 3547 [TIMADJH] = igb_set_timadjh, 3548 3549 [IP6AT ... IP6AT + 3] = igb_mac_writereg, 3550 [IP4AT ... IP4AT + 6] = igb_mac_writereg, 3551 [RA] = igb_mac_writereg, 3552 [RA + 1] = igb_mac_setmacaddr, 3553 [RA + 2 ... RA + 31] = igb_mac_writereg, 3554 [RA2 ... RA2 + 31] = igb_mac_writereg, 3555 [WUPM ... WUPM + 31] = igb_mac_writereg, 3556 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3557 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg, 3558 [FFMT ... FFMT + 254] = igb_set_4bit, 3559 [MDEF ... MDEF + 7] = igb_mac_writereg, 3560 [FTFT ... FTFT + 254] = igb_mac_writereg, 3561 [RETA ... RETA + 31] = igb_mac_writereg, 3562 [RSSRK ... RSSRK + 9] = igb_mac_writereg, 3563 [MAVTV0 ... MAVTV3] = igb_mac_writereg, 3564 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr, 3565 3566 /* IGB specific: */ 3567 [FWSM] = igb_mac_writereg, 3568 [SW_FW_SYNC] = igb_mac_writereg, 3569 [EICR] = igb_set_eicr, 3570 [EICS] = igb_set_eics, 3571 [EIAC] = igb_set_eiac, 3572 [EIAM] = igb_set_eiam, 3573 [EIMC] = igb_set_eimc, 3574 [EIMS] = igb_set_eims, 3575 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg, 3576 igb_putreg(IVAR_MISC), 3577 igb_putreg(VT_CTL), 3578 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox, 3579 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox, 3580 [MBVFICR] = igb_w1c, 3581 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg, 3582 igb_putreg(MBVFIMR), 3583 [VFLRE] = igb_w1c, 3584 igb_putreg(VFRE), 3585 igb_putreg(VFTE), 3586 igb_putreg(QDE), 3587 igb_putreg(DTXSWC), 3588 igb_putreg(RPLOLR), 3589 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg, 3590 [VMVIR0 ... VMVIR7] = igb_mac_writereg, 3591 [VMOLR0 ... VMOLR7] = igb_mac_writereg, 3592 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3593 [PVTCTRL0] = igb_set_vtctrl, 3594 [PVTCTRL1] = igb_set_vtctrl, 3595 [PVTCTRL2] = igb_set_vtctrl, 3596 [PVTCTRL3] = igb_set_vtctrl, 3597 [PVTCTRL4] = igb_set_vtctrl, 3598 [PVTCTRL5] = igb_set_vtctrl, 3599 [PVTCTRL6] = igb_set_vtctrl, 3600 [PVTCTRL7] = igb_set_vtctrl, 3601 [PVTEICS0] = igb_set_vteics, 3602 [PVTEICS1] = igb_set_vteics, 3603 [PVTEICS2] = igb_set_vteics, 3604 [PVTEICS3] = igb_set_vteics, 3605 [PVTEICS4] = igb_set_vteics, 3606 [PVTEICS5] = igb_set_vteics, 3607 [PVTEICS6] = igb_set_vteics, 3608 [PVTEICS7] = igb_set_vteics, 3609 [PVTEIMS0] = igb_set_vteims, 3610 [PVTEIMS1] = igb_set_vteims, 3611 [PVTEIMS2] = igb_set_vteims, 3612 [PVTEIMS3] = igb_set_vteims, 3613 [PVTEIMS4] = igb_set_vteims, 3614 [PVTEIMS5] = igb_set_vteims, 3615 [PVTEIMS6] = igb_set_vteims, 3616 [PVTEIMS7] = igb_set_vteims, 3617 [PVTEIMC0] = igb_set_vteimc, 3618 [PVTEIMC1] = igb_set_vteimc, 3619 [PVTEIMC2] = igb_set_vteimc, 3620 [PVTEIMC3] = igb_set_vteimc, 3621 [PVTEIMC4] = igb_set_vteimc, 3622 [PVTEIMC5] = igb_set_vteimc, 3623 [PVTEIMC6] = igb_set_vteimc, 3624 [PVTEIMC7] = igb_set_vteimc, 3625 [PVTEIAC0] = igb_set_vteiac, 3626 [PVTEIAC1] = igb_set_vteiac, 3627 [PVTEIAC2] = igb_set_vteiac, 3628 [PVTEIAC3] = igb_set_vteiac, 3629 [PVTEIAC4] = igb_set_vteiac, 3630 [PVTEIAC5] = igb_set_vteiac, 3631 [PVTEIAC6] = igb_set_vteiac, 3632 [PVTEIAC7] = igb_set_vteiac, 3633 [PVTEIAM0] = igb_set_vteiam, 3634 [PVTEIAM1] = igb_set_vteiam, 3635 [PVTEIAM2] = igb_set_vteiam, 3636 [PVTEIAM3] = igb_set_vteiam, 3637 [PVTEIAM4] = igb_set_vteiam, 3638 [PVTEIAM5] = igb_set_vteiam, 3639 [PVTEIAM6] = igb_set_vteiam, 3640 [PVTEIAM7] = igb_set_vteiam, 3641 [PVTEICR0] = igb_set_vteicr, 3642 [PVTEICR1] = igb_set_vteicr, 3643 [PVTEICR2] = igb_set_vteicr, 3644 [PVTEICR3] = igb_set_vteicr, 3645 [PVTEICR4] = igb_set_vteicr, 3646 [PVTEICR5] = igb_set_vteicr, 3647 [PVTEICR6] = igb_set_vteicr, 3648 [PVTEICR7] = igb_set_vteicr, 3649 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar, 3650 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg 3651 }; 3652 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) }; 3653 3654 enum { MAC_ACCESS_PARTIAL = 1 }; 3655 3656 /* 3657 * The array below combines alias offsets of the index values for the 3658 * MAC registers that have aliases, with the indication of not fully 3659 * implemented registers (lowest bit). This combination is possible 3660 * because all of the offsets are even. 3661 */ 3662 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3663 /* Alias index offsets */ 3664 [FCRTL_A] = 0x07fe, 3665 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3666 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3667 [RA_A ... RA_A + 31] = 0x14f0, 3668 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3669 3670 [RDBAL0_A] = 0x2600, 3671 [RDBAH0_A] = 0x2600, 3672 [RDLEN0_A] = 0x2600, 3673 [SRRCTL0_A] = 0x2600, 3674 [RDH0_A] = 0x2600, 3675 [RDT0_A] = 0x2600, 3676 [RXDCTL0_A] = 0x2600, 3677 [RXCTL0_A] = 0x2600, 3678 [RQDPC0_A] = 0x2600, 3679 [RDBAL1_A] = 0x25D0, 3680 [RDBAL2_A] = 0x25A0, 3681 [RDBAL3_A] = 0x2570, 3682 [RDBAH1_A] = 0x25D0, 3683 [RDBAH2_A] = 0x25A0, 3684 [RDBAH3_A] = 0x2570, 3685 [RDLEN1_A] = 0x25D0, 3686 [RDLEN2_A] = 0x25A0, 3687 [RDLEN3_A] = 0x2570, 3688 [SRRCTL1_A] = 0x25D0, 3689 [SRRCTL2_A] = 0x25A0, 3690 [SRRCTL3_A] = 0x2570, 3691 [RDH1_A] = 0x25D0, 3692 [RDH2_A] = 0x25A0, 3693 [RDH3_A] = 0x2570, 3694 [RDT1_A] = 0x25D0, 3695 [RDT2_A] = 0x25A0, 3696 [RDT3_A] = 0x2570, 3697 [RXDCTL1_A] = 0x25D0, 3698 [RXDCTL2_A] = 0x25A0, 3699 [RXDCTL3_A] = 0x2570, 3700 [RXCTL1_A] = 0x25D0, 3701 [RXCTL2_A] = 0x25A0, 3702 [RXCTL3_A] = 0x2570, 3703 [RQDPC1_A] = 0x25D0, 3704 [RQDPC2_A] = 0x25A0, 3705 [RQDPC3_A] = 0x2570, 3706 [TDBAL0_A] = 0x2A00, 3707 [TDBAH0_A] = 0x2A00, 3708 [TDLEN0_A] = 0x2A00, 3709 [TDH0_A] = 0x2A00, 3710 [TDT0_A] = 0x2A00, 3711 [TXCTL0_A] = 0x2A00, 3712 [TDWBAL0_A] = 0x2A00, 3713 [TDWBAH0_A] = 0x2A00, 3714 [TDBAL1_A] = 0x29D0, 3715 [TDBAL2_A] = 0x29A0, 3716 [TDBAL3_A] = 0x2970, 3717 [TDBAH1_A] = 0x29D0, 3718 [TDBAH2_A] = 0x29A0, 3719 [TDBAH3_A] = 0x2970, 3720 [TDLEN1_A] = 0x29D0, 3721 [TDLEN2_A] = 0x29A0, 3722 [TDLEN3_A] = 0x2970, 3723 [TDH1_A] = 0x29D0, 3724 [TDH2_A] = 0x29A0, 3725 [TDH3_A] = 0x2970, 3726 [TDT1_A] = 0x29D0, 3727 [TDT2_A] = 0x29A0, 3728 [TDT3_A] = 0x2970, 3729 [TXDCTL0_A] = 0x2A00, 3730 [TXDCTL1_A] = 0x29D0, 3731 [TXDCTL2_A] = 0x29A0, 3732 [TXDCTL3_A] = 0x2970, 3733 [TXCTL1_A] = 0x29D0, 3734 [TXCTL2_A] = 0x29A0, 3735 [TXCTL3_A] = 0x29D0, 3736 [TDWBAL1_A] = 0x29D0, 3737 [TDWBAL2_A] = 0x29A0, 3738 [TDWBAL3_A] = 0x2970, 3739 [TDWBAH1_A] = 0x29D0, 3740 [TDWBAH2_A] = 0x29A0, 3741 [TDWBAH3_A] = 0x2970, 3742 3743 /* Access options */ 3744 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3745 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3746 [RDFPC] = MAC_ACCESS_PARTIAL, 3747 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3748 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3749 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3750 [FLA] = MAC_ACCESS_PARTIAL, 3751 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3752 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3753 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3754 [FCRTH] = MAC_ACCESS_PARTIAL, 3755 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3756 }; 3757 3758 void 3759 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size) 3760 { 3761 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3762 3763 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) { 3764 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3765 trace_e1000e_wrn_regs_write_trivial(index << 2); 3766 } 3767 trace_e1000e_core_write(index << 2, size, val); 3768 igb_macreg_writeops[index](core, index, val); 3769 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3770 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3771 } else { 3772 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3773 } 3774 } 3775 3776 uint64_t 3777 igb_core_read(IGBCore *core, hwaddr addr, unsigned size) 3778 { 3779 uint64_t val; 3780 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3781 3782 if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3783 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3784 trace_e1000e_wrn_regs_read_trivial(index << 2); 3785 } 3786 val = igb_macreg_readops[index](core, index); 3787 trace_e1000e_core_read(index << 2, size, val); 3788 return val; 3789 } else { 3790 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3791 } 3792 return 0; 3793 } 3794 3795 static inline void 3796 igb_autoneg_pause(IGBCore *core) 3797 { 3798 timer_del(core->autoneg_timer); 3799 } 3800 3801 static void 3802 igb_autoneg_resume(IGBCore *core) 3803 { 3804 if (igb_have_autoneg(core) && 3805 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 3806 qemu_get_queue(core->owner_nic)->link_down = false; 3807 timer_mod(core->autoneg_timer, 3808 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3809 } 3810 } 3811 3812 static void 3813 igb_vm_state_change(void *opaque, bool running, RunState state) 3814 { 3815 IGBCore *core = opaque; 3816 3817 if (running) { 3818 trace_e1000e_vm_state_running(); 3819 igb_intrmgr_resume(core); 3820 igb_autoneg_resume(core); 3821 } else { 3822 trace_e1000e_vm_state_stopped(); 3823 igb_autoneg_pause(core); 3824 igb_intrmgr_pause(core); 3825 } 3826 } 3827 3828 void 3829 igb_core_pci_realize(IGBCore *core, 3830 const uint16_t *eeprom_templ, 3831 uint32_t eeprom_size, 3832 const uint8_t *macaddr) 3833 { 3834 int i; 3835 3836 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3837 igb_autoneg_timer, core); 3838 igb_intrmgr_pci_realize(core); 3839 3840 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core); 3841 3842 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3843 net_tx_pkt_init(&core->tx[i].tx_pkt, NULL, E1000E_MAX_TX_FRAGS); 3844 } 3845 3846 net_rx_pkt_init(&core->rx_pkt); 3847 3848 e1000x_core_prepare_eeprom(core->eeprom, 3849 eeprom_templ, 3850 eeprom_size, 3851 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3852 macaddr); 3853 igb_update_rx_offloads(core); 3854 } 3855 3856 void 3857 igb_core_pci_uninit(IGBCore *core) 3858 { 3859 int i; 3860 3861 timer_free(core->autoneg_timer); 3862 3863 igb_intrmgr_pci_unint(core); 3864 3865 qemu_del_vm_change_state_handler(core->vmstate); 3866 3867 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3868 net_tx_pkt_reset(core->tx[i].tx_pkt, NULL); 3869 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3870 } 3871 3872 net_rx_pkt_uninit(core->rx_pkt); 3873 } 3874 3875 static const uint16_t 3876 igb_phy_reg_init[] = { 3877 [MII_BMCR] = MII_BMCR_SPEED1000 | 3878 MII_BMCR_FD | 3879 MII_BMCR_AUTOEN, 3880 3881 [MII_BMSR] = MII_BMSR_EXTCAP | 3882 MII_BMSR_LINK_ST | 3883 MII_BMSR_AUTONEG | 3884 MII_BMSR_MFPS | 3885 MII_BMSR_EXTSTAT | 3886 MII_BMSR_10T_HD | 3887 MII_BMSR_10T_FD | 3888 MII_BMSR_100TX_HD | 3889 MII_BMSR_100TX_FD, 3890 3891 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16, 3892 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1, 3893 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3894 MII_ANAR_10FD | MII_ANAR_TX | 3895 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3896 MII_ANAR_PAUSE_ASYM, 3897 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3898 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3899 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3900 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3901 [MII_ANNP] = 0x1 | MII_ANNP_MP, 3902 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3903 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3904 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3905 MII_STAT1000_ROK | MII_STAT1000_LOK, 3906 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3907 3908 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8), 3909 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS, 3910 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU | 3911 IGP01E1000_PSCFR_SMART_SPEED 3912 }; 3913 3914 static const uint32_t igb_mac_reg_init[] = { 3915 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24), 3916 [EEMNGCTL] = BIT(31), 3917 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16), 3918 [RXDCTL1] = 1 << 16, 3919 [RXDCTL2] = 1 << 16, 3920 [RXDCTL3] = 1 << 16, 3921 [RXDCTL4] = 1 << 16, 3922 [RXDCTL5] = 1 << 16, 3923 [RXDCTL6] = 1 << 16, 3924 [RXDCTL7] = 1 << 16, 3925 [RXDCTL8] = 1 << 16, 3926 [RXDCTL9] = 1 << 16, 3927 [RXDCTL10] = 1 << 16, 3928 [RXDCTL11] = 1 << 16, 3929 [RXDCTL12] = 1 << 16, 3930 [RXDCTL13] = 1 << 16, 3931 [RXDCTL14] = 1 << 16, 3932 [RXDCTL15] = 1 << 16, 3933 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20), 3934 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 | 3935 E1000_CTRL_ADVD3WUC, 3936 [STATUS] = E1000_STATUS_PHYRA | BIT(31), 3937 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES | 3938 (2 << E1000_EECD_SIZE_EX_SHIFT), 3939 [GCR] = E1000_L0S_ADJUST | 3940 E1000_GCR_CMPL_TMOUT_RESEND | 3941 E1000_GCR_CAP_VER2 | 3942 E1000_L1_ENTRY_LATENCY_MSB | 3943 E1000_L1_ENTRY_LATENCY_LSB, 3944 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3945 [TXPBS] = 0x28, 3946 [RXPBS] = 0x40, 3947 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) | 3948 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28), 3949 [TCTL_EXT] = 0x40 | (0x42 << 10), 3950 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT, 3951 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16), 3952 3953 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI, 3954 [MBVFIMR] = 0xFF, 3955 [VFRE] = 0xFF, 3956 [VFTE] = 0xFF, 3957 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC, 3958 [RPLOLR] = E1000_RPLOLR_STRCRC, 3959 [RLPML] = 0x2600, 3960 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3961 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3962 E1000_DCA_TXCTRL_DESC_RRO_EN, 3963 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3964 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3965 E1000_DCA_TXCTRL_DESC_RRO_EN, 3966 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3967 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3968 E1000_DCA_TXCTRL_DESC_RRO_EN, 3969 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3970 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3971 E1000_DCA_TXCTRL_DESC_RRO_EN, 3972 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3973 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3974 E1000_DCA_TXCTRL_DESC_RRO_EN, 3975 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3976 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3977 E1000_DCA_TXCTRL_DESC_RRO_EN, 3978 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3979 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3980 E1000_DCA_TXCTRL_DESC_RRO_EN, 3981 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3982 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3983 E1000_DCA_TXCTRL_DESC_RRO_EN, 3984 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3985 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3986 E1000_DCA_TXCTRL_DESC_RRO_EN, 3987 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3988 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3989 E1000_DCA_TXCTRL_DESC_RRO_EN, 3990 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3991 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3992 E1000_DCA_TXCTRL_DESC_RRO_EN, 3993 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3994 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3995 E1000_DCA_TXCTRL_DESC_RRO_EN, 3996 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN | 3997 E1000_DCA_TXCTRL_TX_WB_RO_EN | 3998 E1000_DCA_TXCTRL_DESC_RRO_EN, 3999 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4000 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4001 E1000_DCA_TXCTRL_DESC_RRO_EN, 4002 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4003 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4004 E1000_DCA_TXCTRL_DESC_RRO_EN, 4005 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4006 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4007 E1000_DCA_TXCTRL_DESC_RRO_EN, 4008 }; 4009 4010 static void igb_reset(IGBCore *core, bool sw) 4011 { 4012 struct igb_tx *tx; 4013 int i; 4014 4015 timer_del(core->autoneg_timer); 4016 4017 igb_intrmgr_reset(core); 4018 4019 memset(core->phy, 0, sizeof core->phy); 4020 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init); 4021 4022 for (i = 0; i < E1000E_MAC_SIZE; i++) { 4023 if (sw && 4024 (i == RXPBS || i == TXPBS || 4025 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) { 4026 continue; 4027 } 4028 4029 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ? 4030 igb_mac_reg_init[i] : 0; 4031 } 4032 4033 if (qemu_get_queue(core->owner_nic)->link_down) { 4034 igb_link_down(core); 4035 } 4036 4037 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 4038 4039 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 4040 /* Set RSTI, so VF can identify a PF reset is in progress */ 4041 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI; 4042 } 4043 4044 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4045 tx = &core->tx[i]; 4046 net_tx_pkt_reset(tx->tx_pkt, NULL); 4047 memset(tx->ctx, 0, sizeof(tx->ctx)); 4048 tx->first = true; 4049 tx->skip_cp = false; 4050 } 4051 } 4052 4053 void 4054 igb_core_reset(IGBCore *core) 4055 { 4056 igb_reset(core, false); 4057 } 4058 4059 void igb_core_pre_save(IGBCore *core) 4060 { 4061 int i; 4062 NetClientState *nc = qemu_get_queue(core->owner_nic); 4063 4064 /* 4065 * If link is down and auto-negotiation is supported and ongoing, 4066 * complete auto-negotiation immediately. This allows us to look 4067 * at MII_BMSR_AN_COMP to infer link status on load. 4068 */ 4069 if (nc->link_down && igb_have_autoneg(core)) { 4070 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP; 4071 igb_update_flowctl_status(core); 4072 } 4073 4074 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4075 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 4076 core->tx[i].skip_cp = true; 4077 } 4078 } 4079 } 4080 4081 int 4082 igb_core_post_load(IGBCore *core) 4083 { 4084 NetClientState *nc = qemu_get_queue(core->owner_nic); 4085 4086 /* 4087 * nc.link_down can't be migrated, so infer link_down according 4088 * to link status bit in core.mac[STATUS]. 4089 */ 4090 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 4091 4092 return 0; 4093 } 4094