1 /* 2 * Core code for QEMU igb emulation 3 * 4 * Datasheet: 5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf 6 * 7 * Copyright (c) 2020-2023 Red Hat, Inc. 8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 9 * Developed by Daynix Computing LTD (http://www.daynix.com) 10 * 11 * Authors: 12 * Akihiko Odaki <akihiko.odaki@daynix.com> 13 * Gal Hammmer <gal.hammer@sap.com> 14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com> 15 * Dmitry Fleytman <dmitry@daynix.com> 16 * Leonid Bloch <leonid@daynix.com> 17 * Yan Vugenfirer <yan@daynix.com> 18 * 19 * Based on work done by: 20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 21 * Copyright (c) 2008 Qumranet 22 * Based on work done by: 23 * Copyright (c) 2007 Dan Aloni 24 * Copyright (c) 2004 Antony T Curtis 25 * 26 * This library is free software; you can redistribute it and/or 27 * modify it under the terms of the GNU Lesser General Public 28 * License as published by the Free Software Foundation; either 29 * version 2.1 of the License, or (at your option) any later version. 30 * 31 * This library is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 34 * Lesser General Public License for more details. 35 * 36 * You should have received a copy of the GNU Lesser General Public 37 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/log.h" 42 #include "net/net.h" 43 #include "net/tap.h" 44 #include "hw/net/mii.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "sysemu/runstate.h" 48 49 #include "net_tx_pkt.h" 50 #include "net_rx_pkt.h" 51 52 #include "igb_common.h" 53 #include "e1000x_common.h" 54 #include "igb_core.h" 55 56 #include "trace.h" 57 58 #define E1000E_MAX_TX_FRAGS (64) 59 60 union e1000_rx_desc_union { 61 struct e1000_rx_desc legacy; 62 union e1000_adv_rx_desc adv; 63 }; 64 65 typedef struct IGBTxPktVmdqCallbackContext { 66 IGBCore *core; 67 NetClientState *nc; 68 } IGBTxPktVmdqCallbackContext; 69 70 typedef struct L2Header { 71 struct eth_header eth; 72 struct vlan_header vlan; 73 } L2Header; 74 75 static ssize_t 76 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 77 bool has_vnet, bool *external_tx); 78 79 static inline void 80 igb_set_interrupt_cause(IGBCore *core, uint32_t val); 81 82 static void igb_update_interrupt_state(IGBCore *core); 83 static void igb_reset(IGBCore *core, bool sw); 84 85 static inline void 86 igb_raise_legacy_irq(IGBCore *core) 87 { 88 trace_e1000e_irq_legacy_notify(true); 89 e1000x_inc_reg_if_not_full(core->mac, IAC); 90 pci_set_irq(core->owner, 1); 91 } 92 93 static inline void 94 igb_lower_legacy_irq(IGBCore *core) 95 { 96 trace_e1000e_irq_legacy_notify(false); 97 pci_set_irq(core->owner, 0); 98 } 99 100 static void igb_msix_notify(IGBCore *core, unsigned int cause) 101 { 102 PCIDevice *dev = core->owner; 103 uint16_t vfn; 104 uint32_t effective_eiac; 105 unsigned int vector; 106 107 vfn = 8 - (cause + 2) / IGBVF_MSIX_VEC_NUM; 108 if (vfn < pcie_sriov_num_vfs(core->owner)) { 109 dev = pcie_sriov_get_vf_at_index(core->owner, vfn); 110 assert(dev); 111 vector = (cause + 2) % IGBVF_MSIX_VEC_NUM; 112 } else if (cause >= IGB_MSIX_VEC_NUM) { 113 qemu_log_mask(LOG_GUEST_ERROR, 114 "igb: Tried to use vector unavailable for PF"); 115 return; 116 } else { 117 vector = cause; 118 } 119 120 msix_notify(dev, vector); 121 122 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]); 123 effective_eiac = core->mac[EIAC] & BIT(cause); 124 core->mac[EICR] &= ~effective_eiac; 125 } 126 127 static inline void 128 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer) 129 { 130 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 131 timer->delay_resolution_ns; 132 133 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 134 135 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 136 137 timer->running = true; 138 } 139 140 static void 141 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer) 142 { 143 if (timer->running) { 144 igb_intrmgr_rearm_timer(timer); 145 } 146 } 147 148 static void 149 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer) 150 { 151 if (timer->running) { 152 timer_del(timer->timer); 153 } 154 } 155 156 static void 157 igb_intrmgr_on_msix_throttling_timer(void *opaque) 158 { 159 IGBIntrDelayTimer *timer = opaque; 160 int idx = timer - &timer->core->eitr[0]; 161 162 timer->running = false; 163 164 trace_e1000e_irq_msix_notify_postponed_vec(idx); 165 igb_msix_notify(timer->core, idx); 166 } 167 168 static void 169 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create) 170 { 171 int i; 172 173 for (i = 0; i < IGB_INTR_NUM; i++) { 174 core->eitr[i].core = core; 175 core->eitr[i].delay_reg = EITR0 + i; 176 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 177 } 178 179 if (!create) { 180 return; 181 } 182 183 for (i = 0; i < IGB_INTR_NUM; i++) { 184 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 185 igb_intrmgr_on_msix_throttling_timer, 186 &core->eitr[i]); 187 } 188 } 189 190 static void 191 igb_intrmgr_resume(IGBCore *core) 192 { 193 int i; 194 195 for (i = 0; i < IGB_INTR_NUM; i++) { 196 igb_intmgr_timer_resume(&core->eitr[i]); 197 } 198 } 199 200 static void 201 igb_intrmgr_pause(IGBCore *core) 202 { 203 int i; 204 205 for (i = 0; i < IGB_INTR_NUM; i++) { 206 igb_intmgr_timer_pause(&core->eitr[i]); 207 } 208 } 209 210 static void 211 igb_intrmgr_reset(IGBCore *core) 212 { 213 int i; 214 215 for (i = 0; i < IGB_INTR_NUM; i++) { 216 if (core->eitr[i].running) { 217 timer_del(core->eitr[i].timer); 218 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 219 } 220 } 221 } 222 223 static void 224 igb_intrmgr_pci_unint(IGBCore *core) 225 { 226 int i; 227 228 for (i = 0; i < IGB_INTR_NUM; i++) { 229 timer_free(core->eitr[i].timer); 230 } 231 } 232 233 static void 234 igb_intrmgr_pci_realize(IGBCore *core) 235 { 236 igb_intrmgr_initialize_all_timers(core, true); 237 } 238 239 static inline bool 240 igb_rx_csum_enabled(IGBCore *core) 241 { 242 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 243 } 244 245 static inline bool 246 igb_rx_use_legacy_descriptor(IGBCore *core) 247 { 248 /* 249 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx 250 * descriptor. 251 */ 252 return false; 253 } 254 255 static inline bool 256 igb_rss_enabled(IGBCore *core) 257 { 258 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ && 259 !igb_rx_csum_enabled(core) && 260 !igb_rx_use_legacy_descriptor(core); 261 } 262 263 typedef struct E1000E_RSSInfo_st { 264 bool enabled; 265 uint32_t hash; 266 uint32_t queue; 267 uint32_t type; 268 } E1000E_RSSInfo; 269 270 static uint32_t 271 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt) 272 { 273 bool hasip4, hasip6; 274 EthL4HdrProto l4hdr_proto; 275 276 assert(igb_rss_enabled(core)); 277 278 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 279 280 if (hasip4) { 281 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 282 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 283 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 284 285 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 286 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 287 return E1000_MRQ_RSS_TYPE_IPV4TCP; 288 } 289 290 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 291 return E1000_MRQ_RSS_TYPE_IPV4; 292 } 293 } else if (hasip6) { 294 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 295 296 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 297 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 298 299 /* 300 * Following two traces must not be combined because resulting 301 * event will have 11 arguments totally and some trace backends 302 * (at least "ust") have limitation of maximum 10 arguments per 303 * event. Events with more arguments fail to compile for 304 * backends like these. 305 */ 306 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 307 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 308 ip6info->has_ext_hdrs, 309 ip6info->rss_ex_dst_valid, 310 ip6info->rss_ex_src_valid, 311 core->mac[MRQC], 312 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), 313 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 314 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 315 316 if ((!ex_dis || !ip6info->has_ext_hdrs) && 317 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 318 ip6info->rss_ex_src_valid))) { 319 320 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 321 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { 322 return E1000_MRQ_RSS_TYPE_IPV6TCPEX; 323 } 324 325 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 326 return E1000_MRQ_RSS_TYPE_IPV6EX; 327 } 328 329 } 330 331 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 332 return E1000_MRQ_RSS_TYPE_IPV6; 333 } 334 335 } 336 337 return E1000_MRQ_RSS_TYPE_NONE; 338 } 339 340 static uint32_t 341 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info) 342 { 343 NetRxPktRssType type; 344 345 assert(igb_rss_enabled(core)); 346 347 switch (info->type) { 348 case E1000_MRQ_RSS_TYPE_IPV4: 349 type = NetPktRssIpV4; 350 break; 351 case E1000_MRQ_RSS_TYPE_IPV4TCP: 352 type = NetPktRssIpV4Tcp; 353 break; 354 case E1000_MRQ_RSS_TYPE_IPV6TCPEX: 355 type = NetPktRssIpV6TcpEx; 356 break; 357 case E1000_MRQ_RSS_TYPE_IPV6: 358 type = NetPktRssIpV6; 359 break; 360 case E1000_MRQ_RSS_TYPE_IPV6EX: 361 type = NetPktRssIpV6Ex; 362 break; 363 default: 364 assert(false); 365 return 0; 366 } 367 368 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 369 } 370 371 static void 372 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx, 373 E1000E_RSSInfo *info) 374 { 375 trace_e1000e_rx_rss_started(); 376 377 if (tx || !igb_rss_enabled(core)) { 378 info->enabled = false; 379 info->hash = 0; 380 info->queue = 0; 381 info->type = 0; 382 trace_e1000e_rx_rss_disabled(); 383 return; 384 } 385 386 info->enabled = true; 387 388 info->type = igb_rss_get_hash_type(core, pkt); 389 390 trace_e1000e_rx_rss_type(info->type); 391 392 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 393 info->hash = 0; 394 info->queue = 0; 395 return; 396 } 397 398 info->hash = igb_rss_calc_hash(core, pkt, info); 399 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 400 } 401 402 static void 403 igb_tx_insert_vlan(IGBCore *core, uint16_t qn, struct igb_tx *tx, 404 uint16_t vlan, bool insert_vlan) 405 { 406 if (core->mac[MRQC] & 1) { 407 uint16_t pool = qn % IGB_NUM_VM_POOLS; 408 409 if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_DEFAULT) { 410 /* always insert default VLAN */ 411 insert_vlan = true; 412 vlan = core->mac[VMVIR0 + pool] & 0xffff; 413 } else if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_NEVER) { 414 insert_vlan = false; 415 } 416 } 417 418 if (insert_vlan) { 419 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan, 420 core->mac[VET] & 0xffff); 421 } 422 } 423 424 static bool 425 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx) 426 { 427 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) { 428 uint32_t idx = (tx->first_olinfo_status >> 4) & 1; 429 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> E1000_ADVTXD_MSS_SHIFT; 430 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) { 431 return false; 432 } 433 434 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 435 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 436 return true; 437 } 438 439 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) { 440 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 441 return false; 442 } 443 } 444 445 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) { 446 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 447 } 448 449 return true; 450 } 451 452 static void igb_tx_pkt_mac_callback(void *core, 453 const struct iovec *iov, 454 int iovcnt, 455 const struct iovec *virt_iov, 456 int virt_iovcnt) 457 { 458 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL); 459 } 460 461 static void igb_tx_pkt_vmdq_callback(void *opaque, 462 const struct iovec *iov, 463 int iovcnt, 464 const struct iovec *virt_iov, 465 int virt_iovcnt) 466 { 467 IGBTxPktVmdqCallbackContext *context = opaque; 468 bool external_tx; 469 470 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true, 471 &external_tx); 472 473 if (external_tx) { 474 if (context->core->has_vnet) { 475 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt); 476 } else { 477 qemu_sendv_packet(context->nc, iov, iovcnt); 478 } 479 } 480 } 481 482 /* TX Packets Switching (7.10.3.6) */ 483 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx, 484 NetClientState *nc) 485 { 486 IGBTxPktVmdqCallbackContext context; 487 488 /* TX switching is only used to serve VM to VM traffic. */ 489 if (!(core->mac[MRQC] & 1)) { 490 goto send_out; 491 } 492 493 /* TX switching requires DTXSWC.Loopback_en bit enabled. */ 494 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) { 495 goto send_out; 496 } 497 498 context.core = core; 499 context.nc = nc; 500 501 return net_tx_pkt_send_custom(tx->tx_pkt, false, 502 igb_tx_pkt_vmdq_callback, &context); 503 504 send_out: 505 return net_tx_pkt_send(tx->tx_pkt, nc); 506 } 507 508 static bool 509 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index) 510 { 511 int target_queue = MIN(core->max_queue_num, queue_index); 512 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 513 514 if (!igb_setup_tx_offloads(core, tx)) { 515 return false; 516 } 517 518 net_tx_pkt_dump(tx->tx_pkt); 519 520 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) || 521 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 522 return net_tx_pkt_send_custom(tx->tx_pkt, false, 523 igb_tx_pkt_mac_callback, core); 524 } else { 525 return igb_tx_pkt_switch(core, tx, queue); 526 } 527 } 528 529 static void 530 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt, int qn) 531 { 532 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 533 PTC1023, PTC1522 }; 534 535 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 536 537 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 538 e1000x_inc_reg_if_not_full(core->mac, TPT); 539 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 540 541 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 542 case ETH_PKT_BCAST: 543 e1000x_inc_reg_if_not_full(core->mac, BPTC); 544 break; 545 case ETH_PKT_MCAST: 546 e1000x_inc_reg_if_not_full(core->mac, MPTC); 547 break; 548 case ETH_PKT_UCAST: 549 break; 550 default: 551 g_assert_not_reached(); 552 } 553 554 e1000x_inc_reg_if_not_full(core->mac, GPTC); 555 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 556 557 if (core->mac[MRQC] & 1) { 558 uint16_t pool = qn % IGB_NUM_VM_POOLS; 559 560 core->mac[PVFGOTC0 + (pool * 64)] += tot_len; 561 core->mac[PVFGPTC0 + (pool * 64)]++; 562 } 563 } 564 565 static void 566 igb_process_tx_desc(IGBCore *core, 567 PCIDevice *dev, 568 struct igb_tx *tx, 569 union e1000_adv_tx_desc *tx_desc, 570 int queue_index) 571 { 572 struct e1000_adv_tx_context_desc *tx_ctx_desc; 573 uint32_t cmd_type_len; 574 uint32_t idx; 575 uint64_t buffer_addr; 576 uint16_t length; 577 578 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 579 580 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) { 581 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) == 582 E1000_ADVTXD_DTYP_DATA) { 583 /* advanced transmit data descriptor */ 584 if (tx->first) { 585 tx->first_cmd_type_len = cmd_type_len; 586 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status); 587 tx->first = false; 588 } 589 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) == 590 E1000_ADVTXD_DTYP_CTXT) { 591 /* advanced transmit context descriptor */ 592 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc; 593 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1; 594 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens); 595 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed); 596 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl); 597 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx); 598 return; 599 } else { 600 /* unknown descriptor type */ 601 return; 602 } 603 } else { 604 /* legacy descriptor */ 605 606 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */ 607 } 608 609 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr); 610 length = cmd_type_len & 0xFFFF; 611 612 if (!tx->skip_cp) { 613 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, dev, 614 buffer_addr, length)) { 615 tx->skip_cp = true; 616 } 617 } 618 619 if (cmd_type_len & E1000_TXD_CMD_EOP) { 620 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 621 idx = (tx->first_olinfo_status >> 4) & 1; 622 igb_tx_insert_vlan(core, queue_index, tx, 623 tx->ctx[idx].vlan_macip_lens >> IGB_TX_FLAGS_VLAN_SHIFT, 624 !!(tx->first_cmd_type_len & E1000_TXD_CMD_VLE)); 625 626 if (igb_tx_pkt_send(core, tx, queue_index)) { 627 igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index); 628 } 629 } 630 631 tx->first = true; 632 tx->skip_cp = false; 633 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, dev); 634 } 635 } 636 637 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx) 638 { 639 uint32_t n, ent = 0; 640 641 n = igb_ivar_entry_tx(queue_idx); 642 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 643 644 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 645 } 646 647 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx) 648 { 649 uint32_t n, ent = 0; 650 651 n = igb_ivar_entry_rx(queue_idx); 652 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff; 653 654 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; 655 } 656 657 typedef struct E1000E_RingInfo_st { 658 int dbah; 659 int dbal; 660 int dlen; 661 int dh; 662 int dt; 663 int idx; 664 } E1000E_RingInfo; 665 666 static inline bool 667 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r) 668 { 669 return core->mac[r->dh] == core->mac[r->dt] || 670 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 671 } 672 673 static inline uint64_t 674 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r) 675 { 676 uint64_t bah = core->mac[r->dbah]; 677 uint64_t bal = core->mac[r->dbal]; 678 679 return (bah << 32) + bal; 680 } 681 682 static inline uint64_t 683 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r) 684 { 685 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 686 } 687 688 static inline void 689 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count) 690 { 691 core->mac[r->dh] += count; 692 693 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 694 core->mac[r->dh] = 0; 695 } 696 } 697 698 static inline uint32_t 699 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r) 700 { 701 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 702 core->mac[r->dh], core->mac[r->dt]); 703 704 if (core->mac[r->dh] <= core->mac[r->dt]) { 705 return core->mac[r->dt] - core->mac[r->dh]; 706 } 707 708 if (core->mac[r->dh] > core->mac[r->dt]) { 709 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 710 core->mac[r->dt] - core->mac[r->dh]; 711 } 712 713 g_assert_not_reached(); 714 return 0; 715 } 716 717 static inline bool 718 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r) 719 { 720 return core->mac[r->dlen] > 0; 721 } 722 723 typedef struct IGB_TxRing_st { 724 const E1000E_RingInfo *i; 725 struct igb_tx *tx; 726 } IGB_TxRing; 727 728 static inline int 729 igb_mq_queue_idx(int base_reg_idx, int reg_idx) 730 { 731 return (reg_idx - base_reg_idx) / 16; 732 } 733 734 static inline void 735 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx) 736 { 737 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 738 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 }, 739 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }, 740 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 }, 741 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 }, 742 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 }, 743 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 }, 744 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 }, 745 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 }, 746 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 }, 747 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 }, 748 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 }, 749 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 }, 750 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 }, 751 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 }, 752 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 }, 753 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 } 754 }; 755 756 assert(idx < ARRAY_SIZE(i)); 757 758 txr->i = &i[idx]; 759 txr->tx = &core->tx[idx]; 760 } 761 762 typedef struct E1000E_RxRing_st { 763 const E1000E_RingInfo *i; 764 } E1000E_RxRing; 765 766 static inline void 767 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx) 768 { 769 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = { 770 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 771 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }, 772 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 }, 773 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 }, 774 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 }, 775 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 }, 776 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 }, 777 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 }, 778 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 }, 779 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 }, 780 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 }, 781 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 }, 782 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 }, 783 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 }, 784 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 }, 785 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 } 786 }; 787 788 assert(idx < ARRAY_SIZE(i)); 789 790 rxr->i = &i[idx]; 791 } 792 793 static uint32_t 794 igb_txdesc_writeback(IGBCore *core, dma_addr_t base, 795 union e1000_adv_tx_desc *tx_desc, 796 const E1000E_RingInfo *txi) 797 { 798 PCIDevice *d; 799 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len); 800 uint64_t tdwba; 801 802 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2]; 803 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32; 804 805 if (!(cmd_type_len & E1000_TXD_CMD_RS)) { 806 return 0; 807 } 808 809 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 810 if (!d) { 811 d = core->owner; 812 } 813 814 if (tdwba & 1) { 815 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]); 816 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer)); 817 } else { 818 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD; 819 820 tx_desc->wb.status = cpu_to_le32(status); 821 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb), 822 &tx_desc->wb, sizeof(tx_desc->wb)); 823 } 824 825 return igb_tx_wb_eic(core, txi->idx); 826 } 827 828 static inline bool 829 igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi) 830 { 831 bool vmdq = core->mac[MRQC] & 1; 832 uint16_t qn = txi->idx; 833 uint16_t pool = qn % IGB_NUM_VM_POOLS; 834 835 return (core->mac[TCTL] & E1000_TCTL_EN) && 836 (!vmdq || core->mac[VFTE] & BIT(pool)) && 837 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE); 838 } 839 840 static void 841 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr) 842 { 843 PCIDevice *d; 844 dma_addr_t base; 845 union e1000_adv_tx_desc desc; 846 const E1000E_RingInfo *txi = txr->i; 847 uint32_t eic = 0; 848 849 if (!igb_tx_enabled(core, txi)) { 850 trace_e1000e_tx_disabled(); 851 return; 852 } 853 854 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8); 855 if (!d) { 856 d = core->owner; 857 } 858 859 while (!igb_ring_empty(core, txi)) { 860 base = igb_ring_head_descr(core, txi); 861 862 pci_dma_read(d, base, &desc, sizeof(desc)); 863 864 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr, 865 desc.read.cmd_type_len, desc.wb.status); 866 867 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx); 868 igb_ring_advance(core, txi, 1); 869 eic |= igb_txdesc_writeback(core, base, &desc, txi); 870 } 871 872 if (eic) { 873 core->mac[EICR] |= eic; 874 igb_set_interrupt_cause(core, E1000_ICR_TXDW); 875 } 876 877 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, d); 878 } 879 880 static uint32_t 881 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r) 882 { 883 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2]; 884 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK; 885 if (bsizepkt) { 886 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT; 887 } 888 889 return e1000x_rxbufsize(core->mac[RCTL]); 890 } 891 892 static bool 893 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size) 894 { 895 uint32_t bufs = igb_ring_free_descr_num(core, r); 896 uint32_t bufsize = igb_rxbufsize(core, r); 897 898 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize); 899 900 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 901 bufsize; 902 } 903 904 void 905 igb_start_recv(IGBCore *core) 906 { 907 int i; 908 909 trace_e1000e_rx_start_recv(); 910 911 for (i = 0; i <= core->max_queue_num; i++) { 912 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 913 } 914 } 915 916 bool 917 igb_can_receive(IGBCore *core) 918 { 919 int i; 920 921 if (!e1000x_rx_ready(core->owner, core->mac)) { 922 return false; 923 } 924 925 for (i = 0; i < IGB_NUM_QUEUES; i++) { 926 E1000E_RxRing rxr; 927 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { 928 continue; 929 } 930 931 igb_rx_ring_init(core, &rxr, i); 932 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) { 933 trace_e1000e_rx_can_recv(); 934 return true; 935 } 936 } 937 938 trace_e1000e_rx_can_recv_rings_full(); 939 return false; 940 } 941 942 ssize_t 943 igb_receive(IGBCore *core, const uint8_t *buf, size_t size) 944 { 945 const struct iovec iov = { 946 .iov_base = (uint8_t *)buf, 947 .iov_len = size 948 }; 949 950 return igb_receive_iov(core, &iov, 1); 951 } 952 953 static inline bool 954 igb_rx_l3_cso_enabled(IGBCore *core) 955 { 956 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 957 } 958 959 static inline bool 960 igb_rx_l4_cso_enabled(IGBCore *core) 961 { 962 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 963 } 964 965 static bool 966 igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size) 967 { 968 uint16_t pool = qn % IGB_NUM_VM_POOLS; 969 bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE); 970 int max_ethernet_lpe_size = 971 core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK; 972 int max_ethernet_vlan_size = 1522; 973 974 return size > (lpe ? max_ethernet_lpe_size : max_ethernet_vlan_size); 975 } 976 977 static uint16_t igb_receive_assign(IGBCore *core, const L2Header *l2_header, 978 size_t size, E1000E_RSSInfo *rss_info, 979 bool *external_tx) 980 { 981 static const int ta_shift[] = { 4, 3, 2, 0 }; 982 const struct eth_header *ehdr = &l2_header->eth; 983 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL]; 984 uint16_t queues = 0; 985 uint16_t oversized = 0; 986 uint16_t vid = be16_to_cpu(l2_header->vlan.h_tci) & VLAN_VID_MASK; 987 int i; 988 989 memset(rss_info, 0, sizeof(E1000E_RSSInfo)); 990 991 if (external_tx) { 992 *external_tx = true; 993 } 994 995 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) && 996 !e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(ehdr))) { 997 return queues; 998 } 999 1000 if (core->mac[MRQC] & 1) { 1001 if (is_broadcast_ether_addr(ehdr->h_dest)) { 1002 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1003 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) { 1004 queues |= BIT(i); 1005 } 1006 } 1007 } else { 1008 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) { 1009 if (!(macp[1] & E1000_RAH_AV)) { 1010 continue; 1011 } 1012 ra[0] = cpu_to_le32(macp[0]); 1013 ra[1] = cpu_to_le32(macp[1]); 1014 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 1015 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 1016 } 1017 } 1018 1019 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 1020 if (!(macp[1] & E1000_RAH_AV)) { 1021 continue; 1022 } 1023 ra[0] = cpu_to_le32(macp[0]); 1024 ra[1] = cpu_to_le32(macp[1]); 1025 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 1026 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1; 1027 } 1028 } 1029 1030 if (!queues) { 1031 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA); 1032 1033 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; 1034 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff; 1035 if (macp[f >> 5] & (1 << (f & 0x1f))) { 1036 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1037 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) { 1038 queues |= BIT(i); 1039 } 1040 } 1041 } 1042 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) { 1043 *external_tx = false; 1044 } 1045 } 1046 1047 if (e1000x_vlan_rx_filter_enabled(core->mac)) { 1048 uint16_t mask = 0; 1049 1050 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) { 1051 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 1052 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid && 1053 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) { 1054 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK; 1055 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT; 1056 } 1057 } 1058 } else { 1059 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1060 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) { 1061 mask |= BIT(i); 1062 } 1063 } 1064 } 1065 1066 queues &= mask; 1067 } 1068 1069 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx && 1070 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) { 1071 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK; 1072 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT); 1073 } 1074 1075 queues &= core->mac[VFRE]; 1076 if (queues) { 1077 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1078 if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) { 1079 oversized |= BIT(i); 1080 } 1081 } 1082 /* 8.19.37 increment ROC if packet is oversized for all queues */ 1083 if (oversized == queues) { 1084 trace_e1000x_rx_oversized(size); 1085 e1000x_inc_reg_if_not_full(core->mac, ROC); 1086 } 1087 queues &= ~oversized; 1088 } 1089 1090 if (queues) { 1091 igb_rss_parse_packet(core, core->rx_pkt, 1092 external_tx != NULL, rss_info); 1093 /* Sec 8.26.1: PQn = VFn + VQn*8 */ 1094 if (rss_info->queue & 1) { 1095 for (i = 0; i < IGB_NUM_VM_POOLS; i++) { 1096 if ((queues & BIT(i)) && 1097 (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) { 1098 queues |= BIT(i + IGB_NUM_VM_POOLS); 1099 queues &= ~BIT(i); 1100 } 1101 } 1102 } 1103 } 1104 } else { 1105 bool accepted = e1000x_rx_group_filter(core->mac, ehdr); 1106 if (!accepted) { 1107 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) { 1108 if (!(macp[1] & E1000_RAH_AV)) { 1109 continue; 1110 } 1111 ra[0] = cpu_to_le32(macp[0]); 1112 ra[1] = cpu_to_le32(macp[1]); 1113 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) { 1114 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2, 1115 MAC_ARG(ehdr->h_dest)); 1116 1117 accepted = true; 1118 break; 1119 } 1120 } 1121 } 1122 1123 if (accepted) { 1124 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info); 1125 queues = BIT(rss_info->queue); 1126 } 1127 } 1128 1129 return queues; 1130 } 1131 1132 static inline void 1133 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1134 hwaddr *buff_addr) 1135 { 1136 *buff_addr = le64_to_cpu(desc->buffer_addr); 1137 } 1138 1139 static inline void 1140 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1141 hwaddr *buff_addr) 1142 { 1143 *buff_addr = le64_to_cpu(desc->read.pkt_addr); 1144 } 1145 1146 static inline void 1147 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1148 hwaddr *buff_addr) 1149 { 1150 if (igb_rx_use_legacy_descriptor(core)) { 1151 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr); 1152 } else { 1153 igb_read_adv_rx_descr(core, &desc->adv, buff_addr); 1154 } 1155 } 1156 1157 static void 1158 igb_verify_csum_in_sw(IGBCore *core, 1159 struct NetRxPkt *pkt, 1160 uint32_t *status_flags, 1161 EthL4HdrProto l4hdr_proto) 1162 { 1163 bool csum_valid; 1164 uint32_t csum_error; 1165 1166 if (igb_rx_l3_cso_enabled(core)) { 1167 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1168 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1169 } else { 1170 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1171 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1172 } 1173 } else { 1174 trace_e1000e_rx_metadata_l3_cso_disabled(); 1175 } 1176 1177 if (!igb_rx_l4_cso_enabled(core)) { 1178 trace_e1000e_rx_metadata_l4_cso_disabled(); 1179 return; 1180 } 1181 1182 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1183 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1184 return; 1185 } 1186 1187 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1188 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1189 1190 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1191 *status_flags |= E1000_RXD_STAT_UDPCS; 1192 } 1193 } 1194 1195 static void 1196 igb_build_rx_metadata(IGBCore *core, 1197 struct NetRxPkt *pkt, 1198 bool is_eop, 1199 const E1000E_RSSInfo *rss_info, 1200 uint16_t *pkt_info, uint16_t *hdr_info, 1201 uint32_t *rss, 1202 uint32_t *status_flags, 1203 uint16_t *ip_id, 1204 uint16_t *vlan_tag) 1205 { 1206 struct virtio_net_hdr *vhdr; 1207 bool hasip4, hasip6; 1208 EthL4HdrProto l4hdr_proto; 1209 1210 *status_flags = E1000_RXD_STAT_DD; 1211 1212 /* No additional metadata needed for non-EOP descriptors */ 1213 /* TODO: EOP apply only to status so don't skip whole function. */ 1214 if (!is_eop) { 1215 goto func_exit; 1216 } 1217 1218 *status_flags |= E1000_RXD_STAT_EOP; 1219 1220 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1221 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1222 1223 /* VLAN state */ 1224 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1225 *status_flags |= E1000_RXD_STAT_VP; 1226 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1227 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1228 } 1229 1230 /* Packet parsing results */ 1231 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1232 if (rss_info->enabled) { 1233 *rss = cpu_to_le32(rss_info->hash); 1234 trace_igb_rx_metadata_rss(*rss); 1235 } 1236 } else if (hasip4) { 1237 *status_flags |= E1000_RXD_STAT_IPIDV; 1238 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1239 trace_e1000e_rx_metadata_ip_id(*ip_id); 1240 } 1241 1242 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) { 1243 *status_flags |= E1000_RXD_STAT_ACK; 1244 trace_e1000e_rx_metadata_ack(); 1245 } 1246 1247 if (pkt_info) { 1248 *pkt_info = rss_info->enabled ? rss_info->type : 0; 1249 1250 if (hasip4) { 1251 *pkt_info |= E1000_ADVRXD_PKT_IP4; 1252 } 1253 1254 if (hasip6) { 1255 *pkt_info |= E1000_ADVRXD_PKT_IP6; 1256 } 1257 1258 switch (l4hdr_proto) { 1259 case ETH_L4_HDR_PROTO_TCP: 1260 *pkt_info |= E1000_ADVRXD_PKT_TCP; 1261 break; 1262 1263 case ETH_L4_HDR_PROTO_UDP: 1264 *pkt_info |= E1000_ADVRXD_PKT_UDP; 1265 break; 1266 1267 default: 1268 break; 1269 } 1270 } 1271 1272 if (hdr_info) { 1273 *hdr_info = 0; 1274 } 1275 1276 /* RX CSO information */ 1277 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1278 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1279 goto func_exit; 1280 } 1281 1282 vhdr = net_rx_pkt_get_vhdr(pkt); 1283 1284 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1285 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1286 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1287 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1288 goto func_exit; 1289 } 1290 1291 if (igb_rx_l3_cso_enabled(core)) { 1292 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1293 } else { 1294 trace_e1000e_rx_metadata_l3_cso_disabled(); 1295 } 1296 1297 if (igb_rx_l4_cso_enabled(core)) { 1298 switch (l4hdr_proto) { 1299 case ETH_L4_HDR_PROTO_TCP: 1300 *status_flags |= E1000_RXD_STAT_TCPCS; 1301 break; 1302 1303 case ETH_L4_HDR_PROTO_UDP: 1304 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1305 break; 1306 1307 default: 1308 break; 1309 } 1310 } else { 1311 trace_e1000e_rx_metadata_l4_cso_disabled(); 1312 } 1313 1314 func_exit: 1315 trace_e1000e_rx_metadata_status_flags(*status_flags); 1316 *status_flags = cpu_to_le32(*status_flags); 1317 } 1318 1319 static inline void 1320 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, 1321 struct NetRxPkt *pkt, 1322 const E1000E_RSSInfo *rss_info, 1323 uint16_t length) 1324 { 1325 uint32_t status_flags, rss; 1326 uint16_t ip_id; 1327 1328 assert(!rss_info->enabled); 1329 desc->length = cpu_to_le16(length); 1330 desc->csum = 0; 1331 1332 igb_build_rx_metadata(core, pkt, pkt != NULL, 1333 rss_info, 1334 NULL, NULL, &rss, 1335 &status_flags, &ip_id, 1336 &desc->special); 1337 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1338 desc->status = (uint8_t) le32_to_cpu(status_flags); 1339 } 1340 1341 static inline void 1342 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, 1343 struct NetRxPkt *pkt, 1344 const E1000E_RSSInfo *rss_info, 1345 uint16_t length) 1346 { 1347 memset(&desc->wb, 0, sizeof(desc->wb)); 1348 1349 desc->wb.upper.length = cpu_to_le16(length); 1350 1351 igb_build_rx_metadata(core, pkt, pkt != NULL, 1352 rss_info, 1353 &desc->wb.lower.lo_dword.pkt_info, 1354 &desc->wb.lower.lo_dword.hdr_info, 1355 &desc->wb.lower.hi_dword.rss, 1356 &desc->wb.upper.status_error, 1357 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1358 &desc->wb.upper.vlan); 1359 } 1360 1361 static inline void 1362 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc, 1363 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length) 1364 { 1365 if (igb_rx_use_legacy_descriptor(core)) { 1366 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length); 1367 } else { 1368 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length); 1369 } 1370 } 1371 1372 static inline void 1373 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr, 1374 union e1000_rx_desc_union *desc, dma_addr_t len) 1375 { 1376 if (igb_rx_use_legacy_descriptor(core)) { 1377 struct e1000_rx_desc *d = &desc->legacy; 1378 size_t offset = offsetof(struct e1000_rx_desc, status); 1379 uint8_t status = d->status; 1380 1381 d->status &= ~E1000_RXD_STAT_DD; 1382 pci_dma_write(dev, addr, desc, len); 1383 1384 if (status & E1000_RXD_STAT_DD) { 1385 d->status = status; 1386 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1387 } 1388 } else { 1389 union e1000_adv_rx_desc *d = &desc->adv; 1390 size_t offset = 1391 offsetof(union e1000_adv_rx_desc, wb.upper.status_error); 1392 uint32_t status = d->wb.upper.status_error; 1393 1394 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1395 pci_dma_write(dev, addr, desc, len); 1396 1397 if (status & E1000_RXD_STAT_DD) { 1398 d->wb.upper.status_error = status; 1399 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1400 } 1401 } 1402 } 1403 1404 static void 1405 igb_write_to_rx_buffers(IGBCore *core, 1406 PCIDevice *d, 1407 hwaddr ba, 1408 uint16_t *written, 1409 const char *data, 1410 dma_addr_t data_len) 1411 { 1412 trace_igb_rx_desc_buff_write(ba, *written, data, data_len); 1413 pci_dma_write(d, ba + *written, data, data_len); 1414 *written += data_len; 1415 } 1416 1417 static void 1418 igb_update_rx_stats(IGBCore *core, const E1000E_RingInfo *rxi, 1419 size_t pkt_size, size_t pkt_fcs_size) 1420 { 1421 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1422 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1423 1424 if (core->mac[MRQC] & 1) { 1425 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS; 1426 1427 core->mac[PVFGORC0 + (pool * 64)] += pkt_size + 4; 1428 core->mac[PVFGPRC0 + (pool * 64)]++; 1429 if (pkt_type == ETH_PKT_MCAST) { 1430 core->mac[PVFMPRC0 + (pool * 64)]++; 1431 } 1432 } 1433 } 1434 1435 static inline bool 1436 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi) 1437 { 1438 return igb_ring_free_descr_num(core, rxi) == 1439 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16; 1440 } 1441 1442 static void 1443 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt, 1444 const E1000E_RxRing *rxr, 1445 const E1000E_RSSInfo *rss_info) 1446 { 1447 PCIDevice *d; 1448 dma_addr_t base; 1449 union e1000_rx_desc_union desc; 1450 size_t desc_size; 1451 size_t desc_offset = 0; 1452 size_t iov_ofs = 0; 1453 1454 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1455 size_t size = net_rx_pkt_get_total_len(pkt); 1456 size_t total_size = size + e1000x_fcs_len(core->mac); 1457 const E1000E_RingInfo *rxi = rxr->i; 1458 size_t bufsize = igb_rxbufsize(core, rxi); 1459 1460 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8); 1461 if (!d) { 1462 d = core->owner; 1463 } 1464 1465 do { 1466 hwaddr ba; 1467 uint16_t written = 0; 1468 bool is_last = false; 1469 1470 desc_size = total_size - desc_offset; 1471 1472 if (desc_size > bufsize) { 1473 desc_size = bufsize; 1474 } 1475 1476 if (igb_ring_empty(core, rxi)) { 1477 return; 1478 } 1479 1480 base = igb_ring_head_descr(core, rxi); 1481 1482 pci_dma_read(d, base, &desc, core->rx_desc_len); 1483 1484 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1485 1486 igb_read_rx_descr(core, &desc, &ba); 1487 1488 if (ba) { 1489 if (desc_offset < size) { 1490 static const uint32_t fcs_pad; 1491 size_t iov_copy; 1492 size_t copy_size = size - desc_offset; 1493 if (copy_size > bufsize) { 1494 copy_size = bufsize; 1495 } 1496 1497 /* Copy packet payload */ 1498 while (copy_size) { 1499 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1500 1501 igb_write_to_rx_buffers(core, d, ba, &written, 1502 iov->iov_base + iov_ofs, iov_copy); 1503 1504 copy_size -= iov_copy; 1505 iov_ofs += iov_copy; 1506 if (iov_ofs == iov->iov_len) { 1507 iov++; 1508 iov_ofs = 0; 1509 } 1510 } 1511 1512 if (desc_offset + desc_size >= total_size) { 1513 /* Simulate FCS checksum presence in the last descriptor */ 1514 igb_write_to_rx_buffers(core, d, ba, &written, 1515 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1516 } 1517 } 1518 } else { /* as per intel docs; skip descriptors with null buf addr */ 1519 trace_e1000e_rx_null_descriptor(); 1520 } 1521 desc_offset += desc_size; 1522 if (desc_offset >= total_size) { 1523 is_last = true; 1524 } 1525 1526 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1527 rss_info, written); 1528 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len); 1529 1530 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1531 1532 } while (desc_offset < total_size); 1533 1534 igb_update_rx_stats(core, rxi, size, total_size); 1535 } 1536 1537 static bool 1538 igb_rx_strip_vlan(IGBCore *core, const E1000E_RingInfo *rxi) 1539 { 1540 if (core->mac[MRQC] & 1) { 1541 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS; 1542 /* Sec 7.10.3.8: CTRL.VME is ignored, only VMOLR/RPLOLR is used */ 1543 return (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) ? 1544 core->mac[RPLOLR] & E1000_RPLOLR_STRVLAN : 1545 core->mac[VMOLR0 + pool] & E1000_VMOLR_STRVLAN; 1546 } 1547 1548 return e1000x_vlan_enabled(core->mac); 1549 } 1550 1551 static inline void 1552 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt) 1553 { 1554 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1555 1556 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1557 net_rx_pkt_fix_l4_csum(pkt); 1558 } 1559 } 1560 1561 ssize_t 1562 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt) 1563 { 1564 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL); 1565 } 1566 1567 static ssize_t 1568 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, 1569 bool has_vnet, bool *external_tx) 1570 { 1571 uint16_t queues = 0; 1572 uint32_t causes = 0; 1573 union { 1574 L2Header l2_header; 1575 uint8_t octets[ETH_ZLEN]; 1576 } buf; 1577 struct iovec min_iov; 1578 size_t size, orig_size; 1579 size_t iov_ofs = 0; 1580 E1000E_RxRing rxr; 1581 E1000E_RSSInfo rss_info; 1582 size_t total_size; 1583 int i; 1584 1585 trace_e1000e_rx_receive_iov(iovcnt); 1586 1587 if (external_tx) { 1588 *external_tx = true; 1589 } 1590 1591 if (!e1000x_hw_rx_enabled(core->mac)) { 1592 return -1; 1593 } 1594 1595 /* Pull virtio header in */ 1596 if (has_vnet) { 1597 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1598 iov_ofs = sizeof(struct virtio_net_hdr); 1599 } else { 1600 net_rx_pkt_unset_vhdr(core->rx_pkt); 1601 } 1602 1603 orig_size = iov_size(iov, iovcnt); 1604 size = orig_size - iov_ofs; 1605 1606 /* Pad to minimum Ethernet frame length */ 1607 if (size < sizeof(buf)) { 1608 iov_to_buf(iov, iovcnt, iov_ofs, &buf, size); 1609 memset(&buf.octets[size], 0, sizeof(buf) - size); 1610 e1000x_inc_reg_if_not_full(core->mac, RUC); 1611 min_iov.iov_base = &buf; 1612 min_iov.iov_len = size = sizeof(buf); 1613 iovcnt = 1; 1614 iov = &min_iov; 1615 iov_ofs = 0; 1616 } else { 1617 iov_to_buf(iov, iovcnt, iov_ofs, &buf, sizeof(buf.l2_header)); 1618 } 1619 1620 /* Discard oversized packets if !LPE and !SBP. */ 1621 if (e1000x_is_oversized(core->mac, size)) { 1622 return orig_size; 1623 } 1624 1625 net_rx_pkt_set_packet_type(core->rx_pkt, 1626 get_eth_packet_type(&buf.l2_header.eth)); 1627 net_rx_pkt_set_protocols(core->rx_pkt, iov, iovcnt, iov_ofs); 1628 1629 queues = igb_receive_assign(core, &buf.l2_header, size, 1630 &rss_info, external_tx); 1631 if (!queues) { 1632 trace_e1000e_rx_flt_dropped(); 1633 return orig_size; 1634 } 1635 1636 for (i = 0; i < IGB_NUM_QUEUES; i++) { 1637 if (!(queues & BIT(i)) || 1638 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) { 1639 continue; 1640 } 1641 1642 igb_rx_ring_init(core, &rxr, i); 1643 1644 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1645 igb_rx_strip_vlan(core, rxr.i), 1646 core->mac[VET] & 0xffff); 1647 1648 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1649 e1000x_fcs_len(core->mac); 1650 1651 if (!igb_has_rxbufs(core, rxr.i, total_size)) { 1652 causes |= E1000_ICS_RXO; 1653 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1654 continue; 1655 } 1656 1657 causes |= E1000_ICR_RXDW; 1658 1659 igb_rx_fix_l4_csum(core, core->rx_pkt); 1660 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1661 1662 /* Check if receive descriptor minimum threshold hit */ 1663 if (igb_rx_descr_threshold_hit(core, rxr.i)) { 1664 causes |= E1000_ICS_RXDMT0; 1665 } 1666 1667 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx); 1668 1669 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1670 } 1671 1672 trace_e1000e_rx_interrupt_set(causes); 1673 igb_set_interrupt_cause(core, causes); 1674 1675 return orig_size; 1676 } 1677 1678 static inline bool 1679 igb_have_autoneg(IGBCore *core) 1680 { 1681 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN; 1682 } 1683 1684 static void igb_update_flowctl_status(IGBCore *core) 1685 { 1686 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) { 1687 trace_e1000e_link_autoneg_flowctl(true); 1688 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1689 } else { 1690 trace_e1000e_link_autoneg_flowctl(false); 1691 } 1692 } 1693 1694 static inline void 1695 igb_link_down(IGBCore *core) 1696 { 1697 e1000x_update_regs_on_link_down(core->mac, core->phy); 1698 igb_update_flowctl_status(core); 1699 } 1700 1701 static inline void 1702 igb_set_phy_ctrl(IGBCore *core, uint16_t val) 1703 { 1704 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1705 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART); 1706 1707 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) { 1708 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer); 1709 } 1710 } 1711 1712 void igb_core_set_link_status(IGBCore *core) 1713 { 1714 NetClientState *nc = qemu_get_queue(core->owner_nic); 1715 uint32_t old_status = core->mac[STATUS]; 1716 1717 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1718 1719 if (nc->link_down) { 1720 e1000x_update_regs_on_link_down(core->mac, core->phy); 1721 } else { 1722 if (igb_have_autoneg(core) && 1723 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 1724 e1000x_restart_autoneg(core->mac, core->phy, 1725 core->autoneg_timer); 1726 } else { 1727 e1000x_update_regs_on_link_up(core->mac, core->phy); 1728 igb_start_recv(core); 1729 } 1730 } 1731 1732 if (core->mac[STATUS] != old_status) { 1733 igb_set_interrupt_cause(core, E1000_ICR_LSC); 1734 } 1735 } 1736 1737 static void 1738 igb_set_ctrl(IGBCore *core, int index, uint32_t val) 1739 { 1740 trace_e1000e_core_ctrl_write(index, val); 1741 1742 /* RST is self clearing */ 1743 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1744 core->mac[CTRL_DUP] = core->mac[CTRL]; 1745 1746 trace_e1000e_link_set_params( 1747 !!(val & E1000_CTRL_ASDE), 1748 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1749 !!(val & E1000_CTRL_FRCSPD), 1750 !!(val & E1000_CTRL_FRCDPX), 1751 !!(val & E1000_CTRL_RFCE), 1752 !!(val & E1000_CTRL_TFCE)); 1753 1754 if (val & E1000_CTRL_RST) { 1755 trace_e1000e_core_ctrl_sw_reset(); 1756 igb_reset(core, true); 1757 } 1758 1759 if (val & E1000_CTRL_PHY_RST) { 1760 trace_e1000e_core_ctrl_phy_reset(); 1761 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1762 } 1763 } 1764 1765 static void 1766 igb_set_rfctl(IGBCore *core, int index, uint32_t val) 1767 { 1768 trace_e1000e_rx_set_rfctl(val); 1769 1770 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1771 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1772 } 1773 1774 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1775 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1776 } 1777 1778 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1779 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1780 } 1781 1782 core->mac[RFCTL] = val; 1783 } 1784 1785 static void 1786 igb_calc_rxdesclen(IGBCore *core) 1787 { 1788 if (igb_rx_use_legacy_descriptor(core)) { 1789 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1790 } else { 1791 core->rx_desc_len = sizeof(union e1000_adv_rx_desc); 1792 } 1793 trace_e1000e_rx_desc_len(core->rx_desc_len); 1794 } 1795 1796 static void 1797 igb_set_rx_control(IGBCore *core, int index, uint32_t val) 1798 { 1799 core->mac[RCTL] = val; 1800 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1801 1802 if (val & E1000_RCTL_DTYP_MASK) { 1803 qemu_log_mask(LOG_GUEST_ERROR, 1804 "igb: RCTL.DTYP must be zero for compatibility"); 1805 } 1806 1807 if (val & E1000_RCTL_EN) { 1808 igb_calc_rxdesclen(core); 1809 igb_start_recv(core); 1810 } 1811 } 1812 1813 static inline void 1814 igb_clear_ims_bits(IGBCore *core, uint32_t bits) 1815 { 1816 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1817 core->mac[IMS] &= ~bits; 1818 } 1819 1820 static inline bool 1821 igb_postpone_interrupt(IGBIntrDelayTimer *timer) 1822 { 1823 if (timer->running) { 1824 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1825 1826 return true; 1827 } 1828 1829 if (timer->core->mac[timer->delay_reg] != 0) { 1830 igb_intrmgr_rearm_timer(timer); 1831 } 1832 1833 return false; 1834 } 1835 1836 static inline bool 1837 igb_eitr_should_postpone(IGBCore *core, int idx) 1838 { 1839 return igb_postpone_interrupt(&core->eitr[idx]); 1840 } 1841 1842 static void igb_send_msix(IGBCore *core) 1843 { 1844 uint32_t causes = core->mac[EICR] & core->mac[EIMS]; 1845 int vector; 1846 1847 for (vector = 0; vector < IGB_INTR_NUM; ++vector) { 1848 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) { 1849 1850 trace_e1000e_irq_msix_notify_vec(vector); 1851 igb_msix_notify(core, vector); 1852 } 1853 } 1854 } 1855 1856 static inline void 1857 igb_fix_icr_asserted(IGBCore *core) 1858 { 1859 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 1860 if (core->mac[ICR]) { 1861 core->mac[ICR] |= E1000_ICR_ASSERTED; 1862 } 1863 1864 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 1865 } 1866 1867 static void 1868 igb_update_interrupt_state(IGBCore *core) 1869 { 1870 uint32_t icr; 1871 uint32_t causes; 1872 uint32_t int_alloc; 1873 1874 icr = core->mac[ICR] & core->mac[IMS]; 1875 1876 if (core->mac[GPIE] & E1000_GPIE_MSIX_MODE) { 1877 if (icr) { 1878 causes = 0; 1879 if (icr & E1000_ICR_DRSTA) { 1880 int_alloc = core->mac[IVAR_MISC] & 0xff; 1881 if (int_alloc & E1000_IVAR_VALID) { 1882 causes |= BIT(int_alloc & 0x1f); 1883 } 1884 } 1885 /* Check if other bits (excluding the TCP Timer) are enabled. */ 1886 if (icr & ~E1000_ICR_DRSTA) { 1887 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff; 1888 if (int_alloc & E1000_IVAR_VALID) { 1889 causes |= BIT(int_alloc & 0x1f); 1890 } 1891 trace_e1000e_irq_add_msi_other(core->mac[EICR]); 1892 } 1893 core->mac[EICR] |= causes; 1894 } 1895 1896 if ((core->mac[EICR] & core->mac[EIMS])) { 1897 igb_send_msix(core); 1898 } 1899 } else { 1900 igb_fix_icr_asserted(core); 1901 1902 if (icr) { 1903 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER; 1904 } else { 1905 core->mac[EICR] &= ~E1000_EICR_OTHER; 1906 } 1907 1908 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 1909 core->mac[ICR], core->mac[IMS]); 1910 1911 if (msix_enabled(core->owner)) { 1912 if (icr) { 1913 trace_e1000e_irq_msix_notify_vec(0); 1914 msix_notify(core->owner, 0); 1915 } 1916 } else if (msi_enabled(core->owner)) { 1917 if (icr) { 1918 msi_notify(core->owner, 0); 1919 } 1920 } else { 1921 if (icr) { 1922 igb_raise_legacy_irq(core); 1923 } else { 1924 igb_lower_legacy_irq(core); 1925 } 1926 } 1927 } 1928 } 1929 1930 static void 1931 igb_set_interrupt_cause(IGBCore *core, uint32_t val) 1932 { 1933 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 1934 1935 core->mac[ICR] |= val; 1936 1937 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 1938 1939 igb_update_interrupt_state(core); 1940 } 1941 1942 static void igb_set_eics(IGBCore *core, int index, uint32_t val) 1943 { 1944 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1945 1946 trace_igb_irq_write_eics(val, msix); 1947 1948 core->mac[EICS] |= 1949 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1950 1951 /* 1952 * TODO: Move to igb_update_interrupt_state if EICS is modified in other 1953 * places. 1954 */ 1955 core->mac[EICR] = core->mac[EICS]; 1956 1957 igb_update_interrupt_state(core); 1958 } 1959 1960 static void igb_set_eims(IGBCore *core, int index, uint32_t val) 1961 { 1962 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 1963 1964 trace_igb_irq_write_eims(val, msix); 1965 1966 core->mac[EIMS] |= 1967 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); 1968 1969 igb_update_interrupt_state(core); 1970 } 1971 1972 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) 1973 { 1974 uint32_t ent = core->mac[VTIVAR_MISC + vfn]; 1975 1976 if ((ent & E1000_IVAR_VALID)) { 1977 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM); 1978 igb_update_interrupt_state(core); 1979 } 1980 } 1981 1982 static void mailbox_interrupt_to_pf(IGBCore *core) 1983 { 1984 igb_set_interrupt_cause(core, E1000_ICR_VMMB); 1985 } 1986 1987 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val) 1988 { 1989 uint16_t vfn = index - P2VMAILBOX0; 1990 1991 trace_igb_set_pfmailbox(vfn, val); 1992 1993 if (val & E1000_P2VMAILBOX_STS) { 1994 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS; 1995 mailbox_interrupt_to_vf(core, vfn); 1996 } 1997 1998 if (val & E1000_P2VMAILBOX_ACK) { 1999 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK; 2000 mailbox_interrupt_to_vf(core, vfn); 2001 } 2002 2003 /* Buffer Taken by PF (can be set only if the VFU is cleared). */ 2004 if (val & E1000_P2VMAILBOX_PFU) { 2005 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) { 2006 core->mac[index] |= E1000_P2VMAILBOX_PFU; 2007 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU; 2008 } 2009 } else { 2010 core->mac[index] &= ~E1000_P2VMAILBOX_PFU; 2011 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU; 2012 } 2013 2014 if (val & E1000_P2VMAILBOX_RVFU) { 2015 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU; 2016 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) | 2017 (E1000_MBVFICR_VFREQ_VF1 << vfn)); 2018 } 2019 } 2020 2021 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val) 2022 { 2023 uint16_t vfn = index - V2PMAILBOX0; 2024 2025 trace_igb_set_vfmailbox(vfn, val); 2026 2027 if (val & E1000_V2PMAILBOX_REQ) { 2028 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn; 2029 mailbox_interrupt_to_pf(core); 2030 } 2031 2032 if (val & E1000_V2PMAILBOX_ACK) { 2033 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn; 2034 mailbox_interrupt_to_pf(core); 2035 } 2036 2037 /* Buffer Taken by VF (can be set only if the PFU is cleared). */ 2038 if (val & E1000_V2PMAILBOX_VFU) { 2039 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) { 2040 core->mac[index] |= E1000_V2PMAILBOX_VFU; 2041 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU; 2042 } 2043 } else { 2044 core->mac[index] &= ~E1000_V2PMAILBOX_VFU; 2045 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU; 2046 } 2047 } 2048 2049 static void igb_vf_reset(IGBCore *core, uint16_t vfn) 2050 { 2051 uint16_t qn0 = vfn; 2052 uint16_t qn1 = vfn + IGB_NUM_VM_POOLS; 2053 2054 /* disable Rx and Tx for the VF*/ 2055 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; 2056 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE; 2057 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; 2058 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE; 2059 core->mac[VFRE] &= ~BIT(vfn); 2060 core->mac[VFTE] &= ~BIT(vfn); 2061 /* indicate VF reset to PF */ 2062 core->mac[VFLRE] |= BIT(vfn); 2063 /* VFLRE and mailbox use the same interrupt cause */ 2064 mailbox_interrupt_to_pf(core); 2065 } 2066 2067 static void igb_w1c(IGBCore *core, int index, uint32_t val) 2068 { 2069 core->mac[index] &= ~val; 2070 } 2071 2072 static void igb_set_eimc(IGBCore *core, int index, uint32_t val) 2073 { 2074 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2075 2076 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */ 2077 core->mac[EIMS] &= 2078 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2079 2080 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix); 2081 igb_update_interrupt_state(core); 2082 } 2083 2084 static void igb_set_eiac(IGBCore *core, int index, uint32_t val) 2085 { 2086 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2087 2088 if (msix) { 2089 trace_igb_irq_write_eiac(val); 2090 2091 /* 2092 * TODO: When using IOV, the bits that correspond to MSI-X vectors 2093 * that are assigned to a VF are read-only. 2094 */ 2095 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK); 2096 } 2097 } 2098 2099 static void igb_set_eiam(IGBCore *core, int index, uint32_t val) 2100 { 2101 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2102 2103 /* 2104 * TODO: When using IOV, the bits that correspond to MSI-X vectors that 2105 * are assigned to a VF are read-only. 2106 */ 2107 core->mac[EIAM] |= 2108 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2109 2110 trace_igb_irq_write_eiam(val, msix); 2111 } 2112 2113 static void igb_set_eicr(IGBCore *core, int index, uint32_t val) 2114 { 2115 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); 2116 2117 /* 2118 * TODO: In IOV mode, only bit zero of this vector is available for the PF 2119 * function. 2120 */ 2121 core->mac[EICR] &= 2122 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); 2123 2124 trace_igb_irq_write_eicr(val, msix); 2125 igb_update_interrupt_state(core); 2126 } 2127 2128 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val) 2129 { 2130 uint16_t vfn; 2131 2132 if (val & E1000_CTRL_RST) { 2133 vfn = (index - PVTCTRL0) / 0x40; 2134 igb_vf_reset(core, vfn); 2135 } 2136 } 2137 2138 static void igb_set_vteics(IGBCore *core, int index, uint32_t val) 2139 { 2140 uint16_t vfn = (index - PVTEICS0) / 0x40; 2141 2142 core->mac[index] = val; 2143 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2144 } 2145 2146 static void igb_set_vteims(IGBCore *core, int index, uint32_t val) 2147 { 2148 uint16_t vfn = (index - PVTEIMS0) / 0x40; 2149 2150 core->mac[index] = val; 2151 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2152 } 2153 2154 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val) 2155 { 2156 uint16_t vfn = (index - PVTEIMC0) / 0x40; 2157 2158 core->mac[index] = val; 2159 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2160 } 2161 2162 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val) 2163 { 2164 uint16_t vfn = (index - PVTEIAC0) / 0x40; 2165 2166 core->mac[index] = val; 2167 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2168 } 2169 2170 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val) 2171 { 2172 uint16_t vfn = (index - PVTEIAM0) / 0x40; 2173 2174 core->mac[index] = val; 2175 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2176 } 2177 2178 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val) 2179 { 2180 uint16_t vfn = (index - PVTEICR0) / 0x40; 2181 2182 core->mac[index] = val; 2183 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM)); 2184 } 2185 2186 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val) 2187 { 2188 uint16_t vfn = (index - VTIVAR); 2189 uint16_t qn = vfn; 2190 uint8_t ent; 2191 int n; 2192 2193 core->mac[index] = val; 2194 2195 /* Get assigned vector associated with queue Rx#0. */ 2196 if ((val & E1000_IVAR_VALID)) { 2197 n = igb_ivar_entry_rx(qn); 2198 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7))); 2199 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2200 } 2201 2202 /* Get assigned vector associated with queue Tx#0 */ 2203 ent = val >> 8; 2204 if ((ent & E1000_IVAR_VALID)) { 2205 n = igb_ivar_entry_tx(qn); 2206 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7))); 2207 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4); 2208 } 2209 2210 /* 2211 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now. 2212 */ 2213 } 2214 2215 static inline void 2216 igb_autoneg_timer(void *opaque) 2217 { 2218 IGBCore *core = opaque; 2219 if (!qemu_get_queue(core->owner_nic)->link_down) { 2220 e1000x_update_regs_on_autoneg_done(core->mac, core->phy); 2221 igb_start_recv(core); 2222 2223 igb_update_flowctl_status(core); 2224 /* signal link status change to the guest */ 2225 igb_set_interrupt_cause(core, E1000_ICR_LSC); 2226 } 2227 } 2228 2229 static inline uint16_t 2230 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2231 { 2232 uint16_t index = (addr & 0x1ffff) >> 2; 2233 return index + (mac_reg_access[index] & 0xfffe); 2234 } 2235 2236 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = { 2237 [MII_BMCR] = PHY_RW, 2238 [MII_BMSR] = PHY_R, 2239 [MII_PHYID1] = PHY_R, 2240 [MII_PHYID2] = PHY_R, 2241 [MII_ANAR] = PHY_RW, 2242 [MII_ANLPAR] = PHY_R, 2243 [MII_ANER] = PHY_R, 2244 [MII_ANNP] = PHY_RW, 2245 [MII_ANLPRNP] = PHY_R, 2246 [MII_CTRL1000] = PHY_RW, 2247 [MII_STAT1000] = PHY_R, 2248 [MII_EXTSTAT] = PHY_R, 2249 2250 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW, 2251 [IGP01E1000_PHY_PORT_STATUS] = PHY_R, 2252 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW, 2253 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R, 2254 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW, 2255 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W 2256 }; 2257 2258 static void 2259 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data) 2260 { 2261 assert(addr <= MAX_PHY_REG_ADDRESS); 2262 2263 if (addr == MII_BMCR) { 2264 igb_set_phy_ctrl(core, data); 2265 } else { 2266 core->phy[addr] = data; 2267 } 2268 } 2269 2270 static void 2271 igb_set_mdic(IGBCore *core, int index, uint32_t val) 2272 { 2273 uint32_t data = val & E1000_MDIC_DATA_MASK; 2274 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2275 2276 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2277 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2278 } else if (val & E1000_MDIC_OP_READ) { 2279 if (!(igb_phy_regcap[addr] & PHY_R)) { 2280 trace_igb_core_mdic_read_unhandled(addr); 2281 val |= E1000_MDIC_ERROR; 2282 } else { 2283 val = (val ^ data) | core->phy[addr]; 2284 trace_igb_core_mdic_read(addr, val); 2285 } 2286 } else if (val & E1000_MDIC_OP_WRITE) { 2287 if (!(igb_phy_regcap[addr] & PHY_W)) { 2288 trace_igb_core_mdic_write_unhandled(addr); 2289 val |= E1000_MDIC_ERROR; 2290 } else { 2291 trace_igb_core_mdic_write(addr, data); 2292 igb_phy_reg_write(core, addr, data); 2293 } 2294 } 2295 core->mac[MDIC] = val | E1000_MDIC_READY; 2296 2297 if (val & E1000_MDIC_INT_EN) { 2298 igb_set_interrupt_cause(core, E1000_ICR_MDAC); 2299 } 2300 } 2301 2302 static void 2303 igb_set_rdt(IGBCore *core, int index, uint32_t val) 2304 { 2305 core->mac[index] = val & 0xffff; 2306 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val); 2307 igb_start_recv(core); 2308 } 2309 2310 static void 2311 igb_set_status(IGBCore *core, int index, uint32_t val) 2312 { 2313 if ((val & E1000_STATUS_PHYRA) == 0) { 2314 core->mac[index] &= ~E1000_STATUS_PHYRA; 2315 } 2316 } 2317 2318 static void 2319 igb_set_ctrlext(IGBCore *core, int index, uint32_t val) 2320 { 2321 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2322 !!(val & E1000_CTRL_EXT_SPD_BYPS), 2323 !!(val & E1000_CTRL_EXT_PFRSTD)); 2324 2325 /* Zero self-clearing bits */ 2326 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2327 core->mac[CTRL_EXT] = val; 2328 2329 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) { 2330 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 2331 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI; 2332 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD; 2333 } 2334 } 2335 } 2336 2337 static void 2338 igb_set_pbaclr(IGBCore *core, int index, uint32_t val) 2339 { 2340 int i; 2341 2342 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2343 2344 if (!msix_enabled(core->owner)) { 2345 return; 2346 } 2347 2348 for (i = 0; i < IGB_INTR_NUM; i++) { 2349 if (core->mac[PBACLR] & BIT(i)) { 2350 msix_clr_pending(core->owner, i); 2351 } 2352 } 2353 } 2354 2355 static void 2356 igb_set_fcrth(IGBCore *core, int index, uint32_t val) 2357 { 2358 core->mac[FCRTH] = val & 0xFFF8; 2359 } 2360 2361 static void 2362 igb_set_fcrtl(IGBCore *core, int index, uint32_t val) 2363 { 2364 core->mac[FCRTL] = val & 0x8000FFF8; 2365 } 2366 2367 #define IGB_LOW_BITS_SET_FUNC(num) \ 2368 static void \ 2369 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \ 2370 { \ 2371 core->mac[index] = val & (BIT(num) - 1); \ 2372 } 2373 2374 IGB_LOW_BITS_SET_FUNC(4) 2375 IGB_LOW_BITS_SET_FUNC(13) 2376 IGB_LOW_BITS_SET_FUNC(16) 2377 2378 static void 2379 igb_set_dlen(IGBCore *core, int index, uint32_t val) 2380 { 2381 core->mac[index] = val & 0xffff0; 2382 } 2383 2384 static void 2385 igb_set_dbal(IGBCore *core, int index, uint32_t val) 2386 { 2387 core->mac[index] = val & E1000_XDBAL_MASK; 2388 } 2389 2390 static void 2391 igb_set_tdt(IGBCore *core, int index, uint32_t val) 2392 { 2393 IGB_TxRing txr; 2394 int qn = igb_mq_queue_idx(TDT0, index); 2395 2396 core->mac[index] = val & 0xffff; 2397 2398 igb_tx_ring_init(core, &txr, qn); 2399 igb_start_xmit(core, &txr); 2400 } 2401 2402 static void 2403 igb_set_ics(IGBCore *core, int index, uint32_t val) 2404 { 2405 trace_e1000e_irq_write_ics(val); 2406 igb_set_interrupt_cause(core, val); 2407 } 2408 2409 static void 2410 igb_set_imc(IGBCore *core, int index, uint32_t val) 2411 { 2412 trace_e1000e_irq_ims_clear_set_imc(val); 2413 igb_clear_ims_bits(core, val); 2414 igb_update_interrupt_state(core); 2415 } 2416 2417 static void 2418 igb_set_ims(IGBCore *core, int index, uint32_t val) 2419 { 2420 uint32_t valid_val = val & 0x77D4FBFD; 2421 2422 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2423 core->mac[IMS] |= valid_val; 2424 igb_update_interrupt_state(core); 2425 } 2426 2427 static void igb_commit_icr(IGBCore *core) 2428 { 2429 /* 2430 * If GPIE.NSICR = 0, then the clear of IMS will occur only if at 2431 * least one bit is set in the IMS and there is a true interrupt as 2432 * reflected in ICR.INTA. 2433 */ 2434 if ((core->mac[GPIE] & E1000_GPIE_NSICR) || 2435 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) { 2436 igb_clear_ims_bits(core, core->mac[IAM]); 2437 } 2438 2439 igb_update_interrupt_state(core); 2440 } 2441 2442 static void igb_set_icr(IGBCore *core, int index, uint32_t val) 2443 { 2444 uint32_t icr = core->mac[ICR] & ~val; 2445 2446 trace_igb_irq_icr_write(val, core->mac[ICR], icr); 2447 core->mac[ICR] = icr; 2448 igb_commit_icr(core); 2449 } 2450 2451 static uint32_t 2452 igb_mac_readreg(IGBCore *core, int index) 2453 { 2454 return core->mac[index]; 2455 } 2456 2457 static uint32_t 2458 igb_mac_ics_read(IGBCore *core, int index) 2459 { 2460 trace_e1000e_irq_read_ics(core->mac[ICS]); 2461 return core->mac[ICS]; 2462 } 2463 2464 static uint32_t 2465 igb_mac_ims_read(IGBCore *core, int index) 2466 { 2467 trace_e1000e_irq_read_ims(core->mac[IMS]); 2468 return core->mac[IMS]; 2469 } 2470 2471 static uint32_t 2472 igb_mac_swsm_read(IGBCore *core, int index) 2473 { 2474 uint32_t val = core->mac[SWSM]; 2475 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2476 return val; 2477 } 2478 2479 static uint32_t 2480 igb_mac_eitr_read(IGBCore *core, int index) 2481 { 2482 return core->eitr_guest_value[index - EITR0]; 2483 } 2484 2485 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index) 2486 { 2487 uint32_t val = core->mac[index]; 2488 2489 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK | 2490 E1000_V2PMAILBOX_RSTD); 2491 2492 return val; 2493 } 2494 2495 static uint32_t 2496 igb_mac_icr_read(IGBCore *core, int index) 2497 { 2498 uint32_t ret = core->mac[ICR]; 2499 trace_e1000e_irq_icr_read_entry(ret); 2500 2501 if (core->mac[GPIE] & E1000_GPIE_NSICR) { 2502 trace_igb_irq_icr_clear_gpie_nsicr(); 2503 core->mac[ICR] = 0; 2504 } else if (core->mac[IMS] == 0) { 2505 trace_e1000e_irq_icr_clear_zero_ims(); 2506 core->mac[ICR] = 0; 2507 } else if (!msix_enabled(core->owner)) { 2508 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2509 core->mac[ICR] = 0; 2510 } 2511 2512 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2513 igb_commit_icr(core); 2514 return ret; 2515 } 2516 2517 static uint32_t 2518 igb_mac_read_clr4(IGBCore *core, int index) 2519 { 2520 uint32_t ret = core->mac[index]; 2521 2522 core->mac[index] = 0; 2523 return ret; 2524 } 2525 2526 static uint32_t 2527 igb_mac_read_clr8(IGBCore *core, int index) 2528 { 2529 uint32_t ret = core->mac[index]; 2530 2531 core->mac[index] = 0; 2532 core->mac[index - 1] = 0; 2533 return ret; 2534 } 2535 2536 static uint32_t 2537 igb_get_ctrl(IGBCore *core, int index) 2538 { 2539 uint32_t val = core->mac[CTRL]; 2540 2541 trace_e1000e_link_read_params( 2542 !!(val & E1000_CTRL_ASDE), 2543 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2544 !!(val & E1000_CTRL_FRCSPD), 2545 !!(val & E1000_CTRL_FRCDPX), 2546 !!(val & E1000_CTRL_RFCE), 2547 !!(val & E1000_CTRL_TFCE)); 2548 2549 return val; 2550 } 2551 2552 static uint32_t igb_get_status(IGBCore *core, int index) 2553 { 2554 uint32_t res = core->mac[STATUS]; 2555 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner); 2556 2557 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2558 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2559 } else { 2560 res |= E1000_STATUS_FD; 2561 } 2562 2563 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2564 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2565 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2566 case E1000_CTRL_SPD_10: 2567 res |= E1000_STATUS_SPEED_10; 2568 break; 2569 case E1000_CTRL_SPD_100: 2570 res |= E1000_STATUS_SPEED_100; 2571 break; 2572 case E1000_CTRL_SPD_1000: 2573 default: 2574 res |= E1000_STATUS_SPEED_1000; 2575 break; 2576 } 2577 } else { 2578 res |= E1000_STATUS_SPEED_1000; 2579 } 2580 2581 if (num_vfs) { 2582 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT; 2583 res |= E1000_STATUS_IOV_MODE; 2584 } 2585 2586 /* 2587 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is 2588 * left set after E1000_CTRL_LRST is set. 2589 */ 2590 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) && 2591 !(core->mac[CTRL] & E1000_CTRL_LRST)) { 2592 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2593 } 2594 2595 return res; 2596 } 2597 2598 static void 2599 igb_mac_writereg(IGBCore *core, int index, uint32_t val) 2600 { 2601 core->mac[index] = val; 2602 } 2603 2604 static void 2605 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val) 2606 { 2607 uint32_t macaddr[2]; 2608 2609 core->mac[index] = val; 2610 2611 macaddr[0] = cpu_to_le32(core->mac[RA]); 2612 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2613 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2614 (uint8_t *) macaddr); 2615 2616 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2617 } 2618 2619 static void 2620 igb_set_eecd(IGBCore *core, int index, uint32_t val) 2621 { 2622 static const uint32_t ro_bits = E1000_EECD_PRES | 2623 E1000_EECD_AUTO_RD | 2624 E1000_EECD_SIZE_EX_MASK; 2625 2626 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2627 } 2628 2629 static void 2630 igb_set_eerd(IGBCore *core, int index, uint32_t val) 2631 { 2632 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2633 uint32_t flags = 0; 2634 uint32_t data = 0; 2635 2636 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2637 data = core->eeprom[addr]; 2638 flags = E1000_EERW_DONE; 2639 } 2640 2641 core->mac[EERD] = flags | 2642 (addr << E1000_EERW_ADDR_SHIFT) | 2643 (data << E1000_EERW_DATA_SHIFT); 2644 } 2645 2646 static void 2647 igb_set_eitr(IGBCore *core, int index, uint32_t val) 2648 { 2649 uint32_t eitr_num = index - EITR0; 2650 2651 trace_igb_irq_eitr_set(eitr_num, val); 2652 2653 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR; 2654 core->mac[index] = val & 0x7FFE; 2655 } 2656 2657 static void 2658 igb_update_rx_offloads(IGBCore *core) 2659 { 2660 int cso_state = igb_rx_l4_cso_enabled(core); 2661 2662 trace_e1000e_rx_set_cso(cso_state); 2663 2664 if (core->has_vnet) { 2665 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2666 cso_state, 0, 0, 0, 0); 2667 } 2668 } 2669 2670 static void 2671 igb_set_rxcsum(IGBCore *core, int index, uint32_t val) 2672 { 2673 core->mac[RXCSUM] = val; 2674 igb_update_rx_offloads(core); 2675 } 2676 2677 static void 2678 igb_set_gcr(IGBCore *core, int index, uint32_t val) 2679 { 2680 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2681 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2682 } 2683 2684 static uint32_t igb_get_systiml(IGBCore *core, int index) 2685 { 2686 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2687 return core->mac[SYSTIML]; 2688 } 2689 2690 static uint32_t igb_get_rxsatrh(IGBCore *core, int index) 2691 { 2692 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2693 return core->mac[RXSATRH]; 2694 } 2695 2696 static uint32_t igb_get_txstmph(IGBCore *core, int index) 2697 { 2698 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2699 return core->mac[TXSTMPH]; 2700 } 2701 2702 static void igb_set_timinca(IGBCore *core, int index, uint32_t val) 2703 { 2704 e1000x_set_timinca(core->mac, &core->timadj, val); 2705 } 2706 2707 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val) 2708 { 2709 core->mac[TIMADJH] = val; 2710 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2711 } 2712 2713 #define igb_getreg(x) [x] = igb_mac_readreg 2714 typedef uint32_t (*readops)(IGBCore *, int); 2715 static const readops igb_macreg_readops[] = { 2716 igb_getreg(WUFC), 2717 igb_getreg(MANC), 2718 igb_getreg(TOTL), 2719 igb_getreg(RDT0), 2720 igb_getreg(RDT1), 2721 igb_getreg(RDT2), 2722 igb_getreg(RDT3), 2723 igb_getreg(RDT4), 2724 igb_getreg(RDT5), 2725 igb_getreg(RDT6), 2726 igb_getreg(RDT7), 2727 igb_getreg(RDT8), 2728 igb_getreg(RDT9), 2729 igb_getreg(RDT10), 2730 igb_getreg(RDT11), 2731 igb_getreg(RDT12), 2732 igb_getreg(RDT13), 2733 igb_getreg(RDT14), 2734 igb_getreg(RDT15), 2735 igb_getreg(RDBAH0), 2736 igb_getreg(RDBAH1), 2737 igb_getreg(RDBAH2), 2738 igb_getreg(RDBAH3), 2739 igb_getreg(RDBAH4), 2740 igb_getreg(RDBAH5), 2741 igb_getreg(RDBAH6), 2742 igb_getreg(RDBAH7), 2743 igb_getreg(RDBAH8), 2744 igb_getreg(RDBAH9), 2745 igb_getreg(RDBAH10), 2746 igb_getreg(RDBAH11), 2747 igb_getreg(RDBAH12), 2748 igb_getreg(RDBAH13), 2749 igb_getreg(RDBAH14), 2750 igb_getreg(RDBAH15), 2751 igb_getreg(TDBAL0), 2752 igb_getreg(TDBAL1), 2753 igb_getreg(TDBAL2), 2754 igb_getreg(TDBAL3), 2755 igb_getreg(TDBAL4), 2756 igb_getreg(TDBAL5), 2757 igb_getreg(TDBAL6), 2758 igb_getreg(TDBAL7), 2759 igb_getreg(TDBAL8), 2760 igb_getreg(TDBAL9), 2761 igb_getreg(TDBAL10), 2762 igb_getreg(TDBAL11), 2763 igb_getreg(TDBAL12), 2764 igb_getreg(TDBAL13), 2765 igb_getreg(TDBAL14), 2766 igb_getreg(TDBAL15), 2767 igb_getreg(RDLEN0), 2768 igb_getreg(RDLEN1), 2769 igb_getreg(RDLEN2), 2770 igb_getreg(RDLEN3), 2771 igb_getreg(RDLEN4), 2772 igb_getreg(RDLEN5), 2773 igb_getreg(RDLEN6), 2774 igb_getreg(RDLEN7), 2775 igb_getreg(RDLEN8), 2776 igb_getreg(RDLEN9), 2777 igb_getreg(RDLEN10), 2778 igb_getreg(RDLEN11), 2779 igb_getreg(RDLEN12), 2780 igb_getreg(RDLEN13), 2781 igb_getreg(RDLEN14), 2782 igb_getreg(RDLEN15), 2783 igb_getreg(SRRCTL0), 2784 igb_getreg(SRRCTL1), 2785 igb_getreg(SRRCTL2), 2786 igb_getreg(SRRCTL3), 2787 igb_getreg(SRRCTL4), 2788 igb_getreg(SRRCTL5), 2789 igb_getreg(SRRCTL6), 2790 igb_getreg(SRRCTL7), 2791 igb_getreg(SRRCTL8), 2792 igb_getreg(SRRCTL9), 2793 igb_getreg(SRRCTL10), 2794 igb_getreg(SRRCTL11), 2795 igb_getreg(SRRCTL12), 2796 igb_getreg(SRRCTL13), 2797 igb_getreg(SRRCTL14), 2798 igb_getreg(SRRCTL15), 2799 igb_getreg(LATECOL), 2800 igb_getreg(XONTXC), 2801 igb_getreg(TDFH), 2802 igb_getreg(TDFT), 2803 igb_getreg(TDFHS), 2804 igb_getreg(TDFTS), 2805 igb_getreg(TDFPC), 2806 igb_getreg(WUS), 2807 igb_getreg(RDFH), 2808 igb_getreg(RDFT), 2809 igb_getreg(RDFHS), 2810 igb_getreg(RDFTS), 2811 igb_getreg(RDFPC), 2812 igb_getreg(GORCL), 2813 igb_getreg(MGTPRC), 2814 igb_getreg(EERD), 2815 igb_getreg(EIAC), 2816 igb_getreg(MANC2H), 2817 igb_getreg(RXCSUM), 2818 igb_getreg(GSCL_3), 2819 igb_getreg(GSCN_2), 2820 igb_getreg(FCAH), 2821 igb_getreg(FCRTH), 2822 igb_getreg(FLOP), 2823 igb_getreg(RXSTMPH), 2824 igb_getreg(TXSTMPL), 2825 igb_getreg(TIMADJL), 2826 igb_getreg(RDH0), 2827 igb_getreg(RDH1), 2828 igb_getreg(RDH2), 2829 igb_getreg(RDH3), 2830 igb_getreg(RDH4), 2831 igb_getreg(RDH5), 2832 igb_getreg(RDH6), 2833 igb_getreg(RDH7), 2834 igb_getreg(RDH8), 2835 igb_getreg(RDH9), 2836 igb_getreg(RDH10), 2837 igb_getreg(RDH11), 2838 igb_getreg(RDH12), 2839 igb_getreg(RDH13), 2840 igb_getreg(RDH14), 2841 igb_getreg(RDH15), 2842 igb_getreg(TDT0), 2843 igb_getreg(TDT1), 2844 igb_getreg(TDT2), 2845 igb_getreg(TDT3), 2846 igb_getreg(TDT4), 2847 igb_getreg(TDT5), 2848 igb_getreg(TDT6), 2849 igb_getreg(TDT7), 2850 igb_getreg(TDT8), 2851 igb_getreg(TDT9), 2852 igb_getreg(TDT10), 2853 igb_getreg(TDT11), 2854 igb_getreg(TDT12), 2855 igb_getreg(TDT13), 2856 igb_getreg(TDT14), 2857 igb_getreg(TDT15), 2858 igb_getreg(TNCRS), 2859 igb_getreg(RJC), 2860 igb_getreg(IAM), 2861 igb_getreg(GSCL_2), 2862 igb_getreg(TIPG), 2863 igb_getreg(FLMNGCTL), 2864 igb_getreg(FLMNGCNT), 2865 igb_getreg(TSYNCTXCTL), 2866 igb_getreg(EEMNGDATA), 2867 igb_getreg(CTRL_EXT), 2868 igb_getreg(SYSTIMH), 2869 igb_getreg(EEMNGCTL), 2870 igb_getreg(FLMNGDATA), 2871 igb_getreg(TSYNCRXCTL), 2872 igb_getreg(LEDCTL), 2873 igb_getreg(TCTL), 2874 igb_getreg(TCTL_EXT), 2875 igb_getreg(DTXCTL), 2876 igb_getreg(RXPBS), 2877 igb_getreg(TDH0), 2878 igb_getreg(TDH1), 2879 igb_getreg(TDH2), 2880 igb_getreg(TDH3), 2881 igb_getreg(TDH4), 2882 igb_getreg(TDH5), 2883 igb_getreg(TDH6), 2884 igb_getreg(TDH7), 2885 igb_getreg(TDH8), 2886 igb_getreg(TDH9), 2887 igb_getreg(TDH10), 2888 igb_getreg(TDH11), 2889 igb_getreg(TDH12), 2890 igb_getreg(TDH13), 2891 igb_getreg(TDH14), 2892 igb_getreg(TDH15), 2893 igb_getreg(ECOL), 2894 igb_getreg(DC), 2895 igb_getreg(RLEC), 2896 igb_getreg(XOFFTXC), 2897 igb_getreg(RFC), 2898 igb_getreg(RNBC), 2899 igb_getreg(MGTPTC), 2900 igb_getreg(TIMINCA), 2901 igb_getreg(FACTPS), 2902 igb_getreg(GSCL_1), 2903 igb_getreg(GSCN_0), 2904 igb_getreg(PBACLR), 2905 igb_getreg(FCTTV), 2906 igb_getreg(RXSATRL), 2907 igb_getreg(TORL), 2908 igb_getreg(TDLEN0), 2909 igb_getreg(TDLEN1), 2910 igb_getreg(TDLEN2), 2911 igb_getreg(TDLEN3), 2912 igb_getreg(TDLEN4), 2913 igb_getreg(TDLEN5), 2914 igb_getreg(TDLEN6), 2915 igb_getreg(TDLEN7), 2916 igb_getreg(TDLEN8), 2917 igb_getreg(TDLEN9), 2918 igb_getreg(TDLEN10), 2919 igb_getreg(TDLEN11), 2920 igb_getreg(TDLEN12), 2921 igb_getreg(TDLEN13), 2922 igb_getreg(TDLEN14), 2923 igb_getreg(TDLEN15), 2924 igb_getreg(MCC), 2925 igb_getreg(WUC), 2926 igb_getreg(EECD), 2927 igb_getreg(FCRTV), 2928 igb_getreg(TXDCTL0), 2929 igb_getreg(TXDCTL1), 2930 igb_getreg(TXDCTL2), 2931 igb_getreg(TXDCTL3), 2932 igb_getreg(TXDCTL4), 2933 igb_getreg(TXDCTL5), 2934 igb_getreg(TXDCTL6), 2935 igb_getreg(TXDCTL7), 2936 igb_getreg(TXDCTL8), 2937 igb_getreg(TXDCTL9), 2938 igb_getreg(TXDCTL10), 2939 igb_getreg(TXDCTL11), 2940 igb_getreg(TXDCTL12), 2941 igb_getreg(TXDCTL13), 2942 igb_getreg(TXDCTL14), 2943 igb_getreg(TXDCTL15), 2944 igb_getreg(TXCTL0), 2945 igb_getreg(TXCTL1), 2946 igb_getreg(TXCTL2), 2947 igb_getreg(TXCTL3), 2948 igb_getreg(TXCTL4), 2949 igb_getreg(TXCTL5), 2950 igb_getreg(TXCTL6), 2951 igb_getreg(TXCTL7), 2952 igb_getreg(TXCTL8), 2953 igb_getreg(TXCTL9), 2954 igb_getreg(TXCTL10), 2955 igb_getreg(TXCTL11), 2956 igb_getreg(TXCTL12), 2957 igb_getreg(TXCTL13), 2958 igb_getreg(TXCTL14), 2959 igb_getreg(TXCTL15), 2960 igb_getreg(TDWBAL0), 2961 igb_getreg(TDWBAL1), 2962 igb_getreg(TDWBAL2), 2963 igb_getreg(TDWBAL3), 2964 igb_getreg(TDWBAL4), 2965 igb_getreg(TDWBAL5), 2966 igb_getreg(TDWBAL6), 2967 igb_getreg(TDWBAL7), 2968 igb_getreg(TDWBAL8), 2969 igb_getreg(TDWBAL9), 2970 igb_getreg(TDWBAL10), 2971 igb_getreg(TDWBAL11), 2972 igb_getreg(TDWBAL12), 2973 igb_getreg(TDWBAL13), 2974 igb_getreg(TDWBAL14), 2975 igb_getreg(TDWBAL15), 2976 igb_getreg(TDWBAH0), 2977 igb_getreg(TDWBAH1), 2978 igb_getreg(TDWBAH2), 2979 igb_getreg(TDWBAH3), 2980 igb_getreg(TDWBAH4), 2981 igb_getreg(TDWBAH5), 2982 igb_getreg(TDWBAH6), 2983 igb_getreg(TDWBAH7), 2984 igb_getreg(TDWBAH8), 2985 igb_getreg(TDWBAH9), 2986 igb_getreg(TDWBAH10), 2987 igb_getreg(TDWBAH11), 2988 igb_getreg(TDWBAH12), 2989 igb_getreg(TDWBAH13), 2990 igb_getreg(TDWBAH14), 2991 igb_getreg(TDWBAH15), 2992 igb_getreg(PVTCTRL0), 2993 igb_getreg(PVTCTRL1), 2994 igb_getreg(PVTCTRL2), 2995 igb_getreg(PVTCTRL3), 2996 igb_getreg(PVTCTRL4), 2997 igb_getreg(PVTCTRL5), 2998 igb_getreg(PVTCTRL6), 2999 igb_getreg(PVTCTRL7), 3000 igb_getreg(PVTEIMS0), 3001 igb_getreg(PVTEIMS1), 3002 igb_getreg(PVTEIMS2), 3003 igb_getreg(PVTEIMS3), 3004 igb_getreg(PVTEIMS4), 3005 igb_getreg(PVTEIMS5), 3006 igb_getreg(PVTEIMS6), 3007 igb_getreg(PVTEIMS7), 3008 igb_getreg(PVTEIAC0), 3009 igb_getreg(PVTEIAC1), 3010 igb_getreg(PVTEIAC2), 3011 igb_getreg(PVTEIAC3), 3012 igb_getreg(PVTEIAC4), 3013 igb_getreg(PVTEIAC5), 3014 igb_getreg(PVTEIAC6), 3015 igb_getreg(PVTEIAC7), 3016 igb_getreg(PVTEIAM0), 3017 igb_getreg(PVTEIAM1), 3018 igb_getreg(PVTEIAM2), 3019 igb_getreg(PVTEIAM3), 3020 igb_getreg(PVTEIAM4), 3021 igb_getreg(PVTEIAM5), 3022 igb_getreg(PVTEIAM6), 3023 igb_getreg(PVTEIAM7), 3024 igb_getreg(PVFGPRC0), 3025 igb_getreg(PVFGPRC1), 3026 igb_getreg(PVFGPRC2), 3027 igb_getreg(PVFGPRC3), 3028 igb_getreg(PVFGPRC4), 3029 igb_getreg(PVFGPRC5), 3030 igb_getreg(PVFGPRC6), 3031 igb_getreg(PVFGPRC7), 3032 igb_getreg(PVFGPTC0), 3033 igb_getreg(PVFGPTC1), 3034 igb_getreg(PVFGPTC2), 3035 igb_getreg(PVFGPTC3), 3036 igb_getreg(PVFGPTC4), 3037 igb_getreg(PVFGPTC5), 3038 igb_getreg(PVFGPTC6), 3039 igb_getreg(PVFGPTC7), 3040 igb_getreg(PVFGORC0), 3041 igb_getreg(PVFGORC1), 3042 igb_getreg(PVFGORC2), 3043 igb_getreg(PVFGORC3), 3044 igb_getreg(PVFGORC4), 3045 igb_getreg(PVFGORC5), 3046 igb_getreg(PVFGORC6), 3047 igb_getreg(PVFGORC7), 3048 igb_getreg(PVFGOTC0), 3049 igb_getreg(PVFGOTC1), 3050 igb_getreg(PVFGOTC2), 3051 igb_getreg(PVFGOTC3), 3052 igb_getreg(PVFGOTC4), 3053 igb_getreg(PVFGOTC5), 3054 igb_getreg(PVFGOTC6), 3055 igb_getreg(PVFGOTC7), 3056 igb_getreg(PVFMPRC0), 3057 igb_getreg(PVFMPRC1), 3058 igb_getreg(PVFMPRC2), 3059 igb_getreg(PVFMPRC3), 3060 igb_getreg(PVFMPRC4), 3061 igb_getreg(PVFMPRC5), 3062 igb_getreg(PVFMPRC6), 3063 igb_getreg(PVFMPRC7), 3064 igb_getreg(PVFGPRLBC0), 3065 igb_getreg(PVFGPRLBC1), 3066 igb_getreg(PVFGPRLBC2), 3067 igb_getreg(PVFGPRLBC3), 3068 igb_getreg(PVFGPRLBC4), 3069 igb_getreg(PVFGPRLBC5), 3070 igb_getreg(PVFGPRLBC6), 3071 igb_getreg(PVFGPRLBC7), 3072 igb_getreg(PVFGPTLBC0), 3073 igb_getreg(PVFGPTLBC1), 3074 igb_getreg(PVFGPTLBC2), 3075 igb_getreg(PVFGPTLBC3), 3076 igb_getreg(PVFGPTLBC4), 3077 igb_getreg(PVFGPTLBC5), 3078 igb_getreg(PVFGPTLBC6), 3079 igb_getreg(PVFGPTLBC7), 3080 igb_getreg(PVFGORLBC0), 3081 igb_getreg(PVFGORLBC1), 3082 igb_getreg(PVFGORLBC2), 3083 igb_getreg(PVFGORLBC3), 3084 igb_getreg(PVFGORLBC4), 3085 igb_getreg(PVFGORLBC5), 3086 igb_getreg(PVFGORLBC6), 3087 igb_getreg(PVFGORLBC7), 3088 igb_getreg(PVFGOTLBC0), 3089 igb_getreg(PVFGOTLBC1), 3090 igb_getreg(PVFGOTLBC2), 3091 igb_getreg(PVFGOTLBC3), 3092 igb_getreg(PVFGOTLBC4), 3093 igb_getreg(PVFGOTLBC5), 3094 igb_getreg(PVFGOTLBC6), 3095 igb_getreg(PVFGOTLBC7), 3096 igb_getreg(RCTL), 3097 igb_getreg(MDIC), 3098 igb_getreg(FCRUC), 3099 igb_getreg(VET), 3100 igb_getreg(RDBAL0), 3101 igb_getreg(RDBAL1), 3102 igb_getreg(RDBAL2), 3103 igb_getreg(RDBAL3), 3104 igb_getreg(RDBAL4), 3105 igb_getreg(RDBAL5), 3106 igb_getreg(RDBAL6), 3107 igb_getreg(RDBAL7), 3108 igb_getreg(RDBAL8), 3109 igb_getreg(RDBAL9), 3110 igb_getreg(RDBAL10), 3111 igb_getreg(RDBAL11), 3112 igb_getreg(RDBAL12), 3113 igb_getreg(RDBAL13), 3114 igb_getreg(RDBAL14), 3115 igb_getreg(RDBAL15), 3116 igb_getreg(TDBAH0), 3117 igb_getreg(TDBAH1), 3118 igb_getreg(TDBAH2), 3119 igb_getreg(TDBAH3), 3120 igb_getreg(TDBAH4), 3121 igb_getreg(TDBAH5), 3122 igb_getreg(TDBAH6), 3123 igb_getreg(TDBAH7), 3124 igb_getreg(TDBAH8), 3125 igb_getreg(TDBAH9), 3126 igb_getreg(TDBAH10), 3127 igb_getreg(TDBAH11), 3128 igb_getreg(TDBAH12), 3129 igb_getreg(TDBAH13), 3130 igb_getreg(TDBAH14), 3131 igb_getreg(TDBAH15), 3132 igb_getreg(SCC), 3133 igb_getreg(COLC), 3134 igb_getreg(XOFFRXC), 3135 igb_getreg(IPAV), 3136 igb_getreg(GOTCL), 3137 igb_getreg(MGTPDC), 3138 igb_getreg(GCR), 3139 igb_getreg(MFVAL), 3140 igb_getreg(FUNCTAG), 3141 igb_getreg(GSCL_4), 3142 igb_getreg(GSCN_3), 3143 igb_getreg(MRQC), 3144 igb_getreg(FCT), 3145 igb_getreg(FLA), 3146 igb_getreg(RXDCTL0), 3147 igb_getreg(RXDCTL1), 3148 igb_getreg(RXDCTL2), 3149 igb_getreg(RXDCTL3), 3150 igb_getreg(RXDCTL4), 3151 igb_getreg(RXDCTL5), 3152 igb_getreg(RXDCTL6), 3153 igb_getreg(RXDCTL7), 3154 igb_getreg(RXDCTL8), 3155 igb_getreg(RXDCTL9), 3156 igb_getreg(RXDCTL10), 3157 igb_getreg(RXDCTL11), 3158 igb_getreg(RXDCTL12), 3159 igb_getreg(RXDCTL13), 3160 igb_getreg(RXDCTL14), 3161 igb_getreg(RXDCTL15), 3162 igb_getreg(RXSTMPL), 3163 igb_getreg(TIMADJH), 3164 igb_getreg(FCRTL), 3165 igb_getreg(XONRXC), 3166 igb_getreg(RFCTL), 3167 igb_getreg(GSCN_1), 3168 igb_getreg(FCAL), 3169 igb_getreg(GPIE), 3170 igb_getreg(TXPBS), 3171 igb_getreg(RLPML), 3172 3173 [TOTH] = igb_mac_read_clr8, 3174 [GOTCH] = igb_mac_read_clr8, 3175 [PRC64] = igb_mac_read_clr4, 3176 [PRC255] = igb_mac_read_clr4, 3177 [PRC1023] = igb_mac_read_clr4, 3178 [PTC64] = igb_mac_read_clr4, 3179 [PTC255] = igb_mac_read_clr4, 3180 [PTC1023] = igb_mac_read_clr4, 3181 [GPRC] = igb_mac_read_clr4, 3182 [TPT] = igb_mac_read_clr4, 3183 [RUC] = igb_mac_read_clr4, 3184 [BPRC] = igb_mac_read_clr4, 3185 [MPTC] = igb_mac_read_clr4, 3186 [IAC] = igb_mac_read_clr4, 3187 [ICR] = igb_mac_icr_read, 3188 [STATUS] = igb_get_status, 3189 [ICS] = igb_mac_ics_read, 3190 /* 3191 * 8.8.10: Reading the IMC register returns the value of the IMS register. 3192 */ 3193 [IMC] = igb_mac_ims_read, 3194 [TORH] = igb_mac_read_clr8, 3195 [GORCH] = igb_mac_read_clr8, 3196 [PRC127] = igb_mac_read_clr4, 3197 [PRC511] = igb_mac_read_clr4, 3198 [PRC1522] = igb_mac_read_clr4, 3199 [PTC127] = igb_mac_read_clr4, 3200 [PTC511] = igb_mac_read_clr4, 3201 [PTC1522] = igb_mac_read_clr4, 3202 [GPTC] = igb_mac_read_clr4, 3203 [TPR] = igb_mac_read_clr4, 3204 [ROC] = igb_mac_read_clr4, 3205 [MPRC] = igb_mac_read_clr4, 3206 [BPTC] = igb_mac_read_clr4, 3207 [TSCTC] = igb_mac_read_clr4, 3208 [CTRL] = igb_get_ctrl, 3209 [SWSM] = igb_mac_swsm_read, 3210 [IMS] = igb_mac_ims_read, 3211 [SYSTIML] = igb_get_systiml, 3212 [RXSATRH] = igb_get_rxsatrh, 3213 [TXSTMPH] = igb_get_txstmph, 3214 3215 [CRCERRS ... MPC] = igb_mac_readreg, 3216 [IP6AT ... IP6AT + 3] = igb_mac_readreg, 3217 [IP4AT ... IP4AT + 6] = igb_mac_readreg, 3218 [RA ... RA + 31] = igb_mac_readreg, 3219 [RA2 ... RA2 + 31] = igb_mac_readreg, 3220 [WUPM ... WUPM + 31] = igb_mac_readreg, 3221 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg, 3222 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg, 3223 [FFMT ... FFMT + 254] = igb_mac_readreg, 3224 [MDEF ... MDEF + 7] = igb_mac_readreg, 3225 [FTFT ... FTFT + 254] = igb_mac_readreg, 3226 [RETA ... RETA + 31] = igb_mac_readreg, 3227 [RSSRK ... RSSRK + 9] = igb_mac_readreg, 3228 [MAVTV0 ... MAVTV3] = igb_mac_readreg, 3229 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read, 3230 [PVTEICR0] = igb_mac_read_clr4, 3231 [PVTEICR1] = igb_mac_read_clr4, 3232 [PVTEICR2] = igb_mac_read_clr4, 3233 [PVTEICR3] = igb_mac_read_clr4, 3234 [PVTEICR4] = igb_mac_read_clr4, 3235 [PVTEICR5] = igb_mac_read_clr4, 3236 [PVTEICR6] = igb_mac_read_clr4, 3237 [PVTEICR7] = igb_mac_read_clr4, 3238 3239 /* IGB specific: */ 3240 [FWSM] = igb_mac_readreg, 3241 [SW_FW_SYNC] = igb_mac_readreg, 3242 [HTCBDPC] = igb_mac_read_clr4, 3243 [EICR] = igb_mac_read_clr4, 3244 [EIMS] = igb_mac_readreg, 3245 [EIAM] = igb_mac_readreg, 3246 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg, 3247 igb_getreg(IVAR_MISC), 3248 igb_getreg(VT_CTL), 3249 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg, 3250 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read, 3251 igb_getreg(MBVFICR), 3252 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg, 3253 igb_getreg(MBVFIMR), 3254 igb_getreg(VFLRE), 3255 igb_getreg(VFRE), 3256 igb_getreg(VFTE), 3257 igb_getreg(QDE), 3258 igb_getreg(DTXSWC), 3259 igb_getreg(RPLOLR), 3260 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg, 3261 [VMVIR0 ... VMVIR7] = igb_mac_readreg, 3262 [VMOLR0 ... VMOLR7] = igb_mac_readreg, 3263 [WVBR] = igb_mac_read_clr4, 3264 [RQDPC0] = igb_mac_read_clr4, 3265 [RQDPC1] = igb_mac_read_clr4, 3266 [RQDPC2] = igb_mac_read_clr4, 3267 [RQDPC3] = igb_mac_read_clr4, 3268 [RQDPC4] = igb_mac_read_clr4, 3269 [RQDPC5] = igb_mac_read_clr4, 3270 [RQDPC6] = igb_mac_read_clr4, 3271 [RQDPC7] = igb_mac_read_clr4, 3272 [RQDPC8] = igb_mac_read_clr4, 3273 [RQDPC9] = igb_mac_read_clr4, 3274 [RQDPC10] = igb_mac_read_clr4, 3275 [RQDPC11] = igb_mac_read_clr4, 3276 [RQDPC12] = igb_mac_read_clr4, 3277 [RQDPC13] = igb_mac_read_clr4, 3278 [RQDPC14] = igb_mac_read_clr4, 3279 [RQDPC15] = igb_mac_read_clr4, 3280 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg, 3281 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg, 3282 }; 3283 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) }; 3284 3285 #define igb_putreg(x) [x] = igb_mac_writereg 3286 typedef void (*writeops)(IGBCore *, int, uint32_t); 3287 static const writeops igb_macreg_writeops[] = { 3288 igb_putreg(SWSM), 3289 igb_putreg(WUFC), 3290 igb_putreg(RDBAH0), 3291 igb_putreg(RDBAH1), 3292 igb_putreg(RDBAH2), 3293 igb_putreg(RDBAH3), 3294 igb_putreg(RDBAH4), 3295 igb_putreg(RDBAH5), 3296 igb_putreg(RDBAH6), 3297 igb_putreg(RDBAH7), 3298 igb_putreg(RDBAH8), 3299 igb_putreg(RDBAH9), 3300 igb_putreg(RDBAH10), 3301 igb_putreg(RDBAH11), 3302 igb_putreg(RDBAH12), 3303 igb_putreg(RDBAH13), 3304 igb_putreg(RDBAH14), 3305 igb_putreg(RDBAH15), 3306 igb_putreg(SRRCTL0), 3307 igb_putreg(SRRCTL1), 3308 igb_putreg(SRRCTL2), 3309 igb_putreg(SRRCTL3), 3310 igb_putreg(SRRCTL4), 3311 igb_putreg(SRRCTL5), 3312 igb_putreg(SRRCTL6), 3313 igb_putreg(SRRCTL7), 3314 igb_putreg(SRRCTL8), 3315 igb_putreg(SRRCTL9), 3316 igb_putreg(SRRCTL10), 3317 igb_putreg(SRRCTL11), 3318 igb_putreg(SRRCTL12), 3319 igb_putreg(SRRCTL13), 3320 igb_putreg(SRRCTL14), 3321 igb_putreg(SRRCTL15), 3322 igb_putreg(RXDCTL0), 3323 igb_putreg(RXDCTL1), 3324 igb_putreg(RXDCTL2), 3325 igb_putreg(RXDCTL3), 3326 igb_putreg(RXDCTL4), 3327 igb_putreg(RXDCTL5), 3328 igb_putreg(RXDCTL6), 3329 igb_putreg(RXDCTL7), 3330 igb_putreg(RXDCTL8), 3331 igb_putreg(RXDCTL9), 3332 igb_putreg(RXDCTL10), 3333 igb_putreg(RXDCTL11), 3334 igb_putreg(RXDCTL12), 3335 igb_putreg(RXDCTL13), 3336 igb_putreg(RXDCTL14), 3337 igb_putreg(RXDCTL15), 3338 igb_putreg(LEDCTL), 3339 igb_putreg(TCTL), 3340 igb_putreg(TCTL_EXT), 3341 igb_putreg(DTXCTL), 3342 igb_putreg(RXPBS), 3343 igb_putreg(RQDPC0), 3344 igb_putreg(FCAL), 3345 igb_putreg(FCRUC), 3346 igb_putreg(WUC), 3347 igb_putreg(WUS), 3348 igb_putreg(IPAV), 3349 igb_putreg(TDBAH0), 3350 igb_putreg(TDBAH1), 3351 igb_putreg(TDBAH2), 3352 igb_putreg(TDBAH3), 3353 igb_putreg(TDBAH4), 3354 igb_putreg(TDBAH5), 3355 igb_putreg(TDBAH6), 3356 igb_putreg(TDBAH7), 3357 igb_putreg(TDBAH8), 3358 igb_putreg(TDBAH9), 3359 igb_putreg(TDBAH10), 3360 igb_putreg(TDBAH11), 3361 igb_putreg(TDBAH12), 3362 igb_putreg(TDBAH13), 3363 igb_putreg(TDBAH14), 3364 igb_putreg(TDBAH15), 3365 igb_putreg(IAM), 3366 igb_putreg(MANC), 3367 igb_putreg(MANC2H), 3368 igb_putreg(MFVAL), 3369 igb_putreg(FACTPS), 3370 igb_putreg(FUNCTAG), 3371 igb_putreg(GSCL_1), 3372 igb_putreg(GSCL_2), 3373 igb_putreg(GSCL_3), 3374 igb_putreg(GSCL_4), 3375 igb_putreg(GSCN_0), 3376 igb_putreg(GSCN_1), 3377 igb_putreg(GSCN_2), 3378 igb_putreg(GSCN_3), 3379 igb_putreg(MRQC), 3380 igb_putreg(FLOP), 3381 igb_putreg(FLA), 3382 igb_putreg(TXDCTL0), 3383 igb_putreg(TXDCTL1), 3384 igb_putreg(TXDCTL2), 3385 igb_putreg(TXDCTL3), 3386 igb_putreg(TXDCTL4), 3387 igb_putreg(TXDCTL5), 3388 igb_putreg(TXDCTL6), 3389 igb_putreg(TXDCTL7), 3390 igb_putreg(TXDCTL8), 3391 igb_putreg(TXDCTL9), 3392 igb_putreg(TXDCTL10), 3393 igb_putreg(TXDCTL11), 3394 igb_putreg(TXDCTL12), 3395 igb_putreg(TXDCTL13), 3396 igb_putreg(TXDCTL14), 3397 igb_putreg(TXDCTL15), 3398 igb_putreg(TXCTL0), 3399 igb_putreg(TXCTL1), 3400 igb_putreg(TXCTL2), 3401 igb_putreg(TXCTL3), 3402 igb_putreg(TXCTL4), 3403 igb_putreg(TXCTL5), 3404 igb_putreg(TXCTL6), 3405 igb_putreg(TXCTL7), 3406 igb_putreg(TXCTL8), 3407 igb_putreg(TXCTL9), 3408 igb_putreg(TXCTL10), 3409 igb_putreg(TXCTL11), 3410 igb_putreg(TXCTL12), 3411 igb_putreg(TXCTL13), 3412 igb_putreg(TXCTL14), 3413 igb_putreg(TXCTL15), 3414 igb_putreg(TDWBAL0), 3415 igb_putreg(TDWBAL1), 3416 igb_putreg(TDWBAL2), 3417 igb_putreg(TDWBAL3), 3418 igb_putreg(TDWBAL4), 3419 igb_putreg(TDWBAL5), 3420 igb_putreg(TDWBAL6), 3421 igb_putreg(TDWBAL7), 3422 igb_putreg(TDWBAL8), 3423 igb_putreg(TDWBAL9), 3424 igb_putreg(TDWBAL10), 3425 igb_putreg(TDWBAL11), 3426 igb_putreg(TDWBAL12), 3427 igb_putreg(TDWBAL13), 3428 igb_putreg(TDWBAL14), 3429 igb_putreg(TDWBAL15), 3430 igb_putreg(TDWBAH0), 3431 igb_putreg(TDWBAH1), 3432 igb_putreg(TDWBAH2), 3433 igb_putreg(TDWBAH3), 3434 igb_putreg(TDWBAH4), 3435 igb_putreg(TDWBAH5), 3436 igb_putreg(TDWBAH6), 3437 igb_putreg(TDWBAH7), 3438 igb_putreg(TDWBAH8), 3439 igb_putreg(TDWBAH9), 3440 igb_putreg(TDWBAH10), 3441 igb_putreg(TDWBAH11), 3442 igb_putreg(TDWBAH12), 3443 igb_putreg(TDWBAH13), 3444 igb_putreg(TDWBAH14), 3445 igb_putreg(TDWBAH15), 3446 igb_putreg(TIPG), 3447 igb_putreg(RXSTMPH), 3448 igb_putreg(RXSTMPL), 3449 igb_putreg(RXSATRL), 3450 igb_putreg(RXSATRH), 3451 igb_putreg(TXSTMPL), 3452 igb_putreg(TXSTMPH), 3453 igb_putreg(SYSTIML), 3454 igb_putreg(SYSTIMH), 3455 igb_putreg(TIMADJL), 3456 igb_putreg(TSYNCRXCTL), 3457 igb_putreg(TSYNCTXCTL), 3458 igb_putreg(EEMNGCTL), 3459 igb_putreg(GPIE), 3460 igb_putreg(TXPBS), 3461 igb_putreg(RLPML), 3462 igb_putreg(VET), 3463 3464 [TDH0] = igb_set_16bit, 3465 [TDH1] = igb_set_16bit, 3466 [TDH2] = igb_set_16bit, 3467 [TDH3] = igb_set_16bit, 3468 [TDH4] = igb_set_16bit, 3469 [TDH5] = igb_set_16bit, 3470 [TDH6] = igb_set_16bit, 3471 [TDH7] = igb_set_16bit, 3472 [TDH8] = igb_set_16bit, 3473 [TDH9] = igb_set_16bit, 3474 [TDH10] = igb_set_16bit, 3475 [TDH11] = igb_set_16bit, 3476 [TDH12] = igb_set_16bit, 3477 [TDH13] = igb_set_16bit, 3478 [TDH14] = igb_set_16bit, 3479 [TDH15] = igb_set_16bit, 3480 [TDT0] = igb_set_tdt, 3481 [TDT1] = igb_set_tdt, 3482 [TDT2] = igb_set_tdt, 3483 [TDT3] = igb_set_tdt, 3484 [TDT4] = igb_set_tdt, 3485 [TDT5] = igb_set_tdt, 3486 [TDT6] = igb_set_tdt, 3487 [TDT7] = igb_set_tdt, 3488 [TDT8] = igb_set_tdt, 3489 [TDT9] = igb_set_tdt, 3490 [TDT10] = igb_set_tdt, 3491 [TDT11] = igb_set_tdt, 3492 [TDT12] = igb_set_tdt, 3493 [TDT13] = igb_set_tdt, 3494 [TDT14] = igb_set_tdt, 3495 [TDT15] = igb_set_tdt, 3496 [MDIC] = igb_set_mdic, 3497 [ICS] = igb_set_ics, 3498 [RDH0] = igb_set_16bit, 3499 [RDH1] = igb_set_16bit, 3500 [RDH2] = igb_set_16bit, 3501 [RDH3] = igb_set_16bit, 3502 [RDH4] = igb_set_16bit, 3503 [RDH5] = igb_set_16bit, 3504 [RDH6] = igb_set_16bit, 3505 [RDH7] = igb_set_16bit, 3506 [RDH8] = igb_set_16bit, 3507 [RDH9] = igb_set_16bit, 3508 [RDH10] = igb_set_16bit, 3509 [RDH11] = igb_set_16bit, 3510 [RDH12] = igb_set_16bit, 3511 [RDH13] = igb_set_16bit, 3512 [RDH14] = igb_set_16bit, 3513 [RDH15] = igb_set_16bit, 3514 [RDT0] = igb_set_rdt, 3515 [RDT1] = igb_set_rdt, 3516 [RDT2] = igb_set_rdt, 3517 [RDT3] = igb_set_rdt, 3518 [RDT4] = igb_set_rdt, 3519 [RDT5] = igb_set_rdt, 3520 [RDT6] = igb_set_rdt, 3521 [RDT7] = igb_set_rdt, 3522 [RDT8] = igb_set_rdt, 3523 [RDT9] = igb_set_rdt, 3524 [RDT10] = igb_set_rdt, 3525 [RDT11] = igb_set_rdt, 3526 [RDT12] = igb_set_rdt, 3527 [RDT13] = igb_set_rdt, 3528 [RDT14] = igb_set_rdt, 3529 [RDT15] = igb_set_rdt, 3530 [IMC] = igb_set_imc, 3531 [IMS] = igb_set_ims, 3532 [ICR] = igb_set_icr, 3533 [EECD] = igb_set_eecd, 3534 [RCTL] = igb_set_rx_control, 3535 [CTRL] = igb_set_ctrl, 3536 [EERD] = igb_set_eerd, 3537 [TDFH] = igb_set_13bit, 3538 [TDFT] = igb_set_13bit, 3539 [TDFHS] = igb_set_13bit, 3540 [TDFTS] = igb_set_13bit, 3541 [TDFPC] = igb_set_13bit, 3542 [RDFH] = igb_set_13bit, 3543 [RDFT] = igb_set_13bit, 3544 [RDFHS] = igb_set_13bit, 3545 [RDFTS] = igb_set_13bit, 3546 [RDFPC] = igb_set_13bit, 3547 [GCR] = igb_set_gcr, 3548 [RXCSUM] = igb_set_rxcsum, 3549 [TDLEN0] = igb_set_dlen, 3550 [TDLEN1] = igb_set_dlen, 3551 [TDLEN2] = igb_set_dlen, 3552 [TDLEN3] = igb_set_dlen, 3553 [TDLEN4] = igb_set_dlen, 3554 [TDLEN5] = igb_set_dlen, 3555 [TDLEN6] = igb_set_dlen, 3556 [TDLEN7] = igb_set_dlen, 3557 [TDLEN8] = igb_set_dlen, 3558 [TDLEN9] = igb_set_dlen, 3559 [TDLEN10] = igb_set_dlen, 3560 [TDLEN11] = igb_set_dlen, 3561 [TDLEN12] = igb_set_dlen, 3562 [TDLEN13] = igb_set_dlen, 3563 [TDLEN14] = igb_set_dlen, 3564 [TDLEN15] = igb_set_dlen, 3565 [RDLEN0] = igb_set_dlen, 3566 [RDLEN1] = igb_set_dlen, 3567 [RDLEN2] = igb_set_dlen, 3568 [RDLEN3] = igb_set_dlen, 3569 [RDLEN4] = igb_set_dlen, 3570 [RDLEN5] = igb_set_dlen, 3571 [RDLEN6] = igb_set_dlen, 3572 [RDLEN7] = igb_set_dlen, 3573 [RDLEN8] = igb_set_dlen, 3574 [RDLEN9] = igb_set_dlen, 3575 [RDLEN10] = igb_set_dlen, 3576 [RDLEN11] = igb_set_dlen, 3577 [RDLEN12] = igb_set_dlen, 3578 [RDLEN13] = igb_set_dlen, 3579 [RDLEN14] = igb_set_dlen, 3580 [RDLEN15] = igb_set_dlen, 3581 [TDBAL0] = igb_set_dbal, 3582 [TDBAL1] = igb_set_dbal, 3583 [TDBAL2] = igb_set_dbal, 3584 [TDBAL3] = igb_set_dbal, 3585 [TDBAL4] = igb_set_dbal, 3586 [TDBAL5] = igb_set_dbal, 3587 [TDBAL6] = igb_set_dbal, 3588 [TDBAL7] = igb_set_dbal, 3589 [TDBAL8] = igb_set_dbal, 3590 [TDBAL9] = igb_set_dbal, 3591 [TDBAL10] = igb_set_dbal, 3592 [TDBAL11] = igb_set_dbal, 3593 [TDBAL12] = igb_set_dbal, 3594 [TDBAL13] = igb_set_dbal, 3595 [TDBAL14] = igb_set_dbal, 3596 [TDBAL15] = igb_set_dbal, 3597 [RDBAL0] = igb_set_dbal, 3598 [RDBAL1] = igb_set_dbal, 3599 [RDBAL2] = igb_set_dbal, 3600 [RDBAL3] = igb_set_dbal, 3601 [RDBAL4] = igb_set_dbal, 3602 [RDBAL5] = igb_set_dbal, 3603 [RDBAL6] = igb_set_dbal, 3604 [RDBAL7] = igb_set_dbal, 3605 [RDBAL8] = igb_set_dbal, 3606 [RDBAL9] = igb_set_dbal, 3607 [RDBAL10] = igb_set_dbal, 3608 [RDBAL11] = igb_set_dbal, 3609 [RDBAL12] = igb_set_dbal, 3610 [RDBAL13] = igb_set_dbal, 3611 [RDBAL14] = igb_set_dbal, 3612 [RDBAL15] = igb_set_dbal, 3613 [STATUS] = igb_set_status, 3614 [PBACLR] = igb_set_pbaclr, 3615 [CTRL_EXT] = igb_set_ctrlext, 3616 [FCAH] = igb_set_16bit, 3617 [FCT] = igb_set_16bit, 3618 [FCTTV] = igb_set_16bit, 3619 [FCRTV] = igb_set_16bit, 3620 [FCRTH] = igb_set_fcrth, 3621 [FCRTL] = igb_set_fcrtl, 3622 [CTRL_DUP] = igb_set_ctrl, 3623 [RFCTL] = igb_set_rfctl, 3624 [TIMINCA] = igb_set_timinca, 3625 [TIMADJH] = igb_set_timadjh, 3626 3627 [IP6AT ... IP6AT + 3] = igb_mac_writereg, 3628 [IP4AT ... IP4AT + 6] = igb_mac_writereg, 3629 [RA] = igb_mac_writereg, 3630 [RA + 1] = igb_mac_setmacaddr, 3631 [RA + 2 ... RA + 31] = igb_mac_writereg, 3632 [RA2 ... RA2 + 31] = igb_mac_writereg, 3633 [WUPM ... WUPM + 31] = igb_mac_writereg, 3634 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3635 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg, 3636 [FFMT ... FFMT + 254] = igb_set_4bit, 3637 [MDEF ... MDEF + 7] = igb_mac_writereg, 3638 [FTFT ... FTFT + 254] = igb_mac_writereg, 3639 [RETA ... RETA + 31] = igb_mac_writereg, 3640 [RSSRK ... RSSRK + 9] = igb_mac_writereg, 3641 [MAVTV0 ... MAVTV3] = igb_mac_writereg, 3642 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr, 3643 3644 /* IGB specific: */ 3645 [FWSM] = igb_mac_writereg, 3646 [SW_FW_SYNC] = igb_mac_writereg, 3647 [EICR] = igb_set_eicr, 3648 [EICS] = igb_set_eics, 3649 [EIAC] = igb_set_eiac, 3650 [EIAM] = igb_set_eiam, 3651 [EIMC] = igb_set_eimc, 3652 [EIMS] = igb_set_eims, 3653 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg, 3654 igb_putreg(IVAR_MISC), 3655 igb_putreg(VT_CTL), 3656 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox, 3657 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox, 3658 [MBVFICR] = igb_w1c, 3659 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg, 3660 igb_putreg(MBVFIMR), 3661 [VFLRE] = igb_w1c, 3662 igb_putreg(VFRE), 3663 igb_putreg(VFTE), 3664 igb_putreg(QDE), 3665 igb_putreg(DTXSWC), 3666 igb_putreg(RPLOLR), 3667 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg, 3668 [VMVIR0 ... VMVIR7] = igb_mac_writereg, 3669 [VMOLR0 ... VMOLR7] = igb_mac_writereg, 3670 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg, 3671 [PVTCTRL0] = igb_set_vtctrl, 3672 [PVTCTRL1] = igb_set_vtctrl, 3673 [PVTCTRL2] = igb_set_vtctrl, 3674 [PVTCTRL3] = igb_set_vtctrl, 3675 [PVTCTRL4] = igb_set_vtctrl, 3676 [PVTCTRL5] = igb_set_vtctrl, 3677 [PVTCTRL6] = igb_set_vtctrl, 3678 [PVTCTRL7] = igb_set_vtctrl, 3679 [PVTEICS0] = igb_set_vteics, 3680 [PVTEICS1] = igb_set_vteics, 3681 [PVTEICS2] = igb_set_vteics, 3682 [PVTEICS3] = igb_set_vteics, 3683 [PVTEICS4] = igb_set_vteics, 3684 [PVTEICS5] = igb_set_vteics, 3685 [PVTEICS6] = igb_set_vteics, 3686 [PVTEICS7] = igb_set_vteics, 3687 [PVTEIMS0] = igb_set_vteims, 3688 [PVTEIMS1] = igb_set_vteims, 3689 [PVTEIMS2] = igb_set_vteims, 3690 [PVTEIMS3] = igb_set_vteims, 3691 [PVTEIMS4] = igb_set_vteims, 3692 [PVTEIMS5] = igb_set_vteims, 3693 [PVTEIMS6] = igb_set_vteims, 3694 [PVTEIMS7] = igb_set_vteims, 3695 [PVTEIMC0] = igb_set_vteimc, 3696 [PVTEIMC1] = igb_set_vteimc, 3697 [PVTEIMC2] = igb_set_vteimc, 3698 [PVTEIMC3] = igb_set_vteimc, 3699 [PVTEIMC4] = igb_set_vteimc, 3700 [PVTEIMC5] = igb_set_vteimc, 3701 [PVTEIMC6] = igb_set_vteimc, 3702 [PVTEIMC7] = igb_set_vteimc, 3703 [PVTEIAC0] = igb_set_vteiac, 3704 [PVTEIAC1] = igb_set_vteiac, 3705 [PVTEIAC2] = igb_set_vteiac, 3706 [PVTEIAC3] = igb_set_vteiac, 3707 [PVTEIAC4] = igb_set_vteiac, 3708 [PVTEIAC5] = igb_set_vteiac, 3709 [PVTEIAC6] = igb_set_vteiac, 3710 [PVTEIAC7] = igb_set_vteiac, 3711 [PVTEIAM0] = igb_set_vteiam, 3712 [PVTEIAM1] = igb_set_vteiam, 3713 [PVTEIAM2] = igb_set_vteiam, 3714 [PVTEIAM3] = igb_set_vteiam, 3715 [PVTEIAM4] = igb_set_vteiam, 3716 [PVTEIAM5] = igb_set_vteiam, 3717 [PVTEIAM6] = igb_set_vteiam, 3718 [PVTEIAM7] = igb_set_vteiam, 3719 [PVTEICR0] = igb_set_vteicr, 3720 [PVTEICR1] = igb_set_vteicr, 3721 [PVTEICR2] = igb_set_vteicr, 3722 [PVTEICR3] = igb_set_vteicr, 3723 [PVTEICR4] = igb_set_vteicr, 3724 [PVTEICR5] = igb_set_vteicr, 3725 [PVTEICR6] = igb_set_vteicr, 3726 [PVTEICR7] = igb_set_vteicr, 3727 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar, 3728 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg 3729 }; 3730 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) }; 3731 3732 enum { MAC_ACCESS_PARTIAL = 1 }; 3733 3734 /* 3735 * The array below combines alias offsets of the index values for the 3736 * MAC registers that have aliases, with the indication of not fully 3737 * implemented registers (lowest bit). This combination is possible 3738 * because all of the offsets are even. 3739 */ 3740 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3741 /* Alias index offsets */ 3742 [FCRTL_A] = 0x07fe, 3743 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3744 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3745 [RA_A ... RA_A + 31] = 0x14f0, 3746 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3747 3748 [RDBAL0_A] = 0x2600, 3749 [RDBAH0_A] = 0x2600, 3750 [RDLEN0_A] = 0x2600, 3751 [SRRCTL0_A] = 0x2600, 3752 [RDH0_A] = 0x2600, 3753 [RDT0_A] = 0x2600, 3754 [RXDCTL0_A] = 0x2600, 3755 [RXCTL0_A] = 0x2600, 3756 [RQDPC0_A] = 0x2600, 3757 [RDBAL1_A] = 0x25D0, 3758 [RDBAL2_A] = 0x25A0, 3759 [RDBAL3_A] = 0x2570, 3760 [RDBAH1_A] = 0x25D0, 3761 [RDBAH2_A] = 0x25A0, 3762 [RDBAH3_A] = 0x2570, 3763 [RDLEN1_A] = 0x25D0, 3764 [RDLEN2_A] = 0x25A0, 3765 [RDLEN3_A] = 0x2570, 3766 [SRRCTL1_A] = 0x25D0, 3767 [SRRCTL2_A] = 0x25A0, 3768 [SRRCTL3_A] = 0x2570, 3769 [RDH1_A] = 0x25D0, 3770 [RDH2_A] = 0x25A0, 3771 [RDH3_A] = 0x2570, 3772 [RDT1_A] = 0x25D0, 3773 [RDT2_A] = 0x25A0, 3774 [RDT3_A] = 0x2570, 3775 [RXDCTL1_A] = 0x25D0, 3776 [RXDCTL2_A] = 0x25A0, 3777 [RXDCTL3_A] = 0x2570, 3778 [RXCTL1_A] = 0x25D0, 3779 [RXCTL2_A] = 0x25A0, 3780 [RXCTL3_A] = 0x2570, 3781 [RQDPC1_A] = 0x25D0, 3782 [RQDPC2_A] = 0x25A0, 3783 [RQDPC3_A] = 0x2570, 3784 [TDBAL0_A] = 0x2A00, 3785 [TDBAH0_A] = 0x2A00, 3786 [TDLEN0_A] = 0x2A00, 3787 [TDH0_A] = 0x2A00, 3788 [TDT0_A] = 0x2A00, 3789 [TXCTL0_A] = 0x2A00, 3790 [TDWBAL0_A] = 0x2A00, 3791 [TDWBAH0_A] = 0x2A00, 3792 [TDBAL1_A] = 0x29D0, 3793 [TDBAL2_A] = 0x29A0, 3794 [TDBAL3_A] = 0x2970, 3795 [TDBAH1_A] = 0x29D0, 3796 [TDBAH2_A] = 0x29A0, 3797 [TDBAH3_A] = 0x2970, 3798 [TDLEN1_A] = 0x29D0, 3799 [TDLEN2_A] = 0x29A0, 3800 [TDLEN3_A] = 0x2970, 3801 [TDH1_A] = 0x29D0, 3802 [TDH2_A] = 0x29A0, 3803 [TDH3_A] = 0x2970, 3804 [TDT1_A] = 0x29D0, 3805 [TDT2_A] = 0x29A0, 3806 [TDT3_A] = 0x2970, 3807 [TXDCTL0_A] = 0x2A00, 3808 [TXDCTL1_A] = 0x29D0, 3809 [TXDCTL2_A] = 0x29A0, 3810 [TXDCTL3_A] = 0x2970, 3811 [TXCTL1_A] = 0x29D0, 3812 [TXCTL2_A] = 0x29A0, 3813 [TXCTL3_A] = 0x29D0, 3814 [TDWBAL1_A] = 0x29D0, 3815 [TDWBAL2_A] = 0x29A0, 3816 [TDWBAL3_A] = 0x2970, 3817 [TDWBAH1_A] = 0x29D0, 3818 [TDWBAH2_A] = 0x29A0, 3819 [TDWBAH3_A] = 0x2970, 3820 3821 /* Access options */ 3822 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3823 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3824 [RDFPC] = MAC_ACCESS_PARTIAL, 3825 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3826 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3827 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3828 [FLA] = MAC_ACCESS_PARTIAL, 3829 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3830 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3831 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3832 [FCRTH] = MAC_ACCESS_PARTIAL, 3833 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3834 }; 3835 3836 void 3837 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size) 3838 { 3839 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3840 3841 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) { 3842 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3843 trace_e1000e_wrn_regs_write_trivial(index << 2); 3844 } 3845 trace_e1000e_core_write(index << 2, size, val); 3846 igb_macreg_writeops[index](core, index, val); 3847 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3848 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3849 } else { 3850 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3851 } 3852 } 3853 3854 uint64_t 3855 igb_core_read(IGBCore *core, hwaddr addr, unsigned size) 3856 { 3857 uint64_t val; 3858 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr); 3859 3860 if (index < IGB_NREADOPS && igb_macreg_readops[index]) { 3861 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3862 trace_e1000e_wrn_regs_read_trivial(index << 2); 3863 } 3864 val = igb_macreg_readops[index](core, index); 3865 trace_e1000e_core_read(index << 2, size, val); 3866 return val; 3867 } else { 3868 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3869 } 3870 return 0; 3871 } 3872 3873 static inline void 3874 igb_autoneg_pause(IGBCore *core) 3875 { 3876 timer_del(core->autoneg_timer); 3877 } 3878 3879 static void 3880 igb_autoneg_resume(IGBCore *core) 3881 { 3882 if (igb_have_autoneg(core) && 3883 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) { 3884 qemu_get_queue(core->owner_nic)->link_down = false; 3885 timer_mod(core->autoneg_timer, 3886 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3887 } 3888 } 3889 3890 static void 3891 igb_vm_state_change(void *opaque, bool running, RunState state) 3892 { 3893 IGBCore *core = opaque; 3894 3895 if (running) { 3896 trace_e1000e_vm_state_running(); 3897 igb_intrmgr_resume(core); 3898 igb_autoneg_resume(core); 3899 } else { 3900 trace_e1000e_vm_state_stopped(); 3901 igb_autoneg_pause(core); 3902 igb_intrmgr_pause(core); 3903 } 3904 } 3905 3906 void 3907 igb_core_pci_realize(IGBCore *core, 3908 const uint16_t *eeprom_templ, 3909 uint32_t eeprom_size, 3910 const uint8_t *macaddr) 3911 { 3912 int i; 3913 3914 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3915 igb_autoneg_timer, core); 3916 igb_intrmgr_pci_realize(core); 3917 3918 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core); 3919 3920 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3921 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3922 } 3923 3924 net_rx_pkt_init(&core->rx_pkt); 3925 3926 e1000x_core_prepare_eeprom(core->eeprom, 3927 eeprom_templ, 3928 eeprom_size, 3929 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3930 macaddr); 3931 igb_update_rx_offloads(core); 3932 } 3933 3934 void 3935 igb_core_pci_uninit(IGBCore *core) 3936 { 3937 int i; 3938 3939 timer_free(core->autoneg_timer); 3940 3941 igb_intrmgr_pci_unint(core); 3942 3943 qemu_del_vm_change_state_handler(core->vmstate); 3944 3945 for (i = 0; i < IGB_NUM_QUEUES; i++) { 3946 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3947 } 3948 3949 net_rx_pkt_uninit(core->rx_pkt); 3950 } 3951 3952 static const uint16_t 3953 igb_phy_reg_init[] = { 3954 [MII_BMCR] = MII_BMCR_SPEED1000 | 3955 MII_BMCR_FD | 3956 MII_BMCR_AUTOEN, 3957 3958 [MII_BMSR] = MII_BMSR_EXTCAP | 3959 MII_BMSR_LINK_ST | 3960 MII_BMSR_AUTONEG | 3961 MII_BMSR_MFPS | 3962 MII_BMSR_EXTSTAT | 3963 MII_BMSR_10T_HD | 3964 MII_BMSR_10T_FD | 3965 MII_BMSR_100TX_HD | 3966 MII_BMSR_100TX_FD, 3967 3968 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16, 3969 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1, 3970 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3971 MII_ANAR_10FD | MII_ANAR_TX | 3972 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3973 MII_ANAR_PAUSE_ASYM, 3974 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3975 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3976 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3977 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3978 [MII_ANNP] = 0x1 | MII_ANNP_MP, 3979 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3980 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3981 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3982 MII_STAT1000_ROK | MII_STAT1000_LOK, 3983 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3984 3985 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8), 3986 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS, 3987 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU | 3988 IGP01E1000_PSCFR_SMART_SPEED 3989 }; 3990 3991 static const uint32_t igb_mac_reg_init[] = { 3992 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24), 3993 [EEMNGCTL] = BIT(31), 3994 [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE, 3995 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16), 3996 [RXDCTL1] = 1 << 16, 3997 [RXDCTL2] = 1 << 16, 3998 [RXDCTL3] = 1 << 16, 3999 [RXDCTL4] = 1 << 16, 4000 [RXDCTL5] = 1 << 16, 4001 [RXDCTL6] = 1 << 16, 4002 [RXDCTL7] = 1 << 16, 4003 [RXDCTL8] = 1 << 16, 4004 [RXDCTL9] = 1 << 16, 4005 [RXDCTL10] = 1 << 16, 4006 [RXDCTL11] = 1 << 16, 4007 [RXDCTL12] = 1 << 16, 4008 [RXDCTL13] = 1 << 16, 4009 [RXDCTL14] = 1 << 16, 4010 [RXDCTL15] = 1 << 16, 4011 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20), 4012 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 | 4013 E1000_CTRL_ADVD3WUC, 4014 [STATUS] = E1000_STATUS_PHYRA | BIT(31), 4015 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES | 4016 (2 << E1000_EECD_SIZE_EX_SHIFT), 4017 [GCR] = E1000_L0S_ADJUST | 4018 E1000_GCR_CMPL_TMOUT_RESEND | 4019 E1000_GCR_CAP_VER2 | 4020 E1000_L1_ENTRY_LATENCY_MSB | 4021 E1000_L1_ENTRY_LATENCY_LSB, 4022 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 4023 [TXPBS] = 0x28, 4024 [RXPBS] = 0x40, 4025 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) | 4026 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28), 4027 [TCTL_EXT] = 0x40 | (0x42 << 10), 4028 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT, 4029 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16), 4030 4031 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI, 4032 [MBVFIMR] = 0xFF, 4033 [VFRE] = 0xFF, 4034 [VFTE] = 0xFF, 4035 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC, 4036 [RPLOLR] = E1000_RPLOLR_STRCRC, 4037 [RLPML] = 0x2600, 4038 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4039 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4040 E1000_DCA_TXCTRL_DESC_RRO_EN, 4041 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4042 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4043 E1000_DCA_TXCTRL_DESC_RRO_EN, 4044 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4045 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4046 E1000_DCA_TXCTRL_DESC_RRO_EN, 4047 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4048 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4049 E1000_DCA_TXCTRL_DESC_RRO_EN, 4050 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4051 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4052 E1000_DCA_TXCTRL_DESC_RRO_EN, 4053 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4054 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4055 E1000_DCA_TXCTRL_DESC_RRO_EN, 4056 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4057 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4058 E1000_DCA_TXCTRL_DESC_RRO_EN, 4059 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4060 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4061 E1000_DCA_TXCTRL_DESC_RRO_EN, 4062 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4063 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4064 E1000_DCA_TXCTRL_DESC_RRO_EN, 4065 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4066 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4067 E1000_DCA_TXCTRL_DESC_RRO_EN, 4068 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4069 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4070 E1000_DCA_TXCTRL_DESC_RRO_EN, 4071 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4072 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4073 E1000_DCA_TXCTRL_DESC_RRO_EN, 4074 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4075 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4076 E1000_DCA_TXCTRL_DESC_RRO_EN, 4077 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4078 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4079 E1000_DCA_TXCTRL_DESC_RRO_EN, 4080 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4081 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4082 E1000_DCA_TXCTRL_DESC_RRO_EN, 4083 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN | 4084 E1000_DCA_TXCTRL_TX_WB_RO_EN | 4085 E1000_DCA_TXCTRL_DESC_RRO_EN, 4086 }; 4087 4088 static void igb_reset(IGBCore *core, bool sw) 4089 { 4090 struct igb_tx *tx; 4091 int i; 4092 4093 timer_del(core->autoneg_timer); 4094 4095 igb_intrmgr_reset(core); 4096 4097 memset(core->phy, 0, sizeof core->phy); 4098 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init); 4099 4100 for (i = 0; i < E1000E_MAC_SIZE; i++) { 4101 if (sw && 4102 (i == RXPBS || i == TXPBS || 4103 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) { 4104 continue; 4105 } 4106 4107 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ? 4108 igb_mac_reg_init[i] : 0; 4109 } 4110 4111 if (qemu_get_queue(core->owner_nic)->link_down) { 4112 igb_link_down(core); 4113 } 4114 4115 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 4116 4117 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) { 4118 /* Set RSTI, so VF can identify a PF reset is in progress */ 4119 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI; 4120 } 4121 4122 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4123 tx = &core->tx[i]; 4124 memset(tx->ctx, 0, sizeof(tx->ctx)); 4125 tx->first = true; 4126 tx->skip_cp = false; 4127 } 4128 } 4129 4130 void 4131 igb_core_reset(IGBCore *core) 4132 { 4133 igb_reset(core, false); 4134 } 4135 4136 void igb_core_pre_save(IGBCore *core) 4137 { 4138 int i; 4139 NetClientState *nc = qemu_get_queue(core->owner_nic); 4140 4141 /* 4142 * If link is down and auto-negotiation is supported and ongoing, 4143 * complete auto-negotiation immediately. This allows us to look 4144 * at MII_BMSR_AN_COMP to infer link status on load. 4145 */ 4146 if (nc->link_down && igb_have_autoneg(core)) { 4147 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP; 4148 igb_update_flowctl_status(core); 4149 } 4150 4151 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 4152 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 4153 core->tx[i].skip_cp = true; 4154 } 4155 } 4156 } 4157 4158 int 4159 igb_core_post_load(IGBCore *core) 4160 { 4161 NetClientState *nc = qemu_get_queue(core->owner_nic); 4162 4163 /* 4164 * nc.link_down can't be migrated, so infer link_down according 4165 * to link status bit in core.mac[STATUS]. 4166 */ 4167 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 4168 4169 return 0; 4170 } 4171