1 #ifndef HW_I82596_H 2 #define HW_I82596_H 3 4 #define I82596_IOPORT_SIZE 0x20 5 6 #include "exec/memory.h" 7 #include "exec/address-spaces.h" 8 9 #define PORT_RESET 0x00 /* reset 82596 */ 10 #define PORT_SELFTEST 0x01 /* selftest */ 11 #define PORT_ALTSCP 0x02 /* alternate SCB address */ 12 #define PORT_ALTDUMP 0x03 /* Alternate DUMP address */ 13 #define PORT_CA 0x10 /* QEMU-internal CA signal */ 14 15 typedef struct I82596State_st I82596State; 16 17 struct I82596State_st { 18 MemoryRegion mmio; 19 MemoryRegion *as; 20 qemu_irq irq; 21 NICState *nic; 22 NICConf conf; 23 QEMUTimer *flush_queue_timer; 24 25 hwaddr scp; /* pointer to SCP */ 26 uint8_t sysbus; 27 uint32_t scb; /* SCB */ 28 uint16_t scb_status; 29 uint8_t cu_status, rx_status; 30 uint16_t lnkst; 31 32 uint32_t cmd_p; /* addr of current command */ 33 int ca; 34 int ca_active; 35 int send_irq; 36 37 /* Hash register (multicast mask array, multiple individual addresses). */ 38 uint8_t mult[8]; 39 uint8_t config[14]; /* config bytes from CONFIGURE command */ 40 41 uint8_t tx_buffer[0x4000]; 42 }; 43 44 void i82596_h_reset(void *opaque); 45 void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val); 46 uint32_t i82596_ioport_readw(void *opaque, uint32_t addr); 47 void i82596_ioport_writel(void *opaque, uint32_t addr, uint32_t val); 48 uint32_t i82596_ioport_readl(void *opaque, uint32_t addr); 49 uint32_t i82596_bcr_readw(I82596State *s, uint32_t rap); 50 ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t size_); 51 bool i82596_can_receive(NetClientState *nc); 52 void i82596_set_link_status(NetClientState *nc); 53 void i82596_common_init(DeviceState *dev, I82596State *s, NetClientInfo *info); 54 extern const VMStateDescription vmstate_i82596; 55 #endif 56