1 /* 2 * QEMU Intel i82596 (Apricot) emulation 3 * 4 * Copyright (c) 2019 Helge Deller <deller@gmx.de> 5 * This work is licensed under the GNU GPL license version 2 or later. 6 * 7 * This software was written to be compatible with the specification: 8 * https://www.intel.com/assets/pdf/general/82596ca.pdf 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/timer.h" 13 #include "net/net.h" 14 #include "net/eth.h" 15 #include "hw/irq.h" 16 #include "hw/qdev-properties.h" 17 #include "migration/vmstate.h" 18 #include "qemu/module.h" 19 #include "trace.h" 20 #include "i82596.h" 21 #include <zlib.h> /* For crc32 */ 22 23 #if defined(ENABLE_DEBUG) 24 #define DBG(x) x 25 #else 26 #define DBG(x) do { } while (0) 27 #endif 28 29 #define USE_TIMER 0 30 31 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) 32 33 #define PKT_BUF_SZ 1536 34 #define MAX_MC_CNT 64 35 36 #define ISCP_BUSY 0x0001 37 38 #define I596_NULL ((uint32_t)0xffffffff) 39 40 #define SCB_STATUS_CX 0x8000 /* CU finished command with I bit */ 41 #define SCB_STATUS_FR 0x4000 /* RU finished receiving a frame */ 42 #define SCB_STATUS_CNA 0x2000 /* CU left active state */ 43 #define SCB_STATUS_RNR 0x1000 /* RU left active state */ 44 45 #define SCB_COMMAND_ACK_MASK \ 46 (SCB_STATUS_CX | SCB_STATUS_FR | SCB_STATUS_CNA | SCB_STATUS_RNR) 47 48 #define CU_IDLE 0 49 #define CU_SUSPENDED 1 50 #define CU_ACTIVE 2 51 52 #define RX_IDLE 0 53 #define RX_SUSPENDED 1 54 #define RX_READY 4 55 56 #define CMD_EOL 0x8000 /* The last command of the list, stop. */ 57 #define CMD_SUSP 0x4000 /* Suspend after doing cmd. */ 58 #define CMD_INTR 0x2000 /* Interrupt after doing cmd. */ 59 60 #define CMD_FLEX 0x0008 /* Enable flexible memory model */ 61 62 enum commands { 63 CmdNOp = 0, CmdSASetup = 1, CmdConfigure = 2, CmdMulticastList = 3, 64 CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7 65 }; 66 67 #define STAT_C 0x8000 /* Set to 0 after execution */ 68 #define STAT_B 0x4000 /* Command being executed */ 69 #define STAT_OK 0x2000 /* Command executed ok */ 70 #define STAT_A 0x1000 /* Command aborted */ 71 72 #define I596_EOF 0x8000 73 #define SIZE_MASK 0x3fff 74 75 /* various flags in the chip config registers */ 76 #define I596_PREFETCH (s->config[0] & 0x80) 77 #define I596_PROMISC (s->config[8] & 0x01) 78 #define I596_BC_DISABLE (s->config[8] & 0x02) /* broadcast disable */ 79 #define I596_NOCRC_INS (s->config[8] & 0x08) 80 #define I596_CRCINM (s->config[11] & 0x04) /* CRC appended */ 81 #define I596_MC_ALL (s->config[11] & 0x20) 82 #define I596_MULTIIA (s->config[13] & 0x40) 83 84 85 static uint8_t get_byte(uint32_t addr) 86 { 87 return ldub_phys(&address_space_memory, addr); 88 } 89 90 static void set_byte(uint32_t addr, uint8_t c) 91 { 92 return stb_phys(&address_space_memory, addr, c); 93 } 94 95 static uint16_t get_uint16(uint32_t addr) 96 { 97 return lduw_be_phys(&address_space_memory, addr); 98 } 99 100 static void set_uint16(uint32_t addr, uint16_t w) 101 { 102 return stw_be_phys(&address_space_memory, addr, w); 103 } 104 105 static uint32_t get_uint32(uint32_t addr) 106 { 107 uint32_t lo = lduw_be_phys(&address_space_memory, addr); 108 uint32_t hi = lduw_be_phys(&address_space_memory, addr + 2); 109 return (hi << 16) | lo; 110 } 111 112 static void set_uint32(uint32_t addr, uint32_t val) 113 { 114 set_uint16(addr, (uint16_t) val); 115 set_uint16(addr + 2, val >> 16); 116 } 117 118 119 struct qemu_ether_header { 120 uint8_t ether_dhost[6]; 121 uint8_t ether_shost[6]; 122 uint16_t ether_type; 123 }; 124 125 #define PRINT_PKTHDR(txt, BUF) do { \ 126 struct qemu_ether_header *hdr = (void *)(BUF); \ 127 printf(txt ": packet dhost=" MAC_FMT ", shost=" MAC_FMT ", type=0x%04x\n",\ 128 MAC_ARG(hdr->ether_dhost), MAC_ARG(hdr->ether_shost), \ 129 be16_to_cpu(hdr->ether_type)); \ 130 } while (0) 131 132 static void i82596_transmit(I82596State *s, uint32_t addr) 133 { 134 uint32_t tdb_p; /* Transmit Buffer Descriptor */ 135 136 /* TODO: Check flexible mode */ 137 tdb_p = get_uint32(addr + 8); 138 while (tdb_p != I596_NULL) { 139 uint16_t size, len; 140 uint32_t tba; 141 142 size = get_uint16(tdb_p); 143 len = size & SIZE_MASK; 144 tba = get_uint32(tdb_p + 8); 145 trace_i82596_transmit(len, tba); 146 147 if (s->nic && len) { 148 assert(len <= sizeof(s->tx_buffer)); 149 address_space_read(&address_space_memory, tba, 150 MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len); 151 DBG(PRINT_PKTHDR("Send", &s->tx_buffer)); 152 DBG(printf("Sending %d bytes\n", len)); 153 qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len); 154 } 155 156 /* was this the last package? */ 157 if (size & I596_EOF) { 158 break; 159 } 160 161 /* get next buffer pointer */ 162 tdb_p = get_uint32(tdb_p + 4); 163 } 164 } 165 166 static void set_individual_address(I82596State *s, uint32_t addr) 167 { 168 NetClientState *nc; 169 uint8_t *m; 170 171 nc = qemu_get_queue(s->nic); 172 m = s->conf.macaddr.a; 173 address_space_read(&address_space_memory, addr + 8, 174 MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN); 175 qemu_format_nic_info_str(nc, m); 176 trace_i82596_new_mac(nc->info_str); 177 } 178 179 static void set_multicast_list(I82596State *s, uint32_t addr) 180 { 181 uint16_t mc_count, i; 182 183 memset(&s->mult[0], 0, sizeof(s->mult)); 184 mc_count = get_uint16(addr + 8) / ETH_ALEN; 185 addr += 10; 186 if (mc_count > MAX_MC_CNT) { 187 mc_count = MAX_MC_CNT; 188 } 189 for (i = 0; i < mc_count; i++) { 190 uint8_t multicast_addr[ETH_ALEN]; 191 address_space_read(&address_space_memory, addr + i * ETH_ALEN, 192 MEMTXATTRS_UNSPECIFIED, multicast_addr, ETH_ALEN); 193 DBG(printf("Add multicast entry " MAC_FMT "\n", 194 MAC_ARG(multicast_addr))); 195 unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) & 196 BITS(7, 2)) >> 2; 197 assert(mcast_idx < 8 * sizeof(s->mult)); 198 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); 199 } 200 trace_i82596_set_multicast(mc_count); 201 } 202 203 void i82596_set_link_status(NetClientState *nc) 204 { 205 I82596State *d = qemu_get_nic_opaque(nc); 206 207 d->lnkst = nc->link_down ? 0 : 0x8000; 208 } 209 210 static void update_scb_status(I82596State *s) 211 { 212 s->scb_status = (s->scb_status & 0xf000) 213 | (s->cu_status << 8) | (s->rx_status << 4); 214 set_uint16(s->scb, s->scb_status); 215 } 216 217 218 static void i82596_s_reset(I82596State *s) 219 { 220 trace_i82596_s_reset(s); 221 s->scp = 0; 222 s->scb_status = 0; 223 s->cu_status = CU_IDLE; 224 s->rx_status = RX_SUSPENDED; 225 s->cmd_p = I596_NULL; 226 s->lnkst = 0x8000; /* initial link state: up */ 227 s->ca = s->ca_active = 0; 228 s->send_irq = 0; 229 } 230 231 232 static void command_loop(I82596State *s) 233 { 234 uint16_t cmd; 235 uint16_t status; 236 uint8_t byte_cnt; 237 238 DBG(printf("STARTING COMMAND LOOP cmd_p=%08x\n", s->cmd_p)); 239 240 while (s->cmd_p != I596_NULL) { 241 /* set status */ 242 status = STAT_B; 243 set_uint16(s->cmd_p, status); 244 status = STAT_C | STAT_OK; /* update, but write later */ 245 246 cmd = get_uint16(s->cmd_p + 2); 247 DBG(printf("Running command %04x at %08x\n", cmd, s->cmd_p)); 248 249 switch (cmd & 0x07) { 250 case CmdNOp: 251 break; 252 case CmdSASetup: 253 set_individual_address(s, s->cmd_p); 254 break; 255 case CmdConfigure: 256 byte_cnt = get_byte(s->cmd_p + 8) & 0x0f; 257 byte_cnt = MAX(byte_cnt, 4); 258 byte_cnt = MIN(byte_cnt, sizeof(s->config)); 259 /* copy byte_cnt max. */ 260 address_space_read(&address_space_memory, s->cmd_p + 8, 261 MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt); 262 /* config byte according to page 35ff */ 263 s->config[2] &= 0x82; /* mask valid bits */ 264 s->config[2] |= 0x40; 265 s->config[7] &= 0xf7; /* clear zero bit */ 266 assert(I596_NOCRC_INS == 0); /* do CRC insertion */ 267 s->config[10] = MAX(s->config[10], 5); /* min frame length */ 268 s->config[12] &= 0x40; /* only full duplex field valid */ 269 s->config[13] |= 0x3f; /* set ones in byte 13 */ 270 break; 271 case CmdTDR: 272 /* get signal LINK */ 273 set_uint32(s->cmd_p + 8, s->lnkst); 274 break; 275 case CmdTx: 276 i82596_transmit(s, s->cmd_p); 277 break; 278 case CmdMulticastList: 279 set_multicast_list(s, s->cmd_p); 280 break; 281 case CmdDump: 282 case CmdDiagnose: 283 printf("FIXME Command %d !!\n", cmd & 7); 284 assert(0); 285 } 286 287 /* update status */ 288 set_uint16(s->cmd_p, status); 289 290 s->cmd_p = get_uint32(s->cmd_p + 4); /* get link address */ 291 DBG(printf("NEXT addr would be %08x\n", s->cmd_p)); 292 if (s->cmd_p == 0) { 293 s->cmd_p = I596_NULL; 294 } 295 296 /* Stop when last command of the list. */ 297 if (cmd & CMD_EOL) { 298 s->cmd_p = I596_NULL; 299 } 300 /* Suspend after doing cmd? */ 301 if (cmd & CMD_SUSP) { 302 s->cu_status = CU_SUSPENDED; 303 printf("FIXME SUSPEND !!\n"); 304 } 305 /* Interrupt after doing cmd? */ 306 if (cmd & CMD_INTR) { 307 s->scb_status |= SCB_STATUS_CX; 308 } else { 309 s->scb_status &= ~SCB_STATUS_CX; 310 } 311 update_scb_status(s); 312 313 /* Interrupt after doing cmd? */ 314 if (cmd & CMD_INTR) { 315 s->send_irq = 1; 316 } 317 318 if (s->cu_status != CU_ACTIVE) { 319 break; 320 } 321 } 322 DBG(printf("FINISHED COMMAND LOOP\n")); 323 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 324 } 325 326 static void i82596_flush_queue_timer(void *opaque) 327 { 328 I82596State *s = opaque; 329 if (0) { 330 timer_del(s->flush_queue_timer); 331 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 332 timer_mod(s->flush_queue_timer, 333 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000); 334 } 335 } 336 337 static void examine_scb(I82596State *s) 338 { 339 uint16_t command, cuc, ruc; 340 341 /* get the scb command word */ 342 command = get_uint16(s->scb + 2); 343 cuc = (command >> 8) & 0x7; 344 ruc = (command >> 4) & 0x7; 345 DBG(printf("MAIN COMMAND %04x cuc %02x ruc %02x\n", command, cuc, ruc)); 346 /* and clear the scb command word */ 347 set_uint16(s->scb + 2, 0); 348 349 s->scb_status &= ~(command & SCB_COMMAND_ACK_MASK); 350 351 switch (cuc) { 352 case 0: /* no change */ 353 break; 354 case 1: /* CUC_START */ 355 s->cu_status = CU_ACTIVE; 356 break; 357 case 4: /* CUC_ABORT */ 358 s->cu_status = CU_SUSPENDED; 359 s->scb_status |= SCB_STATUS_CNA; /* CU left active state */ 360 break; 361 default: 362 printf("WARNING: Unknown CUC %d!\n", cuc); 363 } 364 365 switch (ruc) { 366 case 0: /* no change */ 367 break; 368 case 1: /* RX_START */ 369 case 2: /* RX_RESUME */ 370 s->rx_status = RX_IDLE; 371 if (USE_TIMER) { 372 timer_mod(s->flush_queue_timer, qemu_clock_get_ms( 373 QEMU_CLOCK_VIRTUAL) + 1000); 374 } 375 break; 376 case 3: /* RX_SUSPEND */ 377 case 4: /* RX_ABORT */ 378 s->rx_status = RX_SUSPENDED; 379 s->scb_status |= SCB_STATUS_RNR; /* RU left active state */ 380 break; 381 default: 382 printf("WARNING: Unknown RUC %d!\n", ruc); 383 } 384 385 if (command & 0x80) { /* reset bit set? */ 386 i82596_s_reset(s); 387 } 388 389 /* execute commands from SCBL */ 390 if (s->cu_status != CU_SUSPENDED) { 391 if (s->cmd_p == I596_NULL) { 392 s->cmd_p = get_uint32(s->scb + 4); 393 } 394 } 395 396 /* update scb status */ 397 update_scb_status(s); 398 399 command_loop(s); 400 } 401 402 static void signal_ca(I82596State *s) 403 { 404 uint32_t iscp = 0; 405 406 /* trace_i82596_channel_attention(s); */ 407 if (s->scp) { 408 /* CA after reset -> do init with new scp. */ 409 s->sysbus = get_byte(s->scp + 3); /* big endian */ 410 DBG(printf("SYSBUS = %08x\n", s->sysbus)); 411 if (((s->sysbus >> 1) & 0x03) != 2) { 412 printf("WARNING: NO LINEAR MODE !!\n"); 413 } 414 if ((s->sysbus >> 7)) { 415 printf("WARNING: 32BIT LINMODE IN B-STEPPING NOT SUPPORTED !!\n"); 416 } 417 iscp = get_uint32(s->scp + 8); 418 s->scb = get_uint32(iscp + 4); 419 set_byte(iscp + 1, 0); /* clear BUSY flag in iscp */ 420 s->scp = 0; 421 } 422 423 s->ca++; /* count ca() */ 424 if (!s->ca_active) { 425 s->ca_active = 1; 426 while (s->ca) { 427 examine_scb(s); 428 s->ca--; 429 } 430 s->ca_active = 0; 431 } 432 433 if (s->send_irq) { 434 s->send_irq = 0; 435 qemu_set_irq(s->irq, 1); 436 } 437 } 438 439 void i82596_ioport_writew(void *opaque, uint32_t addr, uint32_t val) 440 { 441 I82596State *s = opaque; 442 /* printf("i82596_ioport_writew addr=0x%08x val=0x%04x\n", addr, val); */ 443 switch (addr) { 444 case PORT_RESET: /* Reset */ 445 i82596_s_reset(s); 446 break; 447 case PORT_ALTSCP: 448 s->scp = val; 449 break; 450 case PORT_CA: 451 signal_ca(s); 452 break; 453 } 454 } 455 456 uint32_t i82596_ioport_readw(void *opaque, uint32_t addr) 457 { 458 return -1; 459 } 460 461 void i82596_h_reset(void *opaque) 462 { 463 I82596State *s = opaque; 464 465 i82596_s_reset(s); 466 } 467 468 bool i82596_can_receive(NetClientState *nc) 469 { 470 I82596State *s = qemu_get_nic_opaque(nc); 471 472 if (s->rx_status == RX_SUSPENDED) { 473 return false; 474 } 475 476 if (!s->lnkst) { 477 return false; 478 } 479 480 if (USE_TIMER && !timer_pending(s->flush_queue_timer)) { 481 return true; 482 } 483 484 return true; 485 } 486 487 ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz) 488 { 489 I82596State *s = qemu_get_nic_opaque(nc); 490 uint32_t rfd_p; 491 uint32_t rbd; 492 uint16_t is_broadcast = 0; 493 size_t len = sz; /* length of data for guest (including CRC) */ 494 size_t bufsz = sz; /* length of data in buf */ 495 uint32_t crc; 496 uint8_t *crc_ptr; 497 static const uint8_t broadcast_macaddr[6] = { 498 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 499 500 DBG(printf("i82596_receive() start\n")); 501 502 if (USE_TIMER && timer_pending(s->flush_queue_timer)) { 503 return 0; 504 } 505 506 /* first check if receiver is enabled */ 507 if (s->rx_status == RX_SUSPENDED) { 508 trace_i82596_receive_analysis(">>> Receiving suspended"); 509 return -1; 510 } 511 512 if (!s->lnkst) { 513 trace_i82596_receive_analysis(">>> Link down"); 514 return -1; 515 } 516 517 /* Received frame smaller than configured "min frame len"? */ 518 if (sz < s->config[10]) { 519 printf("Received frame too small, %zu vs. %u bytes\n", 520 sz, s->config[10]); 521 return -1; 522 } 523 524 DBG(printf("Received %lu bytes\n", sz)); 525 526 if (I596_PROMISC) { 527 528 /* promiscuous: receive all */ 529 trace_i82596_receive_analysis( 530 ">>> packet received in promiscuous mode"); 531 532 } else { 533 534 if (!memcmp(buf, broadcast_macaddr, 6)) { 535 /* broadcast address */ 536 if (I596_BC_DISABLE) { 537 trace_i82596_receive_analysis(">>> broadcast packet rejected"); 538 539 return len; 540 } 541 542 trace_i82596_receive_analysis(">>> broadcast packet received"); 543 is_broadcast = 1; 544 545 } else if (buf[0] & 0x01) { 546 /* multicast */ 547 if (!I596_MC_ALL) { 548 trace_i82596_receive_analysis(">>> multicast packet rejected"); 549 550 return len; 551 } 552 553 int mcast_idx = (net_crc32(buf, ETH_ALEN) & BITS(7, 2)) >> 2; 554 assert(mcast_idx < 8 * sizeof(s->mult)); 555 556 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { 557 trace_i82596_receive_analysis(">>> multicast address mismatch"); 558 559 return len; 560 } 561 562 trace_i82596_receive_analysis(">>> multicast packet received"); 563 is_broadcast = 1; 564 565 } else if (!memcmp(s->conf.macaddr.a, buf, 6)) { 566 567 /* match */ 568 trace_i82596_receive_analysis( 569 ">>> physical address matching packet received"); 570 571 } else { 572 573 trace_i82596_receive_analysis(">>> unknown packet"); 574 575 return len; 576 } 577 } 578 579 /* Calculate the ethernet checksum (4 bytes) */ 580 len += 4; 581 crc = cpu_to_be32(crc32(~0, buf, sz)); 582 crc_ptr = (uint8_t *) &crc; 583 584 rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */ 585 assert(rfd_p && rfd_p != I596_NULL); 586 587 /* get first Receive Buffer Descriptor Address */ 588 rbd = get_uint32(rfd_p + 8); 589 assert(rbd && rbd != I596_NULL); 590 591 trace_i82596_receive_packet(len); 592 /* PRINT_PKTHDR("Receive", buf); */ 593 594 while (len) { 595 uint16_t command, status; 596 uint32_t next_rfd; 597 598 command = get_uint16(rfd_p + 2); 599 assert(command & CMD_FLEX); /* assert Flex Mode */ 600 /* get first Receive Buffer Descriptor Address */ 601 rbd = get_uint32(rfd_p + 8); 602 assert(get_uint16(rfd_p + 14) == 0); 603 604 /* printf("Receive: rfd is %08x\n", rfd_p); */ 605 606 while (len) { 607 uint16_t buffer_size, num; 608 uint32_t rba; 609 size_t bufcount, crccount; 610 611 /* printf("Receive: rbd is %08x\n", rbd); */ 612 buffer_size = get_uint16(rbd + 12); 613 /* printf("buffer_size is 0x%x\n", buffer_size); */ 614 assert(buffer_size != 0); 615 616 num = buffer_size & SIZE_MASK; 617 if (num > len) { 618 num = len; 619 } 620 rba = get_uint32(rbd + 8); 621 /* printf("rba is 0x%x\n", rba); */ 622 /* 623 * Calculate how many bytes we want from buf[] and how many 624 * from the CRC. 625 */ 626 if ((len - num) >= 4) { 627 /* The whole guest buffer, we haven't hit the CRC yet */ 628 bufcount = num; 629 } else { 630 /* All that's left of buf[] */ 631 bufcount = len - 4; 632 } 633 crccount = num - bufcount; 634 635 if (bufcount > 0) { 636 /* Still some of the actual data buffer to transfer */ 637 assert(bufsz >= bufcount); 638 bufsz -= bufcount; 639 address_space_write(&address_space_memory, rba, 640 MEMTXATTRS_UNSPECIFIED, buf, bufcount); 641 rba += bufcount; 642 buf += bufcount; 643 len -= bufcount; 644 } 645 646 /* Write as much of the CRC as fits */ 647 if (crccount > 0) { 648 address_space_write(&address_space_memory, rba, 649 MEMTXATTRS_UNSPECIFIED, crc_ptr, crccount); 650 rba += crccount; 651 crc_ptr += crccount; 652 len -= crccount; 653 } 654 655 num |= 0x4000; /* set F BIT */ 656 if (len == 0) { 657 num |= I596_EOF; /* set EOF BIT */ 658 } 659 set_uint16(rbd + 0, num); /* write actual count with flags */ 660 661 /* get next rbd */ 662 rbd = get_uint32(rbd + 4); 663 /* printf("Next Receive: rbd is %08x\n", rbd); */ 664 665 if (buffer_size & I596_EOF) /* last entry */ 666 break; 667 } 668 669 /* Housekeeping, see pg. 18 */ 670 next_rfd = get_uint32(rfd_p + 4); 671 set_uint32(next_rfd + 8, rbd); 672 673 status = STAT_C | STAT_OK | is_broadcast; 674 set_uint16(rfd_p, status); 675 676 if (command & CMD_SUSP) { /* suspend after command? */ 677 s->rx_status = RX_SUSPENDED; 678 s->scb_status |= SCB_STATUS_RNR; /* RU left active state */ 679 break; 680 } 681 if (command & CMD_EOL) /* was it last Frame Descriptor? */ 682 break; 683 684 assert(len == 0); 685 } 686 687 assert(len == 0); 688 689 s->scb_status |= SCB_STATUS_FR; /* set "RU finished receiving frame" bit. */ 690 update_scb_status(s); 691 692 /* send IRQ that we received data */ 693 qemu_set_irq(s->irq, 1); 694 /* s->send_irq = 1; */ 695 696 if (0) { 697 DBG(printf("Checking:\n")); 698 rfd_p = get_uint32(s->scb + 8); /* get Receive Frame Descriptor */ 699 DBG(printf("Next Receive: rfd is %08x\n", rfd_p)); 700 rfd_p = get_uint32(rfd_p + 4); /* get Next Receive Frame Descriptor */ 701 DBG(printf("Next Receive: rfd is %08x\n", rfd_p)); 702 /* get first Receive Buffer Descriptor Address */ 703 rbd = get_uint32(rfd_p + 8); 704 DBG(printf("Next Receive: rbd is %08x\n", rbd)); 705 } 706 707 return sz; 708 } 709 710 711 const VMStateDescription vmstate_i82596 = { 712 .name = "i82596", 713 .version_id = 1, 714 .minimum_version_id = 1, 715 .fields = (VMStateField[]) { 716 VMSTATE_UINT16(lnkst, I82596State), 717 VMSTATE_TIMER_PTR(flush_queue_timer, I82596State), 718 VMSTATE_END_OF_LIST() 719 } 720 }; 721 722 void i82596_common_init(DeviceState *dev, I82596State *s, NetClientInfo *info) 723 { 724 if (s->conf.macaddr.a[0] == 0) { 725 qemu_macaddr_default_if_unset(&s->conf.macaddr); 726 } 727 s->nic = qemu_new_nic(info, &s->conf, object_get_typename(OBJECT(dev)), 728 dev->id, s); 729 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 730 731 if (USE_TIMER) { 732 s->flush_queue_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 733 i82596_flush_queue_timer, s); 734 } 735 s->lnkst = 0x8000; /* initial link state: up */ 736 } 737