1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * Copyright (C) 2016-2017, IBM Corporation. 5 * 6 * Based on Coldfire Fast Ethernet Controller emulation. 7 * 8 * Copyright (c) 2007 CodeSourcery. 9 * 10 * This code is licensed under the GPL version 2 or later. See the 11 * COPYING file in the top-level directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "hw/irq.h" 16 #include "hw/net/ftgmac100.h" 17 #include "sysemu/dma.h" 18 #include "qemu/log.h" 19 #include "qemu/module.h" 20 #include "net/checksum.h" 21 #include "net/eth.h" 22 #include "hw/net/mii.h" 23 24 /* For crc32 */ 25 #include <zlib.h> 26 27 /* 28 * FTGMAC100 registers 29 */ 30 #define FTGMAC100_ISR 0x00 31 #define FTGMAC100_IER 0x04 32 #define FTGMAC100_MAC_MADR 0x08 33 #define FTGMAC100_MAC_LADR 0x0c 34 #define FTGMAC100_MATH0 0x10 35 #define FTGMAC100_MATH1 0x14 36 #define FTGMAC100_NPTXPD 0x18 37 #define FTGMAC100_RXPD 0x1C 38 #define FTGMAC100_NPTXR_BADR 0x20 39 #define FTGMAC100_RXR_BADR 0x24 40 #define FTGMAC100_HPTXPD 0x28 41 #define FTGMAC100_HPTXR_BADR 0x2c 42 #define FTGMAC100_ITC 0x30 43 #define FTGMAC100_APTC 0x34 44 #define FTGMAC100_DBLAC 0x38 45 #define FTGMAC100_REVR 0x40 46 #define FTGMAC100_FEAR1 0x44 47 #define FTGMAC100_RBSR 0x4c 48 #define FTGMAC100_TPAFCR 0x48 49 50 #define FTGMAC100_MACCR 0x50 51 #define FTGMAC100_MACSR 0x54 52 #define FTGMAC100_PHYCR 0x60 53 #define FTGMAC100_PHYDATA 0x64 54 #define FTGMAC100_FCR 0x68 55 56 /* 57 * Interrupt status register & interrupt enable register 58 */ 59 #define FTGMAC100_INT_RPKT_BUF (1 << 0) 60 #define FTGMAC100_INT_RPKT_FIFO (1 << 1) 61 #define FTGMAC100_INT_NO_RXBUF (1 << 2) 62 #define FTGMAC100_INT_RPKT_LOST (1 << 3) 63 #define FTGMAC100_INT_XPKT_ETH (1 << 4) 64 #define FTGMAC100_INT_XPKT_FIFO (1 << 5) 65 #define FTGMAC100_INT_NO_NPTXBUF (1 << 6) 66 #define FTGMAC100_INT_XPKT_LOST (1 << 7) 67 #define FTGMAC100_INT_AHB_ERR (1 << 8) 68 #define FTGMAC100_INT_PHYSTS_CHG (1 << 9) 69 #define FTGMAC100_INT_NO_HPTXBUF (1 << 10) 70 71 /* 72 * Automatic polling timer control register 73 */ 74 #define FTGMAC100_APTC_RXPOLL_CNT(x) ((x) & 0xf) 75 #define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 76 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf) 77 #define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 78 79 /* 80 * PHY control register 81 */ 82 #define FTGMAC100_PHYCR_MIIRD (1 << 26) 83 #define FTGMAC100_PHYCR_MIIWR (1 << 27) 84 85 #define FTGMAC100_PHYCR_DEV(x) (((x) >> 16) & 0x1f) 86 #define FTGMAC100_PHYCR_REG(x) (((x) >> 21) & 0x1f) 87 88 /* 89 * PHY data register 90 */ 91 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) 92 #define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff) 93 94 /* 95 * PHY control register - New MDC/MDIO interface 96 */ 97 #define FTGMAC100_PHYCR_NEW_DATA(x) (((x) >> 16) & 0xffff) 98 #define FTGMAC100_PHYCR_NEW_FIRE (1 << 15) 99 #define FTGMAC100_PHYCR_NEW_ST_22 (1 << 12) 100 #define FTGMAC100_PHYCR_NEW_OP(x) (((x) >> 10) & 3) 101 #define FTGMAC100_PHYCR_NEW_OP_WRITE 0x1 102 #define FTGMAC100_PHYCR_NEW_OP_READ 0x2 103 #define FTGMAC100_PHYCR_NEW_DEV(x) (((x) >> 5) & 0x1f) 104 #define FTGMAC100_PHYCR_NEW_REG(x) ((x) & 0x1f) 105 106 /* 107 * Feature Register 108 */ 109 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE (1 << 31) 110 111 /* 112 * MAC control register 113 */ 114 #define FTGMAC100_MACCR_TXDMA_EN (1 << 0) 115 #define FTGMAC100_MACCR_RXDMA_EN (1 << 1) 116 #define FTGMAC100_MACCR_TXMAC_EN (1 << 2) 117 #define FTGMAC100_MACCR_RXMAC_EN (1 << 3) 118 #define FTGMAC100_MACCR_RM_VLAN (1 << 4) 119 #define FTGMAC100_MACCR_HPTXR_EN (1 << 5) 120 #define FTGMAC100_MACCR_LOOP_EN (1 << 6) 121 #define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) 122 #define FTGMAC100_MACCR_FULLDUP (1 << 8) 123 #define FTGMAC100_MACCR_GIGA_MODE (1 << 9) 124 #define FTGMAC100_MACCR_CRC_APD (1 << 10) /* not needed */ 125 #define FTGMAC100_MACCR_RX_RUNT (1 << 12) 126 #define FTGMAC100_MACCR_JUMBO_LF (1 << 13) 127 #define FTGMAC100_MACCR_RX_ALL (1 << 14) 128 #define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) 129 #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) 130 #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) 131 #define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) 132 #define FTGMAC100_MACCR_FAST_MODE (1 << 19) 133 #define FTGMAC100_MACCR_SW_RST (1 << 31) 134 135 /* 136 * Transmit descriptor 137 */ 138 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) 139 #define FTGMAC100_TXDES0_EDOTR (1 << 15) 140 #define FTGMAC100_TXDES0_CRC_ERR (1 << 19) 141 #define FTGMAC100_TXDES0_LTS (1 << 28) 142 #define FTGMAC100_TXDES0_FTS (1 << 29) 143 #define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30) 144 #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) 145 146 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) 147 #define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) 148 #define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) 149 #define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) 150 #define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) 151 #define FTGMAC100_TXDES1_LLC (1 << 22) 152 #define FTGMAC100_TXDES1_TX2FIC (1 << 30) 153 #define FTGMAC100_TXDES1_TXIC (1 << 31) 154 155 /* 156 * Receive descriptor 157 */ 158 #define FTGMAC100_RXDES0_VDBC 0x3fff 159 #define FTGMAC100_RXDES0_EDORR (1 << 15) 160 #define FTGMAC100_RXDES0_MULTICAST (1 << 16) 161 #define FTGMAC100_RXDES0_BROADCAST (1 << 17) 162 #define FTGMAC100_RXDES0_RX_ERR (1 << 18) 163 #define FTGMAC100_RXDES0_CRC_ERR (1 << 19) 164 #define FTGMAC100_RXDES0_FTL (1 << 20) 165 #define FTGMAC100_RXDES0_RUNT (1 << 21) 166 #define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) 167 #define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) 168 #define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) 169 #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) 170 #define FTGMAC100_RXDES0_LRS (1 << 28) 171 #define FTGMAC100_RXDES0_FRS (1 << 29) 172 #define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30) 173 #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) 174 175 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff 176 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) 177 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) 178 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) 179 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) 180 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) 181 #define FTGMAC100_RXDES1_LLC (1 << 22) 182 #define FTGMAC100_RXDES1_DF (1 << 23) 183 #define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) 184 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) 185 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) 186 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) 187 188 /* 189 * Receive and transmit Buffer Descriptor 190 */ 191 typedef struct { 192 uint32_t des0; 193 uint32_t des1; 194 uint32_t des2; /* not used by HW */ 195 uint32_t des3; 196 } FTGMAC100Desc; 197 198 /* 199 * Specific RTL8211E MII Registers 200 */ 201 #define RTL8211E_MII_PHYCR 16 /* PHY Specific Control */ 202 #define RTL8211E_MII_PHYSR 17 /* PHY Specific Status */ 203 #define RTL8211E_MII_INER 18 /* Interrupt Enable */ 204 #define RTL8211E_MII_INSR 19 /* Interrupt Status */ 205 #define RTL8211E_MII_RXERC 24 /* Receive Error Counter */ 206 #define RTL8211E_MII_LDPSR 27 /* Link Down Power Saving */ 207 #define RTL8211E_MII_EPAGSR 30 /* Extension Page Select */ 208 #define RTL8211E_MII_PAGSEL 31 /* Page Select */ 209 210 /* 211 * RTL8211E Interrupt Status 212 */ 213 #define PHY_INT_AUTONEG_ERROR (1 << 15) 214 #define PHY_INT_PAGE_RECV (1 << 12) 215 #define PHY_INT_AUTONEG_COMPLETE (1 << 11) 216 #define PHY_INT_LINK_STATUS (1 << 10) 217 #define PHY_INT_ERROR (1 << 9) 218 #define PHY_INT_DOWN (1 << 8) 219 #define PHY_INT_JABBER (1 << 0) 220 221 /* 222 * Max frame size for the receiving buffer 223 */ 224 #define FTGMAC100_MAX_FRAME_SIZE 9220 225 226 /* Limits depending on the type of the frame 227 * 228 * 9216 for Jumbo frames (+ 4 for VLAN) 229 * 1518 for other frames (+ 4 for VLAN) 230 */ 231 static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto) 232 { 233 int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518); 234 235 return max + (proto == ETH_P_VLAN ? 4 : 0); 236 } 237 238 static void ftgmac100_update_irq(FTGMAC100State *s) 239 { 240 qemu_set_irq(s->irq, s->isr & s->ier); 241 } 242 243 /* 244 * The MII phy could raise a GPIO to the processor which in turn 245 * could be handled as an interrpt by the OS. 246 * For now we don't handle any GPIO/interrupt line, so the OS will 247 * have to poll for the PHY status. 248 */ 249 static void phy_update_irq(FTGMAC100State *s) 250 { 251 ftgmac100_update_irq(s); 252 } 253 254 static void phy_update_link(FTGMAC100State *s) 255 { 256 /* Autonegotiation status mirrors link status. */ 257 if (qemu_get_queue(s->nic)->link_down) { 258 s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 259 s->phy_int |= PHY_INT_DOWN; 260 } else { 261 s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 262 s->phy_int |= PHY_INT_AUTONEG_COMPLETE; 263 } 264 phy_update_irq(s); 265 } 266 267 static void ftgmac100_set_link(NetClientState *nc) 268 { 269 phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc))); 270 } 271 272 static void phy_reset(FTGMAC100State *s) 273 { 274 s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | 275 MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS | 276 MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST | 277 MII_BMSR_EXTCAP); 278 s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000); 279 s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD | 280 MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | 281 MII_ANAR_CSMACD); 282 s->phy_int_mask = 0; 283 s->phy_int = 0; 284 } 285 286 static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg) 287 { 288 uint16_t val; 289 290 switch (reg) { 291 case MII_BMCR: /* Basic Control */ 292 val = s->phy_control; 293 break; 294 case MII_BMSR: /* Basic Status */ 295 val = s->phy_status; 296 break; 297 case MII_PHYID1: /* ID1 */ 298 val = RTL8211E_PHYID1; 299 break; 300 case MII_PHYID2: /* ID2 */ 301 val = RTL8211E_PHYID2; 302 break; 303 case MII_ANAR: /* Auto-neg advertisement */ 304 val = s->phy_advertise; 305 break; 306 case MII_ANLPAR: /* Auto-neg Link Partner Ability */ 307 val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD | 308 MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 | 309 MII_ANLPAR_CSMACD); 310 break; 311 case MII_ANER: /* Auto-neg Expansion */ 312 val = MII_ANER_NWAY; 313 break; 314 case MII_CTRL1000: /* 1000BASE-T control */ 315 val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL); 316 break; 317 case MII_STAT1000: /* 1000BASE-T status */ 318 val = MII_STAT1000_FULL; 319 break; 320 case RTL8211E_MII_INSR: /* Interrupt status. */ 321 val = s->phy_int; 322 s->phy_int = 0; 323 phy_update_irq(s); 324 break; 325 case RTL8211E_MII_INER: /* Interrupt enable */ 326 val = s->phy_int_mask; 327 break; 328 case RTL8211E_MII_PHYCR: 329 case RTL8211E_MII_PHYSR: 330 case RTL8211E_MII_RXERC: 331 case RTL8211E_MII_LDPSR: 332 case RTL8211E_MII_EPAGSR: 333 case RTL8211E_MII_PAGSEL: 334 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", 335 __func__, reg); 336 val = 0; 337 break; 338 default: 339 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", 340 __func__, reg); 341 val = 0; 342 break; 343 } 344 345 return val; 346 } 347 348 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | \ 349 MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \ 350 MII_BMCR_FD | MII_BMCR_CTST) 351 #define MII_ANAR_MASK 0x2d7f 352 353 static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val) 354 { 355 switch (reg) { 356 case MII_BMCR: /* Basic Control */ 357 if (val & MII_BMCR_RESET) { 358 phy_reset(s); 359 } else { 360 s->phy_control = val & MII_BMCR_MASK; 361 /* Complete autonegotiation immediately. */ 362 if (val & MII_BMCR_AUTOEN) { 363 s->phy_status |= MII_BMSR_AN_COMP; 364 } 365 } 366 break; 367 case MII_ANAR: /* Auto-neg advertisement */ 368 s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX; 369 break; 370 case RTL8211E_MII_INER: /* Interrupt enable */ 371 s->phy_int_mask = val & 0xff; 372 phy_update_irq(s); 373 break; 374 case RTL8211E_MII_PHYCR: 375 case RTL8211E_MII_PHYSR: 376 case RTL8211E_MII_RXERC: 377 case RTL8211E_MII_LDPSR: 378 case RTL8211E_MII_EPAGSR: 379 case RTL8211E_MII_PAGSEL: 380 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", 381 __func__, reg); 382 break; 383 default: 384 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", 385 __func__, reg); 386 break; 387 } 388 } 389 390 static void do_phy_new_ctl(FTGMAC100State *s) 391 { 392 uint8_t reg; 393 uint16_t data; 394 395 if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) { 396 qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__); 397 return; 398 } 399 400 /* Nothing to do */ 401 if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) { 402 return; 403 } 404 405 reg = FTGMAC100_PHYCR_NEW_REG(s->phycr); 406 data = FTGMAC100_PHYCR_NEW_DATA(s->phycr); 407 408 switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) { 409 case FTGMAC100_PHYCR_NEW_OP_WRITE: 410 do_phy_write(s, reg, data); 411 break; 412 case FTGMAC100_PHYCR_NEW_OP_READ: 413 s->phydata = do_phy_read(s, reg) & 0xffff; 414 break; 415 default: 416 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n", 417 __func__, s->phycr); 418 } 419 420 s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE; 421 } 422 423 static void do_phy_ctl(FTGMAC100State *s) 424 { 425 uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr); 426 427 if (s->phycr & FTGMAC100_PHYCR_MIIWR) { 428 do_phy_write(s, reg, s->phydata & 0xffff); 429 s->phycr &= ~FTGMAC100_PHYCR_MIIWR; 430 } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) { 431 s->phydata = do_phy_read(s, reg) << 16; 432 s->phycr &= ~FTGMAC100_PHYCR_MIIRD; 433 } else { 434 qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n", 435 __func__, s->phycr); 436 } 437 } 438 439 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr) 440 { 441 if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) { 442 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%" 443 HWADDR_PRIx "\n", __func__, addr); 444 return -1; 445 } 446 bd->des0 = le32_to_cpu(bd->des0); 447 bd->des1 = le32_to_cpu(bd->des1); 448 bd->des2 = le32_to_cpu(bd->des2); 449 bd->des3 = le32_to_cpu(bd->des3); 450 return 0; 451 } 452 453 static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr) 454 { 455 FTGMAC100Desc lebd; 456 457 lebd.des0 = cpu_to_le32(bd->des0); 458 lebd.des1 = cpu_to_le32(bd->des1); 459 lebd.des2 = cpu_to_le32(bd->des2); 460 lebd.des3 = cpu_to_le32(bd->des3); 461 if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))) { 462 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%" 463 HWADDR_PRIx "\n", __func__, addr); 464 return -1; 465 } 466 return 0; 467 } 468 469 static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring, 470 uint32_t tx_descriptor) 471 { 472 int frame_size = 0; 473 uint8_t *ptr = s->frame; 474 uint32_t addr = tx_descriptor; 475 uint32_t flags = 0; 476 477 while (1) { 478 FTGMAC100Desc bd; 479 int len; 480 481 if (ftgmac100_read_bd(&bd, addr) || 482 ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) { 483 /* Run out of descriptors to transmit. */ 484 s->isr |= FTGMAC100_INT_NO_NPTXBUF; 485 break; 486 } 487 488 /* record transmit flags as they are valid only on the first 489 * segment */ 490 if (bd.des0 & FTGMAC100_TXDES0_FTS) { 491 flags = bd.des1; 492 } 493 494 len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0); 495 if (frame_size + len > sizeof(s->frame)) { 496 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n", 497 __func__, len); 498 s->isr |= FTGMAC100_INT_XPKT_LOST; 499 len = sizeof(s->frame) - frame_size; 500 } 501 502 if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) { 503 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n", 504 __func__, bd.des3); 505 s->isr |= FTGMAC100_INT_NO_NPTXBUF; 506 break; 507 } 508 509 /* Check for VLAN */ 510 if (bd.des0 & FTGMAC100_TXDES0_FTS && 511 bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG && 512 be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) { 513 if (frame_size + len + 4 > sizeof(s->frame)) { 514 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n", 515 __func__, len); 516 s->isr |= FTGMAC100_INT_XPKT_LOST; 517 len = sizeof(s->frame) - frame_size - 4; 518 } 519 memmove(ptr + 16, ptr + 12, len - 12); 520 stw_be_p(ptr + 12, ETH_P_VLAN); 521 stw_be_p(ptr + 14, bd.des1); 522 len += 4; 523 } 524 525 ptr += len; 526 frame_size += len; 527 if (bd.des0 & FTGMAC100_TXDES0_LTS) { 528 if (flags & FTGMAC100_TXDES1_IP_CHKSUM) { 529 net_checksum_calculate(s->frame, frame_size); 530 } 531 /* Last buffer in frame. */ 532 qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size); 533 ptr = s->frame; 534 frame_size = 0; 535 if (flags & FTGMAC100_TXDES1_TXIC) { 536 s->isr |= FTGMAC100_INT_XPKT_ETH; 537 } 538 } 539 540 if (flags & FTGMAC100_TXDES1_TX2FIC) { 541 s->isr |= FTGMAC100_INT_XPKT_FIFO; 542 } 543 bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN; 544 545 /* Write back the modified descriptor. */ 546 ftgmac100_write_bd(&bd, addr); 547 /* Advance to the next descriptor. */ 548 if (bd.des0 & s->txdes0_edotr) { 549 addr = tx_ring; 550 } else { 551 addr += sizeof(FTGMAC100Desc); 552 } 553 } 554 555 s->tx_descriptor = addr; 556 557 ftgmac100_update_irq(s); 558 } 559 560 static int ftgmac100_can_receive(NetClientState *nc) 561 { 562 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); 563 FTGMAC100Desc bd; 564 565 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) 566 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) { 567 return 0; 568 } 569 570 if (ftgmac100_read_bd(&bd, s->rx_descriptor)) { 571 return 0; 572 } 573 return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY); 574 } 575 576 /* 577 * This is purely informative. The HW can poll the RW (and RX) ring 578 * buffers for available descriptors but we don't need to trigger a 579 * timer for that in qemu. 580 */ 581 static uint32_t ftgmac100_rxpoll(FTGMAC100State *s) 582 { 583 /* Polling times : 584 * 585 * Speed TIME_SEL=0 TIME_SEL=1 586 * 587 * 10 51.2 ms 819.2 ms 588 * 100 5.12 ms 81.92 ms 589 * 1000 1.024 ms 16.384 ms 590 */ 591 static const int div[] = { 20, 200, 1000 }; 592 593 uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr); 594 uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0; 595 596 if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) { 597 cnt <<= 4; 598 } 599 600 if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) { 601 speed = 2; 602 } 603 604 return cnt / div[speed]; 605 } 606 607 static void ftgmac100_reset(DeviceState *d) 608 { 609 FTGMAC100State *s = FTGMAC100(d); 610 611 /* Reset the FTGMAC100 */ 612 s->isr = 0; 613 s->ier = 0; 614 s->rx_enabled = 0; 615 s->rx_ring = 0; 616 s->rbsr = 0x640; 617 s->rx_descriptor = 0; 618 s->tx_ring = 0; 619 s->tx_descriptor = 0; 620 s->math[0] = 0; 621 s->math[1] = 0; 622 s->itc = 0; 623 s->aptcr = 1; 624 s->dblac = 0x00022f00; 625 s->revr = 0; 626 s->fear1 = 0; 627 s->tpafcr = 0xf1; 628 629 s->maccr = 0; 630 s->phycr = 0; 631 s->phydata = 0; 632 s->fcr = 0x400; 633 634 /* and the PHY */ 635 phy_reset(s); 636 } 637 638 static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size) 639 { 640 FTGMAC100State *s = FTGMAC100(opaque); 641 642 switch (addr & 0xff) { 643 case FTGMAC100_ISR: 644 return s->isr; 645 case FTGMAC100_IER: 646 return s->ier; 647 case FTGMAC100_MAC_MADR: 648 return (s->conf.macaddr.a[0] << 8) | s->conf.macaddr.a[1]; 649 case FTGMAC100_MAC_LADR: 650 return ((uint32_t) s->conf.macaddr.a[2] << 24) | 651 (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) | 652 s->conf.macaddr.a[5]; 653 case FTGMAC100_MATH0: 654 return s->math[0]; 655 case FTGMAC100_MATH1: 656 return s->math[1]; 657 case FTGMAC100_ITC: 658 return s->itc; 659 case FTGMAC100_DBLAC: 660 return s->dblac; 661 case FTGMAC100_REVR: 662 return s->revr; 663 case FTGMAC100_FEAR1: 664 return s->fear1; 665 case FTGMAC100_TPAFCR: 666 return s->tpafcr; 667 case FTGMAC100_FCR: 668 return s->fcr; 669 case FTGMAC100_MACCR: 670 return s->maccr; 671 case FTGMAC100_PHYCR: 672 return s->phycr; 673 case FTGMAC100_PHYDATA: 674 return s->phydata; 675 676 /* We might want to support these one day */ 677 case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */ 678 case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */ 679 case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */ 680 qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%" 681 HWADDR_PRIx "\n", __func__, addr); 682 return 0; 683 default: 684 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%" 685 HWADDR_PRIx "\n", __func__, addr); 686 return 0; 687 } 688 } 689 690 static void ftgmac100_write(void *opaque, hwaddr addr, 691 uint64_t value, unsigned size) 692 { 693 FTGMAC100State *s = FTGMAC100(opaque); 694 695 switch (addr & 0xff) { 696 case FTGMAC100_ISR: /* Interrupt status */ 697 s->isr &= ~value; 698 break; 699 case FTGMAC100_IER: /* Interrupt control */ 700 s->ier = value; 701 break; 702 case FTGMAC100_MAC_MADR: /* MAC */ 703 s->conf.macaddr.a[0] = value >> 8; 704 s->conf.macaddr.a[1] = value; 705 break; 706 case FTGMAC100_MAC_LADR: 707 s->conf.macaddr.a[2] = value >> 24; 708 s->conf.macaddr.a[3] = value >> 16; 709 s->conf.macaddr.a[4] = value >> 8; 710 s->conf.macaddr.a[5] = value; 711 break; 712 case FTGMAC100_MATH0: /* Multicast Address Hash Table 0 */ 713 s->math[0] = value; 714 break; 715 case FTGMAC100_MATH1: /* Multicast Address Hash Table 1 */ 716 s->math[1] = value; 717 break; 718 case FTGMAC100_ITC: /* TODO: Interrupt Timer Control */ 719 s->itc = value; 720 break; 721 case FTGMAC100_RXR_BADR: /* Ring buffer address */ 722 s->rx_ring = value; 723 s->rx_descriptor = s->rx_ring; 724 break; 725 726 case FTGMAC100_RBSR: /* DMA buffer size */ 727 s->rbsr = value; 728 break; 729 730 case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */ 731 s->tx_ring = value; 732 s->tx_descriptor = s->tx_ring; 733 break; 734 735 case FTGMAC100_NPTXPD: /* Trigger transmit */ 736 if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) 737 == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) { 738 /* TODO: high priority tx ring */ 739 ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor); 740 } 741 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) { 742 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 743 } 744 break; 745 746 case FTGMAC100_RXPD: /* Receive Poll Demand Register */ 747 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) { 748 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 749 } 750 break; 751 752 case FTGMAC100_APTC: /* Automatic polling */ 753 s->aptcr = value; 754 755 if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) { 756 ftgmac100_rxpoll(s); 757 } 758 759 if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) { 760 qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__); 761 } 762 break; 763 764 case FTGMAC100_MACCR: /* MAC Device control */ 765 s->maccr = value; 766 if (value & FTGMAC100_MACCR_SW_RST) { 767 ftgmac100_reset(DEVICE(s)); 768 } 769 770 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) { 771 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 772 } 773 break; 774 775 case FTGMAC100_PHYCR: /* PHY Device control */ 776 s->phycr = value; 777 if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) { 778 do_phy_new_ctl(s); 779 } else { 780 do_phy_ctl(s); 781 } 782 break; 783 case FTGMAC100_PHYDATA: 784 s->phydata = value & 0xffff; 785 break; 786 case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */ 787 s->dblac = value; 788 break; 789 case FTGMAC100_REVR: /* Feature Register */ 790 s->revr = value; 791 break; 792 case FTGMAC100_FEAR1: /* Feature Register 1 */ 793 s->fear1 = value; 794 break; 795 case FTGMAC100_TPAFCR: /* Transmit Priority Arbitration and FIFO Control */ 796 s->tpafcr = value; 797 break; 798 case FTGMAC100_FCR: /* Flow Control */ 799 s->fcr = value; 800 break; 801 802 case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */ 803 case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */ 804 case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */ 805 qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%" 806 HWADDR_PRIx "\n", __func__, addr); 807 break; 808 default: 809 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%" 810 HWADDR_PRIx "\n", __func__, addr); 811 break; 812 } 813 814 ftgmac100_update_irq(s); 815 } 816 817 static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len) 818 { 819 unsigned mcast_idx; 820 821 if (s->maccr & FTGMAC100_MACCR_RX_ALL) { 822 return 1; 823 } 824 825 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) { 826 case ETH_PKT_BCAST: 827 if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) { 828 return 0; 829 } 830 break; 831 case ETH_PKT_MCAST: 832 if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) { 833 if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) { 834 return 0; 835 } 836 837 mcast_idx = net_crc32_le(buf, ETH_ALEN); 838 mcast_idx = (~(mcast_idx >> 2)) & 0x3f; 839 if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) { 840 return 0; 841 } 842 } 843 break; 844 case ETH_PKT_UCAST: 845 if (memcmp(s->conf.macaddr.a, buf, 6)) { 846 return 0; 847 } 848 break; 849 } 850 851 return 1; 852 } 853 854 static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf, 855 size_t len) 856 { 857 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); 858 FTGMAC100Desc bd; 859 uint32_t flags = 0; 860 uint32_t addr; 861 uint32_t crc; 862 uint32_t buf_addr; 863 uint8_t *crc_ptr; 864 uint32_t buf_len; 865 size_t size = len; 866 uint32_t first = FTGMAC100_RXDES0_FRS; 867 uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto); 868 int max_frame_size = ftgmac100_max_frame_size(s, proto); 869 870 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) 871 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) { 872 return -1; 873 } 874 875 /* TODO : Pad to minimum Ethernet frame length */ 876 /* handle small packets. */ 877 if (size < 10) { 878 qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped frame of %zd bytes\n", 879 __func__, size); 880 return size; 881 } 882 883 if (!ftgmac100_filter(s, buf, size)) { 884 return size; 885 } 886 887 /* 4 bytes for the CRC. */ 888 size += 4; 889 crc = cpu_to_be32(crc32(~0, buf, size)); 890 crc_ptr = (uint8_t *) &crc; 891 892 /* Huge frames are truncated. */ 893 if (size > max_frame_size) { 894 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n", 895 __func__, size); 896 size = max_frame_size; 897 flags |= FTGMAC100_RXDES0_FTL; 898 } 899 900 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) { 901 case ETH_PKT_BCAST: 902 flags |= FTGMAC100_RXDES0_BROADCAST; 903 break; 904 case ETH_PKT_MCAST: 905 flags |= FTGMAC100_RXDES0_MULTICAST; 906 break; 907 case ETH_PKT_UCAST: 908 break; 909 } 910 911 addr = s->rx_descriptor; 912 while (size > 0) { 913 if (!ftgmac100_can_receive(nc)) { 914 qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__); 915 return -1; 916 } 917 918 if (ftgmac100_read_bd(&bd, addr) || 919 (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) { 920 /* No descriptors available. Bail out. */ 921 qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n", 922 __func__); 923 s->isr |= FTGMAC100_INT_NO_RXBUF; 924 break; 925 } 926 buf_len = (size <= s->rbsr) ? size : s->rbsr; 927 bd.des0 |= buf_len & 0x3fff; 928 size -= buf_len; 929 930 /* The last 4 bytes are the CRC. */ 931 if (size < 4) { 932 buf_len += size - 4; 933 } 934 buf_addr = bd.des3; 935 if (first && proto == ETH_P_VLAN && buf_len >= 18) { 936 bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL; 937 938 if (s->maccr & FTGMAC100_MACCR_RM_VLAN) { 939 dma_memory_write(&address_space_memory, buf_addr, buf, 12); 940 dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16, 941 buf_len - 16); 942 } else { 943 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); 944 } 945 } else { 946 bd.des1 = 0; 947 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); 948 } 949 buf += buf_len; 950 if (size < 4) { 951 dma_memory_write(&address_space_memory, buf_addr + buf_len, 952 crc_ptr, 4 - size); 953 crc_ptr += 4 - size; 954 } 955 956 bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY; 957 first = 0; 958 if (size == 0) { 959 /* Last buffer in frame. */ 960 bd.des0 |= flags | FTGMAC100_RXDES0_LRS; 961 s->isr |= FTGMAC100_INT_RPKT_BUF; 962 } else { 963 s->isr |= FTGMAC100_INT_RPKT_FIFO; 964 } 965 ftgmac100_write_bd(&bd, addr); 966 if (bd.des0 & s->rxdes0_edorr) { 967 addr = s->rx_ring; 968 } else { 969 addr += sizeof(FTGMAC100Desc); 970 } 971 } 972 s->rx_descriptor = addr; 973 974 ftgmac100_update_irq(s); 975 return len; 976 } 977 978 static const MemoryRegionOps ftgmac100_ops = { 979 .read = ftgmac100_read, 980 .write = ftgmac100_write, 981 .valid.min_access_size = 4, 982 .valid.max_access_size = 4, 983 .endianness = DEVICE_LITTLE_ENDIAN, 984 }; 985 986 static void ftgmac100_cleanup(NetClientState *nc) 987 { 988 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); 989 990 s->nic = NULL; 991 } 992 993 static NetClientInfo net_ftgmac100_info = { 994 .type = NET_CLIENT_DRIVER_NIC, 995 .size = sizeof(NICState), 996 .can_receive = ftgmac100_can_receive, 997 .receive = ftgmac100_receive, 998 .cleanup = ftgmac100_cleanup, 999 .link_status_changed = ftgmac100_set_link, 1000 }; 1001 1002 static void ftgmac100_realize(DeviceState *dev, Error **errp) 1003 { 1004 FTGMAC100State *s = FTGMAC100(dev); 1005 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1006 1007 if (s->aspeed) { 1008 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED; 1009 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED; 1010 } else { 1011 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR; 1012 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR; 1013 } 1014 1015 memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s, 1016 TYPE_FTGMAC100, 0x2000); 1017 sysbus_init_mmio(sbd, &s->iomem); 1018 sysbus_init_irq(sbd, &s->irq); 1019 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1020 1021 s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf, 1022 object_get_typename(OBJECT(dev)), DEVICE(dev)->id, 1023 s); 1024 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 1025 } 1026 1027 static const VMStateDescription vmstate_ftgmac100 = { 1028 .name = TYPE_FTGMAC100, 1029 .version_id = 1, 1030 .minimum_version_id = 1, 1031 .fields = (VMStateField[]) { 1032 VMSTATE_UINT32(irq_state, FTGMAC100State), 1033 VMSTATE_UINT32(isr, FTGMAC100State), 1034 VMSTATE_UINT32(ier, FTGMAC100State), 1035 VMSTATE_UINT32(rx_enabled, FTGMAC100State), 1036 VMSTATE_UINT32(rx_ring, FTGMAC100State), 1037 VMSTATE_UINT32(rbsr, FTGMAC100State), 1038 VMSTATE_UINT32(tx_ring, FTGMAC100State), 1039 VMSTATE_UINT32(rx_descriptor, FTGMAC100State), 1040 VMSTATE_UINT32(tx_descriptor, FTGMAC100State), 1041 VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2), 1042 VMSTATE_UINT32(itc, FTGMAC100State), 1043 VMSTATE_UINT32(aptcr, FTGMAC100State), 1044 VMSTATE_UINT32(dblac, FTGMAC100State), 1045 VMSTATE_UINT32(revr, FTGMAC100State), 1046 VMSTATE_UINT32(fear1, FTGMAC100State), 1047 VMSTATE_UINT32(tpafcr, FTGMAC100State), 1048 VMSTATE_UINT32(maccr, FTGMAC100State), 1049 VMSTATE_UINT32(phycr, FTGMAC100State), 1050 VMSTATE_UINT32(phydata, FTGMAC100State), 1051 VMSTATE_UINT32(fcr, FTGMAC100State), 1052 VMSTATE_UINT32(phy_status, FTGMAC100State), 1053 VMSTATE_UINT32(phy_control, FTGMAC100State), 1054 VMSTATE_UINT32(phy_advertise, FTGMAC100State), 1055 VMSTATE_UINT32(phy_int, FTGMAC100State), 1056 VMSTATE_UINT32(phy_int_mask, FTGMAC100State), 1057 VMSTATE_UINT32(txdes0_edotr, FTGMAC100State), 1058 VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State), 1059 VMSTATE_END_OF_LIST() 1060 } 1061 }; 1062 1063 static Property ftgmac100_properties[] = { 1064 DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false), 1065 DEFINE_NIC_PROPERTIES(FTGMAC100State, conf), 1066 DEFINE_PROP_END_OF_LIST(), 1067 }; 1068 1069 static void ftgmac100_class_init(ObjectClass *klass, void *data) 1070 { 1071 DeviceClass *dc = DEVICE_CLASS(klass); 1072 1073 dc->vmsd = &vmstate_ftgmac100; 1074 dc->reset = ftgmac100_reset; 1075 dc->props = ftgmac100_properties; 1076 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1077 dc->realize = ftgmac100_realize; 1078 dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation"; 1079 } 1080 1081 static const TypeInfo ftgmac100_info = { 1082 .name = TYPE_FTGMAC100, 1083 .parent = TYPE_SYS_BUS_DEVICE, 1084 .instance_size = sizeof(FTGMAC100State), 1085 .class_init = ftgmac100_class_init, 1086 }; 1087 1088 static void ftgmac100_register_types(void) 1089 { 1090 type_register_static(&ftgmac100_info); 1091 } 1092 1093 type_init(ftgmac100_register_types) 1094