xref: /openbmc/qemu/hw/net/ftgmac100.c (revision 650d103d3ea959212f826acb9d3fe80cf30e347b)
1 /*
2  * Faraday FTGMAC100 Gigabit Ethernet
3  *
4  * Copyright (C) 2016-2017, IBM Corporation.
5  *
6  * Based on Coldfire Fast Ethernet Controller emulation.
7  *
8  * Copyright (c) 2007 CodeSourcery.
9  *
10  * This code is licensed under the GPL version 2 or later. See the
11  * COPYING file in the top-level directory.
12  */
13 
14 #include "qemu/osdep.h"
15 #include "hw/irq.h"
16 #include "hw/net/ftgmac100.h"
17 #include "sysemu/dma.h"
18 #include "qemu/log.h"
19 #include "qemu/module.h"
20 #include "net/checksum.h"
21 #include "net/eth.h"
22 #include "hw/net/mii.h"
23 #include "migration/vmstate.h"
24 
25 /* For crc32 */
26 #include <zlib.h>
27 
28 /*
29  * FTGMAC100 registers
30  */
31 #define FTGMAC100_ISR             0x00
32 #define FTGMAC100_IER             0x04
33 #define FTGMAC100_MAC_MADR        0x08
34 #define FTGMAC100_MAC_LADR        0x0c
35 #define FTGMAC100_MATH0           0x10
36 #define FTGMAC100_MATH1           0x14
37 #define FTGMAC100_NPTXPD          0x18
38 #define FTGMAC100_RXPD            0x1C
39 #define FTGMAC100_NPTXR_BADR      0x20
40 #define FTGMAC100_RXR_BADR        0x24
41 #define FTGMAC100_HPTXPD          0x28
42 #define FTGMAC100_HPTXR_BADR      0x2c
43 #define FTGMAC100_ITC             0x30
44 #define FTGMAC100_APTC            0x34
45 #define FTGMAC100_DBLAC           0x38
46 #define FTGMAC100_REVR            0x40
47 #define FTGMAC100_FEAR1           0x44
48 #define FTGMAC100_RBSR            0x4c
49 #define FTGMAC100_TPAFCR          0x48
50 
51 #define FTGMAC100_MACCR           0x50
52 #define FTGMAC100_MACSR           0x54
53 #define FTGMAC100_PHYCR           0x60
54 #define FTGMAC100_PHYDATA         0x64
55 #define FTGMAC100_FCR             0x68
56 
57 /*
58  * Interrupt status register & interrupt enable register
59  */
60 #define FTGMAC100_INT_RPKT_BUF    (1 << 0)
61 #define FTGMAC100_INT_RPKT_FIFO   (1 << 1)
62 #define FTGMAC100_INT_NO_RXBUF    (1 << 2)
63 #define FTGMAC100_INT_RPKT_LOST   (1 << 3)
64 #define FTGMAC100_INT_XPKT_ETH    (1 << 4)
65 #define FTGMAC100_INT_XPKT_FIFO   (1 << 5)
66 #define FTGMAC100_INT_NO_NPTXBUF  (1 << 6)
67 #define FTGMAC100_INT_XPKT_LOST   (1 << 7)
68 #define FTGMAC100_INT_AHB_ERR     (1 << 8)
69 #define FTGMAC100_INT_PHYSTS_CHG  (1 << 9)
70 #define FTGMAC100_INT_NO_HPTXBUF  (1 << 10)
71 
72 /*
73  * Automatic polling timer control register
74  */
75 #define FTGMAC100_APTC_RXPOLL_CNT(x)        ((x) & 0xf)
76 #define FTGMAC100_APTC_RXPOLL_TIME_SEL      (1 << 4)
77 #define FTGMAC100_APTC_TXPOLL_CNT(x)        (((x) >> 8) & 0xf)
78 #define FTGMAC100_APTC_TXPOLL_TIME_SEL      (1 << 12)
79 
80 /*
81  * PHY control register
82  */
83 #define FTGMAC100_PHYCR_MIIRD               (1 << 26)
84 #define FTGMAC100_PHYCR_MIIWR               (1 << 27)
85 
86 #define FTGMAC100_PHYCR_DEV(x)              (((x) >> 16) & 0x1f)
87 #define FTGMAC100_PHYCR_REG(x)              (((x) >> 21) & 0x1f)
88 
89 /*
90  * PHY data register
91  */
92 #define FTGMAC100_PHYDATA_MIIWDATA(x)       ((x) & 0xffff)
93 #define FTGMAC100_PHYDATA_MIIRDATA(x)       (((x) >> 16) & 0xffff)
94 
95 /*
96  * PHY control register - New MDC/MDIO interface
97  */
98 #define FTGMAC100_PHYCR_NEW_DATA(x)     (((x) >> 16) & 0xffff)
99 #define FTGMAC100_PHYCR_NEW_FIRE        (1 << 15)
100 #define FTGMAC100_PHYCR_NEW_ST_22       (1 << 12)
101 #define FTGMAC100_PHYCR_NEW_OP(x)       (((x) >> 10) & 3)
102 #define   FTGMAC100_PHYCR_NEW_OP_WRITE    0x1
103 #define   FTGMAC100_PHYCR_NEW_OP_READ     0x2
104 #define FTGMAC100_PHYCR_NEW_DEV(x)      (((x) >> 5) & 0x1f)
105 #define FTGMAC100_PHYCR_NEW_REG(x)      ((x) & 0x1f)
106 
107 /*
108  * Feature Register
109  */
110 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE   (1 << 31)
111 
112 /*
113  * MAC control register
114  */
115 #define FTGMAC100_MACCR_TXDMA_EN         (1 << 0)
116 #define FTGMAC100_MACCR_RXDMA_EN         (1 << 1)
117 #define FTGMAC100_MACCR_TXMAC_EN         (1 << 2)
118 #define FTGMAC100_MACCR_RXMAC_EN         (1 << 3)
119 #define FTGMAC100_MACCR_RM_VLAN          (1 << 4)
120 #define FTGMAC100_MACCR_HPTXR_EN         (1 << 5)
121 #define FTGMAC100_MACCR_LOOP_EN          (1 << 6)
122 #define FTGMAC100_MACCR_ENRX_IN_HALFTX   (1 << 7)
123 #define FTGMAC100_MACCR_FULLDUP          (1 << 8)
124 #define FTGMAC100_MACCR_GIGA_MODE        (1 << 9)
125 #define FTGMAC100_MACCR_CRC_APD          (1 << 10) /* not needed */
126 #define FTGMAC100_MACCR_RX_RUNT          (1 << 12)
127 #define FTGMAC100_MACCR_JUMBO_LF         (1 << 13)
128 #define FTGMAC100_MACCR_RX_ALL           (1 << 14)
129 #define FTGMAC100_MACCR_HT_MULTI_EN      (1 << 15)
130 #define FTGMAC100_MACCR_RX_MULTIPKT      (1 << 16)
131 #define FTGMAC100_MACCR_RX_BROADPKT      (1 << 17)
132 #define FTGMAC100_MACCR_DISCARD_CRCERR   (1 << 18)
133 #define FTGMAC100_MACCR_FAST_MODE        (1 << 19)
134 #define FTGMAC100_MACCR_SW_RST           (1 << 31)
135 
136 /*
137  * Transmit descriptor
138  */
139 #define FTGMAC100_TXDES0_TXBUF_SIZE(x)   ((x) & 0x3fff)
140 #define FTGMAC100_TXDES0_EDOTR           (1 << 15)
141 #define FTGMAC100_TXDES0_CRC_ERR         (1 << 19)
142 #define FTGMAC100_TXDES0_LTS             (1 << 28)
143 #define FTGMAC100_TXDES0_FTS             (1 << 29)
144 #define FTGMAC100_TXDES0_EDOTR_ASPEED    (1 << 30)
145 #define FTGMAC100_TXDES0_TXDMA_OWN       (1 << 31)
146 
147 #define FTGMAC100_TXDES1_VLANTAG_CI(x)   ((x) & 0xffff)
148 #define FTGMAC100_TXDES1_INS_VLANTAG     (1 << 16)
149 #define FTGMAC100_TXDES1_TCP_CHKSUM      (1 << 17)
150 #define FTGMAC100_TXDES1_UDP_CHKSUM      (1 << 18)
151 #define FTGMAC100_TXDES1_IP_CHKSUM       (1 << 19)
152 #define FTGMAC100_TXDES1_LLC             (1 << 22)
153 #define FTGMAC100_TXDES1_TX2FIC          (1 << 30)
154 #define FTGMAC100_TXDES1_TXIC            (1 << 31)
155 
156 /*
157  * Receive descriptor
158  */
159 #define FTGMAC100_RXDES0_VDBC            0x3fff
160 #define FTGMAC100_RXDES0_EDORR           (1 << 15)
161 #define FTGMAC100_RXDES0_MULTICAST       (1 << 16)
162 #define FTGMAC100_RXDES0_BROADCAST       (1 << 17)
163 #define FTGMAC100_RXDES0_RX_ERR          (1 << 18)
164 #define FTGMAC100_RXDES0_CRC_ERR         (1 << 19)
165 #define FTGMAC100_RXDES0_FTL             (1 << 20)
166 #define FTGMAC100_RXDES0_RUNT            (1 << 21)
167 #define FTGMAC100_RXDES0_RX_ODD_NB       (1 << 22)
168 #define FTGMAC100_RXDES0_FIFO_FULL       (1 << 23)
169 #define FTGMAC100_RXDES0_PAUSE_OPCODE    (1 << 24)
170 #define FTGMAC100_RXDES0_PAUSE_FRAME     (1 << 25)
171 #define FTGMAC100_RXDES0_LRS             (1 << 28)
172 #define FTGMAC100_RXDES0_FRS             (1 << 29)
173 #define FTGMAC100_RXDES0_EDORR_ASPEED    (1 << 30)
174 #define FTGMAC100_RXDES0_RXPKT_RDY       (1 << 31)
175 
176 #define FTGMAC100_RXDES1_VLANTAG_CI      0xffff
177 #define FTGMAC100_RXDES1_PROT_MASK       (0x3 << 20)
178 #define FTGMAC100_RXDES1_PROT_NONIP      (0x0 << 20)
179 #define FTGMAC100_RXDES1_PROT_IP         (0x1 << 20)
180 #define FTGMAC100_RXDES1_PROT_TCPIP      (0x2 << 20)
181 #define FTGMAC100_RXDES1_PROT_UDPIP      (0x3 << 20)
182 #define FTGMAC100_RXDES1_LLC             (1 << 22)
183 #define FTGMAC100_RXDES1_DF              (1 << 23)
184 #define FTGMAC100_RXDES1_VLANTAG_AVAIL   (1 << 24)
185 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR  (1 << 25)
186 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR  (1 << 26)
187 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR   (1 << 27)
188 
189 /*
190  * Receive and transmit Buffer Descriptor
191  */
192 typedef struct {
193     uint32_t        des0;
194     uint32_t        des1;
195     uint32_t        des2;        /* not used by HW */
196     uint32_t        des3;
197 } FTGMAC100Desc;
198 
199 /*
200  * Specific RTL8211E MII Registers
201  */
202 #define RTL8211E_MII_PHYCR        16 /* PHY Specific Control */
203 #define RTL8211E_MII_PHYSR        17 /* PHY Specific Status */
204 #define RTL8211E_MII_INER         18 /* Interrupt Enable */
205 #define RTL8211E_MII_INSR         19 /* Interrupt Status */
206 #define RTL8211E_MII_RXERC        24 /* Receive Error Counter */
207 #define RTL8211E_MII_LDPSR        27 /* Link Down Power Saving */
208 #define RTL8211E_MII_EPAGSR       30 /* Extension Page Select */
209 #define RTL8211E_MII_PAGSEL       31 /* Page Select */
210 
211 /*
212  * RTL8211E Interrupt Status
213  */
214 #define PHY_INT_AUTONEG_ERROR       (1 << 15)
215 #define PHY_INT_PAGE_RECV           (1 << 12)
216 #define PHY_INT_AUTONEG_COMPLETE    (1 << 11)
217 #define PHY_INT_LINK_STATUS         (1 << 10)
218 #define PHY_INT_ERROR               (1 << 9)
219 #define PHY_INT_DOWN                (1 << 8)
220 #define PHY_INT_JABBER              (1 << 0)
221 
222 /*
223  * Max frame size for the receiving buffer
224  */
225 #define FTGMAC100_MAX_FRAME_SIZE    9220
226 
227 /* Limits depending on the type of the frame
228  *
229  *   9216 for Jumbo frames (+ 4 for VLAN)
230  *   1518 for other frames (+ 4 for VLAN)
231  */
232 static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto)
233 {
234     int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518);
235 
236     return max + (proto == ETH_P_VLAN ? 4 : 0);
237 }
238 
239 static void ftgmac100_update_irq(FTGMAC100State *s)
240 {
241     qemu_set_irq(s->irq, s->isr & s->ier);
242 }
243 
244 /*
245  * The MII phy could raise a GPIO to the processor which in turn
246  * could be handled as an interrpt by the OS.
247  * For now we don't handle any GPIO/interrupt line, so the OS will
248  * have to poll for the PHY status.
249  */
250 static void phy_update_irq(FTGMAC100State *s)
251 {
252     ftgmac100_update_irq(s);
253 }
254 
255 static void phy_update_link(FTGMAC100State *s)
256 {
257     /* Autonegotiation status mirrors link status.  */
258     if (qemu_get_queue(s->nic)->link_down) {
259         s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
260         s->phy_int |= PHY_INT_DOWN;
261     } else {
262         s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
263         s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
264     }
265     phy_update_irq(s);
266 }
267 
268 static void ftgmac100_set_link(NetClientState *nc)
269 {
270     phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc)));
271 }
272 
273 static void phy_reset(FTGMAC100State *s)
274 {
275     s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
276                      MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS |
277                      MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST |
278                      MII_BMSR_EXTCAP);
279     s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000);
280     s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD |
281                         MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |
282                         MII_ANAR_CSMACD);
283     s->phy_int_mask = 0;
284     s->phy_int = 0;
285 }
286 
287 static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg)
288 {
289     uint16_t val;
290 
291     switch (reg) {
292     case MII_BMCR: /* Basic Control */
293         val = s->phy_control;
294         break;
295     case MII_BMSR: /* Basic Status */
296         val = s->phy_status;
297         break;
298     case MII_PHYID1: /* ID1 */
299         val = RTL8211E_PHYID1;
300         break;
301     case MII_PHYID2: /* ID2 */
302         val = RTL8211E_PHYID2;
303         break;
304     case MII_ANAR: /* Auto-neg advertisement */
305         val = s->phy_advertise;
306         break;
307     case MII_ANLPAR: /* Auto-neg Link Partner Ability */
308         val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD |
309                MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 |
310                MII_ANLPAR_CSMACD);
311         break;
312     case MII_ANER: /* Auto-neg Expansion */
313         val = MII_ANER_NWAY;
314         break;
315     case MII_CTRL1000: /* 1000BASE-T control  */
316         val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL);
317         break;
318     case MII_STAT1000: /* 1000BASE-T status  */
319         val = MII_STAT1000_FULL;
320         break;
321     case RTL8211E_MII_INSR:  /* Interrupt status.  */
322         val = s->phy_int;
323         s->phy_int = 0;
324         phy_update_irq(s);
325         break;
326     case RTL8211E_MII_INER:  /* Interrupt enable */
327         val = s->phy_int_mask;
328         break;
329     case RTL8211E_MII_PHYCR:
330     case RTL8211E_MII_PHYSR:
331     case RTL8211E_MII_RXERC:
332     case RTL8211E_MII_LDPSR:
333     case RTL8211E_MII_EPAGSR:
334     case RTL8211E_MII_PAGSEL:
335         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
336                       __func__, reg);
337         val = 0;
338         break;
339     default:
340         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
341                       __func__, reg);
342         val = 0;
343         break;
344     }
345 
346     return val;
347 }
348 
349 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |          \
350                        MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
351                        MII_BMCR_FD | MII_BMCR_CTST)
352 #define MII_ANAR_MASK 0x2d7f
353 
354 static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val)
355 {
356     switch (reg) {
357     case MII_BMCR:     /* Basic Control */
358         if (val & MII_BMCR_RESET) {
359             phy_reset(s);
360         } else {
361             s->phy_control = val & MII_BMCR_MASK;
362             /* Complete autonegotiation immediately.  */
363             if (val & MII_BMCR_AUTOEN) {
364                 s->phy_status |= MII_BMSR_AN_COMP;
365             }
366         }
367         break;
368     case MII_ANAR:     /* Auto-neg advertisement */
369         s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX;
370         break;
371     case RTL8211E_MII_INER: /* Interrupt enable */
372         s->phy_int_mask = val & 0xff;
373         phy_update_irq(s);
374         break;
375     case RTL8211E_MII_PHYCR:
376     case RTL8211E_MII_PHYSR:
377     case RTL8211E_MII_RXERC:
378     case RTL8211E_MII_LDPSR:
379     case RTL8211E_MII_EPAGSR:
380     case RTL8211E_MII_PAGSEL:
381         qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
382                       __func__, reg);
383         break;
384     default:
385         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
386                       __func__, reg);
387         break;
388     }
389 }
390 
391 static void do_phy_new_ctl(FTGMAC100State *s)
392 {
393     uint8_t reg;
394     uint16_t data;
395 
396     if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) {
397         qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
398         return;
399     }
400 
401     /* Nothing to do */
402     if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) {
403         return;
404     }
405 
406     reg = FTGMAC100_PHYCR_NEW_REG(s->phycr);
407     data = FTGMAC100_PHYCR_NEW_DATA(s->phycr);
408 
409     switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) {
410     case FTGMAC100_PHYCR_NEW_OP_WRITE:
411         do_phy_write(s, reg, data);
412         break;
413     case FTGMAC100_PHYCR_NEW_OP_READ:
414         s->phydata = do_phy_read(s, reg) & 0xffff;
415         break;
416     default:
417         qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
418                       __func__, s->phycr);
419     }
420 
421     s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE;
422 }
423 
424 static void do_phy_ctl(FTGMAC100State *s)
425 {
426     uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr);
427 
428     if (s->phycr & FTGMAC100_PHYCR_MIIWR) {
429         do_phy_write(s, reg, s->phydata & 0xffff);
430         s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
431     } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) {
432         s->phydata = do_phy_read(s, reg) << 16;
433         s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
434     } else {
435         qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n",
436                       __func__, s->phycr);
437     }
438 }
439 
440 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
441 {
442     if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
443         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%"
444                       HWADDR_PRIx "\n", __func__, addr);
445         return -1;
446     }
447     bd->des0 = le32_to_cpu(bd->des0);
448     bd->des1 = le32_to_cpu(bd->des1);
449     bd->des2 = le32_to_cpu(bd->des2);
450     bd->des3 = le32_to_cpu(bd->des3);
451     return 0;
452 }
453 
454 static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
455 {
456     FTGMAC100Desc lebd;
457 
458     lebd.des0 = cpu_to_le32(bd->des0);
459     lebd.des1 = cpu_to_le32(bd->des1);
460     lebd.des2 = cpu_to_le32(bd->des2);
461     lebd.des3 = cpu_to_le32(bd->des3);
462     if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))) {
463         qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%"
464                       HWADDR_PRIx "\n", __func__, addr);
465         return -1;
466     }
467     return 0;
468 }
469 
470 static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
471                             uint32_t tx_descriptor)
472 {
473     int frame_size = 0;
474     uint8_t *ptr = s->frame;
475     uint32_t addr = tx_descriptor;
476     uint32_t flags = 0;
477 
478     while (1) {
479         FTGMAC100Desc bd;
480         int len;
481 
482         if (ftgmac100_read_bd(&bd, addr) ||
483             ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) {
484             /* Run out of descriptors to transmit.  */
485             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
486             break;
487         }
488 
489         /* record transmit flags as they are valid only on the first
490          * segment */
491         if (bd.des0 & FTGMAC100_TXDES0_FTS) {
492             flags = bd.des1;
493         }
494 
495         len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
496         if (frame_size + len > sizeof(s->frame)) {
497             qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
498                           __func__, len);
499             s->isr |= FTGMAC100_INT_XPKT_LOST;
500             len =  sizeof(s->frame) - frame_size;
501         }
502 
503         if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
504             qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
505                           __func__, bd.des3);
506             s->isr |= FTGMAC100_INT_NO_NPTXBUF;
507             break;
508         }
509 
510         /* Check for VLAN */
511         if (bd.des0 & FTGMAC100_TXDES0_FTS &&
512             bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&
513             be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {
514             if (frame_size + len + 4 > sizeof(s->frame)) {
515                 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
516                               __func__, len);
517                 s->isr |= FTGMAC100_INT_XPKT_LOST;
518                 len =  sizeof(s->frame) - frame_size - 4;
519             }
520             memmove(ptr + 16, ptr + 12, len - 12);
521             stw_be_p(ptr + 12, ETH_P_VLAN);
522             stw_be_p(ptr + 14, bd.des1);
523             len += 4;
524         }
525 
526         ptr += len;
527         frame_size += len;
528         if (bd.des0 & FTGMAC100_TXDES0_LTS) {
529             if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {
530                 net_checksum_calculate(s->frame, frame_size);
531             }
532             /* Last buffer in frame.  */
533             qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
534             ptr = s->frame;
535             frame_size = 0;
536             if (flags & FTGMAC100_TXDES1_TXIC) {
537                 s->isr |= FTGMAC100_INT_XPKT_ETH;
538             }
539         }
540 
541         if (flags & FTGMAC100_TXDES1_TX2FIC) {
542             s->isr |= FTGMAC100_INT_XPKT_FIFO;
543         }
544         bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN;
545 
546         /* Write back the modified descriptor.  */
547         ftgmac100_write_bd(&bd, addr);
548         /* Advance to the next descriptor.  */
549         if (bd.des0 & s->txdes0_edotr) {
550             addr = tx_ring;
551         } else {
552             addr += sizeof(FTGMAC100Desc);
553         }
554     }
555 
556     s->tx_descriptor = addr;
557 
558     ftgmac100_update_irq(s);
559 }
560 
561 static int ftgmac100_can_receive(NetClientState *nc)
562 {
563     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
564     FTGMAC100Desc bd;
565 
566     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
567          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
568         return 0;
569     }
570 
571     if (ftgmac100_read_bd(&bd, s->rx_descriptor)) {
572         return 0;
573     }
574     return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY);
575 }
576 
577 /*
578  * This is purely informative. The HW can poll the RW (and RX) ring
579  * buffers for available descriptors but we don't need to trigger a
580  * timer for that in qemu.
581  */
582 static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)
583 {
584     /* Polling times :
585      *
586      * Speed      TIME_SEL=0    TIME_SEL=1
587      *
588      *    10         51.2 ms      819.2 ms
589      *   100         5.12 ms      81.92 ms
590      *  1000        1.024 ms     16.384 ms
591      */
592     static const int div[] = { 20, 200, 1000 };
593 
594     uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr);
595     uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0;
596 
597     if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) {
598         cnt <<= 4;
599     }
600 
601     if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) {
602         speed = 2;
603     }
604 
605     return cnt / div[speed];
606 }
607 
608 static void ftgmac100_reset(DeviceState *d)
609 {
610     FTGMAC100State *s = FTGMAC100(d);
611 
612     /* Reset the FTGMAC100 */
613     s->isr = 0;
614     s->ier = 0;
615     s->rx_enabled = 0;
616     s->rx_ring = 0;
617     s->rbsr = 0x640;
618     s->rx_descriptor = 0;
619     s->tx_ring = 0;
620     s->tx_descriptor = 0;
621     s->math[0] = 0;
622     s->math[1] = 0;
623     s->itc = 0;
624     s->aptcr = 1;
625     s->dblac = 0x00022f00;
626     s->revr = 0;
627     s->fear1 = 0;
628     s->tpafcr = 0xf1;
629 
630     s->maccr = 0;
631     s->phycr = 0;
632     s->phydata = 0;
633     s->fcr = 0x400;
634 
635     /* and the PHY */
636     phy_reset(s);
637 }
638 
639 static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
640 {
641     FTGMAC100State *s = FTGMAC100(opaque);
642 
643     switch (addr & 0xff) {
644     case FTGMAC100_ISR:
645         return s->isr;
646     case FTGMAC100_IER:
647         return s->ier;
648     case FTGMAC100_MAC_MADR:
649         return (s->conf.macaddr.a[0] << 8)  | s->conf.macaddr.a[1];
650     case FTGMAC100_MAC_LADR:
651         return ((uint32_t) s->conf.macaddr.a[2] << 24) |
652             (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) |
653             s->conf.macaddr.a[5];
654     case FTGMAC100_MATH0:
655         return s->math[0];
656     case FTGMAC100_MATH1:
657         return s->math[1];
658     case FTGMAC100_ITC:
659         return s->itc;
660     case FTGMAC100_DBLAC:
661         return s->dblac;
662     case FTGMAC100_REVR:
663         return s->revr;
664     case FTGMAC100_FEAR1:
665         return s->fear1;
666     case FTGMAC100_TPAFCR:
667         return s->tpafcr;
668     case FTGMAC100_FCR:
669         return s->fcr;
670     case FTGMAC100_MACCR:
671         return s->maccr;
672     case FTGMAC100_PHYCR:
673         return s->phycr;
674     case FTGMAC100_PHYDATA:
675         return s->phydata;
676 
677         /* We might want to support these one day */
678     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
679     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
680     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
681         qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
682                       HWADDR_PRIx "\n", __func__, addr);
683         return 0;
684     default:
685         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
686                       HWADDR_PRIx "\n", __func__, addr);
687         return 0;
688     }
689 }
690 
691 static void ftgmac100_write(void *opaque, hwaddr addr,
692                           uint64_t value, unsigned size)
693 {
694     FTGMAC100State *s = FTGMAC100(opaque);
695 
696     switch (addr & 0xff) {
697     case FTGMAC100_ISR: /* Interrupt status */
698         s->isr &= ~value;
699         break;
700     case FTGMAC100_IER: /* Interrupt control */
701         s->ier = value;
702         break;
703     case FTGMAC100_MAC_MADR: /* MAC */
704         s->conf.macaddr.a[0] = value >> 8;
705         s->conf.macaddr.a[1] = value;
706         break;
707     case FTGMAC100_MAC_LADR:
708         s->conf.macaddr.a[2] = value >> 24;
709         s->conf.macaddr.a[3] = value >> 16;
710         s->conf.macaddr.a[4] = value >> 8;
711         s->conf.macaddr.a[5] = value;
712         break;
713     case FTGMAC100_MATH0: /* Multicast Address Hash Table 0 */
714         s->math[0] = value;
715         break;
716     case FTGMAC100_MATH1: /* Multicast Address Hash Table 1 */
717         s->math[1] = value;
718         break;
719     case FTGMAC100_ITC: /* TODO: Interrupt Timer Control */
720         s->itc = value;
721         break;
722     case FTGMAC100_RXR_BADR: /* Ring buffer address */
723         s->rx_ring = value;
724         s->rx_descriptor = s->rx_ring;
725         break;
726 
727     case FTGMAC100_RBSR: /* DMA buffer size */
728         s->rbsr = value;
729         break;
730 
731     case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
732         s->tx_ring = value;
733         s->tx_descriptor = s->tx_ring;
734         break;
735 
736     case FTGMAC100_NPTXPD: /* Trigger transmit */
737         if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN))
738             == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) {
739             /* TODO: high priority tx ring */
740             ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor);
741         }
742         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
743             qemu_flush_queued_packets(qemu_get_queue(s->nic));
744         }
745         break;
746 
747     case FTGMAC100_RXPD: /* Receive Poll Demand Register */
748         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
749             qemu_flush_queued_packets(qemu_get_queue(s->nic));
750         }
751         break;
752 
753     case FTGMAC100_APTC: /* Automatic polling */
754         s->aptcr = value;
755 
756         if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) {
757             ftgmac100_rxpoll(s);
758         }
759 
760         if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) {
761             qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__);
762         }
763         break;
764 
765     case FTGMAC100_MACCR: /* MAC Device control */
766         s->maccr = value;
767         if (value & FTGMAC100_MACCR_SW_RST) {
768             ftgmac100_reset(DEVICE(s));
769         }
770 
771         if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
772             qemu_flush_queued_packets(qemu_get_queue(s->nic));
773         }
774         break;
775 
776     case FTGMAC100_PHYCR:  /* PHY Device control */
777         s->phycr = value;
778         if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) {
779             do_phy_new_ctl(s);
780         } else {
781             do_phy_ctl(s);
782         }
783         break;
784     case FTGMAC100_PHYDATA:
785         s->phydata = value & 0xffff;
786         break;
787     case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */
788         s->dblac = value;
789         break;
790     case FTGMAC100_REVR:  /* Feature Register */
791         s->revr = value;
792         break;
793     case FTGMAC100_FEAR1: /* Feature Register 1 */
794         s->fear1 = value;
795         break;
796     case FTGMAC100_TPAFCR: /* Transmit Priority Arbitration and FIFO Control */
797         s->tpafcr = value;
798         break;
799     case FTGMAC100_FCR: /* Flow Control  */
800         s->fcr  = value;
801         break;
802 
803     case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
804     case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
805     case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
806         qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
807                       HWADDR_PRIx "\n", __func__, addr);
808         break;
809     default:
810         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
811                       HWADDR_PRIx "\n", __func__, addr);
812         break;
813     }
814 
815     ftgmac100_update_irq(s);
816 }
817 
818 static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
819 {
820     unsigned mcast_idx;
821 
822     if (s->maccr & FTGMAC100_MACCR_RX_ALL) {
823         return 1;
824     }
825 
826     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
827     case ETH_PKT_BCAST:
828         if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) {
829             return 0;
830         }
831         break;
832     case ETH_PKT_MCAST:
833         if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) {
834             if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) {
835                 return 0;
836             }
837 
838             mcast_idx = net_crc32_le(buf, ETH_ALEN);
839             mcast_idx = (~(mcast_idx >> 2)) & 0x3f;
840             if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
841                 return 0;
842             }
843         }
844         break;
845     case ETH_PKT_UCAST:
846         if (memcmp(s->conf.macaddr.a, buf, 6)) {
847             return 0;
848         }
849         break;
850     }
851 
852     return 1;
853 }
854 
855 static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
856                                  size_t len)
857 {
858     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
859     FTGMAC100Desc bd;
860     uint32_t flags = 0;
861     uint32_t addr;
862     uint32_t crc;
863     uint32_t buf_addr;
864     uint8_t *crc_ptr;
865     uint32_t buf_len;
866     size_t size = len;
867     uint32_t first = FTGMAC100_RXDES0_FRS;
868     uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto);
869     int max_frame_size = ftgmac100_max_frame_size(s, proto);
870 
871     if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
872          != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
873         return -1;
874     }
875 
876     /* TODO : Pad to minimum Ethernet frame length */
877     /* handle small packets.  */
878     if (size < 10) {
879         qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped frame of %zd bytes\n",
880                       __func__, size);
881         return size;
882     }
883 
884     if (!ftgmac100_filter(s, buf, size)) {
885         return size;
886     }
887 
888     /* 4 bytes for the CRC.  */
889     size += 4;
890     crc = cpu_to_be32(crc32(~0, buf, size));
891     crc_ptr = (uint8_t *) &crc;
892 
893     /* Huge frames are truncated.  */
894     if (size > max_frame_size) {
895         qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
896                       __func__, size);
897         size = max_frame_size;
898         flags |= FTGMAC100_RXDES0_FTL;
899     }
900 
901     switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
902     case ETH_PKT_BCAST:
903         flags |= FTGMAC100_RXDES0_BROADCAST;
904         break;
905     case ETH_PKT_MCAST:
906         flags |= FTGMAC100_RXDES0_MULTICAST;
907         break;
908     case ETH_PKT_UCAST:
909         break;
910     }
911 
912     addr = s->rx_descriptor;
913     while (size > 0) {
914         if (!ftgmac100_can_receive(nc)) {
915             qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__);
916             return -1;
917         }
918 
919         if (ftgmac100_read_bd(&bd, addr) ||
920             (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) {
921             /* No descriptors available.  Bail out.  */
922             qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n",
923                           __func__);
924             s->isr |= FTGMAC100_INT_NO_RXBUF;
925             break;
926         }
927         buf_len = (size <= s->rbsr) ? size : s->rbsr;
928         bd.des0 |= buf_len & 0x3fff;
929         size -= buf_len;
930 
931         /* The last 4 bytes are the CRC.  */
932         if (size < 4) {
933             buf_len += size - 4;
934         }
935         buf_addr = bd.des3;
936         if (first && proto == ETH_P_VLAN && buf_len >= 18) {
937             bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
938 
939             if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
940                 dma_memory_write(&address_space_memory, buf_addr, buf, 12);
941                 dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16,
942                                  buf_len - 16);
943             } else {
944                 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
945             }
946         } else {
947             bd.des1 = 0;
948             dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
949         }
950         buf += buf_len;
951         if (size < 4) {
952             dma_memory_write(&address_space_memory, buf_addr + buf_len,
953                              crc_ptr, 4 - size);
954             crc_ptr += 4 - size;
955         }
956 
957         bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY;
958         first = 0;
959         if (size == 0) {
960             /* Last buffer in frame.  */
961             bd.des0 |= flags | FTGMAC100_RXDES0_LRS;
962             s->isr |= FTGMAC100_INT_RPKT_BUF;
963         } else {
964             s->isr |= FTGMAC100_INT_RPKT_FIFO;
965         }
966         ftgmac100_write_bd(&bd, addr);
967         if (bd.des0 & s->rxdes0_edorr) {
968             addr = s->rx_ring;
969         } else {
970             addr += sizeof(FTGMAC100Desc);
971         }
972     }
973     s->rx_descriptor = addr;
974 
975     ftgmac100_update_irq(s);
976     return len;
977 }
978 
979 static const MemoryRegionOps ftgmac100_ops = {
980     .read = ftgmac100_read,
981     .write = ftgmac100_write,
982     .valid.min_access_size = 4,
983     .valid.max_access_size = 4,
984     .endianness = DEVICE_LITTLE_ENDIAN,
985 };
986 
987 static void ftgmac100_cleanup(NetClientState *nc)
988 {
989     FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
990 
991     s->nic = NULL;
992 }
993 
994 static NetClientInfo net_ftgmac100_info = {
995     .type = NET_CLIENT_DRIVER_NIC,
996     .size = sizeof(NICState),
997     .can_receive = ftgmac100_can_receive,
998     .receive = ftgmac100_receive,
999     .cleanup = ftgmac100_cleanup,
1000     .link_status_changed = ftgmac100_set_link,
1001 };
1002 
1003 static void ftgmac100_realize(DeviceState *dev, Error **errp)
1004 {
1005     FTGMAC100State *s = FTGMAC100(dev);
1006     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1007 
1008     if (s->aspeed) {
1009         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
1010         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
1011     } else {
1012         s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
1013         s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
1014     }
1015 
1016     memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
1017                           TYPE_FTGMAC100, 0x2000);
1018     sysbus_init_mmio(sbd, &s->iomem);
1019     sysbus_init_irq(sbd, &s->irq);
1020     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1021 
1022     s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf,
1023                           object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
1024                           s);
1025     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1026 }
1027 
1028 static const VMStateDescription vmstate_ftgmac100 = {
1029     .name = TYPE_FTGMAC100,
1030     .version_id = 1,
1031     .minimum_version_id = 1,
1032     .fields = (VMStateField[]) {
1033         VMSTATE_UINT32(irq_state, FTGMAC100State),
1034         VMSTATE_UINT32(isr, FTGMAC100State),
1035         VMSTATE_UINT32(ier, FTGMAC100State),
1036         VMSTATE_UINT32(rx_enabled, FTGMAC100State),
1037         VMSTATE_UINT32(rx_ring, FTGMAC100State),
1038         VMSTATE_UINT32(rbsr, FTGMAC100State),
1039         VMSTATE_UINT32(tx_ring, FTGMAC100State),
1040         VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
1041         VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
1042         VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
1043         VMSTATE_UINT32(itc, FTGMAC100State),
1044         VMSTATE_UINT32(aptcr, FTGMAC100State),
1045         VMSTATE_UINT32(dblac, FTGMAC100State),
1046         VMSTATE_UINT32(revr, FTGMAC100State),
1047         VMSTATE_UINT32(fear1, FTGMAC100State),
1048         VMSTATE_UINT32(tpafcr, FTGMAC100State),
1049         VMSTATE_UINT32(maccr, FTGMAC100State),
1050         VMSTATE_UINT32(phycr, FTGMAC100State),
1051         VMSTATE_UINT32(phydata, FTGMAC100State),
1052         VMSTATE_UINT32(fcr, FTGMAC100State),
1053         VMSTATE_UINT32(phy_status, FTGMAC100State),
1054         VMSTATE_UINT32(phy_control, FTGMAC100State),
1055         VMSTATE_UINT32(phy_advertise, FTGMAC100State),
1056         VMSTATE_UINT32(phy_int, FTGMAC100State),
1057         VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
1058         VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
1059         VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
1060         VMSTATE_END_OF_LIST()
1061     }
1062 };
1063 
1064 static Property ftgmac100_properties[] = {
1065     DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
1066     DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
1067     DEFINE_PROP_END_OF_LIST(),
1068 };
1069 
1070 static void ftgmac100_class_init(ObjectClass *klass, void *data)
1071 {
1072     DeviceClass *dc = DEVICE_CLASS(klass);
1073 
1074     dc->vmsd = &vmstate_ftgmac100;
1075     dc->reset = ftgmac100_reset;
1076     dc->props = ftgmac100_properties;
1077     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1078     dc->realize = ftgmac100_realize;
1079     dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation";
1080 }
1081 
1082 static const TypeInfo ftgmac100_info = {
1083     .name = TYPE_FTGMAC100,
1084     .parent = TYPE_SYS_BUS_DEVICE,
1085     .instance_size = sizeof(FTGMAC100State),
1086     .class_init = ftgmac100_class_init,
1087 };
1088 
1089 static void ftgmac100_register_types(void)
1090 {
1091     type_register_static(&ftgmac100_info);
1092 }
1093 
1094 type_init(ftgmac100_register_types)
1095