1 /* 2 * QEMU Freescale eTSEC Emulator 3 * 4 * Copyright (c) 2011-2013 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "net/checksum.h" 26 #include "qemu/log.h" 27 #include "etsec.h" 28 #include "registers.h" 29 30 /* #define ETSEC_RING_DEBUG */ 31 /* #define HEX_DUMP */ 32 /* #define DEBUG_BD */ 33 34 #ifdef ETSEC_RING_DEBUG 35 static const int debug_etsec = 1; 36 #else 37 static const int debug_etsec; 38 #endif 39 40 #define RING_DEBUG(fmt, ...) do { \ 41 if (debug_etsec) { \ 42 qemu_log(fmt , ## __VA_ARGS__); \ 43 } \ 44 } while (0) 45 46 #ifdef DEBUG_BD 47 48 static void print_tx_bd_flags(uint16_t flags) 49 { 50 qemu_log(" Ready: %d\n", !!(flags & BD_TX_READY)); 51 qemu_log(" PAD/CRC: %d\n", !!(flags & BD_TX_PADCRC)); 52 qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP)); 53 qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT)); 54 qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST)); 55 qemu_log(" Tx CRC: %d\n", !!(flags & BD_TX_TC)); 56 qemu_log(" User-defined preamble / defer: %d\n", 57 !!(flags & BD_TX_PREDEF)); 58 qemu_log(" Huge frame enable / Late collision: %d\n", 59 !!(flags & BD_TX_HFELC)); 60 qemu_log(" Control frame / Retransmission Limit: %d\n", 61 !!(flags & BD_TX_CFRL)); 62 qemu_log(" Retry count: %d\n", 63 (flags >> BD_TX_RC_OFFSET) & BD_TX_RC_MASK); 64 qemu_log(" Underrun / TCP/IP off-load enable: %d\n", 65 !!(flags & BD_TX_TOEUN)); 66 qemu_log(" Truncation: %d\n", !!(flags & BD_TX_TR)); 67 } 68 69 static void print_rx_bd_flags(uint16_t flags) 70 { 71 qemu_log(" Empty: %d\n", !!(flags & BD_RX_EMPTY)); 72 qemu_log(" Receive software ownership: %d\n", !!(flags & BD_RX_RO1)); 73 qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP)); 74 qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT)); 75 qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST)); 76 qemu_log(" First in frame: %d\n", !!(flags & BD_RX_FIRST)); 77 qemu_log(" Miss: %d\n", !!(flags & BD_RX_MISS)); 78 qemu_log(" Broadcast: %d\n", !!(flags & BD_RX_BROADCAST)); 79 qemu_log(" Multicast: %d\n", !!(flags & BD_RX_MULTICAST)); 80 qemu_log(" Rx frame length violation: %d\n", !!(flags & BD_RX_LG)); 81 qemu_log(" Rx non-octet aligned frame: %d\n", !!(flags & BD_RX_NO)); 82 qemu_log(" Short frame: %d\n", !!(flags & BD_RX_SH)); 83 qemu_log(" Rx CRC Error: %d\n", !!(flags & BD_RX_CR)); 84 qemu_log(" Overrun: %d\n", !!(flags & BD_RX_OV)); 85 qemu_log(" Truncation: %d\n", !!(flags & BD_RX_TR)); 86 } 87 88 89 static void print_bd(eTSEC_rxtx_bd bd, int mode, uint32_t index) 90 { 91 qemu_log("eTSEC %s Data Buffer Descriptor (%u)\n", 92 mode == eTSEC_TRANSMIT ? "Transmit" : "Receive", 93 index); 94 qemu_log(" Flags : 0x%04x\n", bd.flags); 95 if (mode == eTSEC_TRANSMIT) { 96 print_tx_bd_flags(bd.flags); 97 } else { 98 print_rx_bd_flags(bd.flags); 99 } 100 qemu_log(" Length : 0x%04x\n", bd.length); 101 qemu_log(" Pointer : 0x%08x\n", bd.bufptr); 102 } 103 104 #endif /* DEBUG_BD */ 105 106 static void read_buffer_descriptor(eTSEC *etsec, 107 hwaddr addr, 108 eTSEC_rxtx_bd *bd) 109 { 110 assert(bd != NULL); 111 112 RING_DEBUG("READ Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr); 113 cpu_physical_memory_read(addr, 114 bd, 115 sizeof(eTSEC_rxtx_bd)); 116 117 if (etsec->regs[DMACTRL].value & DMACTRL_LE) { 118 bd->flags = lduw_le_p(&bd->flags); 119 bd->length = lduw_le_p(&bd->length); 120 bd->bufptr = ldl_le_p(&bd->bufptr); 121 } else { 122 bd->flags = lduw_be_p(&bd->flags); 123 bd->length = lduw_be_p(&bd->length); 124 bd->bufptr = ldl_be_p(&bd->bufptr); 125 } 126 } 127 128 static void write_buffer_descriptor(eTSEC *etsec, 129 hwaddr addr, 130 eTSEC_rxtx_bd *bd) 131 { 132 assert(bd != NULL); 133 134 if (etsec->regs[DMACTRL].value & DMACTRL_LE) { 135 stw_le_p(&bd->flags, bd->flags); 136 stw_le_p(&bd->length, bd->length); 137 stl_le_p(&bd->bufptr, bd->bufptr); 138 } else { 139 stw_be_p(&bd->flags, bd->flags); 140 stw_be_p(&bd->length, bd->length); 141 stl_be_p(&bd->bufptr, bd->bufptr); 142 } 143 144 RING_DEBUG("Write Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr); 145 cpu_physical_memory_write(addr, 146 bd, 147 sizeof(eTSEC_rxtx_bd)); 148 } 149 150 static void ievent_set(eTSEC *etsec, 151 uint32_t flags) 152 { 153 etsec->regs[IEVENT].value |= flags; 154 155 etsec_update_irq(etsec); 156 } 157 158 static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len) 159 { 160 int add = min_frame_len - etsec->tx_buffer_len; 161 162 /* Padding */ 163 if (add > 0) { 164 RING_DEBUG("pad:%u\n", add); 165 etsec->tx_buffer = g_realloc(etsec->tx_buffer, 166 etsec->tx_buffer_len + add); 167 168 memset(etsec->tx_buffer + etsec->tx_buffer_len, 0x0, add); 169 etsec->tx_buffer_len += add; 170 } 171 172 /* Never add CRC in QEMU */ 173 } 174 175 static void process_tx_fcb(eTSEC *etsec) 176 { 177 uint8_t flags = (uint8_t)(*etsec->tx_buffer); 178 /* L3 header offset from start of frame */ 179 uint8_t l3_header_offset = (uint8_t)*(etsec->tx_buffer + 3); 180 /* L4 header offset from start of L3 header */ 181 uint8_t l4_header_offset = (uint8_t)*(etsec->tx_buffer + 2); 182 /* L3 header */ 183 uint8_t *l3_header = etsec->tx_buffer + 8 + l3_header_offset; 184 /* L4 header */ 185 uint8_t *l4_header = l3_header + l4_header_offset; 186 int csum = 0; 187 188 /* if packet is IP4 and IP checksum is requested */ 189 if (flags & FCB_TX_IP && flags & FCB_TX_CIP) { 190 csum |= CSUM_IP; 191 } 192 /* TODO Check the correct usage of the PHCS field of the FCB in case the NPH 193 * flag is on */ 194 195 /* if packet is IP4 and TCP or UDP */ 196 if (flags & FCB_TX_IP && flags & FCB_TX_TUP) { 197 /* if UDP */ 198 if (flags & FCB_TX_UDP) { 199 /* if checksum is requested */ 200 if (flags & FCB_TX_CTU) { 201 /* do UDP checksum */ 202 csum |= CSUM_UDP; 203 } else { 204 /* set checksum field to 0 */ 205 l4_header[6] = 0; 206 l4_header[7] = 0; 207 } 208 } else if (flags & FCB_TX_CTU) { /* if TCP and checksum is requested */ 209 /* do TCP checksum */ 210 csum |= CSUM_TCP; 211 } 212 } 213 214 if (csum) { 215 net_checksum_calculate(etsec->tx_buffer + 8, 216 etsec->tx_buffer_len - 8, csum); 217 } 218 } 219 220 static void process_tx_bd(eTSEC *etsec, 221 eTSEC_rxtx_bd *bd) 222 { 223 uint8_t *tmp_buff = NULL; 224 hwaddr tbdbth = (hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32; 225 226 if (bd->length == 0) { 227 /* ERROR */ 228 return; 229 } 230 231 if (etsec->tx_buffer_len == 0) { 232 /* It's the first BD */ 233 etsec->first_bd = *bd; 234 } 235 236 /* TODO: if TxBD[TOE/UN] skip the Tx Frame Control Block*/ 237 238 /* Load this Data Buffer */ 239 etsec->tx_buffer = g_realloc(etsec->tx_buffer, 240 etsec->tx_buffer_len + bd->length); 241 tmp_buff = etsec->tx_buffer + etsec->tx_buffer_len; 242 cpu_physical_memory_read(bd->bufptr + tbdbth, tmp_buff, bd->length); 243 244 /* Update buffer length */ 245 etsec->tx_buffer_len += bd->length; 246 247 248 if (etsec->tx_buffer_len != 0 && (bd->flags & BD_LAST)) { 249 if (etsec->regs[MACCFG1].value & MACCFG1_TX_EN) { 250 /* MAC Transmit enabled */ 251 252 /* Process offload Tx FCB */ 253 if (etsec->first_bd.flags & BD_TX_TOEUN) { 254 process_tx_fcb(etsec); 255 } 256 257 if (etsec->first_bd.flags & BD_TX_PADCRC 258 || etsec->regs[MACCFG2].value & MACCFG2_PADCRC) { 259 260 /* Padding and CRC (Padding implies CRC) */ 261 tx_padding_and_crc(etsec, 60); 262 263 } else if (etsec->first_bd.flags & BD_TX_TC 264 || etsec->regs[MACCFG2].value & MACCFG2_CRC_EN) { 265 266 /* Only CRC */ 267 /* Never add CRC in QEMU */ 268 } 269 270 #if defined(HEX_DUMP) 271 qemu_log("eTSEC Send packet size:%d\n", etsec->tx_buffer_len); 272 qemu_hexdump(stderr, "", etsec->tx_buffer, etsec->tx_buffer_len); 273 #endif /* ETSEC_RING_DEBUG */ 274 275 if (etsec->first_bd.flags & BD_TX_TOEUN) { 276 qemu_send_packet(qemu_get_queue(etsec->nic), 277 etsec->tx_buffer + 8, 278 etsec->tx_buffer_len - 8); 279 } else { 280 qemu_send_packet(qemu_get_queue(etsec->nic), 281 etsec->tx_buffer, 282 etsec->tx_buffer_len); 283 } 284 285 } 286 287 etsec->tx_buffer_len = 0; 288 289 if (bd->flags & BD_INTERRUPT) { 290 ievent_set(etsec, IEVENT_TXF); 291 } 292 } else { 293 if (bd->flags & BD_INTERRUPT) { 294 ievent_set(etsec, IEVENT_TXB); 295 } 296 } 297 298 /* Update DB flags */ 299 300 /* Clear Ready */ 301 bd->flags &= ~BD_TX_READY; 302 303 /* Clear Defer */ 304 bd->flags &= ~BD_TX_PREDEF; 305 306 /* Clear Late Collision */ 307 bd->flags &= ~BD_TX_HFELC; 308 309 /* Clear Retransmission Limit */ 310 bd->flags &= ~BD_TX_CFRL; 311 312 /* Clear Retry Count */ 313 bd->flags &= ~(BD_TX_RC_MASK << BD_TX_RC_OFFSET); 314 315 /* Clear Underrun */ 316 bd->flags &= ~BD_TX_TOEUN; 317 318 /* Clear Truncation */ 319 bd->flags &= ~BD_TX_TR; 320 } 321 322 void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr) 323 { 324 hwaddr ring_base = 0; 325 hwaddr bd_addr = 0; 326 eTSEC_rxtx_bd bd; 327 uint16_t bd_flags; 328 329 if (!(etsec->regs[MACCFG1].value & MACCFG1_TX_EN)) { 330 RING_DEBUG("%s: MAC Transmit not enabled\n", __func__); 331 return; 332 } 333 334 ring_base = (hwaddr)(etsec->regs[TBASEH].value & 0xF) << 32; 335 ring_base += etsec->regs[TBASE0 + ring_nbr].value & ~0x7; 336 bd_addr = etsec->regs[TBPTR0 + ring_nbr].value & ~0x7; 337 338 do { 339 read_buffer_descriptor(etsec, bd_addr, &bd); 340 341 #ifdef DEBUG_BD 342 print_bd(bd, 343 eTSEC_TRANSMIT, 344 (bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd)); 345 346 #endif /* DEBUG_BD */ 347 348 /* Save flags before BD update */ 349 bd_flags = bd.flags; 350 351 if (!(bd_flags & BD_TX_READY)) { 352 break; 353 } 354 355 process_tx_bd(etsec, &bd); 356 /* Write back BD after update */ 357 write_buffer_descriptor(etsec, bd_addr, &bd); 358 359 /* Wrap or next BD */ 360 if (bd_flags & BD_WRAP) { 361 bd_addr = ring_base; 362 } else { 363 bd_addr += sizeof(eTSEC_rxtx_bd); 364 } 365 } while (TRUE); 366 367 /* Save the Buffer Descriptor Pointers to last bd that was not 368 * succesfully closed */ 369 etsec->regs[TBPTR0 + ring_nbr].value = bd_addr; 370 371 /* Set transmit halt THLTx */ 372 etsec->regs[TSTAT].value |= 1 << (31 - ring_nbr); 373 } 374 375 static void fill_rx_bd(eTSEC *etsec, 376 eTSEC_rxtx_bd *bd, 377 const uint8_t **buf, 378 size_t *size) 379 { 380 uint16_t to_write; 381 hwaddr bufptr = bd->bufptr + 382 ((hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32); 383 uint8_t padd[etsec->rx_padding]; 384 uint8_t rem; 385 386 RING_DEBUG("eTSEC fill Rx buffer @ 0x%016" HWADDR_PRIx 387 " size:%zu(padding + crc:%u) + fcb:%u\n", 388 bufptr, *size, etsec->rx_padding, etsec->rx_fcb_size); 389 390 bd->length = 0; 391 392 /* This operation will only write FCB */ 393 if (etsec->rx_fcb_size != 0) { 394 395 cpu_physical_memory_write(bufptr, etsec->rx_fcb, etsec->rx_fcb_size); 396 397 bufptr += etsec->rx_fcb_size; 398 bd->length += etsec->rx_fcb_size; 399 etsec->rx_fcb_size = 0; 400 401 } 402 403 /* We remove padding from the computation of to_write because it is not 404 * allocated in the buffer. 405 */ 406 to_write = MIN(*size - etsec->rx_padding, 407 etsec->regs[MRBLR].value - etsec->rx_fcb_size); 408 409 /* This operation can only write packet data and no padding */ 410 if (to_write > 0) { 411 cpu_physical_memory_write(bufptr, *buf, to_write); 412 413 *buf += to_write; 414 bufptr += to_write; 415 *size -= to_write; 416 417 bd->flags &= ~BD_RX_EMPTY; 418 bd->length += to_write; 419 } 420 421 if (*size == etsec->rx_padding) { 422 /* The remaining bytes are only for padding which is not actually 423 * allocated in the data buffer. 424 */ 425 426 rem = MIN(etsec->regs[MRBLR].value - bd->length, etsec->rx_padding); 427 428 if (rem > 0) { 429 memset(padd, 0x0, sizeof(padd)); 430 etsec->rx_padding -= rem; 431 *size -= rem; 432 bd->length += rem; 433 cpu_physical_memory_write(bufptr, padd, rem); 434 } 435 } 436 } 437 438 static void rx_init_frame(eTSEC *etsec, const uint8_t *buf, size_t size) 439 { 440 uint32_t fcb_size = 0; 441 uint8_t prsdep = (etsec->regs[RCTRL].value >> RCTRL_PRSDEP_OFFSET) 442 & RCTRL_PRSDEP_MASK; 443 444 if (prsdep != 0) { 445 /* Prepend FCB (FCB size + RCTRL[PAL]) */ 446 fcb_size = 8 + ((etsec->regs[RCTRL].value >> 16) & 0x1F); 447 448 etsec->rx_fcb_size = fcb_size; 449 450 /* TODO: fill_FCB(etsec); */ 451 memset(etsec->rx_fcb, 0x0, sizeof(etsec->rx_fcb)); 452 453 } else { 454 etsec->rx_fcb_size = 0; 455 } 456 457 g_free(etsec->rx_buffer); 458 459 /* Do not copy the frame for now */ 460 etsec->rx_buffer = (uint8_t *)buf; 461 etsec->rx_buffer_len = size; 462 463 /* CRC padding (We don't have to compute the CRC) */ 464 etsec->rx_padding = 4; 465 466 /* 467 * Ensure that payload length + CRC length is at least 802.3 468 * minimum MTU size bytes long (64) 469 */ 470 if (etsec->rx_buffer_len < 60) { 471 etsec->rx_padding += 60 - etsec->rx_buffer_len; 472 } 473 474 etsec->rx_first_in_frame = 1; 475 etsec->rx_remaining_data = etsec->rx_buffer_len; 476 RING_DEBUG("%s: rx_buffer_len:%u rx_padding+crc:%u\n", __func__, 477 etsec->rx_buffer_len, etsec->rx_padding); 478 } 479 480 ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size) 481 { 482 int ring_nbr = 0; /* Always use ring0 (no filer) */ 483 484 if (etsec->rx_buffer_len != 0) { 485 RING_DEBUG("%s: We can't receive now," 486 " a buffer is already in the pipe\n", __func__); 487 return 0; 488 } 489 490 if (etsec->regs[RSTAT].value & 1 << (23 - ring_nbr)) { 491 RING_DEBUG("%s: The ring is halted\n", __func__); 492 return -1; 493 } 494 495 if (etsec->regs[DMACTRL].value & DMACTRL_GRS) { 496 RING_DEBUG("%s: Graceful receive stop\n", __func__); 497 return -1; 498 } 499 500 if (!(etsec->regs[MACCFG1].value & MACCFG1_RX_EN)) { 501 RING_DEBUG("%s: MAC Receive not enabled\n", __func__); 502 return -1; 503 } 504 505 if (!(etsec->regs[RCTRL].value & RCTRL_RSF) && (size < 60)) { 506 /* CRC is not in the packet yet, so short frame is below 60 bytes */ 507 RING_DEBUG("%s: Drop short frame\n", __func__); 508 return -1; 509 } 510 511 rx_init_frame(etsec, buf, size); 512 513 etsec_walk_rx_ring(etsec, ring_nbr); 514 515 return size; 516 } 517 518 void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr) 519 { 520 hwaddr ring_base = 0; 521 hwaddr bd_addr = 0; 522 hwaddr start_bd_addr = 0; 523 eTSEC_rxtx_bd bd; 524 uint16_t bd_flags; 525 size_t remaining_data; 526 const uint8_t *buf; 527 uint8_t *tmp_buf; 528 size_t size; 529 530 if (etsec->rx_buffer_len == 0) { 531 /* No frame to send */ 532 RING_DEBUG("No frame to send\n"); 533 return; 534 } 535 536 remaining_data = etsec->rx_remaining_data + etsec->rx_padding; 537 buf = etsec->rx_buffer 538 + (etsec->rx_buffer_len - etsec->rx_remaining_data); 539 size = etsec->rx_buffer_len + etsec->rx_padding; 540 541 ring_base = (hwaddr)(etsec->regs[RBASEH].value & 0xF) << 32; 542 ring_base += etsec->regs[RBASE0 + ring_nbr].value & ~0x7; 543 start_bd_addr = bd_addr = etsec->regs[RBPTR0 + ring_nbr].value & ~0x7; 544 545 do { 546 read_buffer_descriptor(etsec, bd_addr, &bd); 547 548 #ifdef DEBUG_BD 549 print_bd(bd, 550 eTSEC_RECEIVE, 551 (bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd)); 552 553 #endif /* DEBUG_BD */ 554 555 /* Save flags before BD update */ 556 bd_flags = bd.flags; 557 558 if (bd_flags & BD_RX_EMPTY) { 559 fill_rx_bd(etsec, &bd, &buf, &remaining_data); 560 561 if (etsec->rx_first_in_frame) { 562 bd.flags |= BD_RX_FIRST; 563 etsec->rx_first_in_frame = 0; 564 etsec->rx_first_bd = bd; 565 } 566 567 /* Last in frame */ 568 if (remaining_data == 0) { 569 570 /* Clear flags */ 571 572 bd.flags &= ~0x7ff; 573 574 bd.flags |= BD_LAST; 575 576 /* NOTE: non-octet aligned frame is impossible in qemu */ 577 578 if (size >= etsec->regs[MAXFRM].value) { 579 /* frame length violation */ 580 qemu_log("%s frame length violation: size:%zu MAXFRM:%d\n", 581 __func__, size, etsec->regs[MAXFRM].value); 582 583 bd.flags |= BD_RX_LG; 584 } 585 586 if (size < 64) { 587 /* Short frame */ 588 bd.flags |= BD_RX_SH; 589 } 590 591 /* TODO: Broadcast and Multicast */ 592 593 if (bd.flags & BD_INTERRUPT) { 594 /* Set RXFx */ 595 etsec->regs[RSTAT].value |= 1 << (7 - ring_nbr); 596 597 /* Set IEVENT */ 598 ievent_set(etsec, IEVENT_RXF); 599 } 600 601 } else { 602 if (bd.flags & BD_INTERRUPT) { 603 /* Set IEVENT */ 604 ievent_set(etsec, IEVENT_RXB); 605 } 606 } 607 608 /* Write back BD after update */ 609 write_buffer_descriptor(etsec, bd_addr, &bd); 610 } 611 612 /* Wrap or next BD */ 613 if (bd_flags & BD_WRAP) { 614 bd_addr = ring_base; 615 } else { 616 bd_addr += sizeof(eTSEC_rxtx_bd); 617 } 618 } while (remaining_data != 0 619 && (bd_flags & BD_RX_EMPTY) 620 && bd_addr != start_bd_addr); 621 622 /* Reset ring ptr */ 623 etsec->regs[RBPTR0 + ring_nbr].value = bd_addr; 624 625 /* The frame is too large to fit in the Rx ring */ 626 if (remaining_data > 0) { 627 628 /* Set RSTAT[QHLTx] */ 629 etsec->regs[RSTAT].value |= 1 << (23 - ring_nbr); 630 631 /* Save remaining data to send the end of the frame when the ring will 632 * be restarted 633 */ 634 etsec->rx_remaining_data = remaining_data; 635 636 /* Copy the frame */ 637 tmp_buf = g_malloc(size); 638 memcpy(tmp_buf, etsec->rx_buffer, size); 639 etsec->rx_buffer = tmp_buf; 640 641 RING_DEBUG("no empty RxBD available any more\n"); 642 } else { 643 etsec->rx_buffer_len = 0; 644 etsec->rx_buffer = NULL; 645 if (etsec->need_flush) { 646 qemu_flush_queued_packets(qemu_get_queue(etsec->nic)); 647 } 648 } 649 650 RING_DEBUG("eTSEC End of ring_write: remaining_data:%zu\n", remaining_data); 651 } 652