1 /* 2 * QEMU Freescale eTSEC Emulator 3 * 4 * Copyright (c) 2011-2013 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "etsec.h" 26 #include "registers.h" 27 28 /* #define DEBUG_MIIM */ 29 30 #define MIIM_CONTROL 0 31 #define MIIM_STATUS 1 32 #define MIIM_PHY_ID_1 2 33 #define MIIM_PHY_ID_2 3 34 #define MIIM_T2_STATUS 10 35 #define MIIM_EXT_STATUS 15 36 37 static void miim_read_cycle(eTSEC *etsec) 38 { 39 uint8_t phy; 40 uint8_t addr; 41 uint16_t value; 42 43 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; 44 (void)phy; /* Unreferenced */ 45 addr = etsec->regs[MIIMADD].value & 0x1F; 46 47 switch (addr) { 48 case MIIM_CONTROL: 49 value = etsec->phy_control; 50 break; 51 case MIIM_STATUS: 52 value = etsec->phy_status; 53 break; 54 case MIIM_T2_STATUS: 55 value = 0x1800; /* Local and remote receivers OK */ 56 break; 57 default: 58 value = 0x0; 59 break; 60 }; 61 62 #ifdef DEBUG_MIIM 63 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); 64 #endif 65 66 etsec->regs[MIIMSTAT].value = value; 67 } 68 69 static void miim_write_cycle(eTSEC *etsec) 70 { 71 uint8_t phy; 72 uint8_t addr; 73 uint16_t value; 74 75 phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F; 76 (void)phy; /* Unreferenced */ 77 addr = etsec->regs[MIIMADD].value & 0x1F; 78 value = etsec->regs[MIIMCON].value & 0xffff; 79 80 #ifdef DEBUG_MIIM 81 qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value); 82 #endif 83 84 switch (addr) { 85 case MIIM_CONTROL: 86 etsec->phy_control = value & ~(0x8100); 87 break; 88 default: 89 break; 90 }; 91 } 92 93 void etsec_write_miim(eTSEC *etsec, 94 eTSEC_Register *reg, 95 uint32_t reg_index, 96 uint32_t value) 97 { 98 99 switch (reg_index) { 100 101 case MIIMCOM: 102 /* Read and scan cycle */ 103 104 if ((!(reg->value & MIIMCOM_READ)) && (value & MIIMCOM_READ)) { 105 /* Read */ 106 miim_read_cycle(etsec); 107 } 108 reg->value = value; 109 break; 110 111 case MIIMCON: 112 reg->value = value & 0xffff; 113 miim_write_cycle(etsec); 114 break; 115 116 default: 117 /* Default handling */ 118 switch (reg->access) { 119 120 case ACC_RW: 121 case ACC_WO: 122 reg->value = value; 123 break; 124 125 case ACC_W1C: 126 reg->value &= ~value; 127 break; 128 129 case ACC_RO: 130 default: 131 /* Read Only or Unknown register */ 132 break; 133 } 134 } 135 136 } 137 138 void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc) 139 { 140 /* Set link status */ 141 if (nc->link_down) { 142 etsec->phy_status &= ~MII_SR_LINK_STATUS; 143 } else { 144 etsec->phy_status |= MII_SR_LINK_STATUS; 145 } 146 } 147