xref: /openbmc/qemu/hw/net/fsl_etsec/etsec.c (revision 64552b6b)
1 /*
2  * QEMU Freescale eTSEC Emulator
3  *
4  * Copyright (c) 2011-2013 AdaCore
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 /*
26  * This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.
27  */
28 
29 #include "qemu/osdep.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/sysbus.h"
32 #include "hw/irq.h"
33 #include "hw/ptimer.h"
34 #include "etsec.h"
35 #include "registers.h"
36 #include "qemu/log.h"
37 #include "qemu/module.h"
38 
39 /* #define HEX_DUMP */
40 /* #define DEBUG_REGISTER */
41 
42 #ifdef DEBUG_REGISTER
43 static const int debug_etsec = 1;
44 #else
45 static const int debug_etsec;
46 #endif
47 
48 #define DPRINTF(fmt, ...) do {                 \
49     if (debug_etsec) {                         \
50         qemu_log(fmt , ## __VA_ARGS__);        \
51     }                                          \
52     } while (0)
53 
54 /* call after any change to IEVENT or IMASK */
55 void etsec_update_irq(eTSEC *etsec)
56 {
57     uint32_t ievent = etsec->regs[IEVENT].value;
58     uint32_t imask  = etsec->regs[IMASK].value;
59     uint32_t active = ievent & imask;
60 
61     int tx  = !!(active & IEVENT_TX_MASK);
62     int rx  = !!(active & IEVENT_RX_MASK);
63     int err = !!(active & IEVENT_ERR_MASK);
64 
65     DPRINTF("%s IRQ ievent=%"PRIx32" imask=%"PRIx32" %c%c%c",
66             __func__, ievent, imask,
67             tx  ? 'T' : '_',
68             rx  ? 'R' : '_',
69             err ? 'E' : '_');
70 
71     qemu_set_irq(etsec->tx_irq, tx);
72     qemu_set_irq(etsec->rx_irq, rx);
73     qemu_set_irq(etsec->err_irq, err);
74 }
75 
76 static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
77 {
78     eTSEC          *etsec     = opaque;
79     uint32_t        reg_index = addr / 4;
80     eTSEC_Register *reg       = NULL;
81     uint32_t        ret       = 0x0;
82 
83     assert(reg_index < ETSEC_REG_NUMBER);
84 
85     reg = &etsec->regs[reg_index];
86 
87 
88     switch (reg->access) {
89     case ACC_WO:
90         ret = 0x00000000;
91         break;
92 
93     case ACC_RW:
94     case ACC_W1C:
95     case ACC_RO:
96     default:
97         ret = reg->value;
98         break;
99     }
100 
101     DPRINTF("Read  0x%08x @ 0x" TARGET_FMT_plx
102             "                            : %s (%s)\n",
103             ret, addr, reg->name, reg->desc);
104 
105     return ret;
106 }
107 
108 static void write_tstat(eTSEC          *etsec,
109                         eTSEC_Register *reg,
110                         uint32_t        reg_index,
111                         uint32_t        value)
112 {
113     int i = 0;
114 
115     for (i = 0; i < 8; i++) {
116         /* Check THLTi flag in TSTAT */
117         if (value & (1 << (31 - i))) {
118             etsec_walk_tx_ring(etsec, i);
119         }
120     }
121 
122     /* Write 1 to clear */
123     reg->value &= ~value;
124 }
125 
126 static void write_rstat(eTSEC          *etsec,
127                         eTSEC_Register *reg,
128                         uint32_t        reg_index,
129                         uint32_t        value)
130 {
131     int i = 0;
132 
133     for (i = 0; i < 8; i++) {
134         /* Check QHLTi flag in RSTAT */
135         if (value & (1 << (23 - i)) && !(reg->value & (1 << (23 - i)))) {
136             etsec_walk_rx_ring(etsec, i);
137         }
138     }
139 
140     /* Write 1 to clear */
141     reg->value &= ~value;
142 }
143 
144 static void write_tbasex(eTSEC          *etsec,
145                          eTSEC_Register *reg,
146                          uint32_t        reg_index,
147                          uint32_t        value)
148 {
149     reg->value = value & ~0x7;
150 
151     /* Copy this value in the ring's TxBD pointer */
152     etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7;
153 }
154 
155 static void write_rbasex(eTSEC          *etsec,
156                          eTSEC_Register *reg,
157                          uint32_t        reg_index,
158                          uint32_t        value)
159 {
160     reg->value = value & ~0x7;
161 
162     /* Copy this value in the ring's RxBD pointer */
163     etsec->regs[RBPTR0 + (reg_index - RBASE0)].value = value & ~0x7;
164 }
165 
166 static void write_dmactrl(eTSEC          *etsec,
167                           eTSEC_Register *reg,
168                           uint32_t        reg_index,
169                           uint32_t        value)
170 {
171     reg->value = value;
172 
173     if (value & DMACTRL_GRS) {
174 
175         if (etsec->rx_buffer_len != 0) {
176             /* Graceful receive stop delayed until end of frame */
177         } else {
178             /* Graceful receive stop now */
179             etsec->regs[IEVENT].value |= IEVENT_GRSC;
180             etsec_update_irq(etsec);
181         }
182     }
183 
184     if (value & DMACTRL_GTS) {
185 
186         if (etsec->tx_buffer_len != 0) {
187             /* Graceful transmit stop delayed until end of frame */
188         } else {
189             /* Graceful transmit stop now */
190             etsec->regs[IEVENT].value |= IEVENT_GTSC;
191             etsec_update_irq(etsec);
192         }
193     }
194 
195     if (!(value & DMACTRL_WOP)) {
196         /* Start polling */
197         ptimer_stop(etsec->ptimer);
198         ptimer_set_count(etsec->ptimer, 1);
199         ptimer_run(etsec->ptimer, 1);
200     }
201 }
202 
203 static void etsec_write(void     *opaque,
204                         hwaddr    addr,
205                         uint64_t  value,
206                         unsigned  size)
207 {
208     eTSEC          *etsec     = opaque;
209     uint32_t        reg_index = addr / 4;
210     eTSEC_Register *reg       = NULL;
211     uint32_t        before    = 0x0;
212 
213     assert(reg_index < ETSEC_REG_NUMBER);
214 
215     reg = &etsec->regs[reg_index];
216     before = reg->value;
217 
218     switch (reg_index) {
219     case IEVENT:
220         /* Write 1 to clear */
221         reg->value &= ~value;
222 
223         etsec_update_irq(etsec);
224         break;
225 
226     case IMASK:
227         reg->value = value;
228 
229         etsec_update_irq(etsec);
230         break;
231 
232     case DMACTRL:
233         write_dmactrl(etsec, reg, reg_index, value);
234         break;
235 
236     case TSTAT:
237         write_tstat(etsec, reg, reg_index, value);
238         break;
239 
240     case RSTAT:
241         write_rstat(etsec, reg, reg_index, value);
242         break;
243 
244     case TBASE0 ... TBASE7:
245         write_tbasex(etsec, reg, reg_index, value);
246         break;
247 
248     case RBASE0 ... RBASE7:
249         write_rbasex(etsec, reg, reg_index, value);
250         break;
251 
252     case MIIMCFG ... MIIMIND:
253         etsec_write_miim(etsec, reg, reg_index, value);
254         break;
255 
256     default:
257         /* Default handling */
258         switch (reg->access) {
259 
260         case ACC_RW:
261         case ACC_WO:
262             reg->value = value;
263             break;
264 
265         case ACC_W1C:
266             reg->value &= ~value;
267             break;
268 
269         case ACC_RO:
270         default:
271             /* Read Only or Unknown register */
272             break;
273         }
274     }
275 
276     DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
277             " val:0x%08x->0x%08x : %s (%s)\n",
278             (unsigned int)value, addr, before, reg->value,
279             reg->name, reg->desc);
280 }
281 
282 static const MemoryRegionOps etsec_ops = {
283     .read = etsec_read,
284     .write = etsec_write,
285     .endianness = DEVICE_NATIVE_ENDIAN,
286     .impl = {
287         .min_access_size = 4,
288         .max_access_size = 4,
289     },
290 };
291 
292 static void etsec_timer_hit(void *opaque)
293 {
294     eTSEC *etsec = opaque;
295 
296     ptimer_stop(etsec->ptimer);
297 
298     if (!(etsec->regs[DMACTRL].value & DMACTRL_WOP)) {
299 
300         if (!(etsec->regs[DMACTRL].value & DMACTRL_GTS)) {
301             etsec_walk_tx_ring(etsec, 0);
302         }
303         ptimer_set_count(etsec->ptimer, 1);
304         ptimer_run(etsec->ptimer, 1);
305     }
306 }
307 
308 static void etsec_reset(DeviceState *d)
309 {
310     eTSEC *etsec = ETSEC_COMMON(d);
311     int i = 0;
312     int reg_index = 0;
313 
314     /* Default value for all registers */
315     for (i = 0; i < ETSEC_REG_NUMBER; i++) {
316         etsec->regs[i].name   = "Reserved";
317         etsec->regs[i].desc   = "";
318         etsec->regs[i].access = ACC_UNKNOWN;
319         etsec->regs[i].value  = 0x00000000;
320     }
321 
322     /* Set-up known registers */
323     for (i = 0; eTSEC_registers_def[i].name != NULL; i++) {
324 
325         reg_index = eTSEC_registers_def[i].offset / 4;
326 
327         etsec->regs[reg_index].name   = eTSEC_registers_def[i].name;
328         etsec->regs[reg_index].desc   = eTSEC_registers_def[i].desc;
329         etsec->regs[reg_index].access = eTSEC_registers_def[i].access;
330         etsec->regs[reg_index].value  = eTSEC_registers_def[i].reset;
331     }
332 
333     etsec->tx_buffer     = NULL;
334     etsec->tx_buffer_len = 0;
335     etsec->rx_buffer     = NULL;
336     etsec->rx_buffer_len = 0;
337 
338     etsec->phy_status =
339         MII_SR_EXTENDED_CAPS    | MII_SR_LINK_STATUS   | MII_SR_AUTONEG_CAPS  |
340         MII_SR_AUTONEG_COMPLETE | MII_SR_PREAMBLE_SUPPRESS |
341         MII_SR_EXTENDED_STATUS  | MII_SR_100T2_HD_CAPS | MII_SR_100T2_FD_CAPS |
342         MII_SR_10T_HD_CAPS      | MII_SR_10T_FD_CAPS   | MII_SR_100X_HD_CAPS  |
343         MII_SR_100X_FD_CAPS     | MII_SR_100T4_CAPS;
344 
345     etsec_update_irq(etsec);
346 }
347 
348 static ssize_t etsec_receive(NetClientState *nc,
349                              const uint8_t  *buf,
350                              size_t          size)
351 {
352     ssize_t ret;
353     eTSEC *etsec = qemu_get_nic_opaque(nc);
354 
355 #if defined(HEX_DUMP)
356     fprintf(stderr, "%s receive size:%zd\n", nc->name, size);
357     qemu_hexdump((void *)buf, stderr, "", size);
358 #endif
359     /* Flush is unnecessary as are already in receiving path */
360     etsec->need_flush = false;
361     ret = etsec_rx_ring_write(etsec, buf, size);
362     if (ret == 0) {
363         /* The packet will be queued, let's flush it when buffer is available
364          * again. */
365         etsec->need_flush = true;
366     }
367     return ret;
368 }
369 
370 
371 static void etsec_set_link_status(NetClientState *nc)
372 {
373     eTSEC *etsec = qemu_get_nic_opaque(nc);
374 
375     etsec_miim_link_status(etsec, nc);
376 }
377 
378 static NetClientInfo net_etsec_info = {
379     .type = NET_CLIENT_DRIVER_NIC,
380     .size = sizeof(NICState),
381     .receive = etsec_receive,
382     .link_status_changed = etsec_set_link_status,
383 };
384 
385 static void etsec_realize(DeviceState *dev, Error **errp)
386 {
387     eTSEC        *etsec = ETSEC_COMMON(dev);
388 
389     etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
390                               object_get_typename(OBJECT(dev)), dev->id, etsec);
391     qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);
392 
393 
394     etsec->bh     = qemu_bh_new(etsec_timer_hit, etsec);
395     etsec->ptimer = ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT);
396     ptimer_set_freq(etsec->ptimer, 100);
397 }
398 
399 static void etsec_instance_init(Object *obj)
400 {
401     eTSEC        *etsec = ETSEC_COMMON(obj);
402     SysBusDevice *sbd   = SYS_BUS_DEVICE(obj);
403 
404     memory_region_init_io(&etsec->io_area, OBJECT(etsec), &etsec_ops, etsec,
405                           "eTSEC", 0x1000);
406     sysbus_init_mmio(sbd, &etsec->io_area);
407 
408     sysbus_init_irq(sbd, &etsec->tx_irq);
409     sysbus_init_irq(sbd, &etsec->rx_irq);
410     sysbus_init_irq(sbd, &etsec->err_irq);
411 }
412 
413 static Property etsec_properties[] = {
414     DEFINE_NIC_PROPERTIES(eTSEC, conf),
415     DEFINE_PROP_END_OF_LIST(),
416 };
417 
418 static void etsec_class_init(ObjectClass *klass, void *data)
419 {
420     DeviceClass *dc = DEVICE_CLASS(klass);
421 
422     dc->realize = etsec_realize;
423     dc->reset = etsec_reset;
424     dc->props = etsec_properties;
425     /* Supported by ppce500 machine */
426     dc->user_creatable = true;
427 }
428 
429 static TypeInfo etsec_info = {
430     .name                  = "eTSEC",
431     .parent                = TYPE_SYS_BUS_DEVICE,
432     .instance_size         = sizeof(eTSEC),
433     .class_init            = etsec_class_init,
434     .instance_init         = etsec_instance_init,
435 };
436 
437 static void etsec_register_types(void)
438 {
439     type_register_static(&etsec_info);
440 }
441 
442 type_init(etsec_register_types)
443 
444 DeviceState *etsec_create(hwaddr         base,
445                           MemoryRegion * mr,
446                           NICInfo      * nd,
447                           qemu_irq       tx_irq,
448                           qemu_irq       rx_irq,
449                           qemu_irq       err_irq)
450 {
451     DeviceState *dev;
452 
453     dev = qdev_create(NULL, "eTSEC");
454     qdev_set_nic_properties(dev, nd);
455     qdev_init_nofail(dev);
456 
457     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, tx_irq);
458     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, rx_irq);
459     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, err_irq);
460 
461     memory_region_add_subregion(mr, base,
462                                 SYS_BUS_DEVICE(dev)->mmio[0].memory);
463 
464     return dev;
465 }
466