1 /* 2 * QEMU i8255x (PRO100) emulation 3 * 4 * Copyright (C) 2006-2011 Stefan Weil 5 * 6 * Portions of the code are copies from grub / etherboot eepro100.c 7 * and linux e100.c. 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation, either version 2 of the License, or 12 * (at your option) version 3 or any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 * 22 * Tested features (i82559): 23 * PXE boot (i386 guest, i386 / mips / mipsel / ppc host) ok 24 * Linux networking (i386) ok 25 * 26 * Untested: 27 * Windows networking 28 * 29 * References: 30 * 31 * Intel 8255x 10/100 Mbps Ethernet Controller Family 32 * Open Source Software Developer Manual 33 * 34 * TODO: 35 * * PHY emulation should be separated from nic emulation. 36 * Most nic emulations could share the same phy code. 37 * * i82550 is untested. It is programmed like the i82559. 38 * * i82562 is untested. It is programmed like the i82559. 39 * * Power management (i82558 and later) is not implemented. 40 * * Wake-on-LAN is not implemented. 41 */ 42 43 #include "qemu/osdep.h" 44 #include "qemu/units.h" 45 #include "hw/pci/pci.h" 46 #include "hw/qdev-properties.h" 47 #include "migration/vmstate.h" 48 #include "net/net.h" 49 #include "net/eth.h" 50 #include "hw/nvram/eeprom93xx.h" 51 #include "sysemu/sysemu.h" 52 #include "sysemu/dma.h" 53 #include "sysemu/reset.h" 54 #include "qemu/bitops.h" 55 #include "qemu/module.h" 56 #include "qapi/error.h" 57 58 /* QEMU sends frames smaller than 60 bytes to ethernet nics. 59 * Such frames are rejected by real nics and their emulations. 60 * To avoid this behaviour, other nic emulations pad received 61 * frames. The following definition enables this padding for 62 * eepro100, too. We keep the define around in case it might 63 * become useful the future if the core networking is ever 64 * changed to pad short packets itself. */ 65 #define CONFIG_PAD_RECEIVED_FRAMES 66 67 /* Debug EEPRO100 card. */ 68 #if 0 69 # define DEBUG_EEPRO100 70 #endif 71 72 #ifdef DEBUG_EEPRO100 73 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__) 74 #else 75 #define logout(fmt, ...) ((void)0) 76 #endif 77 78 /* Set flags to 0 to disable debug output. */ 79 #define INT 1 /* interrupt related actions */ 80 #define MDI 1 /* mdi related actions */ 81 #define OTHER 1 82 #define RXTX 1 83 #define EEPROM 1 /* eeprom related actions */ 84 85 #define TRACE(flag, command) ((flag) ? (command) : (void)0) 86 87 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n") 88 89 #define MAX_ETH_FRAME_SIZE 1514 90 91 /* This driver supports several different devices which are declared here. */ 92 #define i82550 0x82550 93 #define i82551 0x82551 94 #define i82557A 0x82557a 95 #define i82557B 0x82557b 96 #define i82557C 0x82557c 97 #define i82558A 0x82558a 98 #define i82558B 0x82558b 99 #define i82559A 0x82559a 100 #define i82559B 0x82559b 101 #define i82559C 0x82559c 102 #define i82559ER 0x82559e 103 #define i82562 0x82562 104 #define i82801 0x82801 105 106 /* Use 64 word EEPROM. TODO: could be a runtime option. */ 107 #define EEPROM_SIZE 64 108 109 #define PCI_MEM_SIZE (4 * KiB) 110 #define PCI_IO_SIZE 64 111 #define PCI_FLASH_SIZE (128 * KiB) 112 113 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) 114 115 /* The SCB accepts the following controls for the Tx and Rx units: */ 116 #define CU_NOP 0x0000 /* No operation. */ 117 #define CU_START 0x0010 /* CU start. */ 118 #define CU_RESUME 0x0020 /* CU resume. */ 119 #define CU_STATSADDR 0x0040 /* Load dump counters address. */ 120 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ 121 #define CU_CMD_BASE 0x0060 /* Load CU base address. */ 122 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ 123 #define CU_SRESUME 0x00a0 /* CU static resume. */ 124 125 #define RU_NOP 0x0000 126 #define RX_START 0x0001 127 #define RX_RESUME 0x0002 128 #define RU_ABORT 0x0004 129 #define RX_ADDR_LOAD 0x0006 130 #define RX_RESUMENR 0x0007 131 #define INT_MASK 0x0100 132 #define DRVR_INT 0x0200 /* Driver generated interrupt. */ 133 134 typedef struct { 135 const char *name; 136 const char *desc; 137 uint16_t device_id; 138 uint8_t revision; 139 uint16_t subsystem_vendor_id; 140 uint16_t subsystem_id; 141 142 uint32_t device; 143 uint8_t stats_size; 144 bool has_extended_tcb_support; 145 bool power_management; 146 } E100PCIDeviceInfo; 147 148 /* Offsets to the various registers. 149 All accesses need not be longword aligned. */ 150 typedef enum { 151 SCBStatus = 0, /* Status Word. */ 152 SCBAck = 1, 153 SCBCmd = 2, /* Rx/Command Unit command and status. */ 154 SCBIntmask = 3, 155 SCBPointer = 4, /* General purpose pointer. */ 156 SCBPort = 8, /* Misc. commands and operands. */ 157 SCBflash = 12, /* Flash memory control. */ 158 SCBeeprom = 14, /* EEPROM control. */ 159 SCBCtrlMDI = 16, /* MDI interface control. */ 160 SCBEarlyRx = 20, /* Early receive byte count. */ 161 SCBFlow = 24, /* Flow Control. */ 162 SCBpmdr = 27, /* Power Management Driver. */ 163 SCBgctrl = 28, /* General Control. */ 164 SCBgstat = 29, /* General Status. */ 165 } E100RegisterOffset; 166 167 /* A speedo3 transmit buffer descriptor with two buffers... */ 168 typedef struct { 169 uint16_t status; 170 uint16_t command; 171 uint32_t link; /* void * */ 172 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */ 173 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */ 174 uint8_t tx_threshold; /* transmit threshold */ 175 uint8_t tbd_count; /* TBD number */ 176 #if 0 177 /* This constitutes two "TBD" entries: hdr and data */ 178 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */ 179 int32_t tx_buf_size0; /* Length of Tx hdr. */ 180 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */ 181 int32_t tx_buf_size1; /* Length of Tx data. */ 182 #endif 183 } eepro100_tx_t; 184 185 /* Receive frame descriptor. */ 186 typedef struct { 187 int16_t status; 188 uint16_t command; 189 uint32_t link; /* struct RxFD * */ 190 uint32_t rx_buf_addr; /* void * */ 191 uint16_t count; 192 uint16_t size; 193 /* Ethernet frame data follows. */ 194 } eepro100_rx_t; 195 196 typedef enum { 197 COMMAND_EL = BIT(15), 198 COMMAND_S = BIT(14), 199 COMMAND_I = BIT(13), 200 COMMAND_NC = BIT(4), 201 COMMAND_SF = BIT(3), 202 COMMAND_CMD = BITS(2, 0), 203 } scb_command_bit; 204 205 typedef enum { 206 STATUS_C = BIT(15), 207 STATUS_OK = BIT(13), 208 } scb_status_bit; 209 210 typedef struct { 211 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, 212 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, 213 tx_multiple_collisions, tx_total_collisions; 214 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, 215 rx_resource_errors, rx_overrun_errors, rx_cdt_errors, 216 rx_short_frame_errors; 217 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; 218 uint16_t xmt_tco_frames, rcv_tco_frames; 219 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */ 220 uint32_t reserved[4]; 221 } eepro100_stats_t; 222 223 typedef enum { 224 cu_idle = 0, 225 cu_suspended = 1, 226 cu_active = 2, 227 cu_lpq_active = 2, 228 cu_hqp_active = 3 229 } cu_state_t; 230 231 typedef enum { 232 ru_idle = 0, 233 ru_suspended = 1, 234 ru_no_resources = 2, 235 ru_ready = 4 236 } ru_state_t; 237 238 typedef struct { 239 PCIDevice dev; 240 /* Hash register (multicast mask array, multiple individual addresses). */ 241 uint8_t mult[8]; 242 MemoryRegion mmio_bar; 243 MemoryRegion io_bar; 244 MemoryRegion flash_bar; 245 NICState *nic; 246 NICConf conf; 247 uint8_t scb_stat; /* SCB stat/ack byte */ 248 uint8_t int_stat; /* PCI interrupt status */ 249 /* region must not be saved by nic_save. */ 250 uint16_t mdimem[32]; 251 eeprom_t *eeprom; 252 uint32_t device; /* device variant */ 253 /* (cu_base + cu_offset) address the next command block in the command block list. */ 254 uint32_t cu_base; /* CU base address */ 255 uint32_t cu_offset; /* CU address offset */ 256 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ 257 uint32_t ru_base; /* RU base address */ 258 uint32_t ru_offset; /* RU address offset */ 259 uint32_t statsaddr; /* pointer to eepro100_stats_t */ 260 261 /* Temporary status information (no need to save these values), 262 * used while processing CU commands. */ 263 eepro100_tx_t tx; /* transmit buffer descriptor */ 264 uint32_t cb_address; /* = cu_base + cu_offset */ 265 266 /* Statistical counters. Also used for wake-up packet (i82559). */ 267 eepro100_stats_t statistics; 268 269 /* Data in mem is always in the byte order of the controller (le). 270 * It must be dword aligned to allow direct access to 32 bit values. */ 271 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8))); 272 273 /* Configuration bytes. */ 274 uint8_t configuration[22]; 275 276 /* vmstate for each particular nic */ 277 VMStateDescription *vmstate; 278 279 /* Quasi static device properties (no need to save them). */ 280 uint16_t stats_size; 281 bool has_extended_tcb_support; 282 } EEPRO100State; 283 284 /* Word indices in EEPROM. */ 285 typedef enum { 286 EEPROM_CNFG_MDIX = 0x03, 287 EEPROM_ID = 0x05, 288 EEPROM_PHY_ID = 0x06, 289 EEPROM_VENDOR_ID = 0x0c, 290 EEPROM_CONFIG_ASF = 0x0d, 291 EEPROM_DEVICE_ID = 0x23, 292 EEPROM_SMBUS_ADDR = 0x90, 293 } EEPROMOffset; 294 295 /* Bit values for EEPROM ID word. */ 296 typedef enum { 297 EEPROM_ID_MDM = BIT(0), /* Modem */ 298 EEPROM_ID_STB = BIT(1), /* Standby Enable */ 299 EEPROM_ID_WMR = BIT(2), /* ??? */ 300 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */ 301 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */ 302 EEPROM_ID_ALT = BIT(7), /* */ 303 /* BITS(10, 8) device revision */ 304 EEPROM_ID_BD = BIT(11), /* boot disable */ 305 EEPROM_ID_ID = BIT(13), /* id bit */ 306 /* BITS(15, 14) signature */ 307 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */ 308 } eeprom_id_bit; 309 310 /* Default values for MDI (PHY) registers */ 311 static const uint16_t eepro100_mdi_default[] = { 312 /* MDI Registers 0 - 6, 7 */ 313 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, 314 /* MDI Registers 8 - 15 */ 315 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 316 /* MDI Registers 16 - 31 */ 317 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 318 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 319 }; 320 321 /* Readonly mask for MDI (PHY) registers */ 322 static const uint16_t eepro100_mdi_mask[] = { 323 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, 324 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 325 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 326 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 327 }; 328 329 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s); 330 331 /* Read a 16 bit control/status (CSR) register. */ 332 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr) 333 { 334 assert(!((uintptr_t)&s->mem[addr] & 1)); 335 return lduw_le_p(&s->mem[addr]); 336 } 337 338 /* Read a 32 bit control/status (CSR) register. */ 339 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr) 340 { 341 assert(!((uintptr_t)&s->mem[addr] & 3)); 342 return ldl_le_p(&s->mem[addr]); 343 } 344 345 /* Write a 16 bit control/status (CSR) register. */ 346 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr, 347 uint16_t val) 348 { 349 assert(!((uintptr_t)&s->mem[addr] & 1)); 350 stw_le_p(&s->mem[addr], val); 351 } 352 353 /* Read a 32 bit control/status (CSR) register. */ 354 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr, 355 uint32_t val) 356 { 357 assert(!((uintptr_t)&s->mem[addr] & 3)); 358 stl_le_p(&s->mem[addr], val); 359 } 360 361 #if defined(DEBUG_EEPRO100) 362 static const char *nic_dump(const uint8_t * buf, unsigned size) 363 { 364 static char dump[3 * 16 + 1]; 365 char *p = &dump[0]; 366 if (size > 16) { 367 size = 16; 368 } 369 while (size-- > 0) { 370 p += sprintf(p, " %02x", *buf++); 371 } 372 return dump; 373 } 374 #endif /* DEBUG_EEPRO100 */ 375 376 enum scb_stat_ack { 377 stat_ack_not_ours = 0x00, 378 stat_ack_sw_gen = 0x04, 379 stat_ack_rnr = 0x10, 380 stat_ack_cu_idle = 0x20, 381 stat_ack_frame_rx = 0x40, 382 stat_ack_cu_cmd_done = 0x80, 383 stat_ack_not_present = 0xFF, 384 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), 385 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), 386 }; 387 388 static void disable_interrupt(EEPRO100State * s) 389 { 390 if (s->int_stat) { 391 TRACE(INT, logout("interrupt disabled\n")); 392 pci_irq_deassert(&s->dev); 393 s->int_stat = 0; 394 } 395 } 396 397 static void enable_interrupt(EEPRO100State * s) 398 { 399 if (!s->int_stat) { 400 TRACE(INT, logout("interrupt enabled\n")); 401 pci_irq_assert(&s->dev); 402 s->int_stat = 1; 403 } 404 } 405 406 static void eepro100_acknowledge(EEPRO100State * s) 407 { 408 s->scb_stat &= ~s->mem[SCBAck]; 409 s->mem[SCBAck] = s->scb_stat; 410 if (s->scb_stat == 0) { 411 disable_interrupt(s); 412 } 413 } 414 415 static void eepro100_interrupt(EEPRO100State * s, uint8_t status) 416 { 417 uint8_t mask = ~s->mem[SCBIntmask]; 418 s->mem[SCBAck] |= status; 419 status = s->scb_stat = s->mem[SCBAck]; 420 status &= (mask | 0x0f); 421 #if 0 422 status &= (~s->mem[SCBIntmask] | 0x0xf); 423 #endif 424 if (status && (mask & 0x01)) { 425 /* SCB mask and SCB Bit M do not disable interrupt. */ 426 enable_interrupt(s); 427 } else if (s->int_stat) { 428 disable_interrupt(s); 429 } 430 } 431 432 static void eepro100_cx_interrupt(EEPRO100State * s) 433 { 434 /* CU completed action command. */ 435 /* Transmit not ok (82557 only, not in emulation). */ 436 eepro100_interrupt(s, 0x80); 437 } 438 439 static void eepro100_cna_interrupt(EEPRO100State * s) 440 { 441 /* CU left the active state. */ 442 eepro100_interrupt(s, 0x20); 443 } 444 445 static void eepro100_fr_interrupt(EEPRO100State * s) 446 { 447 /* RU received a complete frame. */ 448 eepro100_interrupt(s, 0x40); 449 } 450 451 static void eepro100_rnr_interrupt(EEPRO100State * s) 452 { 453 /* RU is not ready. */ 454 eepro100_interrupt(s, 0x10); 455 } 456 457 static void eepro100_mdi_interrupt(EEPRO100State * s) 458 { 459 /* MDI completed read or write cycle. */ 460 eepro100_interrupt(s, 0x08); 461 } 462 463 static void eepro100_swi_interrupt(EEPRO100State * s) 464 { 465 /* Software has requested an interrupt. */ 466 eepro100_interrupt(s, 0x04); 467 } 468 469 #if 0 470 static void eepro100_fcp_interrupt(EEPRO100State * s) 471 { 472 /* Flow control pause interrupt (82558 and later). */ 473 eepro100_interrupt(s, 0x01); 474 } 475 #endif 476 477 static void e100_pci_reset(EEPRO100State *s, Error **errp) 478 { 479 E100PCIDeviceInfo *info = eepro100_get_class(s); 480 uint32_t device = s->device; 481 uint8_t *pci_conf = s->dev.config; 482 483 TRACE(OTHER, logout("%p\n", s)); 484 485 /* PCI Status */ 486 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | 487 PCI_STATUS_FAST_BACK); 488 /* PCI Latency Timer */ 489 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ 490 /* Capability Pointer is set by PCI framework. */ 491 /* Interrupt Line */ 492 /* Interrupt Pin */ 493 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */ 494 /* Minimum Grant */ 495 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08); 496 /* Maximum Latency */ 497 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18); 498 499 s->stats_size = info->stats_size; 500 s->has_extended_tcb_support = info->has_extended_tcb_support; 501 502 switch (device) { 503 case i82550: 504 case i82551: 505 case i82557A: 506 case i82557B: 507 case i82557C: 508 case i82558A: 509 case i82558B: 510 case i82559A: 511 case i82559B: 512 case i82559ER: 513 case i82562: 514 case i82801: 515 case i82559C: 516 break; 517 default: 518 logout("Device %X is undefined!\n", device); 519 } 520 521 /* Standard TxCB. */ 522 s->configuration[6] |= BIT(4); 523 524 /* Standard statistical counters. */ 525 s->configuration[6] |= BIT(5); 526 527 if (s->stats_size == 80) { 528 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */ 529 if (s->configuration[6] & BIT(2)) { 530 /* TCO statistical counters. */ 531 assert(s->configuration[6] & BIT(5)); 532 } else { 533 if (s->configuration[6] & BIT(5)) { 534 /* No extended statistical counters, i82557 compatible. */ 535 s->stats_size = 64; 536 } else { 537 /* i82558 compatible. */ 538 s->stats_size = 76; 539 } 540 } 541 } else { 542 if (s->configuration[6] & BIT(5)) { 543 /* No extended statistical counters. */ 544 s->stats_size = 64; 545 } 546 } 547 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics)); 548 549 if (info->power_management) { 550 /* Power Management Capabilities */ 551 int cfg_offset = 0xdc; 552 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM, 553 cfg_offset, PCI_PM_SIZEOF, 554 errp); 555 if (r < 0) { 556 return; 557 } 558 559 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); 560 #if 0 /* TODO: replace dummy code for power management emulation. */ 561 /* TODO: Power Management Control / Status. */ 562 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000); 563 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */ 564 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000); 565 #endif 566 } 567 568 #if EEPROM_SIZE > 0 569 if (device == i82557C || device == i82558B || device == i82559C) { 570 /* 571 TODO: get vendor id from EEPROM for i82557C or later. 572 TODO: get device id from EEPROM for i82557C or later. 573 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559. 574 TODO: header type is determined by EEPROM for i82559. 575 TODO: get subsystem id from EEPROM for i82557C or later. 576 TODO: get subsystem vendor id from EEPROM for i82557C or later. 577 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later. 578 TODO: capability pointer depends on EEPROM for i82558. 579 */ 580 logout("Get device id and revision from EEPROM!!!\n"); 581 } 582 #endif /* EEPROM_SIZE > 0 */ 583 } 584 585 static void nic_selective_reset(EEPRO100State * s) 586 { 587 size_t i; 588 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); 589 #if 0 590 eeprom93xx_reset(s->eeprom); 591 #endif 592 memcpy(eeprom_contents, s->conf.macaddr.a, 6); 593 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID; 594 if (s->device == i82557B || s->device == i82557C) 595 eeprom_contents[5] = 0x0100; 596 eeprom_contents[EEPROM_PHY_ID] = 1; 597 uint16_t sum = 0; 598 for (i = 0; i < EEPROM_SIZE - 1; i++) { 599 sum += eeprom_contents[i]; 600 } 601 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; 602 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1])); 603 604 memset(s->mem, 0, sizeof(s->mem)); 605 e100_write_reg4(s, SCBCtrlMDI, BIT(21)); 606 607 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); 608 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); 609 } 610 611 static void nic_reset(void *opaque) 612 { 613 EEPRO100State *s = opaque; 614 TRACE(OTHER, logout("%p\n", s)); 615 /* TODO: Clearing of hash register for selective reset, too? */ 616 memset(&s->mult[0], 0, sizeof(s->mult)); 617 nic_selective_reset(s); 618 } 619 620 #if defined(DEBUG_EEPRO100) 621 static const char * const e100_reg[PCI_IO_SIZE / 4] = { 622 "Command/Status", 623 "General Pointer", 624 "Port", 625 "EEPROM/Flash Control", 626 "MDI Control", 627 "Receive DMA Byte Count", 628 "Flow Control", 629 "General Status/Control" 630 }; 631 632 static char *regname(uint32_t addr) 633 { 634 static char buf[32]; 635 if (addr < PCI_IO_SIZE) { 636 const char *r = e100_reg[addr / 4]; 637 if (r != 0) { 638 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4); 639 } else { 640 snprintf(buf, sizeof(buf), "0x%02x", addr); 641 } 642 } else { 643 snprintf(buf, sizeof(buf), "??? 0x%08x", addr); 644 } 645 return buf; 646 } 647 #endif /* DEBUG_EEPRO100 */ 648 649 /***************************************************************************** 650 * 651 * Command emulation. 652 * 653 ****************************************************************************/ 654 655 #if 0 656 static uint16_t eepro100_read_command(EEPRO100State * s) 657 { 658 uint16_t val = 0xffff; 659 TRACE(OTHER, logout("val=0x%04x\n", val)); 660 return val; 661 } 662 #endif 663 664 /* Commands that can be put in a command list entry. */ 665 enum commands { 666 CmdNOp = 0, 667 CmdIASetup = 1, 668 CmdConfigure = 2, 669 CmdMulticastList = 3, 670 CmdTx = 4, 671 CmdTDR = 5, /* load microcode */ 672 CmdDump = 6, 673 CmdDiagnose = 7, 674 675 /* And some extra flags: */ 676 CmdSuspend = 0x4000, /* Suspend after completion. */ 677 CmdIntr = 0x2000, /* Interrupt after completion. */ 678 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ 679 }; 680 681 static cu_state_t get_cu_state(EEPRO100State * s) 682 { 683 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6); 684 } 685 686 static void set_cu_state(EEPRO100State * s, cu_state_t state) 687 { 688 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6); 689 } 690 691 static ru_state_t get_ru_state(EEPRO100State * s) 692 { 693 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2); 694 } 695 696 static void set_ru_state(EEPRO100State * s, ru_state_t state) 697 { 698 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2); 699 } 700 701 static void dump_statistics(EEPRO100State * s) 702 { 703 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 704 705 /* Dump statistical data. Most data is never changed by the emulation 706 * and always 0, so we first just copy the whole block and then those 707 * values which really matter. 708 * Number of data should check configuration!!! 709 */ 710 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size); 711 stl_le_pci_dma(&s->dev, s->statsaddr + 0, 712 s->statistics.tx_good_frames, attrs); 713 stl_le_pci_dma(&s->dev, s->statsaddr + 36, 714 s->statistics.rx_good_frames, attrs); 715 stl_le_pci_dma(&s->dev, s->statsaddr + 48, 716 s->statistics.rx_resource_errors, attrs); 717 stl_le_pci_dma(&s->dev, s->statsaddr + 60, 718 s->statistics.rx_short_frame_errors, attrs); 719 #if 0 720 stw_le_pci_dma(&s->dev, s->statsaddr + 76, 721 s->statistics.xmt_tco_frames, attrs); 722 stw_le_pci_dma(&s->dev, s->statsaddr + 78, 723 s->statistics.rcv_tco_frames, attrs); 724 missing("CU dump statistical counters"); 725 #endif 726 } 727 728 static void read_cb(EEPRO100State *s) 729 { 730 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx)); 731 s->tx.status = le16_to_cpu(s->tx.status); 732 s->tx.command = le16_to_cpu(s->tx.command); 733 s->tx.link = le32_to_cpu(s->tx.link); 734 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr); 735 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes); 736 } 737 738 static void tx_command(EEPRO100State *s) 739 { 740 uint32_t tbd_array = s->tx.tbd_array_addr; 741 uint16_t tcb_bytes = s->tx.tcb_bytes & 0x3fff; 742 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */ 743 uint8_t buf[2600]; 744 uint16_t size = 0; 745 uint32_t tbd_address = s->cb_address + 0x10; 746 TRACE(RXTX, logout 747 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n", 748 tbd_array, tcb_bytes, s->tx.tbd_count)); 749 750 if (tcb_bytes > 2600) { 751 logout("TCB byte count too large, using 2600\n"); 752 tcb_bytes = 2600; 753 } 754 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { 755 logout 756 ("illegal values of TBD array address and TCB byte count!\n"); 757 } 758 assert(tcb_bytes <= sizeof(buf)); 759 while (size < tcb_bytes) { 760 TRACE(RXTX, logout 761 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n", 762 tbd_address, tcb_bytes)); 763 pci_dma_read(&s->dev, tbd_address, &buf[size], tcb_bytes); 764 size += tcb_bytes; 765 } 766 if (tbd_array == 0xffffffff) { 767 /* Simplified mode. Was already handled by code above. */ 768 } else { 769 /* Flexible mode. */ 770 uint8_t tbd_count = 0; 771 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) { 772 /* Extended Flexible TCB. */ 773 for (; tbd_count < 2; tbd_count++) { 774 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, 775 tbd_address); 776 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, 777 tbd_address + 4); 778 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, 779 tbd_address + 6); 780 tbd_address += 8; 781 TRACE(RXTX, logout 782 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n", 783 tx_buffer_address, tx_buffer_size)); 784 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); 785 pci_dma_read(&s->dev, tx_buffer_address, 786 &buf[size], tx_buffer_size); 787 size += tx_buffer_size; 788 if (tx_buffer_el & 1) { 789 break; 790 } 791 } 792 } 793 tbd_address = tbd_array; 794 for (; tbd_count < s->tx.tbd_count; tbd_count++) { 795 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address); 796 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4); 797 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6); 798 tbd_address += 8; 799 TRACE(RXTX, logout 800 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n", 801 tx_buffer_address, tx_buffer_size)); 802 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size); 803 pci_dma_read(&s->dev, tx_buffer_address, 804 &buf[size], tx_buffer_size); 805 size += tx_buffer_size; 806 if (tx_buffer_el & 1) { 807 break; 808 } 809 } 810 } 811 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size))); 812 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 813 s->statistics.tx_good_frames++; 814 /* Transmit with bad status would raise an CX/TNO interrupt. 815 * (82557 only). Emulation never has bad status. */ 816 #if 0 817 eepro100_cx_interrupt(s); 818 #endif 819 } 820 821 static void set_multicast_list(EEPRO100State *s) 822 { 823 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0); 824 uint16_t i; 825 memset(&s->mult[0], 0, sizeof(s->mult)); 826 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count)); 827 for (i = 0; i < multicast_count; i += 6) { 828 uint8_t multicast_addr[6]; 829 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6); 830 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6))); 831 unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) & 832 BITS(7, 2)) >> 2; 833 assert(mcast_idx < 64); 834 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7)); 835 } 836 } 837 838 static void action_command(EEPRO100State *s) 839 { 840 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 841 /* The loop below won't stop if it gets special handcrafted data. 842 Therefore we limit the number of iterations. */ 843 unsigned max_loop_count = 16; 844 845 for (;;) { 846 bool bit_el; 847 bool bit_s; 848 bool bit_i; 849 bool bit_nc; 850 uint16_t ok_status = STATUS_OK; 851 s->cb_address = s->cu_base + s->cu_offset; 852 read_cb(s); 853 bit_el = ((s->tx.command & COMMAND_EL) != 0); 854 bit_s = ((s->tx.command & COMMAND_S) != 0); 855 bit_i = ((s->tx.command & COMMAND_I) != 0); 856 bit_nc = ((s->tx.command & COMMAND_NC) != 0); 857 #if 0 858 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0); 859 #endif 860 861 if (max_loop_count-- == 0) { 862 /* Prevent an endless loop. */ 863 logout("loop in %s:%u\n", __FILE__, __LINE__); 864 break; 865 } 866 867 s->cu_offset = s->tx.link; 868 TRACE(OTHER, 869 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n", 870 s->tx.status, s->tx.command, s->tx.link)); 871 switch (s->tx.command & COMMAND_CMD) { 872 case CmdNOp: 873 /* Do nothing. */ 874 break; 875 case CmdIASetup: 876 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6); 877 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6))); 878 break; 879 case CmdConfigure: 880 pci_dma_read(&s->dev, s->cb_address + 8, 881 &s->configuration[0], sizeof(s->configuration)); 882 TRACE(OTHER, logout("configuration: %s\n", 883 nic_dump(&s->configuration[0], 16))); 884 TRACE(OTHER, logout("configuration: %s\n", 885 nic_dump(&s->configuration[16], 886 ARRAY_SIZE(s->configuration) - 16))); 887 if (s->configuration[20] & BIT(6)) { 888 TRACE(OTHER, logout("Multiple IA bit\n")); 889 } 890 break; 891 case CmdMulticastList: 892 set_multicast_list(s); 893 break; 894 case CmdTx: 895 if (bit_nc) { 896 missing("CmdTx: NC = 0"); 897 ok_status = 0; 898 break; 899 } 900 tx_command(s); 901 break; 902 case CmdTDR: 903 TRACE(OTHER, logout("load microcode\n")); 904 /* Starting with offset 8, the command contains 905 * 64 dwords microcode which we just ignore here. */ 906 break; 907 case CmdDiagnose: 908 TRACE(OTHER, logout("diagnose\n")); 909 /* Make sure error flag is not set. */ 910 s->tx.status = 0; 911 break; 912 default: 913 missing("undefined command"); 914 ok_status = 0; 915 break; 916 } 917 /* Write new status. */ 918 stw_le_pci_dma(&s->dev, s->cb_address, 919 s->tx.status | ok_status | STATUS_C, attrs); 920 if (bit_i) { 921 /* CU completed action. */ 922 eepro100_cx_interrupt(s); 923 } 924 if (bit_el) { 925 /* CU becomes idle. Terminate command loop. */ 926 set_cu_state(s, cu_idle); 927 eepro100_cna_interrupt(s); 928 break; 929 } else if (bit_s) { 930 /* CU becomes suspended. Terminate command loop. */ 931 set_cu_state(s, cu_suspended); 932 eepro100_cna_interrupt(s); 933 break; 934 } else { 935 /* More entries in list. */ 936 TRACE(OTHER, logout("CU list with at least one more entry\n")); 937 } 938 } 939 TRACE(OTHER, logout("CU list empty\n")); 940 /* List is empty. Now CU is idle or suspended. */ 941 } 942 943 static void eepro100_cu_command(EEPRO100State * s, uint8_t val) 944 { 945 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 946 cu_state_t cu_state; 947 switch (val) { 948 case CU_NOP: 949 /* No operation. */ 950 break; 951 case CU_START: 952 cu_state = get_cu_state(s); 953 if (cu_state != cu_idle && cu_state != cu_suspended) { 954 /* Intel documentation says that CU must be idle or suspended 955 * for the CU start command. */ 956 logout("unexpected CU state is %u\n", cu_state); 957 } 958 set_cu_state(s, cu_active); 959 s->cu_offset = e100_read_reg4(s, SCBPointer); 960 action_command(s); 961 break; 962 case CU_RESUME: 963 if (get_cu_state(s) != cu_suspended) { 964 logout("bad CU resume from CU state %u\n", get_cu_state(s)); 965 /* Workaround for bad Linux eepro100 driver which resumes 966 * from idle state. */ 967 #if 0 968 missing("cu resume"); 969 #endif 970 set_cu_state(s, cu_suspended); 971 } 972 if (get_cu_state(s) == cu_suspended) { 973 TRACE(OTHER, logout("CU resuming\n")); 974 set_cu_state(s, cu_active); 975 action_command(s); 976 } 977 break; 978 case CU_STATSADDR: 979 /* Load dump counters address. */ 980 s->statsaddr = e100_read_reg4(s, SCBPointer); 981 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val)); 982 if (s->statsaddr & 3) { 983 /* Memory must be Dword aligned. */ 984 logout("unaligned dump counters address\n"); 985 /* Handling of misaligned addresses is undefined. 986 * Here we align the address by ignoring the lower bits. */ 987 /* TODO: Test unaligned dump counter address on real hardware. */ 988 s->statsaddr &= ~3; 989 } 990 break; 991 case CU_SHOWSTATS: 992 /* Dump statistical counters. */ 993 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val)); 994 dump_statistics(s); 995 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005, attrs); 996 break; 997 case CU_CMD_BASE: 998 /* Load CU base. */ 999 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val)); 1000 s->cu_base = e100_read_reg4(s, SCBPointer); 1001 break; 1002 case CU_DUMPSTATS: 1003 /* Dump and reset statistical counters. */ 1004 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val)); 1005 dump_statistics(s); 1006 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007, attrs); 1007 memset(&s->statistics, 0, sizeof(s->statistics)); 1008 break; 1009 case CU_SRESUME: 1010 /* CU static resume. */ 1011 missing("CU static resume"); 1012 break; 1013 default: 1014 missing("Undefined CU command"); 1015 } 1016 } 1017 1018 static void eepro100_ru_command(EEPRO100State * s, uint8_t val) 1019 { 1020 switch (val) { 1021 case RU_NOP: 1022 /* No operation. */ 1023 break; 1024 case RX_START: 1025 /* RU start. */ 1026 if (get_ru_state(s) != ru_idle) { 1027 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle); 1028 #if 0 1029 assert(!"wrong RU state"); 1030 #endif 1031 } 1032 set_ru_state(s, ru_ready); 1033 s->ru_offset = e100_read_reg4(s, SCBPointer); 1034 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1035 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val)); 1036 break; 1037 case RX_RESUME: 1038 /* Restart RU. */ 1039 if (get_ru_state(s) != ru_suspended) { 1040 logout("RU state is %u, should be %u\n", get_ru_state(s), 1041 ru_suspended); 1042 #if 0 1043 assert(!"wrong RU state"); 1044 #endif 1045 } 1046 set_ru_state(s, ru_ready); 1047 break; 1048 case RU_ABORT: 1049 /* RU abort. */ 1050 if (get_ru_state(s) == ru_ready) { 1051 eepro100_rnr_interrupt(s); 1052 } 1053 set_ru_state(s, ru_idle); 1054 break; 1055 case RX_ADDR_LOAD: 1056 /* Load RU base. */ 1057 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val)); 1058 s->ru_base = e100_read_reg4(s, SCBPointer); 1059 break; 1060 default: 1061 logout("val=0x%02x (undefined RU command)\n", val); 1062 missing("Undefined SU command"); 1063 } 1064 } 1065 1066 static void eepro100_write_command(EEPRO100State * s, uint8_t val) 1067 { 1068 eepro100_ru_command(s, val & 0x0f); 1069 eepro100_cu_command(s, val & 0xf0); 1070 if ((val) == 0) { 1071 TRACE(OTHER, logout("val=0x%02x\n", val)); 1072 } 1073 /* Clear command byte after command was accepted. */ 1074 s->mem[SCBCmd] = 0; 1075 } 1076 1077 /***************************************************************************** 1078 * 1079 * EEPROM emulation. 1080 * 1081 ****************************************************************************/ 1082 1083 #define EEPROM_CS 0x02 1084 #define EEPROM_SK 0x01 1085 #define EEPROM_DI 0x04 1086 #define EEPROM_DO 0x08 1087 1088 static uint16_t eepro100_read_eeprom(EEPRO100State * s) 1089 { 1090 uint16_t val = e100_read_reg2(s, SCBeeprom); 1091 if (eeprom93xx_read(s->eeprom)) { 1092 val |= EEPROM_DO; 1093 } else { 1094 val &= ~EEPROM_DO; 1095 } 1096 TRACE(EEPROM, logout("val=0x%04x\n", val)); 1097 return val; 1098 } 1099 1100 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) 1101 { 1102 TRACE(EEPROM, logout("val=0x%02x\n", val)); 1103 1104 /* mask unwritable bits */ 1105 #if 0 1106 val = SET_MASKED(val, 0x31, eeprom->value); 1107 #endif 1108 1109 int eecs = ((val & EEPROM_CS) != 0); 1110 int eesk = ((val & EEPROM_SK) != 0); 1111 int eedi = ((val & EEPROM_DI) != 0); 1112 eeprom93xx_write(eeprom, eecs, eesk, eedi); 1113 } 1114 1115 /***************************************************************************** 1116 * 1117 * MDI emulation. 1118 * 1119 ****************************************************************************/ 1120 1121 #if defined(DEBUG_EEPRO100) 1122 static const char * const mdi_op_name[] = { 1123 "opcode 0", 1124 "write", 1125 "read", 1126 "opcode 3" 1127 }; 1128 1129 static const char * const mdi_reg_name[] = { 1130 "Control", 1131 "Status", 1132 "PHY Identification (Word 1)", 1133 "PHY Identification (Word 2)", 1134 "Auto-Negotiation Advertisement", 1135 "Auto-Negotiation Link Partner Ability", 1136 "Auto-Negotiation Expansion" 1137 }; 1138 1139 static const char *reg2name(uint8_t reg) 1140 { 1141 static char buffer[10]; 1142 const char *p = buffer; 1143 if (reg < ARRAY_SIZE(mdi_reg_name)) { 1144 p = mdi_reg_name[reg]; 1145 } else { 1146 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg); 1147 } 1148 return p; 1149 } 1150 #endif /* DEBUG_EEPRO100 */ 1151 1152 static uint32_t eepro100_read_mdi(EEPRO100State * s) 1153 { 1154 uint32_t val = e100_read_reg4(s, SCBCtrlMDI); 1155 1156 #ifdef DEBUG_EEPRO100 1157 uint8_t raiseint = (val & BIT(29)) >> 29; 1158 uint8_t opcode = (val & BITS(27, 26)) >> 26; 1159 uint8_t phy = (val & BITS(25, 21)) >> 21; 1160 uint8_t reg = (val & BITS(20, 16)) >> 16; 1161 uint16_t data = (val & BITS(15, 0)); 1162 #endif 1163 /* Emulation takes no time to finish MDI transaction. */ 1164 val |= BIT(28); 1165 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", 1166 val, raiseint, mdi_op_name[opcode], phy, 1167 reg2name(reg), data)); 1168 return val; 1169 } 1170 1171 static void eepro100_write_mdi(EEPRO100State *s) 1172 { 1173 uint32_t val = e100_read_reg4(s, SCBCtrlMDI); 1174 uint8_t raiseint = (val & BIT(29)) >> 29; 1175 uint8_t opcode = (val & BITS(27, 26)) >> 26; 1176 uint8_t phy = (val & BITS(25, 21)) >> 21; 1177 uint8_t reg = (val & BITS(20, 16)) >> 16; 1178 uint16_t data = (val & BITS(15, 0)); 1179 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", 1180 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data)); 1181 if (phy != 1) { 1182 /* Unsupported PHY address. */ 1183 #if 0 1184 logout("phy must be 1 but is %u\n", phy); 1185 #endif 1186 data = 0; 1187 } else if (opcode != 1 && opcode != 2) { 1188 /* Unsupported opcode. */ 1189 logout("opcode must be 1 or 2 but is %u\n", opcode); 1190 data = 0; 1191 } else if (reg > 6) { 1192 /* Unsupported register. */ 1193 logout("register must be 0...6 but is %u\n", reg); 1194 data = 0; 1195 } else { 1196 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n", 1197 val, raiseint, mdi_op_name[opcode], phy, 1198 reg2name(reg), data)); 1199 if (opcode == 1) { 1200 /* MDI write */ 1201 switch (reg) { 1202 case 0: /* Control Register */ 1203 if (data & 0x8000) { 1204 /* Reset status and control registers to default. */ 1205 s->mdimem[0] = eepro100_mdi_default[0]; 1206 s->mdimem[1] = eepro100_mdi_default[1]; 1207 data = s->mdimem[reg]; 1208 } else { 1209 /* Restart Auto Configuration = Normal Operation */ 1210 data &= ~0x0200; 1211 } 1212 break; 1213 case 1: /* Status Register */ 1214 missing("not writable"); 1215 break; 1216 case 2: /* PHY Identification Register (Word 1) */ 1217 case 3: /* PHY Identification Register (Word 2) */ 1218 missing("not implemented"); 1219 break; 1220 case 4: /* Auto-Negotiation Advertisement Register */ 1221 case 5: /* Auto-Negotiation Link Partner Ability Register */ 1222 break; 1223 case 6: /* Auto-Negotiation Expansion Register */ 1224 default: 1225 missing("not implemented"); 1226 } 1227 s->mdimem[reg] &= eepro100_mdi_mask[reg]; 1228 s->mdimem[reg] |= data & ~eepro100_mdi_mask[reg]; 1229 } else if (opcode == 2) { 1230 /* MDI read */ 1231 switch (reg) { 1232 case 0: /* Control Register */ 1233 if (data & 0x8000) { 1234 /* Reset status and control registers to default. */ 1235 s->mdimem[0] = eepro100_mdi_default[0]; 1236 s->mdimem[1] = eepro100_mdi_default[1]; 1237 } 1238 break; 1239 case 1: /* Status Register */ 1240 s->mdimem[reg] |= 0x0020; 1241 break; 1242 case 2: /* PHY Identification Register (Word 1) */ 1243 case 3: /* PHY Identification Register (Word 2) */ 1244 case 4: /* Auto-Negotiation Advertisement Register */ 1245 break; 1246 case 5: /* Auto-Negotiation Link Partner Ability Register */ 1247 s->mdimem[reg] = 0x41fe; 1248 break; 1249 case 6: /* Auto-Negotiation Expansion Register */ 1250 s->mdimem[reg] = 0x0001; 1251 break; 1252 } 1253 data = s->mdimem[reg]; 1254 } 1255 /* Emulation takes no time to finish MDI transaction. 1256 * Set MDI bit in SCB status register. */ 1257 s->mem[SCBAck] |= 0x08; 1258 val |= BIT(28); 1259 if (raiseint) { 1260 eepro100_mdi_interrupt(s); 1261 } 1262 } 1263 val = (val & 0xffff0000) + data; 1264 e100_write_reg4(s, SCBCtrlMDI, val); 1265 } 1266 1267 /***************************************************************************** 1268 * 1269 * Port emulation. 1270 * 1271 ****************************************************************************/ 1272 1273 #define PORT_SOFTWARE_RESET 0 1274 #define PORT_SELFTEST 1 1275 #define PORT_SELECTIVE_RESET 2 1276 #define PORT_DUMP 3 1277 #define PORT_SELECTION_MASK 3 1278 1279 typedef struct { 1280 uint32_t st_sign; /* Self Test Signature */ 1281 uint32_t st_result; /* Self Test Results */ 1282 } eepro100_selftest_t; 1283 1284 static uint32_t eepro100_read_port(EEPRO100State * s) 1285 { 1286 return 0; 1287 } 1288 1289 static void eepro100_write_port(EEPRO100State *s) 1290 { 1291 uint32_t val = e100_read_reg4(s, SCBPort); 1292 uint32_t address = (val & ~PORT_SELECTION_MASK); 1293 uint8_t selection = (val & PORT_SELECTION_MASK); 1294 switch (selection) { 1295 case PORT_SOFTWARE_RESET: 1296 nic_reset(s); 1297 break; 1298 case PORT_SELFTEST: 1299 TRACE(OTHER, logout("selftest address=0x%08x\n", address)); 1300 eepro100_selftest_t data; 1301 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data)); 1302 data.st_sign = 0xffffffff; 1303 data.st_result = 0; 1304 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data)); 1305 break; 1306 case PORT_SELECTIVE_RESET: 1307 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address)); 1308 nic_selective_reset(s); 1309 break; 1310 default: 1311 logout("val=0x%08x\n", val); 1312 missing("unknown port selection"); 1313 } 1314 } 1315 1316 /***************************************************************************** 1317 * 1318 * General hardware emulation. 1319 * 1320 ****************************************************************************/ 1321 1322 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr) 1323 { 1324 uint8_t val = 0; 1325 if (addr <= sizeof(s->mem) - sizeof(val)) { 1326 val = s->mem[addr]; 1327 } 1328 1329 switch (addr) { 1330 case SCBStatus: 1331 case SCBAck: 1332 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1333 break; 1334 case SCBCmd: 1335 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1336 #if 0 1337 val = eepro100_read_command(s); 1338 #endif 1339 break; 1340 case SCBIntmask: 1341 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1342 break; 1343 case SCBPort + 3: 1344 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1345 break; 1346 case SCBeeprom: 1347 val = eepro100_read_eeprom(s); 1348 break; 1349 case SCBCtrlMDI: 1350 case SCBCtrlMDI + 1: 1351 case SCBCtrlMDI + 2: 1352 case SCBCtrlMDI + 3: 1353 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); 1354 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1355 break; 1356 case SCBpmdr: /* Power Management Driver Register */ 1357 val = 0; 1358 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1359 break; 1360 case SCBgctrl: /* General Control Register */ 1361 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1362 break; 1363 case SCBgstat: /* General Status Register */ 1364 /* 100 Mbps full duplex, valid link */ 1365 val = 0x07; 1366 TRACE(OTHER, logout("addr=General Status val=%02x\n", val)); 1367 break; 1368 default: 1369 logout("addr=%s val=0x%02x\n", regname(addr), val); 1370 missing("unknown byte read"); 1371 } 1372 return val; 1373 } 1374 1375 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr) 1376 { 1377 uint16_t val = 0; 1378 if (addr <= sizeof(s->mem) - sizeof(val)) { 1379 val = e100_read_reg2(s, addr); 1380 } 1381 1382 switch (addr) { 1383 case SCBStatus: 1384 case SCBCmd: 1385 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1386 break; 1387 case SCBeeprom: 1388 val = eepro100_read_eeprom(s); 1389 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1390 break; 1391 case SCBCtrlMDI: 1392 case SCBCtrlMDI + 2: 1393 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3))); 1394 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1395 break; 1396 default: 1397 logout("addr=%s val=0x%04x\n", regname(addr), val); 1398 missing("unknown word read"); 1399 } 1400 return val; 1401 } 1402 1403 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr) 1404 { 1405 uint32_t val = 0; 1406 if (addr <= sizeof(s->mem) - sizeof(val)) { 1407 val = e100_read_reg4(s, addr); 1408 } 1409 1410 switch (addr) { 1411 case SCBStatus: 1412 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1413 break; 1414 case SCBPointer: 1415 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1416 break; 1417 case SCBPort: 1418 val = eepro100_read_port(s); 1419 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1420 break; 1421 case SCBflash: 1422 val = eepro100_read_eeprom(s); 1423 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1424 break; 1425 case SCBCtrlMDI: 1426 val = eepro100_read_mdi(s); 1427 break; 1428 default: 1429 logout("addr=%s val=0x%08x\n", regname(addr), val); 1430 missing("unknown longword read"); 1431 } 1432 return val; 1433 } 1434 1435 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) 1436 { 1437 /* SCBStatus is readonly. */ 1438 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { 1439 s->mem[addr] = val; 1440 } 1441 1442 switch (addr) { 1443 case SCBStatus: 1444 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1445 break; 1446 case SCBAck: 1447 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1448 eepro100_acknowledge(s); 1449 break; 1450 case SCBCmd: 1451 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1452 eepro100_write_command(s, val); 1453 break; 1454 case SCBIntmask: 1455 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1456 if (val & BIT(1)) { 1457 eepro100_swi_interrupt(s); 1458 } 1459 eepro100_interrupt(s, 0); 1460 break; 1461 case SCBPointer: 1462 case SCBPointer + 1: 1463 case SCBPointer + 2: 1464 case SCBPointer + 3: 1465 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1466 break; 1467 case SCBPort: 1468 case SCBPort + 1: 1469 case SCBPort + 2: 1470 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1471 break; 1472 case SCBPort + 3: 1473 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1474 eepro100_write_port(s); 1475 break; 1476 case SCBFlow: /* does not exist on 82557 */ 1477 case SCBFlow + 1: 1478 case SCBFlow + 2: 1479 case SCBpmdr: /* does not exist on 82557 */ 1480 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1481 break; 1482 case SCBeeprom: 1483 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1484 eepro100_write_eeprom(s->eeprom, val); 1485 break; 1486 case SCBCtrlMDI: 1487 case SCBCtrlMDI + 1: 1488 case SCBCtrlMDI + 2: 1489 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1490 break; 1491 case SCBCtrlMDI + 3: 1492 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val)); 1493 eepro100_write_mdi(s); 1494 break; 1495 default: 1496 logout("addr=%s val=0x%02x\n", regname(addr), val); 1497 missing("unknown byte write"); 1498 } 1499 } 1500 1501 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) 1502 { 1503 /* SCBStatus is readonly. */ 1504 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) { 1505 e100_write_reg2(s, addr, val); 1506 } 1507 1508 switch (addr) { 1509 case SCBStatus: 1510 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1511 s->mem[SCBAck] = (val >> 8); 1512 eepro100_acknowledge(s); 1513 break; 1514 case SCBCmd: 1515 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1516 eepro100_write_command(s, val); 1517 eepro100_write1(s, SCBIntmask, val >> 8); 1518 break; 1519 case SCBPointer: 1520 case SCBPointer + 2: 1521 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1522 break; 1523 case SCBPort: 1524 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1525 break; 1526 case SCBPort + 2: 1527 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1528 eepro100_write_port(s); 1529 break; 1530 case SCBeeprom: 1531 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1532 eepro100_write_eeprom(s->eeprom, val); 1533 break; 1534 case SCBCtrlMDI: 1535 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1536 break; 1537 case SCBCtrlMDI + 2: 1538 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val)); 1539 eepro100_write_mdi(s); 1540 break; 1541 default: 1542 logout("addr=%s val=0x%04x\n", regname(addr), val); 1543 missing("unknown word write"); 1544 } 1545 } 1546 1547 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) 1548 { 1549 if (addr <= sizeof(s->mem) - sizeof(val)) { 1550 e100_write_reg4(s, addr, val); 1551 } 1552 1553 switch (addr) { 1554 case SCBPointer: 1555 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1556 break; 1557 case SCBPort: 1558 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1559 eepro100_write_port(s); 1560 break; 1561 case SCBflash: 1562 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1563 val = val >> 16; 1564 eepro100_write_eeprom(s->eeprom, val); 1565 break; 1566 case SCBCtrlMDI: 1567 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val)); 1568 eepro100_write_mdi(s); 1569 break; 1570 default: 1571 logout("addr=%s val=0x%08x\n", regname(addr), val); 1572 missing("unknown longword write"); 1573 } 1574 } 1575 1576 static uint64_t eepro100_read(void *opaque, hwaddr addr, 1577 unsigned size) 1578 { 1579 EEPRO100State *s = opaque; 1580 1581 switch (size) { 1582 case 1: return eepro100_read1(s, addr); 1583 case 2: return eepro100_read2(s, addr); 1584 case 4: return eepro100_read4(s, addr); 1585 default: abort(); 1586 } 1587 } 1588 1589 static void eepro100_write(void *opaque, hwaddr addr, 1590 uint64_t data, unsigned size) 1591 { 1592 EEPRO100State *s = opaque; 1593 1594 switch (size) { 1595 case 1: 1596 eepro100_write1(s, addr, data); 1597 break; 1598 case 2: 1599 eepro100_write2(s, addr, data); 1600 break; 1601 case 4: 1602 eepro100_write4(s, addr, data); 1603 break; 1604 default: 1605 abort(); 1606 } 1607 } 1608 1609 static const MemoryRegionOps eepro100_ops = { 1610 .read = eepro100_read, 1611 .write = eepro100_write, 1612 .endianness = DEVICE_LITTLE_ENDIAN, 1613 }; 1614 1615 static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size) 1616 { 1617 /* TODO: 1618 * - Magic packets should set bit 30 in power management driver register. 1619 * - Interesting packets should set bit 29 in power management driver register. 1620 */ 1621 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 1622 EEPRO100State *s = qemu_get_nic_opaque(nc); 1623 uint16_t rfd_status = 0xa000; 1624 #if defined(CONFIG_PAD_RECEIVED_FRAMES) 1625 uint8_t min_buf[60]; 1626 #endif 1627 static const uint8_t broadcast_macaddr[6] = 1628 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1629 1630 #if defined(CONFIG_PAD_RECEIVED_FRAMES) 1631 /* Pad to minimum Ethernet frame length */ 1632 if (size < sizeof(min_buf)) { 1633 memcpy(min_buf, buf, size); 1634 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1635 buf = min_buf; 1636 size = sizeof(min_buf); 1637 } 1638 #endif 1639 1640 if (s->configuration[8] & 0x80) { 1641 /* CSMA is disabled. */ 1642 logout("%p received while CSMA is disabled\n", s); 1643 return -1; 1644 #if !defined(CONFIG_PAD_RECEIVED_FRAMES) 1645 } else if (size < 64 && (s->configuration[7] & BIT(0))) { 1646 /* Short frame and configuration byte 7/0 (discard short receive) set: 1647 * Short frame is discarded */ 1648 logout("%p received short frame (%zu byte)\n", s, size); 1649 s->statistics.rx_short_frame_errors++; 1650 return -1; 1651 #endif 1652 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) { 1653 /* Long frame and configuration byte 18/3 (long receive ok) not set: 1654 * Long frames are discarded. */ 1655 logout("%p received long frame (%zu byte), ignored\n", s, size); 1656 return -1; 1657 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */ 1658 /* Frame matches individual address. */ 1659 /* TODO: check configuration byte 15/4 (ignore U/L). */ 1660 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size)); 1661 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) { 1662 /* Broadcast frame. */ 1663 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size)); 1664 rfd_status |= 0x0002; 1665 } else if (buf[0] & 0x01) { 1666 /* Multicast frame. */ 1667 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size))); 1668 if (s->configuration[21] & BIT(3)) { 1669 /* Multicast all bit is set, receive all multicast frames. */ 1670 } else { 1671 unsigned mcast_idx = (net_crc32(buf, ETH_ALEN) & BITS(7, 2)) >> 2; 1672 assert(mcast_idx < 64); 1673 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { 1674 /* Multicast frame is allowed in hash table. */ 1675 } else if (s->configuration[15] & BIT(0)) { 1676 /* Promiscuous: receive all. */ 1677 rfd_status |= 0x0004; 1678 } else { 1679 TRACE(RXTX, logout("%p multicast ignored\n", s)); 1680 return -1; 1681 } 1682 } 1683 /* TODO: Next not for promiscuous mode? */ 1684 rfd_status |= 0x0002; 1685 } else if (s->configuration[15] & BIT(0)) { 1686 /* Promiscuous: receive all. */ 1687 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size)); 1688 rfd_status |= 0x0004; 1689 } else if (s->configuration[20] & BIT(6)) { 1690 /* Multiple IA bit set. */ 1691 unsigned mcast_idx = net_crc32(buf, ETH_ALEN) >> 26; 1692 assert(mcast_idx < 64); 1693 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) { 1694 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s)); 1695 } else { 1696 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s)); 1697 return -1; 1698 } 1699 } else { 1700 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size, 1701 nic_dump(buf, size))); 1702 return size; 1703 } 1704 1705 if (get_ru_state(s) != ru_ready) { 1706 /* No resources available. */ 1707 logout("no resources, state=%u\n", get_ru_state(s)); 1708 /* TODO: RNR interrupt only at first failed frame? */ 1709 eepro100_rnr_interrupt(s); 1710 s->statistics.rx_resource_errors++; 1711 #if 0 1712 assert(!"no resources"); 1713 #endif 1714 return -1; 1715 } 1716 /* !!! */ 1717 eepro100_rx_t rx; 1718 pci_dma_read(&s->dev, s->ru_base + s->ru_offset, 1719 &rx, sizeof(eepro100_rx_t)); 1720 uint16_t rfd_command = le16_to_cpu(rx.command); 1721 uint16_t rfd_size = le16_to_cpu(rx.size); 1722 1723 if (size > rfd_size) { 1724 logout("Receive buffer (%" PRId16 " bytes) too small for data " 1725 "(%zu bytes); data truncated\n", rfd_size, size); 1726 size = rfd_size; 1727 } 1728 #if !defined(CONFIG_PAD_RECEIVED_FRAMES) 1729 if (size < 64) { 1730 rfd_status |= 0x0080; 1731 } 1732 #endif 1733 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", 1734 rfd_command, rx.link, rx.rx_buf_addr, rfd_size)); 1735 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + 1736 offsetof(eepro100_rx_t, status), rfd_status, attrs); 1737 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset + 1738 offsetof(eepro100_rx_t, count), size, attrs); 1739 /* Early receive interrupt not supported. */ 1740 #if 0 1741 eepro100_er_interrupt(s); 1742 #endif 1743 /* Receive CRC Transfer not supported. */ 1744 if (s->configuration[18] & BIT(2)) { 1745 missing("Receive CRC Transfer"); 1746 return -1; 1747 } 1748 /* TODO: check stripping enable bit. */ 1749 #if 0 1750 assert(!(s->configuration[17] & BIT(0))); 1751 #endif 1752 pci_dma_write(&s->dev, s->ru_base + s->ru_offset + 1753 sizeof(eepro100_rx_t), buf, size); 1754 s->statistics.rx_good_frames++; 1755 eepro100_fr_interrupt(s); 1756 s->ru_offset = le32_to_cpu(rx.link); 1757 if (rfd_command & COMMAND_EL) { 1758 /* EL bit is set, so this was the last frame. */ 1759 logout("receive: Running out of frames\n"); 1760 set_ru_state(s, ru_no_resources); 1761 eepro100_rnr_interrupt(s); 1762 } 1763 if (rfd_command & COMMAND_S) { 1764 /* S bit is set. */ 1765 set_ru_state(s, ru_suspended); 1766 } 1767 return size; 1768 } 1769 1770 static const VMStateDescription vmstate_eepro100 = { 1771 .version_id = 3, 1772 .minimum_version_id = 2, 1773 .fields = (VMStateField[]) { 1774 VMSTATE_PCI_DEVICE(dev, EEPRO100State), 1775 VMSTATE_UNUSED(32), 1776 VMSTATE_BUFFER(mult, EEPRO100State), 1777 VMSTATE_BUFFER(mem, EEPRO100State), 1778 /* Save all members of struct between scb_stat and mem. */ 1779 VMSTATE_UINT8(scb_stat, EEPRO100State), 1780 VMSTATE_UINT8(int_stat, EEPRO100State), 1781 VMSTATE_UNUSED(3*4), 1782 VMSTATE_MACADDR(conf.macaddr, EEPRO100State), 1783 VMSTATE_UNUSED(19*4), 1784 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32), 1785 /* The eeprom should be saved and restored by its own routines. */ 1786 VMSTATE_UINT32(device, EEPRO100State), 1787 /* TODO check device. */ 1788 VMSTATE_UINT32(cu_base, EEPRO100State), 1789 VMSTATE_UINT32(cu_offset, EEPRO100State), 1790 VMSTATE_UINT32(ru_base, EEPRO100State), 1791 VMSTATE_UINT32(ru_offset, EEPRO100State), 1792 VMSTATE_UINT32(statsaddr, EEPRO100State), 1793 /* Save eepro100_stats_t statistics. */ 1794 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State), 1795 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State), 1796 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State), 1797 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State), 1798 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State), 1799 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State), 1800 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State), 1801 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State), 1802 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State), 1803 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State), 1804 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State), 1805 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State), 1806 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State), 1807 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State), 1808 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State), 1809 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State), 1810 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State), 1811 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State), 1812 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State), 1813 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State), 1814 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State), 1815 /* Configuration bytes. */ 1816 VMSTATE_BUFFER(configuration, EEPRO100State), 1817 VMSTATE_END_OF_LIST() 1818 } 1819 }; 1820 1821 static void pci_nic_uninit(PCIDevice *pci_dev) 1822 { 1823 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); 1824 1825 vmstate_unregister(VMSTATE_IF(&pci_dev->qdev), s->vmstate, s); 1826 g_free(s->vmstate); 1827 eeprom93xx_free(&pci_dev->qdev, s->eeprom); 1828 qemu_del_nic(s->nic); 1829 } 1830 1831 static NetClientInfo net_eepro100_info = { 1832 .type = NET_CLIENT_DRIVER_NIC, 1833 .size = sizeof(NICState), 1834 .receive = nic_receive, 1835 }; 1836 1837 static void e100_nic_realize(PCIDevice *pci_dev, Error **errp) 1838 { 1839 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev); 1840 E100PCIDeviceInfo *info = eepro100_get_class(s); 1841 Error *local_err = NULL; 1842 1843 TRACE(OTHER, logout("\n")); 1844 1845 s->device = info->device; 1846 1847 e100_pci_reset(s, &local_err); 1848 if (local_err) { 1849 error_propagate(errp, local_err); 1850 return; 1851 } 1852 1853 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM, 1854 * i82559 and later support 64 or 256 word EEPROM. */ 1855 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE); 1856 1857 /* Handler for memory-mapped I/O */ 1858 memory_region_init_io(&s->mmio_bar, OBJECT(s), &eepro100_ops, s, 1859 "eepro100-mmio", PCI_MEM_SIZE); 1860 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar); 1861 memory_region_init_io(&s->io_bar, OBJECT(s), &eepro100_ops, s, 1862 "eepro100-io", PCI_IO_SIZE); 1863 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1864 /* FIXME: flash aliases to mmio?! */ 1865 memory_region_init_io(&s->flash_bar, OBJECT(s), &eepro100_ops, s, 1866 "eepro100-flash", PCI_FLASH_SIZE); 1867 pci_register_bar(&s->dev, 2, 0, &s->flash_bar); 1868 1869 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1870 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)); 1871 1872 nic_reset(s); 1873 1874 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf, 1875 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s); 1876 1877 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 1878 TRACE(OTHER, logout("%s\n", qemu_get_queue(s->nic)->info_str)); 1879 1880 qemu_register_reset(nic_reset, s); 1881 1882 s->vmstate = g_memdup(&vmstate_eepro100, sizeof(vmstate_eepro100)); 1883 s->vmstate->name = qemu_get_queue(s->nic)->model; 1884 vmstate_register(VMSTATE_IF(&pci_dev->qdev), VMSTATE_INSTANCE_ID_ANY, 1885 s->vmstate, s); 1886 } 1887 1888 static void eepro100_instance_init(Object *obj) 1889 { 1890 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, PCI_DEVICE(obj)); 1891 device_add_bootindex_property(obj, &s->conf.bootindex, 1892 "bootindex", "/ethernet-phy@0", 1893 DEVICE(s)); 1894 } 1895 1896 static E100PCIDeviceInfo e100_devices[] = { 1897 { 1898 .name = "i82550", 1899 .desc = "Intel i82550 Ethernet", 1900 .device = i82550, 1901 /* TODO: check device id. */ 1902 .device_id = PCI_DEVICE_ID_INTEL_82551IT, 1903 /* Revision ID: 0x0c, 0x0d, 0x0e. */ 1904 .revision = 0x0e, 1905 /* TODO: check size of statistical counters. */ 1906 .stats_size = 80, 1907 /* TODO: check extended tcb support. */ 1908 .has_extended_tcb_support = true, 1909 .power_management = true, 1910 },{ 1911 .name = "i82551", 1912 .desc = "Intel i82551 Ethernet", 1913 .device = i82551, 1914 .device_id = PCI_DEVICE_ID_INTEL_82551IT, 1915 /* Revision ID: 0x0f, 0x10. */ 1916 .revision = 0x0f, 1917 /* TODO: check size of statistical counters. */ 1918 .stats_size = 80, 1919 .has_extended_tcb_support = true, 1920 .power_management = true, 1921 },{ 1922 .name = "i82557a", 1923 .desc = "Intel i82557A Ethernet", 1924 .device = i82557A, 1925 .device_id = PCI_DEVICE_ID_INTEL_82557, 1926 .revision = 0x01, 1927 .power_management = false, 1928 },{ 1929 .name = "i82557b", 1930 .desc = "Intel i82557B Ethernet", 1931 .device = i82557B, 1932 .device_id = PCI_DEVICE_ID_INTEL_82557, 1933 .revision = 0x02, 1934 .power_management = false, 1935 },{ 1936 .name = "i82557c", 1937 .desc = "Intel i82557C Ethernet", 1938 .device = i82557C, 1939 .device_id = PCI_DEVICE_ID_INTEL_82557, 1940 .revision = 0x03, 1941 .power_management = false, 1942 },{ 1943 .name = "i82558a", 1944 .desc = "Intel i82558A Ethernet", 1945 .device = i82558A, 1946 .device_id = PCI_DEVICE_ID_INTEL_82557, 1947 .revision = 0x04, 1948 .stats_size = 76, 1949 .has_extended_tcb_support = true, 1950 .power_management = true, 1951 },{ 1952 .name = "i82558b", 1953 .desc = "Intel i82558B Ethernet", 1954 .device = i82558B, 1955 .device_id = PCI_DEVICE_ID_INTEL_82557, 1956 .revision = 0x05, 1957 .stats_size = 76, 1958 .has_extended_tcb_support = true, 1959 .power_management = true, 1960 },{ 1961 .name = "i82559a", 1962 .desc = "Intel i82559A Ethernet", 1963 .device = i82559A, 1964 .device_id = PCI_DEVICE_ID_INTEL_82557, 1965 .revision = 0x06, 1966 .stats_size = 80, 1967 .has_extended_tcb_support = true, 1968 .power_management = true, 1969 },{ 1970 .name = "i82559b", 1971 .desc = "Intel i82559B Ethernet", 1972 .device = i82559B, 1973 .device_id = PCI_DEVICE_ID_INTEL_82557, 1974 .revision = 0x07, 1975 .stats_size = 80, 1976 .has_extended_tcb_support = true, 1977 .power_management = true, 1978 },{ 1979 .name = "i82559c", 1980 .desc = "Intel i82559C Ethernet", 1981 .device = i82559C, 1982 .device_id = PCI_DEVICE_ID_INTEL_82557, 1983 #if 0 1984 .revision = 0x08, 1985 #endif 1986 /* TODO: Windows wants revision id 0x0c. */ 1987 .revision = 0x0c, 1988 #if EEPROM_SIZE > 0 1989 .subsystem_vendor_id = PCI_VENDOR_ID_INTEL, 1990 .subsystem_id = 0x0040, 1991 #endif 1992 .stats_size = 80, 1993 .has_extended_tcb_support = true, 1994 .power_management = true, 1995 },{ 1996 .name = "i82559er", 1997 .desc = "Intel i82559ER Ethernet", 1998 .device = i82559ER, 1999 .device_id = PCI_DEVICE_ID_INTEL_82551IT, 2000 .revision = 0x09, 2001 .stats_size = 80, 2002 .has_extended_tcb_support = true, 2003 .power_management = true, 2004 },{ 2005 .name = "i82562", 2006 .desc = "Intel i82562 Ethernet", 2007 .device = i82562, 2008 /* TODO: check device id. */ 2009 .device_id = PCI_DEVICE_ID_INTEL_82551IT, 2010 /* TODO: wrong revision id. */ 2011 .revision = 0x0e, 2012 .stats_size = 80, 2013 .has_extended_tcb_support = true, 2014 .power_management = true, 2015 },{ 2016 /* Toshiba Tecra 8200. */ 2017 .name = "i82801", 2018 .desc = "Intel i82801 Ethernet", 2019 .device = i82801, 2020 .device_id = 0x2449, 2021 .revision = 0x03, 2022 .stats_size = 80, 2023 .has_extended_tcb_support = true, 2024 .power_management = true, 2025 } 2026 }; 2027 2028 static E100PCIDeviceInfo *eepro100_get_class_by_name(const char *typename) 2029 { 2030 E100PCIDeviceInfo *info = NULL; 2031 int i; 2032 2033 /* This is admittedly awkward but also temporary. QOM allows for 2034 * parameterized typing and for subclassing both of which would suitable 2035 * handle what's going on here. But class_data is already being used as 2036 * a stop-gap hack to allow incremental qdev conversion so we cannot use it 2037 * right now. Once we merge the final QOM series, we can come back here and 2038 * do this in a much more elegant fashion. 2039 */ 2040 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) { 2041 if (strcmp(e100_devices[i].name, typename) == 0) { 2042 info = &e100_devices[i]; 2043 break; 2044 } 2045 } 2046 assert(info != NULL); 2047 2048 return info; 2049 } 2050 2051 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s) 2052 { 2053 return eepro100_get_class_by_name(object_get_typename(OBJECT(s))); 2054 } 2055 2056 static Property e100_properties[] = { 2057 DEFINE_NIC_PROPERTIES(EEPRO100State, conf), 2058 DEFINE_PROP_END_OF_LIST(), 2059 }; 2060 2061 static void eepro100_class_init(ObjectClass *klass, void *data) 2062 { 2063 DeviceClass *dc = DEVICE_CLASS(klass); 2064 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2065 E100PCIDeviceInfo *info; 2066 2067 info = eepro100_get_class_by_name(object_class_get_name(klass)); 2068 2069 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 2070 device_class_set_props(dc, e100_properties); 2071 dc->desc = info->desc; 2072 k->vendor_id = PCI_VENDOR_ID_INTEL; 2073 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 2074 k->romfile = "pxe-eepro100.rom"; 2075 k->realize = e100_nic_realize; 2076 k->exit = pci_nic_uninit; 2077 k->device_id = info->device_id; 2078 k->revision = info->revision; 2079 k->subsystem_vendor_id = info->subsystem_vendor_id; 2080 k->subsystem_id = info->subsystem_id; 2081 } 2082 2083 static void eepro100_register_types(void) 2084 { 2085 size_t i; 2086 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) { 2087 TypeInfo type_info = {}; 2088 E100PCIDeviceInfo *info = &e100_devices[i]; 2089 2090 type_info.name = info->name; 2091 type_info.parent = TYPE_PCI_DEVICE; 2092 type_info.class_init = eepro100_class_init; 2093 type_info.instance_size = sizeof(EEPRO100State); 2094 type_info.instance_init = eepro100_instance_init; 2095 type_info.interfaces = (InterfaceInfo[]) { 2096 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2097 { }, 2098 }; 2099 2100 type_register(&type_info); 2101 } 2102 } 2103 2104 type_init(eepro100_register_types) 2105