1 /* 2 * QEMU e1000(e) emulation - shared code 3 * 4 * Copyright (c) 2008 Qumranet 5 * 6 * Based on work done by: 7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 8 * Copyright (c) 2007 Dan Aloni 9 * Copyright (c) 2004 Antony T Curtis 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2.1 of the License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU Lesser General Public 22 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/net/mii.h" 28 #include "hw/pci/pci_device.h" 29 #include "net/eth.h" 30 #include "net/net.h" 31 32 #include "e1000_common.h" 33 #include "e1000x_common.h" 34 35 #include "trace.h" 36 37 bool e1000x_rx_ready(PCIDevice *d, uint32_t *mac) 38 { 39 bool link_up = mac[STATUS] & E1000_STATUS_LU; 40 bool rx_enabled = mac[RCTL] & E1000_RCTL_EN; 41 bool pci_master = d->config[PCI_COMMAND] & PCI_COMMAND_MASTER; 42 43 if (!link_up || !rx_enabled || !pci_master) { 44 trace_e1000x_rx_can_recv_disabled(link_up, rx_enabled, pci_master); 45 return false; 46 } 47 48 return true; 49 } 50 51 bool e1000x_is_vlan_packet(const void *buf, uint16_t vet) 52 { 53 uint16_t eth_proto = lduw_be_p(&PKT_GET_ETH_HDR(buf)->h_proto); 54 bool res = (eth_proto == vet); 55 56 trace_e1000x_vlan_is_vlan_pkt(res, eth_proto, vet); 57 58 return res; 59 } 60 61 bool e1000x_rx_group_filter(uint32_t *mac, const uint8_t *buf) 62 { 63 static const int mta_shift[] = { 4, 3, 2, 0 }; 64 uint32_t f, ra[2], *rp, rctl = mac[RCTL]; 65 66 for (rp = mac + RA; rp < mac + RA + 32; rp += 2) { 67 if (!(rp[1] & E1000_RAH_AV)) { 68 continue; 69 } 70 ra[0] = cpu_to_le32(rp[0]); 71 ra[1] = cpu_to_le32(rp[1]); 72 if (!memcmp(buf, (uint8_t *)ra, ETH_ALEN)) { 73 trace_e1000x_rx_flt_ucast_match((int)(rp - mac - RA) / 2, 74 MAC_ARG(buf)); 75 return true; 76 } 77 } 78 trace_e1000x_rx_flt_ucast_mismatch(MAC_ARG(buf)); 79 80 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; 81 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff; 82 if (mac[MTA + (f >> 5)] & (1 << (f & 0x1f))) { 83 e1000x_inc_reg_if_not_full(mac, MPRC); 84 return true; 85 } 86 87 trace_e1000x_rx_flt_inexact_mismatch(MAC_ARG(buf), 88 (rctl >> E1000_RCTL_MO_SHIFT) & 3, 89 f >> 5, 90 mac[MTA + (f >> 5)]); 91 92 return false; 93 } 94 95 bool e1000x_hw_rx_enabled(uint32_t *mac) 96 { 97 if (!(mac[STATUS] & E1000_STATUS_LU)) { 98 trace_e1000x_rx_link_down(mac[STATUS]); 99 return false; 100 } 101 102 if (!(mac[RCTL] & E1000_RCTL_EN)) { 103 trace_e1000x_rx_disabled(mac[RCTL]); 104 return false; 105 } 106 107 return true; 108 } 109 110 bool e1000x_is_oversized(uint32_t *mac, size_t size) 111 { 112 /* this is the size past which hardware will 113 drop packets when setting LPE=0 */ 114 static const int maximum_ethernet_vlan_size = 1522; 115 /* this is the size past which hardware will 116 drop packets when setting LPE=1 */ 117 static const int maximum_ethernet_lpe_size = 16 * KiB; 118 119 if ((size > maximum_ethernet_lpe_size || 120 (size > maximum_ethernet_vlan_size 121 && !(mac[RCTL] & E1000_RCTL_LPE))) 122 && !(mac[RCTL] & E1000_RCTL_SBP)) { 123 e1000x_inc_reg_if_not_full(mac, ROC); 124 trace_e1000x_rx_oversized(size); 125 return true; 126 } 127 128 return false; 129 } 130 131 void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer) 132 { 133 e1000x_update_regs_on_link_down(mac, phy); 134 trace_e1000x_link_negotiation_start(); 135 timer_mod(timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 136 } 137 138 void e1000x_reset_mac_addr(NICState *nic, uint32_t *mac_regs, 139 uint8_t *mac_addr) 140 { 141 int i; 142 143 mac_regs[RA] = 0; 144 mac_regs[RA + 1] = E1000_RAH_AV; 145 for (i = 0; i < 4; i++) { 146 mac_regs[RA] |= mac_addr[i] << (8 * i); 147 mac_regs[RA + 1] |= 148 (i < 2) ? mac_addr[i + 4] << (8 * i) : 0; 149 } 150 151 qemu_format_nic_info_str(qemu_get_queue(nic), mac_addr); 152 trace_e1000x_mac_indicate(MAC_ARG(mac_addr)); 153 } 154 155 void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy) 156 { 157 e1000x_update_regs_on_link_up(mac, phy); 158 phy[MII_ANLPAR] |= MII_ANLPAR_ACK; 159 phy[MII_BMSR] |= MII_BMSR_AN_COMP; 160 trace_e1000x_link_negotiation_done(); 161 } 162 163 void 164 e1000x_core_prepare_eeprom(uint16_t *eeprom, 165 const uint16_t *templ, 166 uint32_t templ_size, 167 uint16_t dev_id, 168 const uint8_t *macaddr) 169 { 170 uint16_t checksum = 0; 171 int i; 172 173 memmove(eeprom, templ, templ_size); 174 175 for (i = 0; i < 3; i++) { 176 eeprom[i] = (macaddr[2 * i + 1] << 8) | macaddr[2 * i]; 177 } 178 179 eeprom[11] = eeprom[13] = dev_id; 180 181 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 182 checksum += eeprom[i]; 183 } 184 185 checksum = (uint16_t) EEPROM_SUM - checksum; 186 187 eeprom[EEPROM_CHECKSUM_REG] = checksum; 188 } 189 190 uint32_t 191 e1000x_rxbufsize(uint32_t rctl) 192 { 193 rctl &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 | 194 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 | 195 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256; 196 switch (rctl) { 197 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384: 198 return 16384; 199 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192: 200 return 8192; 201 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096: 202 return 4096; 203 case E1000_RCTL_SZ_1024: 204 return 1024; 205 case E1000_RCTL_SZ_512: 206 return 512; 207 case E1000_RCTL_SZ_256: 208 return 256; 209 } 210 return 2048; 211 } 212 213 void 214 e1000x_update_rx_total_stats(uint32_t *mac, 215 size_t data_size, 216 size_t data_fcs_size) 217 { 218 static const int PRCregs[6] = { PRC64, PRC127, PRC255, PRC511, 219 PRC1023, PRC1522 }; 220 221 e1000x_increase_size_stats(mac, PRCregs, data_fcs_size); 222 e1000x_inc_reg_if_not_full(mac, TPR); 223 mac[GPRC] = mac[TPR]; 224 /* TOR - Total Octets Received: 225 * This register includes bytes received in a packet from the <Destination 226 * Address> field through the <CRC> field, inclusively. 227 * Always include FCS length (4) in size. 228 */ 229 e1000x_grow_8reg_if_not_full(mac, TORL, data_size + 4); 230 mac[GORCL] = mac[TORL]; 231 mac[GORCH] = mac[TORH]; 232 } 233 234 void 235 e1000x_increase_size_stats(uint32_t *mac, const int *size_regs, int size) 236 { 237 if (size > 1023) { 238 e1000x_inc_reg_if_not_full(mac, size_regs[5]); 239 } else if (size > 511) { 240 e1000x_inc_reg_if_not_full(mac, size_regs[4]); 241 } else if (size > 255) { 242 e1000x_inc_reg_if_not_full(mac, size_regs[3]); 243 } else if (size > 127) { 244 e1000x_inc_reg_if_not_full(mac, size_regs[2]); 245 } else if (size > 64) { 246 e1000x_inc_reg_if_not_full(mac, size_regs[1]); 247 } else if (size == 64) { 248 e1000x_inc_reg_if_not_full(mac, size_regs[0]); 249 } 250 } 251 252 void 253 e1000x_read_tx_ctx_descr(struct e1000_context_desc *d, 254 e1000x_txd_props *props) 255 { 256 uint32_t op = le32_to_cpu(d->cmd_and_length); 257 258 props->ipcss = d->lower_setup.ip_fields.ipcss; 259 props->ipcso = d->lower_setup.ip_fields.ipcso; 260 props->ipcse = le16_to_cpu(d->lower_setup.ip_fields.ipcse); 261 props->tucss = d->upper_setup.tcp_fields.tucss; 262 props->tucso = d->upper_setup.tcp_fields.tucso; 263 props->tucse = le16_to_cpu(d->upper_setup.tcp_fields.tucse); 264 props->paylen = op & 0xfffff; 265 props->hdr_len = d->tcp_seg_setup.fields.hdr_len; 266 props->mss = le16_to_cpu(d->tcp_seg_setup.fields.mss); 267 props->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0; 268 props->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0; 269 props->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0; 270 } 271 272 void e1000x_timestamp(uint32_t *mac, int64_t timadj, size_t lo, size_t hi) 273 { 274 int64_t ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 275 uint32_t timinca = mac[TIMINCA]; 276 uint32_t incvalue = timinca & E1000_TIMINCA_INCVALUE_MASK; 277 uint32_t incperiod = MAX(timinca >> E1000_TIMINCA_INCPERIOD_SHIFT, 1); 278 int64_t timestamp = timadj + muldiv64(ns, incvalue, incperiod * 16); 279 280 mac[lo] = timestamp & 0xffffffff; 281 mac[hi] = timestamp >> 32; 282 } 283 284 void e1000x_set_timinca(uint32_t *mac, int64_t *timadj, uint32_t val) 285 { 286 int64_t ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 287 uint32_t old_val = mac[TIMINCA]; 288 uint32_t old_incvalue = old_val & E1000_TIMINCA_INCVALUE_MASK; 289 uint32_t old_incperiod = MAX(old_val >> E1000_TIMINCA_INCPERIOD_SHIFT, 1); 290 uint32_t incvalue = val & E1000_TIMINCA_INCVALUE_MASK; 291 uint32_t incperiod = MAX(val >> E1000_TIMINCA_INCPERIOD_SHIFT, 1); 292 293 mac[TIMINCA] = val; 294 *timadj += (muldiv64(ns, incvalue, incperiod) - muldiv64(ns, old_incvalue, old_incperiod)) / 16; 295 } 296