1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000_common.h" 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 55 #define E1000E_MIN_XITR (500) 56 57 #define E1000E_MAX_TX_FRAGS (64) 58 59 union e1000_rx_desc_union { 60 struct e1000_rx_desc legacy; 61 union e1000_rx_desc_extended extended; 62 union e1000_rx_desc_packet_split packet_split; 63 }; 64 65 static ssize_t 66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 67 bool has_vnet); 68 69 static inline void 70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 71 72 static void e1000e_reset(E1000ECore *core, bool sw); 73 74 static inline void 75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 76 { 77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 78 trace_e1000e_wrn_no_ts_support(); 79 } 80 } 81 82 static inline void 83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 84 { 85 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 86 trace_e1000e_wrn_no_snap_support(); 87 } 88 } 89 90 static inline void 91 e1000e_raise_legacy_irq(E1000ECore *core) 92 { 93 trace_e1000e_irq_legacy_notify(true); 94 e1000x_inc_reg_if_not_full(core->mac, IAC); 95 pci_set_irq(core->owner, 1); 96 } 97 98 static inline void 99 e1000e_lower_legacy_irq(E1000ECore *core) 100 { 101 trace_e1000e_irq_legacy_notify(false); 102 pci_set_irq(core->owner, 0); 103 } 104 105 static inline void 106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 107 { 108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 109 timer->delay_resolution_ns; 110 111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 112 113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 114 115 timer->running = true; 116 } 117 118 static void 119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 e1000e_intrmgr_rearm_timer(timer); 123 } 124 } 125 126 static void 127 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 128 { 129 if (timer->running) { 130 timer_del(timer->timer); 131 } 132 } 133 134 static inline void 135 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 136 { 137 if (timer->running) { 138 timer_del(timer->timer); 139 timer->running = false; 140 } 141 } 142 143 static inline void 144 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 145 { 146 trace_e1000e_irq_fire_delayed_interrupts(); 147 e1000e_set_interrupt_cause(core, 0); 148 } 149 150 static void 151 e1000e_intrmgr_on_timer(void *opaque) 152 { 153 E1000IntrDelayTimer *timer = opaque; 154 155 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 156 157 timer->running = false; 158 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 159 } 160 161 static void 162 e1000e_intrmgr_on_throttling_timer(void *opaque) 163 { 164 E1000IntrDelayTimer *timer = opaque; 165 166 timer->running = false; 167 168 if (msi_enabled(timer->core->owner)) { 169 trace_e1000e_irq_msi_notify_postponed(); 170 /* Clear msi_causes_pending to fire MSI eventually */ 171 timer->core->msi_causes_pending = 0; 172 e1000e_set_interrupt_cause(timer->core, 0); 173 } else { 174 trace_e1000e_irq_legacy_notify_postponed(); 175 e1000e_set_interrupt_cause(timer->core, 0); 176 } 177 } 178 179 static void 180 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 181 { 182 E1000IntrDelayTimer *timer = opaque; 183 int idx = timer - &timer->core->eitr[0]; 184 185 timer->running = false; 186 187 trace_e1000e_irq_msix_notify_postponed_vec(idx); 188 msix_notify(timer->core->owner, idx); 189 } 190 191 static void 192 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 193 { 194 int i; 195 196 core->radv.delay_reg = RADV; 197 core->rdtr.delay_reg = RDTR; 198 core->raid.delay_reg = RAID; 199 core->tadv.delay_reg = TADV; 200 core->tidv.delay_reg = TIDV; 201 202 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 207 208 core->radv.core = core; 209 core->rdtr.core = core; 210 core->raid.core = core; 211 core->tadv.core = core; 212 core->tidv.core = core; 213 214 core->itr.core = core; 215 core->itr.delay_reg = ITR; 216 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 217 218 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 219 core->eitr[i].core = core; 220 core->eitr[i].delay_reg = EITR + i; 221 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 222 } 223 224 if (!create) { 225 return; 226 } 227 228 core->radv.timer = 229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 230 core->rdtr.timer = 231 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 232 core->raid.timer = 233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 234 235 core->tadv.timer = 236 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 237 core->tidv.timer = 238 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 239 240 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 241 e1000e_intrmgr_on_throttling_timer, 242 &core->itr); 243 244 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 245 core->eitr[i].timer = 246 timer_new_ns(QEMU_CLOCK_VIRTUAL, 247 e1000e_intrmgr_on_msix_throttling_timer, 248 &core->eitr[i]); 249 } 250 } 251 252 static inline void 253 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 254 { 255 e1000e_intrmgr_stop_timer(&core->radv); 256 e1000e_intrmgr_stop_timer(&core->rdtr); 257 e1000e_intrmgr_stop_timer(&core->raid); 258 e1000e_intrmgr_stop_timer(&core->tidv); 259 e1000e_intrmgr_stop_timer(&core->tadv); 260 } 261 262 static bool 263 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 264 { 265 uint32_t delayable_causes; 266 uint32_t rdtr = core->mac[RDTR]; 267 uint32_t radv = core->mac[RADV]; 268 uint32_t raid = core->mac[RAID]; 269 270 if (msix_enabled(core->owner)) { 271 return false; 272 } 273 274 delayable_causes = E1000_ICR_RXQ0 | 275 E1000_ICR_RXQ1 | 276 E1000_ICR_RXT0; 277 278 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 279 delayable_causes |= E1000_ICR_ACK; 280 } 281 282 /* Clean up all causes that may be delayed */ 283 core->delayed_causes |= *causes & delayable_causes; 284 *causes &= ~delayable_causes; 285 286 /* 287 * Check if delayed RX interrupts disabled by client 288 * or if there are causes that cannot be delayed 289 */ 290 if ((rdtr == 0) || (*causes != 0)) { 291 return false; 292 } 293 294 /* 295 * Check if delayed RX ACK interrupts disabled by client 296 * and there is an ACK packet received 297 */ 298 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 299 return false; 300 } 301 302 /* All causes delayed */ 303 e1000e_intrmgr_rearm_timer(&core->rdtr); 304 305 if (!core->radv.running && (radv != 0)) { 306 e1000e_intrmgr_rearm_timer(&core->radv); 307 } 308 309 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 310 e1000e_intrmgr_rearm_timer(&core->raid); 311 } 312 313 return true; 314 } 315 316 static bool 317 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 318 { 319 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 320 E1000_ICR_TXQ1 | 321 E1000_ICR_TXQE | 322 E1000_ICR_TXDW; 323 324 if (msix_enabled(core->owner)) { 325 return false; 326 } 327 328 /* Clean up all causes that may be delayed */ 329 core->delayed_causes |= *causes & delayable_causes; 330 *causes &= ~delayable_causes; 331 332 /* If there are causes that cannot be delayed */ 333 if (*causes != 0) { 334 return false; 335 } 336 337 /* All causes delayed */ 338 e1000e_intrmgr_rearm_timer(&core->tidv); 339 340 if (!core->tadv.running && (core->mac[TADV] != 0)) { 341 e1000e_intrmgr_rearm_timer(&core->tadv); 342 } 343 344 return true; 345 } 346 347 static uint32_t 348 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 349 { 350 uint32_t res; 351 352 if (msix_enabled(core->owner)) { 353 assert(core->delayed_causes == 0); 354 return 0; 355 } 356 357 res = core->delayed_causes; 358 core->delayed_causes = 0; 359 360 e1000e_intrmgr_stop_delay_timers(core); 361 362 return res; 363 } 364 365 static void 366 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 367 { 368 int i; 369 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 370 371 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 372 core->mac[ICR] |= val; 373 374 if (core->itr.running) { 375 timer_del(core->itr.timer); 376 e1000e_intrmgr_on_throttling_timer(&core->itr); 377 } 378 379 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 380 if (core->eitr[i].running) { 381 timer_del(core->eitr[i].timer); 382 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 383 } 384 } 385 } 386 387 static void 388 e1000e_intrmgr_resume(E1000ECore *core) 389 { 390 int i; 391 392 e1000e_intmgr_timer_resume(&core->radv); 393 e1000e_intmgr_timer_resume(&core->rdtr); 394 e1000e_intmgr_timer_resume(&core->raid); 395 e1000e_intmgr_timer_resume(&core->tidv); 396 e1000e_intmgr_timer_resume(&core->tadv); 397 398 e1000e_intmgr_timer_resume(&core->itr); 399 400 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 401 e1000e_intmgr_timer_resume(&core->eitr[i]); 402 } 403 } 404 405 static void 406 e1000e_intrmgr_pause(E1000ECore *core) 407 { 408 int i; 409 410 e1000e_intmgr_timer_pause(&core->radv); 411 e1000e_intmgr_timer_pause(&core->rdtr); 412 e1000e_intmgr_timer_pause(&core->raid); 413 e1000e_intmgr_timer_pause(&core->tidv); 414 e1000e_intmgr_timer_pause(&core->tadv); 415 416 e1000e_intmgr_timer_pause(&core->itr); 417 418 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 419 e1000e_intmgr_timer_pause(&core->eitr[i]); 420 } 421 } 422 423 static void 424 e1000e_intrmgr_reset(E1000ECore *core) 425 { 426 int i; 427 428 core->delayed_causes = 0; 429 430 e1000e_intrmgr_stop_delay_timers(core); 431 432 e1000e_intrmgr_stop_timer(&core->itr); 433 434 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 435 e1000e_intrmgr_stop_timer(&core->eitr[i]); 436 } 437 } 438 439 static void 440 e1000e_intrmgr_pci_unint(E1000ECore *core) 441 { 442 int i; 443 444 timer_free(core->radv.timer); 445 timer_free(core->rdtr.timer); 446 timer_free(core->raid.timer); 447 448 timer_free(core->tadv.timer); 449 timer_free(core->tidv.timer); 450 451 timer_free(core->itr.timer); 452 453 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 454 timer_free(core->eitr[i].timer); 455 } 456 } 457 458 static void 459 e1000e_intrmgr_pci_realize(E1000ECore *core) 460 { 461 e1000e_intrmgr_initialize_all_timers(core, true); 462 } 463 464 static inline bool 465 e1000e_rx_csum_enabled(E1000ECore *core) 466 { 467 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 468 } 469 470 static inline bool 471 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 472 { 473 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 474 } 475 476 static inline bool 477 e1000e_rx_use_ps_descriptor(E1000ECore *core) 478 { 479 return !e1000e_rx_use_legacy_descriptor(core) && 480 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 481 } 482 483 static inline bool 484 e1000e_rss_enabled(E1000ECore *core) 485 { 486 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 487 !e1000e_rx_csum_enabled(core) && 488 !e1000e_rx_use_legacy_descriptor(core); 489 } 490 491 typedef struct E1000E_RSSInfo_st { 492 bool enabled; 493 uint32_t hash; 494 uint32_t queue; 495 uint32_t type; 496 } E1000E_RSSInfo; 497 498 static uint32_t 499 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 500 { 501 bool hasip4, hasip6; 502 EthL4HdrProto l4hdr_proto; 503 504 assert(e1000e_rss_enabled(core)); 505 506 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 507 508 if (hasip4) { 509 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 511 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 512 513 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 514 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 515 return E1000_MRQ_RSS_TYPE_IPV4TCP; 516 } 517 518 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 519 return E1000_MRQ_RSS_TYPE_IPV4; 520 } 521 } else if (hasip6) { 522 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 523 524 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 525 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 526 527 /* 528 * Following two traces must not be combined because resulting 529 * event will have 11 arguments totally and some trace backends 530 * (at least "ust") have limitation of maximum 10 arguments per 531 * event. Events with more arguments fail to compile for 532 * backends like these. 533 */ 534 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 535 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 536 ip6info->has_ext_hdrs, 537 ip6info->rss_ex_dst_valid, 538 ip6info->rss_ex_src_valid, 539 core->mac[MRQC], 540 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 541 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 542 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 543 544 if ((!ex_dis || !ip6info->has_ext_hdrs) && 545 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 546 ip6info->rss_ex_src_valid))) { 547 548 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 549 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 550 return E1000_MRQ_RSS_TYPE_IPV6TCP; 551 } 552 553 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 554 return E1000_MRQ_RSS_TYPE_IPV6EX; 555 } 556 557 } 558 559 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 560 return E1000_MRQ_RSS_TYPE_IPV6; 561 } 562 563 } 564 565 return E1000_MRQ_RSS_TYPE_NONE; 566 } 567 568 static uint32_t 569 e1000e_rss_calc_hash(E1000ECore *core, 570 struct NetRxPkt *pkt, 571 E1000E_RSSInfo *info) 572 { 573 NetRxPktRssType type; 574 575 assert(e1000e_rss_enabled(core)); 576 577 switch (info->type) { 578 case E1000_MRQ_RSS_TYPE_IPV4: 579 type = NetPktRssIpV4; 580 break; 581 case E1000_MRQ_RSS_TYPE_IPV4TCP: 582 type = NetPktRssIpV4Tcp; 583 break; 584 case E1000_MRQ_RSS_TYPE_IPV6TCP: 585 type = NetPktRssIpV6TcpEx; 586 break; 587 case E1000_MRQ_RSS_TYPE_IPV6: 588 type = NetPktRssIpV6; 589 break; 590 case E1000_MRQ_RSS_TYPE_IPV6EX: 591 type = NetPktRssIpV6Ex; 592 break; 593 default: 594 assert(false); 595 return 0; 596 } 597 598 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 599 } 600 601 static void 602 e1000e_rss_parse_packet(E1000ECore *core, 603 struct NetRxPkt *pkt, 604 E1000E_RSSInfo *info) 605 { 606 trace_e1000e_rx_rss_started(); 607 608 if (!e1000e_rss_enabled(core)) { 609 info->enabled = false; 610 info->hash = 0; 611 info->queue = 0; 612 info->type = 0; 613 trace_e1000e_rx_rss_disabled(); 614 return; 615 } 616 617 info->enabled = true; 618 619 info->type = e1000e_rss_get_hash_type(core, pkt); 620 621 trace_e1000e_rx_rss_type(info->type); 622 623 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 624 info->hash = 0; 625 info->queue = 0; 626 return; 627 } 628 629 info->hash = e1000e_rss_calc_hash(core, pkt, info); 630 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 631 } 632 633 static bool 634 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 635 { 636 if (tx->props.tse && tx->cptse) { 637 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 638 return false; 639 } 640 641 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 642 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 643 return true; 644 } 645 646 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 647 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 648 return false; 649 } 650 } 651 652 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 653 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 654 } 655 656 return true; 657 } 658 659 static void e1000e_tx_pkt_callback(void *core, 660 const struct iovec *iov, 661 int iovcnt, 662 const struct iovec *virt_iov, 663 int virt_iovcnt) 664 { 665 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 666 } 667 668 static bool 669 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 670 { 671 int target_queue = MIN(core->max_queue_num, queue_index); 672 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 673 674 if (!e1000e_setup_tx_offloads(core, tx)) { 675 return false; 676 } 677 678 net_tx_pkt_dump(tx->tx_pkt); 679 680 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 681 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 682 return net_tx_pkt_send_custom(tx->tx_pkt, false, 683 e1000e_tx_pkt_callback, core); 684 } else { 685 return net_tx_pkt_send(tx->tx_pkt, queue); 686 } 687 } 688 689 static void 690 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 691 { 692 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 693 PTC1023, PTC1522 }; 694 695 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 696 697 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 698 e1000x_inc_reg_if_not_full(core->mac, TPT); 699 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 700 701 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 702 case ETH_PKT_BCAST: 703 e1000x_inc_reg_if_not_full(core->mac, BPTC); 704 break; 705 case ETH_PKT_MCAST: 706 e1000x_inc_reg_if_not_full(core->mac, MPTC); 707 break; 708 case ETH_PKT_UCAST: 709 break; 710 default: 711 g_assert_not_reached(); 712 } 713 714 e1000x_inc_reg_if_not_full(core->mac, GPTC); 715 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 716 } 717 718 static void 719 e1000e_process_tx_desc(E1000ECore *core, 720 struct e1000e_tx *tx, 721 struct e1000_tx_desc *dp, 722 int queue_index) 723 { 724 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 725 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 726 unsigned int split_size = txd_lower & 0xffff; 727 uint64_t addr; 728 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 729 bool eop = txd_lower & E1000_TXD_CMD_EOP; 730 731 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 732 e1000x_read_tx_ctx_descr(xp, &tx->props); 733 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 734 return; 735 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 736 /* data descriptor */ 737 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 738 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 739 e1000e_process_ts_option(core, dp); 740 } else { 741 /* legacy descriptor */ 742 e1000e_process_ts_option(core, dp); 743 tx->cptse = 0; 744 } 745 746 addr = le64_to_cpu(dp->buffer_addr); 747 748 if (!tx->skip_cp) { 749 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, 750 addr, split_size)) { 751 tx->skip_cp = true; 752 } 753 } 754 755 if (eop) { 756 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 757 if (e1000x_vlan_enabled(core->mac) && 758 e1000x_is_vlan_txd(txd_lower)) { 759 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 760 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 761 } 762 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 763 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 764 } 765 } 766 767 tx->skip_cp = false; 768 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 769 770 tx->sum_needed = 0; 771 tx->cptse = 0; 772 } 773 } 774 775 static inline uint32_t 776 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 777 { 778 if (!msix_enabled(core->owner)) { 779 return E1000_ICR_TXDW; 780 } 781 782 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 783 } 784 785 static inline uint32_t 786 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 787 bool min_threshold_hit) 788 { 789 if (!msix_enabled(core->owner)) { 790 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 791 } 792 793 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 794 } 795 796 static uint32_t 797 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 798 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 799 { 800 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 801 802 if (!(txd_lower & E1000_TXD_CMD_RS) && 803 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 804 return 0; 805 } 806 807 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 808 809 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 810 811 dp->upper.data = cpu_to_le32(txd_upper); 812 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 813 &dp->upper, sizeof(dp->upper)); 814 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 815 } 816 817 typedef struct E1000E_RingInfo_st { 818 int dbah; 819 int dbal; 820 int dlen; 821 int dh; 822 int dt; 823 int idx; 824 } E1000E_RingInfo; 825 826 static inline bool 827 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 828 { 829 return core->mac[r->dh] == core->mac[r->dt] || 830 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 831 } 832 833 static inline uint64_t 834 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 835 { 836 uint64_t bah = core->mac[r->dbah]; 837 uint64_t bal = core->mac[r->dbal]; 838 839 return (bah << 32) + bal; 840 } 841 842 static inline uint64_t 843 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 844 { 845 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 846 } 847 848 static inline void 849 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 850 { 851 core->mac[r->dh] += count; 852 853 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 854 core->mac[r->dh] = 0; 855 } 856 } 857 858 static inline uint32_t 859 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 860 { 861 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 862 core->mac[r->dh], core->mac[r->dt]); 863 864 if (core->mac[r->dh] <= core->mac[r->dt]) { 865 return core->mac[r->dt] - core->mac[r->dh]; 866 } 867 868 if (core->mac[r->dh] > core->mac[r->dt]) { 869 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 870 core->mac[r->dt] - core->mac[r->dh]; 871 } 872 873 g_assert_not_reached(); 874 return 0; 875 } 876 877 static inline bool 878 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 879 { 880 return core->mac[r->dlen] > 0; 881 } 882 883 static inline uint32_t 884 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 885 { 886 return core->mac[r->dlen]; 887 } 888 889 typedef struct E1000E_TxRing_st { 890 const E1000E_RingInfo *i; 891 struct e1000e_tx *tx; 892 } E1000E_TxRing; 893 894 static inline int 895 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 896 { 897 return (reg_idx - base_reg_idx) / (0x100 >> 2); 898 } 899 900 static inline void 901 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 902 { 903 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 904 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 905 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 906 }; 907 908 assert(idx < ARRAY_SIZE(i)); 909 910 txr->i = &i[idx]; 911 txr->tx = &core->tx[idx]; 912 } 913 914 typedef struct E1000E_RxRing_st { 915 const E1000E_RingInfo *i; 916 } E1000E_RxRing; 917 918 static inline void 919 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 920 { 921 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 922 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 923 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 924 }; 925 926 assert(idx < ARRAY_SIZE(i)); 927 928 rxr->i = &i[idx]; 929 } 930 931 static void 932 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 933 { 934 dma_addr_t base; 935 struct e1000_tx_desc desc; 936 bool ide = false; 937 const E1000E_RingInfo *txi = txr->i; 938 uint32_t cause = E1000_ICS_TXQE; 939 940 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 941 trace_e1000e_tx_disabled(); 942 return; 943 } 944 945 while (!e1000e_ring_empty(core, txi)) { 946 base = e1000e_ring_head_descr(core, txi); 947 948 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 949 950 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 951 desc.lower.data, desc.upper.data); 952 953 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 954 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 955 956 e1000e_ring_advance(core, txi, 1); 957 } 958 959 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 960 e1000e_set_interrupt_cause(core, cause); 961 } 962 } 963 964 static bool 965 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 966 size_t total_size) 967 { 968 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 969 970 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 971 core->rx_desc_buf_size); 972 973 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 974 core->rx_desc_buf_size; 975 } 976 977 void 978 e1000e_start_recv(E1000ECore *core) 979 { 980 int i; 981 982 trace_e1000e_rx_start_recv(); 983 984 for (i = 0; i <= core->max_queue_num; i++) { 985 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 986 } 987 } 988 989 bool 990 e1000e_can_receive(E1000ECore *core) 991 { 992 int i; 993 994 if (!e1000x_rx_ready(core->owner, core->mac)) { 995 return false; 996 } 997 998 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 999 E1000E_RxRing rxr; 1000 1001 e1000e_rx_ring_init(core, &rxr, i); 1002 if (e1000e_ring_enabled(core, rxr.i) && 1003 e1000e_has_rxbufs(core, rxr.i, 1)) { 1004 trace_e1000e_rx_can_recv(); 1005 return true; 1006 } 1007 } 1008 1009 trace_e1000e_rx_can_recv_rings_full(); 1010 return false; 1011 } 1012 1013 ssize_t 1014 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 1015 { 1016 const struct iovec iov = { 1017 .iov_base = (uint8_t *)buf, 1018 .iov_len = size 1019 }; 1020 1021 return e1000e_receive_iov(core, &iov, 1); 1022 } 1023 1024 static inline bool 1025 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1026 { 1027 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1028 } 1029 1030 static inline bool 1031 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1032 { 1033 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1034 } 1035 1036 static bool 1037 e1000e_receive_filter(E1000ECore *core, const void *buf) 1038 { 1039 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || 1040 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && 1041 e1000x_rx_group_filter(core->mac, buf); 1042 } 1043 1044 static inline void 1045 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1046 hwaddr *buff_addr) 1047 { 1048 *buff_addr = le64_to_cpu(desc->buffer_addr); 1049 } 1050 1051 static inline void 1052 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1053 hwaddr *buff_addr) 1054 { 1055 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1056 } 1057 1058 static inline void 1059 e1000e_read_ps_rx_descr(E1000ECore *core, 1060 union e1000_rx_desc_packet_split *desc, 1061 hwaddr buff_addr[MAX_PS_BUFFERS]) 1062 { 1063 int i; 1064 1065 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1066 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1067 } 1068 1069 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1070 buff_addr[2], buff_addr[3]); 1071 } 1072 1073 static inline void 1074 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1075 hwaddr buff_addr[MAX_PS_BUFFERS]) 1076 { 1077 if (e1000e_rx_use_legacy_descriptor(core)) { 1078 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1079 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1080 } else { 1081 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1082 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1083 } else { 1084 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1085 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1086 } 1087 } 1088 } 1089 1090 static void 1091 e1000e_verify_csum_in_sw(E1000ECore *core, 1092 struct NetRxPkt *pkt, 1093 uint32_t *status_flags, 1094 EthL4HdrProto l4hdr_proto) 1095 { 1096 bool csum_valid; 1097 uint32_t csum_error; 1098 1099 if (e1000e_rx_l3_cso_enabled(core)) { 1100 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1101 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1102 } else { 1103 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1104 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1105 } 1106 } else { 1107 trace_e1000e_rx_metadata_l3_cso_disabled(); 1108 } 1109 1110 if (!e1000e_rx_l4_cso_enabled(core)) { 1111 trace_e1000e_rx_metadata_l4_cso_disabled(); 1112 return; 1113 } 1114 1115 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1116 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1117 return; 1118 } 1119 1120 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1121 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1122 1123 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1124 *status_flags |= E1000_RXD_STAT_UDPCS; 1125 } 1126 } 1127 1128 static inline bool 1129 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1130 { 1131 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1132 return false; 1133 } 1134 1135 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1136 return !net_rx_pkt_has_tcp_data(rx_pkt); 1137 } 1138 1139 return true; 1140 } 1141 1142 static void 1143 e1000e_build_rx_metadata(E1000ECore *core, 1144 struct NetRxPkt *pkt, 1145 bool is_eop, 1146 const E1000E_RSSInfo *rss_info, 1147 uint32_t *rss, uint32_t *mrq, 1148 uint32_t *status_flags, 1149 uint16_t *ip_id, 1150 uint16_t *vlan_tag) 1151 { 1152 struct virtio_net_hdr *vhdr; 1153 bool hasip4, hasip6; 1154 EthL4HdrProto l4hdr_proto; 1155 uint32_t pkt_type; 1156 1157 *status_flags = E1000_RXD_STAT_DD; 1158 1159 /* No additional metadata needed for non-EOP descriptors */ 1160 if (!is_eop) { 1161 goto func_exit; 1162 } 1163 1164 *status_flags |= E1000_RXD_STAT_EOP; 1165 1166 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1167 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1168 1169 /* VLAN state */ 1170 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1171 *status_flags |= E1000_RXD_STAT_VP; 1172 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1173 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1174 } 1175 1176 /* Packet parsing results */ 1177 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1178 if (rss_info->enabled) { 1179 *rss = cpu_to_le32(rss_info->hash); 1180 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1181 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1182 } 1183 } else if (hasip4) { 1184 *status_flags |= E1000_RXD_STAT_IPIDV; 1185 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1186 trace_e1000e_rx_metadata_ip_id(*ip_id); 1187 } 1188 1189 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { 1190 *status_flags |= E1000_RXD_STAT_ACK; 1191 trace_e1000e_rx_metadata_ack(); 1192 } 1193 1194 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1195 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1196 pkt_type = E1000_RXD_PKT_MAC; 1197 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1198 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1199 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1200 } else if (hasip4 || hasip6) { 1201 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1202 } else { 1203 pkt_type = E1000_RXD_PKT_MAC; 1204 } 1205 1206 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1207 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1208 1209 /* RX CSO information */ 1210 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1211 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1212 goto func_exit; 1213 } 1214 1215 vhdr = net_rx_pkt_get_vhdr(pkt); 1216 1217 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1218 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1219 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1220 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1221 goto func_exit; 1222 } 1223 1224 if (e1000e_rx_l3_cso_enabled(core)) { 1225 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1226 } else { 1227 trace_e1000e_rx_metadata_l3_cso_disabled(); 1228 } 1229 1230 if (e1000e_rx_l4_cso_enabled(core)) { 1231 switch (l4hdr_proto) { 1232 case ETH_L4_HDR_PROTO_TCP: 1233 *status_flags |= E1000_RXD_STAT_TCPCS; 1234 break; 1235 1236 case ETH_L4_HDR_PROTO_UDP: 1237 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1238 break; 1239 1240 default: 1241 break; 1242 } 1243 } else { 1244 trace_e1000e_rx_metadata_l4_cso_disabled(); 1245 } 1246 1247 trace_e1000e_rx_metadata_status_flags(*status_flags); 1248 1249 func_exit: 1250 *status_flags = cpu_to_le32(*status_flags); 1251 } 1252 1253 static inline void 1254 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1255 struct NetRxPkt *pkt, 1256 const E1000E_RSSInfo *rss_info, 1257 uint16_t length) 1258 { 1259 uint32_t status_flags, rss, mrq; 1260 uint16_t ip_id; 1261 1262 assert(!rss_info->enabled); 1263 1264 desc->length = cpu_to_le16(length); 1265 desc->csum = 0; 1266 1267 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1268 rss_info, 1269 &rss, &mrq, 1270 &status_flags, &ip_id, 1271 &desc->special); 1272 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1273 desc->status = (uint8_t) le32_to_cpu(status_flags); 1274 } 1275 1276 static inline void 1277 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1278 struct NetRxPkt *pkt, 1279 const E1000E_RSSInfo *rss_info, 1280 uint16_t length) 1281 { 1282 memset(&desc->wb, 0, sizeof(desc->wb)); 1283 1284 desc->wb.upper.length = cpu_to_le16(length); 1285 1286 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1287 rss_info, 1288 &desc->wb.lower.hi_dword.rss, 1289 &desc->wb.lower.mrq, 1290 &desc->wb.upper.status_error, 1291 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1292 &desc->wb.upper.vlan); 1293 } 1294 1295 static inline void 1296 e1000e_write_ps_rx_descr(E1000ECore *core, 1297 union e1000_rx_desc_packet_split *desc, 1298 struct NetRxPkt *pkt, 1299 const E1000E_RSSInfo *rss_info, 1300 size_t ps_hdr_len, 1301 uint16_t(*written)[MAX_PS_BUFFERS]) 1302 { 1303 int i; 1304 1305 memset(&desc->wb, 0, sizeof(desc->wb)); 1306 1307 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1308 1309 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1310 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1311 } 1312 1313 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1314 rss_info, 1315 &desc->wb.lower.hi_dword.rss, 1316 &desc->wb.lower.mrq, 1317 &desc->wb.middle.status_error, 1318 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1319 &desc->wb.middle.vlan); 1320 1321 desc->wb.upper.header_status = 1322 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1323 1324 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1325 (*written)[2], (*written)[3]); 1326 } 1327 1328 static inline void 1329 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1330 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1331 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1332 { 1333 if (e1000e_rx_use_legacy_descriptor(core)) { 1334 assert(ps_hdr_len == 0); 1335 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1336 (*written)[0]); 1337 } else { 1338 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1339 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1340 ps_hdr_len, written); 1341 } else { 1342 assert(ps_hdr_len == 0); 1343 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1344 (*written)[0]); 1345 } 1346 } 1347 } 1348 1349 static inline void 1350 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1351 union e1000_rx_desc_union *desc, dma_addr_t len) 1352 { 1353 PCIDevice *dev = core->owner; 1354 1355 if (e1000e_rx_use_legacy_descriptor(core)) { 1356 struct e1000_rx_desc *d = &desc->legacy; 1357 size_t offset = offsetof(struct e1000_rx_desc, status); 1358 uint8_t status = d->status; 1359 1360 d->status &= ~E1000_RXD_STAT_DD; 1361 pci_dma_write(dev, addr, desc, len); 1362 1363 if (status & E1000_RXD_STAT_DD) { 1364 d->status = status; 1365 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1366 } 1367 } else { 1368 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1369 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1370 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1371 wb.middle.status_error); 1372 uint32_t status = d->wb.middle.status_error; 1373 1374 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1375 pci_dma_write(dev, addr, desc, len); 1376 1377 if (status & E1000_RXD_STAT_DD) { 1378 d->wb.middle.status_error = status; 1379 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1380 } 1381 } else { 1382 union e1000_rx_desc_extended *d = &desc->extended; 1383 size_t offset = offsetof(union e1000_rx_desc_extended, 1384 wb.upper.status_error); 1385 uint32_t status = d->wb.upper.status_error; 1386 1387 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1388 pci_dma_write(dev, addr, desc, len); 1389 1390 if (status & E1000_RXD_STAT_DD) { 1391 d->wb.upper.status_error = status; 1392 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1393 } 1394 } 1395 } 1396 } 1397 1398 typedef struct e1000e_ba_state_st { 1399 uint16_t written[MAX_PS_BUFFERS]; 1400 uint8_t cur_idx; 1401 } e1000e_ba_state; 1402 1403 static inline void 1404 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1405 hwaddr ba[MAX_PS_BUFFERS], 1406 e1000e_ba_state *bastate, 1407 const char *data, 1408 dma_addr_t data_len) 1409 { 1410 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1411 1412 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1413 bastate->written[0] += data_len; 1414 1415 bastate->cur_idx = 1; 1416 } 1417 1418 static void 1419 e1000e_write_to_rx_buffers(E1000ECore *core, 1420 hwaddr ba[MAX_PS_BUFFERS], 1421 e1000e_ba_state *bastate, 1422 const char *data, 1423 dma_addr_t data_len) 1424 { 1425 while (data_len > 0) { 1426 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1427 uint32_t cur_buf_bytes_left = cur_buf_len - 1428 bastate->written[bastate->cur_idx]; 1429 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1430 1431 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1432 ba[bastate->cur_idx], 1433 bastate->written[bastate->cur_idx], 1434 data, 1435 bytes_to_write); 1436 1437 pci_dma_write(core->owner, 1438 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1439 data, bytes_to_write); 1440 1441 bastate->written[bastate->cur_idx] += bytes_to_write; 1442 data += bytes_to_write; 1443 data_len -= bytes_to_write; 1444 1445 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1446 bastate->cur_idx++; 1447 } 1448 1449 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1450 } 1451 } 1452 1453 static void 1454 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) 1455 { 1456 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1457 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1458 } 1459 1460 static inline bool 1461 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1462 { 1463 return e1000e_ring_free_descr_num(core, rxi) == 1464 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1465 } 1466 1467 static bool 1468 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1469 { 1470 bool hasip4, hasip6; 1471 EthL4HdrProto l4hdr_proto; 1472 bool fragment; 1473 1474 if (!e1000e_rx_use_ps_descriptor(core)) { 1475 return false; 1476 } 1477 1478 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1479 1480 if (hasip4) { 1481 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1482 } else if (hasip6) { 1483 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1484 } else { 1485 return false; 1486 } 1487 1488 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1489 return false; 1490 } 1491 1492 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1493 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1494 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1495 } else { 1496 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1497 } 1498 1499 if ((*hdr_len > core->rxbuf_sizes[0]) || 1500 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1501 return false; 1502 } 1503 1504 return true; 1505 } 1506 1507 static void 1508 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1509 const E1000E_RxRing *rxr, 1510 const E1000E_RSSInfo *rss_info) 1511 { 1512 PCIDevice *d = core->owner; 1513 dma_addr_t base; 1514 union e1000_rx_desc_union desc; 1515 size_t desc_size; 1516 size_t desc_offset = 0; 1517 size_t iov_ofs = 0; 1518 1519 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1520 size_t size = net_rx_pkt_get_total_len(pkt); 1521 size_t total_size = size + e1000x_fcs_len(core->mac); 1522 const E1000E_RingInfo *rxi; 1523 size_t ps_hdr_len = 0; 1524 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1525 bool is_first = true; 1526 1527 rxi = rxr->i; 1528 1529 do { 1530 hwaddr ba[MAX_PS_BUFFERS]; 1531 e1000e_ba_state bastate = { { 0 } }; 1532 bool is_last = false; 1533 1534 desc_size = total_size - desc_offset; 1535 1536 if (desc_size > core->rx_desc_buf_size) { 1537 desc_size = core->rx_desc_buf_size; 1538 } 1539 1540 if (e1000e_ring_empty(core, rxi)) { 1541 return; 1542 } 1543 1544 base = e1000e_ring_head_descr(core, rxi); 1545 1546 pci_dma_read(d, base, &desc, core->rx_desc_len); 1547 1548 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1549 1550 e1000e_read_rx_descr(core, &desc, ba); 1551 1552 if (ba[0]) { 1553 if (desc_offset < size) { 1554 static const uint32_t fcs_pad; 1555 size_t iov_copy; 1556 size_t copy_size = size - desc_offset; 1557 if (copy_size > core->rx_desc_buf_size) { 1558 copy_size = core->rx_desc_buf_size; 1559 } 1560 1561 /* For PS mode copy the packet header first */ 1562 if (do_ps) { 1563 if (is_first) { 1564 size_t ps_hdr_copied = 0; 1565 do { 1566 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1567 iov->iov_len - iov_ofs); 1568 1569 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1570 iov->iov_base, iov_copy); 1571 1572 copy_size -= iov_copy; 1573 ps_hdr_copied += iov_copy; 1574 1575 iov_ofs += iov_copy; 1576 if (iov_ofs == iov->iov_len) { 1577 iov++; 1578 iov_ofs = 0; 1579 } 1580 } while (ps_hdr_copied < ps_hdr_len); 1581 1582 is_first = false; 1583 } else { 1584 /* Leave buffer 0 of each descriptor except first */ 1585 /* empty as per spec 7.1.5.1 */ 1586 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1587 NULL, 0); 1588 } 1589 } 1590 1591 /* Copy packet payload */ 1592 while (copy_size) { 1593 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1594 1595 e1000e_write_to_rx_buffers(core, ba, &bastate, 1596 iov->iov_base + iov_ofs, iov_copy); 1597 1598 copy_size -= iov_copy; 1599 iov_ofs += iov_copy; 1600 if (iov_ofs == iov->iov_len) { 1601 iov++; 1602 iov_ofs = 0; 1603 } 1604 } 1605 1606 if (desc_offset + desc_size >= total_size) { 1607 /* Simulate FCS checksum presence in the last descriptor */ 1608 e1000e_write_to_rx_buffers(core, ba, &bastate, 1609 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1610 } 1611 } 1612 } else { /* as per intel docs; skip descriptors with null buf addr */ 1613 trace_e1000e_rx_null_descriptor(); 1614 } 1615 desc_offset += desc_size; 1616 if (desc_offset >= total_size) { 1617 is_last = true; 1618 } 1619 1620 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1621 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1622 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1623 1624 e1000e_ring_advance(core, rxi, 1625 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1626 1627 } while (desc_offset < total_size); 1628 1629 e1000e_update_rx_stats(core, size, total_size); 1630 } 1631 1632 static inline void 1633 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1634 { 1635 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1636 1637 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1638 net_rx_pkt_fix_l4_csum(pkt); 1639 } 1640 } 1641 1642 ssize_t 1643 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1644 { 1645 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1646 } 1647 1648 static ssize_t 1649 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1650 bool has_vnet) 1651 { 1652 uint32_t n = 0; 1653 uint8_t buf[ETH_ZLEN]; 1654 struct iovec min_iov; 1655 size_t size, orig_size; 1656 size_t iov_ofs = 0; 1657 E1000E_RxRing rxr; 1658 E1000E_RSSInfo rss_info; 1659 size_t total_size; 1660 ssize_t retval; 1661 bool rdmts_hit; 1662 1663 trace_e1000e_rx_receive_iov(iovcnt); 1664 1665 if (!e1000x_hw_rx_enabled(core->mac)) { 1666 return -1; 1667 } 1668 1669 /* Pull virtio header in */ 1670 if (has_vnet) { 1671 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1672 iov_ofs = sizeof(struct virtio_net_hdr); 1673 } else { 1674 net_rx_pkt_unset_vhdr(core->rx_pkt); 1675 } 1676 1677 orig_size = iov_size(iov, iovcnt); 1678 size = orig_size - iov_ofs; 1679 1680 /* Pad to minimum Ethernet frame length */ 1681 if (size < sizeof(buf)) { 1682 iov_to_buf(iov, iovcnt, iov_ofs, buf, size); 1683 memset(&buf[size], 0, sizeof(buf) - size); 1684 e1000x_inc_reg_if_not_full(core->mac, RUC); 1685 min_iov.iov_base = buf; 1686 min_iov.iov_len = size = sizeof(buf); 1687 iovcnt = 1; 1688 iov = &min_iov; 1689 iov_ofs = 0; 1690 } else { 1691 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4); 1692 } 1693 1694 /* Discard oversized packets if !LPE and !SBP. */ 1695 if (e1000x_is_oversized(core->mac, size)) { 1696 return orig_size; 1697 } 1698 1699 net_rx_pkt_set_packet_type(core->rx_pkt, 1700 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1701 1702 if (!e1000e_receive_filter(core, buf)) { 1703 trace_e1000e_rx_flt_dropped(); 1704 return orig_size; 1705 } 1706 1707 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1708 e1000x_vlan_enabled(core->mac), core->mac[VET]); 1709 1710 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1711 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1712 1713 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1714 e1000x_fcs_len(core->mac); 1715 1716 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1717 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1718 1719 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1720 1721 retval = orig_size; 1722 1723 /* Perform small receive detection (RSRPD) */ 1724 if (total_size < core->mac[RSRPD]) { 1725 n |= E1000_ICS_SRPD; 1726 } 1727 1728 /* Perform ACK receive detection */ 1729 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1730 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1731 n |= E1000_ICS_ACK; 1732 } 1733 1734 /* Check if receive descriptor minimum threshold hit */ 1735 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1736 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1737 1738 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1739 } else { 1740 n |= E1000_ICS_RXO; 1741 retval = 0; 1742 1743 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1744 } 1745 1746 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1747 trace_e1000e_rx_interrupt_set(n); 1748 e1000e_set_interrupt_cause(core, n); 1749 } else { 1750 trace_e1000e_rx_interrupt_delayed(n); 1751 } 1752 1753 return retval; 1754 } 1755 1756 static inline bool 1757 e1000e_have_autoneg(E1000ECore *core) 1758 { 1759 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1760 } 1761 1762 static void e1000e_update_flowctl_status(E1000ECore *core) 1763 { 1764 if (e1000e_have_autoneg(core) && 1765 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1766 trace_e1000e_link_autoneg_flowctl(true); 1767 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1768 } else { 1769 trace_e1000e_link_autoneg_flowctl(false); 1770 } 1771 } 1772 1773 static inline void 1774 e1000e_link_down(E1000ECore *core) 1775 { 1776 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1777 e1000e_update_flowctl_status(core); 1778 } 1779 1780 static inline void 1781 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1782 { 1783 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1784 core->phy[0][MII_BMCR] = val & ~(0x3f | 1785 MII_BMCR_RESET | 1786 MII_BMCR_ANRESTART); 1787 1788 if ((val & MII_BMCR_ANRESTART) && 1789 e1000e_have_autoneg(core)) { 1790 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1791 } 1792 } 1793 1794 static void 1795 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1796 { 1797 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1798 1799 if (val & BIT(10)) { 1800 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1801 } 1802 } 1803 1804 static void 1805 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1806 { 1807 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1808 } 1809 1810 void 1811 e1000e_core_set_link_status(E1000ECore *core) 1812 { 1813 NetClientState *nc = qemu_get_queue(core->owner_nic); 1814 uint32_t old_status = core->mac[STATUS]; 1815 1816 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1817 1818 if (nc->link_down) { 1819 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1820 } else { 1821 if (e1000e_have_autoneg(core) && 1822 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1823 e1000x_restart_autoneg(core->mac, core->phy[0], 1824 core->autoneg_timer); 1825 } else { 1826 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1827 e1000e_start_recv(core); 1828 } 1829 } 1830 1831 if (core->mac[STATUS] != old_status) { 1832 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1833 } 1834 } 1835 1836 static void 1837 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1838 { 1839 trace_e1000e_core_ctrl_write(index, val); 1840 1841 /* RST is self clearing */ 1842 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1843 core->mac[CTRL_DUP] = core->mac[CTRL]; 1844 1845 trace_e1000e_link_set_params( 1846 !!(val & E1000_CTRL_ASDE), 1847 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1848 !!(val & E1000_CTRL_FRCSPD), 1849 !!(val & E1000_CTRL_FRCDPX), 1850 !!(val & E1000_CTRL_RFCE), 1851 !!(val & E1000_CTRL_TFCE)); 1852 1853 if (val & E1000_CTRL_RST) { 1854 trace_e1000e_core_ctrl_sw_reset(); 1855 e1000e_reset(core, true); 1856 } 1857 1858 if (val & E1000_CTRL_PHY_RST) { 1859 trace_e1000e_core_ctrl_phy_reset(); 1860 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1861 } 1862 } 1863 1864 static void 1865 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1866 { 1867 trace_e1000e_rx_set_rfctl(val); 1868 1869 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1870 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1871 } 1872 1873 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1874 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1875 } 1876 1877 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1878 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1879 } 1880 1881 core->mac[RFCTL] = val; 1882 } 1883 1884 static void 1885 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1886 { 1887 int i; 1888 core->rx_desc_buf_size = 0; 1889 1890 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1891 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1892 } 1893 } 1894 1895 static void 1896 e1000e_parse_rxbufsize(E1000ECore *core) 1897 { 1898 uint32_t rctl = core->mac[RCTL]; 1899 1900 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1901 1902 if (rctl & E1000_RCTL_DTYP_MASK) { 1903 uint32_t bsize; 1904 1905 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1906 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1907 1908 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1909 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1910 1911 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1912 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1913 1914 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1915 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1916 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1917 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1918 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1919 } else { 1920 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1921 } 1922 1923 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1924 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1925 1926 e1000e_calc_per_desc_buf_size(core); 1927 } 1928 1929 static void 1930 e1000e_calc_rxdesclen(E1000ECore *core) 1931 { 1932 if (e1000e_rx_use_legacy_descriptor(core)) { 1933 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1934 } else { 1935 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1936 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1937 } else { 1938 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1939 } 1940 } 1941 trace_e1000e_rx_desc_len(core->rx_desc_len); 1942 } 1943 1944 static void 1945 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1946 { 1947 core->mac[RCTL] = val; 1948 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1949 1950 if (val & E1000_RCTL_EN) { 1951 e1000e_parse_rxbufsize(core); 1952 e1000e_calc_rxdesclen(core); 1953 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1954 E1000_RING_DESC_LEN_SHIFT; 1955 1956 e1000e_start_recv(core); 1957 } 1958 } 1959 1960 static 1961 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1962 (E1000ECore *, int, uint16_t) = { 1963 [0] = { 1964 [MII_BMCR] = e1000e_set_phy_ctrl, 1965 [PHY_PAGE] = e1000e_set_phy_page, 1966 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1967 } 1968 }; 1969 1970 static inline void 1971 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 1972 { 1973 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1974 core->mac[IMS] &= ~bits; 1975 } 1976 1977 static inline bool 1978 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 1979 { 1980 if (timer->running) { 1981 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1982 1983 return true; 1984 } 1985 1986 if (timer->core->mac[timer->delay_reg] != 0) { 1987 e1000e_intrmgr_rearm_timer(timer); 1988 } 1989 1990 return false; 1991 } 1992 1993 static inline bool 1994 e1000e_itr_should_postpone(E1000ECore *core) 1995 { 1996 return e1000e_postpone_interrupt(&core->itr); 1997 } 1998 1999 static inline bool 2000 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 2001 { 2002 return e1000e_postpone_interrupt(&core->eitr[idx]); 2003 } 2004 2005 static void 2006 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2007 { 2008 uint32_t effective_eiac; 2009 2010 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2011 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2012 if (vec < E1000E_MSIX_VEC_NUM) { 2013 if (!e1000e_eitr_should_postpone(core, vec)) { 2014 trace_e1000e_irq_msix_notify_vec(vec); 2015 msix_notify(core->owner, vec); 2016 } 2017 } else { 2018 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2019 } 2020 } else { 2021 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2022 } 2023 2024 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2025 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2026 core->mac[IAM] &= ~cause; 2027 } 2028 2029 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2030 2031 effective_eiac = core->mac[EIAC] & cause; 2032 2033 core->mac[ICR] &= ~effective_eiac; 2034 core->msi_causes_pending &= ~effective_eiac; 2035 2036 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2037 core->mac[IMS] &= ~effective_eiac; 2038 } 2039 } 2040 2041 static void 2042 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2043 { 2044 if (causes & E1000_ICR_RXQ0) { 2045 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2046 E1000_IVAR_RXQ0(core->mac[IVAR])); 2047 } 2048 2049 if (causes & E1000_ICR_RXQ1) { 2050 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2051 E1000_IVAR_RXQ1(core->mac[IVAR])); 2052 } 2053 2054 if (causes & E1000_ICR_TXQ0) { 2055 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2056 E1000_IVAR_TXQ0(core->mac[IVAR])); 2057 } 2058 2059 if (causes & E1000_ICR_TXQ1) { 2060 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2061 E1000_IVAR_TXQ1(core->mac[IVAR])); 2062 } 2063 2064 if (causes & E1000_ICR_OTHER) { 2065 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2066 E1000_IVAR_OTHER(core->mac[IVAR])); 2067 } 2068 } 2069 2070 static void 2071 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2072 { 2073 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2074 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2075 if (vec < E1000E_MSIX_VEC_NUM) { 2076 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2077 msix_clr_pending(core->owner, vec); 2078 } else { 2079 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2080 } 2081 } else { 2082 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2083 } 2084 } 2085 2086 static void 2087 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2088 { 2089 if (causes & E1000_ICR_RXQ0) { 2090 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2091 E1000_IVAR_RXQ0(core->mac[IVAR])); 2092 } 2093 2094 if (causes & E1000_ICR_RXQ1) { 2095 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2096 E1000_IVAR_RXQ1(core->mac[IVAR])); 2097 } 2098 2099 if (causes & E1000_ICR_TXQ0) { 2100 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2101 E1000_IVAR_TXQ0(core->mac[IVAR])); 2102 } 2103 2104 if (causes & E1000_ICR_TXQ1) { 2105 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2106 E1000_IVAR_TXQ1(core->mac[IVAR])); 2107 } 2108 2109 if (causes & E1000_ICR_OTHER) { 2110 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2111 E1000_IVAR_OTHER(core->mac[IVAR])); 2112 } 2113 } 2114 2115 static inline void 2116 e1000e_fix_icr_asserted(E1000ECore *core) 2117 { 2118 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2119 if (core->mac[ICR]) { 2120 core->mac[ICR] |= E1000_ICR_ASSERTED; 2121 } 2122 2123 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2124 } 2125 2126 static void 2127 e1000e_send_msi(E1000ECore *core, bool msix) 2128 { 2129 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2130 2131 core->msi_causes_pending &= causes; 2132 causes ^= core->msi_causes_pending; 2133 if (causes == 0) { 2134 return; 2135 } 2136 core->msi_causes_pending |= causes; 2137 2138 if (msix) { 2139 e1000e_msix_notify(core, causes); 2140 } else { 2141 if (!e1000e_itr_should_postpone(core)) { 2142 trace_e1000e_irq_msi_notify(causes); 2143 msi_notify(core->owner, 0); 2144 } 2145 } 2146 } 2147 2148 static void 2149 e1000e_update_interrupt_state(E1000ECore *core) 2150 { 2151 bool interrupts_pending; 2152 bool is_msix = msix_enabled(core->owner); 2153 2154 /* Set ICR[OTHER] for MSI-X */ 2155 if (is_msix) { 2156 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2157 core->mac[ICR] |= E1000_ICR_OTHER; 2158 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2159 } 2160 } 2161 2162 e1000e_fix_icr_asserted(core); 2163 2164 /* 2165 * Make sure ICR and ICS registers have the same value. 2166 * The spec says that the ICS register is write-only. However in practice, 2167 * on real hardware ICS is readable, and for reads it has the same value as 2168 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2169 * 2170 * The VxWorks PRO/1000 driver uses this behaviour. 2171 */ 2172 core->mac[ICS] = core->mac[ICR]; 2173 2174 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2175 if (!interrupts_pending) { 2176 core->msi_causes_pending = 0; 2177 } 2178 2179 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2180 core->mac[ICR], core->mac[IMS]); 2181 2182 if (is_msix || msi_enabled(core->owner)) { 2183 if (interrupts_pending) { 2184 e1000e_send_msi(core, is_msix); 2185 } 2186 } else { 2187 if (interrupts_pending) { 2188 if (!e1000e_itr_should_postpone(core)) { 2189 e1000e_raise_legacy_irq(core); 2190 } 2191 } else { 2192 e1000e_lower_legacy_irq(core); 2193 } 2194 } 2195 } 2196 2197 static void 2198 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2199 { 2200 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2201 2202 val |= e1000e_intmgr_collect_delayed_causes(core); 2203 core->mac[ICR] |= val; 2204 2205 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2206 2207 e1000e_update_interrupt_state(core); 2208 } 2209 2210 static inline void 2211 e1000e_autoneg_timer(void *opaque) 2212 { 2213 E1000ECore *core = opaque; 2214 if (!qemu_get_queue(core->owner_nic)->link_down) { 2215 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2216 e1000e_start_recv(core); 2217 2218 e1000e_update_flowctl_status(core); 2219 /* signal link status change to the guest */ 2220 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2221 } 2222 } 2223 2224 static inline uint16_t 2225 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2226 { 2227 uint16_t index = (addr & 0x1ffff) >> 2; 2228 return index + (mac_reg_access[index] & 0xfffe); 2229 } 2230 2231 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2232 [0] = { 2233 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2234 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2235 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2236 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2237 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2238 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2239 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2240 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2241 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2242 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2243 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2244 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2245 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2246 2247 [PHY_COPPER_CTRL1] = PHY_RW, 2248 [PHY_COPPER_STAT1] = PHY_R, 2249 [PHY_COPPER_CTRL3] = PHY_RW, 2250 [PHY_RX_ERR_CNTR] = PHY_R, 2251 [PHY_OEM_BITS] = PHY_RW, 2252 [PHY_BIAS_1] = PHY_RW, 2253 [PHY_BIAS_2] = PHY_RW, 2254 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2255 [PHY_COPPER_STAT2] = PHY_R, 2256 [PHY_COPPER_CTRL2] = PHY_RW 2257 }, 2258 [2] = { 2259 [PHY_MAC_CTRL1] = PHY_RW, 2260 [PHY_MAC_INT_ENABLE] = PHY_RW, 2261 [PHY_MAC_STAT] = PHY_R, 2262 [PHY_MAC_CTRL2] = PHY_RW 2263 }, 2264 [3] = { 2265 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2266 [PHY_LED_03_POL_CTRL] = PHY_RW, 2267 [PHY_LED_TIMER_CTRL] = PHY_RW, 2268 [PHY_LED_45_CTRL] = PHY_RW 2269 }, 2270 [5] = { 2271 [PHY_1000T_SKEW] = PHY_R, 2272 [PHY_1000T_SWAP] = PHY_R 2273 }, 2274 [6] = { 2275 [PHY_CRC_COUNTERS] = PHY_R 2276 } 2277 }; 2278 2279 static bool 2280 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2281 char cap, uint8_t *page) 2282 { 2283 *page = 2284 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2285 : core->phy[0][PHY_PAGE]; 2286 2287 if (*page >= E1000E_PHY_PAGES) { 2288 return false; 2289 } 2290 2291 return e1000e_phy_regcap[*page][addr] & cap; 2292 } 2293 2294 static void 2295 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2296 uint32_t addr, uint16_t data) 2297 { 2298 assert(page < E1000E_PHY_PAGES); 2299 assert(addr < E1000E_PHY_PAGE_SIZE); 2300 2301 if (e1000e_phyreg_writeops[page][addr]) { 2302 e1000e_phyreg_writeops[page][addr](core, addr, data); 2303 } else { 2304 core->phy[page][addr] = data; 2305 } 2306 } 2307 2308 static void 2309 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2310 { 2311 uint32_t data = val & E1000_MDIC_DATA_MASK; 2312 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2313 uint8_t page; 2314 2315 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2316 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2317 } else if (val & E1000_MDIC_OP_READ) { 2318 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2319 trace_e1000e_core_mdic_read_unhandled(page, addr); 2320 val |= E1000_MDIC_ERROR; 2321 } else { 2322 val = (val ^ data) | core->phy[page][addr]; 2323 trace_e1000e_core_mdic_read(page, addr, val); 2324 } 2325 } else if (val & E1000_MDIC_OP_WRITE) { 2326 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2327 trace_e1000e_core_mdic_write_unhandled(page, addr); 2328 val |= E1000_MDIC_ERROR; 2329 } else { 2330 trace_e1000e_core_mdic_write(page, addr, data); 2331 e1000e_phy_reg_write(core, page, addr, data); 2332 } 2333 } 2334 core->mac[MDIC] = val | E1000_MDIC_READY; 2335 2336 if (val & E1000_MDIC_INT_EN) { 2337 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2338 } 2339 } 2340 2341 static void 2342 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2343 { 2344 core->mac[index] = val & 0xffff; 2345 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2346 e1000e_start_recv(core); 2347 } 2348 2349 static void 2350 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2351 { 2352 if ((val & E1000_STATUS_PHYRA) == 0) { 2353 core->mac[index] &= ~E1000_STATUS_PHYRA; 2354 } 2355 } 2356 2357 static void 2358 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2359 { 2360 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2361 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2362 2363 /* Zero self-clearing bits */ 2364 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2365 core->mac[CTRL_EXT] = val; 2366 } 2367 2368 static void 2369 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2370 { 2371 int i; 2372 2373 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2374 2375 if (!msix_enabled(core->owner)) { 2376 return; 2377 } 2378 2379 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2380 if (core->mac[PBACLR] & BIT(i)) { 2381 msix_clr_pending(core->owner, i); 2382 } 2383 } 2384 } 2385 2386 static void 2387 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2388 { 2389 core->mac[FCRTH] = val & 0xFFF8; 2390 } 2391 2392 static void 2393 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2394 { 2395 core->mac[FCRTL] = val & 0x8000FFF8; 2396 } 2397 2398 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2399 static void \ 2400 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2401 { \ 2402 core->mac[index] = val & (BIT(num) - 1); \ 2403 } 2404 2405 E1000E_LOW_BITS_SET_FUNC(4) 2406 E1000E_LOW_BITS_SET_FUNC(6) 2407 E1000E_LOW_BITS_SET_FUNC(11) 2408 E1000E_LOW_BITS_SET_FUNC(12) 2409 E1000E_LOW_BITS_SET_FUNC(13) 2410 E1000E_LOW_BITS_SET_FUNC(16) 2411 2412 static void 2413 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2414 { 2415 core->mac[VET] = val & 0xffff; 2416 trace_e1000e_vlan_vet(core->mac[VET]); 2417 } 2418 2419 static void 2420 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2421 { 2422 core->mac[index] = val & E1000_XDLEN_MASK; 2423 } 2424 2425 static void 2426 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2427 { 2428 core->mac[index] = val & E1000_XDBAL_MASK; 2429 } 2430 2431 static void 2432 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2433 { 2434 E1000E_TxRing txr; 2435 core->mac[index] = val; 2436 2437 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2438 e1000e_tx_ring_init(core, &txr, 0); 2439 e1000e_start_xmit(core, &txr); 2440 } 2441 2442 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2443 e1000e_tx_ring_init(core, &txr, 1); 2444 e1000e_start_xmit(core, &txr); 2445 } 2446 } 2447 2448 static void 2449 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2450 { 2451 E1000E_TxRing txr; 2452 int qidx = e1000e_mq_queue_idx(TDT, index); 2453 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2454 2455 core->mac[index] = val & 0xffff; 2456 2457 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2458 e1000e_tx_ring_init(core, &txr, qidx); 2459 e1000e_start_xmit(core, &txr); 2460 } 2461 } 2462 2463 static void 2464 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2465 { 2466 trace_e1000e_irq_write_ics(val); 2467 e1000e_set_interrupt_cause(core, val); 2468 } 2469 2470 static void 2471 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2472 { 2473 uint32_t icr = 0; 2474 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2475 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2476 trace_e1000e_irq_icr_process_iame(); 2477 e1000e_clear_ims_bits(core, core->mac[IAM]); 2478 } 2479 2480 icr = core->mac[ICR] & ~val; 2481 /* 2482 * Windows driver expects that the "receive overrun" bit and other 2483 * ones to be cleared when the "Other" bit (#24) is cleared. 2484 */ 2485 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr; 2486 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); 2487 core->mac[ICR] = icr; 2488 e1000e_update_interrupt_state(core); 2489 } 2490 2491 static void 2492 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2493 { 2494 trace_e1000e_irq_ims_clear_set_imc(val); 2495 e1000e_clear_ims_bits(core, val); 2496 e1000e_update_interrupt_state(core); 2497 } 2498 2499 static void 2500 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2501 { 2502 static const uint32_t ims_ext_mask = 2503 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2504 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2505 E1000_IMS_OTHER; 2506 2507 static const uint32_t ims_valid_mask = 2508 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2509 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2510 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2511 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2512 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2513 E1000_IMS_OTHER; 2514 2515 uint32_t valid_val = val & ims_valid_mask; 2516 2517 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2518 core->mac[IMS] |= valid_val; 2519 2520 if ((valid_val & ims_ext_mask) && 2521 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2522 msix_enabled(core->owner)) { 2523 e1000e_msix_clear(core, valid_val); 2524 } 2525 2526 if ((valid_val == ims_valid_mask) && 2527 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2528 trace_e1000e_irq_fire_all_timers(val); 2529 e1000e_intrmgr_fire_all_timers(core); 2530 } 2531 2532 e1000e_update_interrupt_state(core); 2533 } 2534 2535 static void 2536 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2537 { 2538 e1000e_set_16bit(core, index, val); 2539 2540 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2541 trace_e1000e_irq_rdtr_fpd_running(); 2542 e1000e_intrmgr_fire_delayed_interrupts(core); 2543 } else { 2544 trace_e1000e_irq_rdtr_fpd_not_running(); 2545 } 2546 } 2547 2548 static void 2549 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2550 { 2551 e1000e_set_16bit(core, index, val); 2552 2553 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2554 trace_e1000e_irq_tidv_fpd_running(); 2555 e1000e_intrmgr_fire_delayed_interrupts(core); 2556 } else { 2557 trace_e1000e_irq_tidv_fpd_not_running(); 2558 } 2559 } 2560 2561 static uint32_t 2562 e1000e_mac_readreg(E1000ECore *core, int index) 2563 { 2564 return core->mac[index]; 2565 } 2566 2567 static uint32_t 2568 e1000e_mac_ics_read(E1000ECore *core, int index) 2569 { 2570 trace_e1000e_irq_read_ics(core->mac[ICS]); 2571 return core->mac[ICS]; 2572 } 2573 2574 static uint32_t 2575 e1000e_mac_ims_read(E1000ECore *core, int index) 2576 { 2577 trace_e1000e_irq_read_ims(core->mac[IMS]); 2578 return core->mac[IMS]; 2579 } 2580 2581 static uint32_t 2582 e1000e_mac_swsm_read(E1000ECore *core, int index) 2583 { 2584 uint32_t val = core->mac[SWSM]; 2585 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2586 return val; 2587 } 2588 2589 static uint32_t 2590 e1000e_mac_itr_read(E1000ECore *core, int index) 2591 { 2592 return core->itr_guest_value; 2593 } 2594 2595 static uint32_t 2596 e1000e_mac_eitr_read(E1000ECore *core, int index) 2597 { 2598 return core->eitr_guest_value[index - EITR]; 2599 } 2600 2601 static uint32_t 2602 e1000e_mac_icr_read(E1000ECore *core, int index) 2603 { 2604 uint32_t ret = core->mac[ICR]; 2605 trace_e1000e_irq_icr_read_entry(ret); 2606 2607 if (core->mac[IMS] == 0) { 2608 trace_e1000e_irq_icr_clear_zero_ims(); 2609 core->mac[ICR] = 0; 2610 } 2611 2612 if (!msix_enabled(core->owner)) { 2613 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2614 core->mac[ICR] = 0; 2615 } 2616 2617 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2618 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2619 trace_e1000e_irq_icr_clear_iame(); 2620 core->mac[ICR] = 0; 2621 trace_e1000e_irq_icr_process_iame(); 2622 e1000e_clear_ims_bits(core, core->mac[IAM]); 2623 } 2624 2625 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2626 e1000e_update_interrupt_state(core); 2627 return ret; 2628 } 2629 2630 static uint32_t 2631 e1000e_mac_read_clr4(E1000ECore *core, int index) 2632 { 2633 uint32_t ret = core->mac[index]; 2634 2635 core->mac[index] = 0; 2636 return ret; 2637 } 2638 2639 static uint32_t 2640 e1000e_mac_read_clr8(E1000ECore *core, int index) 2641 { 2642 uint32_t ret = core->mac[index]; 2643 2644 core->mac[index] = 0; 2645 core->mac[index - 1] = 0; 2646 return ret; 2647 } 2648 2649 static uint32_t 2650 e1000e_get_ctrl(E1000ECore *core, int index) 2651 { 2652 uint32_t val = core->mac[CTRL]; 2653 2654 trace_e1000e_link_read_params( 2655 !!(val & E1000_CTRL_ASDE), 2656 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2657 !!(val & E1000_CTRL_FRCSPD), 2658 !!(val & E1000_CTRL_FRCDPX), 2659 !!(val & E1000_CTRL_RFCE), 2660 !!(val & E1000_CTRL_TFCE)); 2661 2662 return val; 2663 } 2664 2665 static uint32_t 2666 e1000e_get_status(E1000ECore *core, int index) 2667 { 2668 uint32_t res = core->mac[STATUS]; 2669 2670 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2671 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2672 } 2673 2674 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2675 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2676 } else { 2677 res |= E1000_STATUS_FD; 2678 } 2679 2680 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2681 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2682 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2683 case E1000_CTRL_SPD_10: 2684 res |= E1000_STATUS_SPEED_10; 2685 break; 2686 case E1000_CTRL_SPD_100: 2687 res |= E1000_STATUS_SPEED_100; 2688 break; 2689 case E1000_CTRL_SPD_1000: 2690 default: 2691 res |= E1000_STATUS_SPEED_1000; 2692 break; 2693 } 2694 } else { 2695 res |= E1000_STATUS_SPEED_1000; 2696 } 2697 2698 trace_e1000e_link_status( 2699 !!(res & E1000_STATUS_LU), 2700 !!(res & E1000_STATUS_FD), 2701 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2702 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2703 2704 return res; 2705 } 2706 2707 static uint32_t 2708 e1000e_get_tarc(E1000ECore *core, int index) 2709 { 2710 return core->mac[index] & ((BIT(11) - 1) | 2711 BIT(27) | 2712 BIT(28) | 2713 BIT(29) | 2714 BIT(30)); 2715 } 2716 2717 static void 2718 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2719 { 2720 core->mac[index] = val; 2721 } 2722 2723 static void 2724 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2725 { 2726 uint32_t macaddr[2]; 2727 2728 core->mac[index] = val; 2729 2730 macaddr[0] = cpu_to_le32(core->mac[RA]); 2731 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2732 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2733 (uint8_t *) macaddr); 2734 2735 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2736 } 2737 2738 static void 2739 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2740 { 2741 static const uint32_t ro_bits = E1000_EECD_PRES | 2742 E1000_EECD_AUTO_RD | 2743 E1000_EECD_SIZE_EX_MASK; 2744 2745 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2746 } 2747 2748 static void 2749 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2750 { 2751 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2752 uint32_t flags = 0; 2753 uint32_t data = 0; 2754 2755 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2756 data = core->eeprom[addr]; 2757 flags = E1000_EERW_DONE; 2758 } 2759 2760 core->mac[EERD] = flags | 2761 (addr << E1000_EERW_ADDR_SHIFT) | 2762 (data << E1000_EERW_DATA_SHIFT); 2763 } 2764 2765 static void 2766 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2767 { 2768 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2769 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2770 uint32_t flags = 0; 2771 2772 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2773 core->eeprom[addr] = data; 2774 flags = E1000_EERW_DONE; 2775 } 2776 2777 core->mac[EERD] = flags | 2778 (addr << E1000_EERW_ADDR_SHIFT) | 2779 (data << E1000_EERW_DATA_SHIFT); 2780 } 2781 2782 static void 2783 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2784 { 2785 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2786 } 2787 2788 static void 2789 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2790 { 2791 uint32_t interval = val & 0xffff; 2792 2793 trace_e1000e_irq_itr_set(val); 2794 2795 core->itr_guest_value = interval; 2796 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2797 } 2798 2799 static void 2800 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2801 { 2802 uint32_t interval = val & 0xffff; 2803 uint32_t eitr_num = index - EITR; 2804 2805 trace_e1000e_irq_eitr_set(eitr_num, val); 2806 2807 core->eitr_guest_value[eitr_num] = interval; 2808 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2809 } 2810 2811 static void 2812 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2813 { 2814 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2815 2816 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2817 qemu_log_mask(LOG_GUEST_ERROR, 2818 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2819 return; 2820 } 2821 2822 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2823 qemu_log_mask(LOG_GUEST_ERROR, 2824 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2825 return; 2826 } 2827 } 2828 2829 core->mac[PSRCTL] = val; 2830 } 2831 2832 static void 2833 e1000e_update_rx_offloads(E1000ECore *core) 2834 { 2835 int cso_state = e1000e_rx_l4_cso_enabled(core); 2836 2837 trace_e1000e_rx_set_cso(cso_state); 2838 2839 if (core->has_vnet) { 2840 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2841 cso_state, 0, 0, 0, 0); 2842 } 2843 } 2844 2845 static void 2846 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2847 { 2848 core->mac[RXCSUM] = val; 2849 e1000e_update_rx_offloads(core); 2850 } 2851 2852 static void 2853 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2854 { 2855 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2856 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2857 } 2858 2859 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) 2860 { 2861 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2862 return core->mac[SYSTIML]; 2863 } 2864 2865 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) 2866 { 2867 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2868 return core->mac[RXSATRH]; 2869 } 2870 2871 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) 2872 { 2873 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2874 return core->mac[TXSTMPH]; 2875 } 2876 2877 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) 2878 { 2879 e1000x_set_timinca(core->mac, &core->timadj, val); 2880 } 2881 2882 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) 2883 { 2884 core->mac[TIMADJH] = val; 2885 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2886 } 2887 2888 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2889 typedef uint32_t (*readops)(E1000ECore *, int); 2890 static const readops e1000e_macreg_readops[] = { 2891 e1000e_getreg(PBA), 2892 e1000e_getreg(WUFC), 2893 e1000e_getreg(MANC), 2894 e1000e_getreg(TOTL), 2895 e1000e_getreg(RDT0), 2896 e1000e_getreg(RDBAH0), 2897 e1000e_getreg(TDBAL1), 2898 e1000e_getreg(RDLEN0), 2899 e1000e_getreg(RDH1), 2900 e1000e_getreg(LATECOL), 2901 e1000e_getreg(SEQEC), 2902 e1000e_getreg(XONTXC), 2903 e1000e_getreg(AIT), 2904 e1000e_getreg(TDFH), 2905 e1000e_getreg(TDFT), 2906 e1000e_getreg(TDFHS), 2907 e1000e_getreg(TDFTS), 2908 e1000e_getreg(TDFPC), 2909 e1000e_getreg(WUS), 2910 e1000e_getreg(PBS), 2911 e1000e_getreg(RDFH), 2912 e1000e_getreg(RDFT), 2913 e1000e_getreg(RDFHS), 2914 e1000e_getreg(RDFTS), 2915 e1000e_getreg(RDFPC), 2916 e1000e_getreg(GORCL), 2917 e1000e_getreg(MGTPRC), 2918 e1000e_getreg(EERD), 2919 e1000e_getreg(EIAC), 2920 e1000e_getreg(PSRCTL), 2921 e1000e_getreg(MANC2H), 2922 e1000e_getreg(RXCSUM), 2923 e1000e_getreg(GSCL_3), 2924 e1000e_getreg(GSCN_2), 2925 e1000e_getreg(RSRPD), 2926 e1000e_getreg(RDBAL1), 2927 e1000e_getreg(FCAH), 2928 e1000e_getreg(FCRTH), 2929 e1000e_getreg(FLOP), 2930 e1000e_getreg(FLASHT), 2931 e1000e_getreg(RXSTMPH), 2932 e1000e_getreg(TXSTMPL), 2933 e1000e_getreg(TIMADJL), 2934 e1000e_getreg(TXDCTL), 2935 e1000e_getreg(RDH0), 2936 e1000e_getreg(TDT1), 2937 e1000e_getreg(TNCRS), 2938 e1000e_getreg(RJC), 2939 e1000e_getreg(IAM), 2940 e1000e_getreg(GSCL_2), 2941 e1000e_getreg(RDBAH1), 2942 e1000e_getreg(FLSWDATA), 2943 e1000e_getreg(TIPG), 2944 e1000e_getreg(FLMNGCTL), 2945 e1000e_getreg(FLMNGCNT), 2946 e1000e_getreg(TSYNCTXCTL), 2947 e1000e_getreg(EXTCNF_SIZE), 2948 e1000e_getreg(EXTCNF_CTRL), 2949 e1000e_getreg(EEMNGDATA), 2950 e1000e_getreg(CTRL_EXT), 2951 e1000e_getreg(SYSTIMH), 2952 e1000e_getreg(EEMNGCTL), 2953 e1000e_getreg(FLMNGDATA), 2954 e1000e_getreg(TSYNCRXCTL), 2955 e1000e_getreg(TDH), 2956 e1000e_getreg(LEDCTL), 2957 e1000e_getreg(TCTL), 2958 e1000e_getreg(TDBAL), 2959 e1000e_getreg(TDLEN), 2960 e1000e_getreg(TDH1), 2961 e1000e_getreg(RADV), 2962 e1000e_getreg(ECOL), 2963 e1000e_getreg(DC), 2964 e1000e_getreg(RLEC), 2965 e1000e_getreg(XOFFTXC), 2966 e1000e_getreg(RFC), 2967 e1000e_getreg(RNBC), 2968 e1000e_getreg(MGTPTC), 2969 e1000e_getreg(TIMINCA), 2970 e1000e_getreg(RXCFGL), 2971 e1000e_getreg(MFUTP01), 2972 e1000e_getreg(FACTPS), 2973 e1000e_getreg(GSCL_1), 2974 e1000e_getreg(GSCN_0), 2975 e1000e_getreg(GCR2), 2976 e1000e_getreg(RDT1), 2977 e1000e_getreg(PBACLR), 2978 e1000e_getreg(FCTTV), 2979 e1000e_getreg(EEWR), 2980 e1000e_getreg(FLSWCTL), 2981 e1000e_getreg(RXDCTL1), 2982 e1000e_getreg(RXSATRL), 2983 e1000e_getreg(RXUDP), 2984 e1000e_getreg(TORL), 2985 e1000e_getreg(TDLEN1), 2986 e1000e_getreg(MCC), 2987 e1000e_getreg(WUC), 2988 e1000e_getreg(EECD), 2989 e1000e_getreg(MFUTP23), 2990 e1000e_getreg(RAID), 2991 e1000e_getreg(FCRTV), 2992 e1000e_getreg(TXDCTL1), 2993 e1000e_getreg(RCTL), 2994 e1000e_getreg(TDT), 2995 e1000e_getreg(MDIC), 2996 e1000e_getreg(FCRUC), 2997 e1000e_getreg(VET), 2998 e1000e_getreg(RDBAL0), 2999 e1000e_getreg(TDBAH1), 3000 e1000e_getreg(RDTR), 3001 e1000e_getreg(SCC), 3002 e1000e_getreg(COLC), 3003 e1000e_getreg(CEXTERR), 3004 e1000e_getreg(XOFFRXC), 3005 e1000e_getreg(IPAV), 3006 e1000e_getreg(GOTCL), 3007 e1000e_getreg(MGTPDC), 3008 e1000e_getreg(GCR), 3009 e1000e_getreg(IVAR), 3010 e1000e_getreg(POEMB), 3011 e1000e_getreg(MFVAL), 3012 e1000e_getreg(FUNCTAG), 3013 e1000e_getreg(GSCL_4), 3014 e1000e_getreg(GSCN_3), 3015 e1000e_getreg(MRQC), 3016 e1000e_getreg(RDLEN1), 3017 e1000e_getreg(FCT), 3018 e1000e_getreg(FLA), 3019 e1000e_getreg(FLOL), 3020 e1000e_getreg(RXDCTL), 3021 e1000e_getreg(RXSTMPL), 3022 e1000e_getreg(TIMADJH), 3023 e1000e_getreg(FCRTL), 3024 e1000e_getreg(TDBAH), 3025 e1000e_getreg(TADV), 3026 e1000e_getreg(XONRXC), 3027 e1000e_getreg(TSCTFC), 3028 e1000e_getreg(RFCTL), 3029 e1000e_getreg(GSCN_1), 3030 e1000e_getreg(FCAL), 3031 e1000e_getreg(FLSWCNT), 3032 3033 [TOTH] = e1000e_mac_read_clr8, 3034 [GOTCH] = e1000e_mac_read_clr8, 3035 [PRC64] = e1000e_mac_read_clr4, 3036 [PRC255] = e1000e_mac_read_clr4, 3037 [PRC1023] = e1000e_mac_read_clr4, 3038 [PTC64] = e1000e_mac_read_clr4, 3039 [PTC255] = e1000e_mac_read_clr4, 3040 [PTC1023] = e1000e_mac_read_clr4, 3041 [GPRC] = e1000e_mac_read_clr4, 3042 [TPT] = e1000e_mac_read_clr4, 3043 [RUC] = e1000e_mac_read_clr4, 3044 [BPRC] = e1000e_mac_read_clr4, 3045 [MPTC] = e1000e_mac_read_clr4, 3046 [IAC] = e1000e_mac_read_clr4, 3047 [ICR] = e1000e_mac_icr_read, 3048 [STATUS] = e1000e_get_status, 3049 [TARC0] = e1000e_get_tarc, 3050 [ICS] = e1000e_mac_ics_read, 3051 [TORH] = e1000e_mac_read_clr8, 3052 [GORCH] = e1000e_mac_read_clr8, 3053 [PRC127] = e1000e_mac_read_clr4, 3054 [PRC511] = e1000e_mac_read_clr4, 3055 [PRC1522] = e1000e_mac_read_clr4, 3056 [PTC127] = e1000e_mac_read_clr4, 3057 [PTC511] = e1000e_mac_read_clr4, 3058 [PTC1522] = e1000e_mac_read_clr4, 3059 [GPTC] = e1000e_mac_read_clr4, 3060 [TPR] = e1000e_mac_read_clr4, 3061 [ROC] = e1000e_mac_read_clr4, 3062 [MPRC] = e1000e_mac_read_clr4, 3063 [BPTC] = e1000e_mac_read_clr4, 3064 [TSCTC] = e1000e_mac_read_clr4, 3065 [ITR] = e1000e_mac_itr_read, 3066 [CTRL] = e1000e_get_ctrl, 3067 [TARC1] = e1000e_get_tarc, 3068 [SWSM] = e1000e_mac_swsm_read, 3069 [IMS] = e1000e_mac_ims_read, 3070 [SYSTIML] = e1000e_get_systiml, 3071 [RXSATRH] = e1000e_get_rxsatrh, 3072 [TXSTMPH] = e1000e_get_txstmph, 3073 3074 [CRCERRS ... MPC] = e1000e_mac_readreg, 3075 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3076 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3077 [RA ... RA + 31] = e1000e_mac_readreg, 3078 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3079 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3080 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3081 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3082 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3083 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3084 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3085 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3086 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3087 [RETA ... RETA + 31] = e1000e_mac_readreg, 3088 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3089 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3090 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3091 }; 3092 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3093 3094 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3095 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3096 static const writeops e1000e_macreg_writeops[] = { 3097 e1000e_putreg(PBA), 3098 e1000e_putreg(SWSM), 3099 e1000e_putreg(WUFC), 3100 e1000e_putreg(RDBAH1), 3101 e1000e_putreg(TDBAH), 3102 e1000e_putreg(TXDCTL), 3103 e1000e_putreg(RDBAH0), 3104 e1000e_putreg(LEDCTL), 3105 e1000e_putreg(FCAL), 3106 e1000e_putreg(FCRUC), 3107 e1000e_putreg(WUC), 3108 e1000e_putreg(WUS), 3109 e1000e_putreg(IPAV), 3110 e1000e_putreg(TDBAH1), 3111 e1000e_putreg(IAM), 3112 e1000e_putreg(EIAC), 3113 e1000e_putreg(IVAR), 3114 e1000e_putreg(TARC0), 3115 e1000e_putreg(TARC1), 3116 e1000e_putreg(FLSWDATA), 3117 e1000e_putreg(POEMB), 3118 e1000e_putreg(MFUTP01), 3119 e1000e_putreg(MFUTP23), 3120 e1000e_putreg(MANC), 3121 e1000e_putreg(MANC2H), 3122 e1000e_putreg(MFVAL), 3123 e1000e_putreg(EXTCNF_CTRL), 3124 e1000e_putreg(FACTPS), 3125 e1000e_putreg(FUNCTAG), 3126 e1000e_putreg(GSCL_1), 3127 e1000e_putreg(GSCL_2), 3128 e1000e_putreg(GSCL_3), 3129 e1000e_putreg(GSCL_4), 3130 e1000e_putreg(GSCN_0), 3131 e1000e_putreg(GSCN_1), 3132 e1000e_putreg(GSCN_2), 3133 e1000e_putreg(GSCN_3), 3134 e1000e_putreg(GCR2), 3135 e1000e_putreg(MRQC), 3136 e1000e_putreg(FLOP), 3137 e1000e_putreg(FLOL), 3138 e1000e_putreg(FLSWCTL), 3139 e1000e_putreg(FLSWCNT), 3140 e1000e_putreg(FLA), 3141 e1000e_putreg(RXDCTL1), 3142 e1000e_putreg(TXDCTL1), 3143 e1000e_putreg(TIPG), 3144 e1000e_putreg(RXSTMPH), 3145 e1000e_putreg(RXSTMPL), 3146 e1000e_putreg(RXSATRL), 3147 e1000e_putreg(RXSATRH), 3148 e1000e_putreg(TXSTMPL), 3149 e1000e_putreg(TXSTMPH), 3150 e1000e_putreg(SYSTIML), 3151 e1000e_putreg(SYSTIMH), 3152 e1000e_putreg(TIMADJL), 3153 e1000e_putreg(RXUDP), 3154 e1000e_putreg(RXCFGL), 3155 e1000e_putreg(TSYNCRXCTL), 3156 e1000e_putreg(TSYNCTXCTL), 3157 e1000e_putreg(EXTCNF_SIZE), 3158 e1000e_putreg(EEMNGCTL), 3159 e1000e_putreg(RA), 3160 3161 [TDH1] = e1000e_set_16bit, 3162 [TDT1] = e1000e_set_tdt, 3163 [TCTL] = e1000e_set_tctl, 3164 [TDT] = e1000e_set_tdt, 3165 [MDIC] = e1000e_set_mdic, 3166 [ICS] = e1000e_set_ics, 3167 [TDH] = e1000e_set_16bit, 3168 [RDH0] = e1000e_set_16bit, 3169 [RDT0] = e1000e_set_rdt, 3170 [IMC] = e1000e_set_imc, 3171 [IMS] = e1000e_set_ims, 3172 [ICR] = e1000e_set_icr, 3173 [EECD] = e1000e_set_eecd, 3174 [RCTL] = e1000e_set_rx_control, 3175 [CTRL] = e1000e_set_ctrl, 3176 [RDTR] = e1000e_set_rdtr, 3177 [RADV] = e1000e_set_16bit, 3178 [TADV] = e1000e_set_16bit, 3179 [ITR] = e1000e_set_itr, 3180 [EERD] = e1000e_set_eerd, 3181 [AIT] = e1000e_set_16bit, 3182 [TDFH] = e1000e_set_13bit, 3183 [TDFT] = e1000e_set_13bit, 3184 [TDFHS] = e1000e_set_13bit, 3185 [TDFTS] = e1000e_set_13bit, 3186 [TDFPC] = e1000e_set_13bit, 3187 [RDFH] = e1000e_set_13bit, 3188 [RDFHS] = e1000e_set_13bit, 3189 [RDFT] = e1000e_set_13bit, 3190 [RDFTS] = e1000e_set_13bit, 3191 [RDFPC] = e1000e_set_13bit, 3192 [PBS] = e1000e_set_6bit, 3193 [GCR] = e1000e_set_gcr, 3194 [PSRCTL] = e1000e_set_psrctl, 3195 [RXCSUM] = e1000e_set_rxcsum, 3196 [RAID] = e1000e_set_16bit, 3197 [RSRPD] = e1000e_set_12bit, 3198 [TIDV] = e1000e_set_tidv, 3199 [TDLEN1] = e1000e_set_dlen, 3200 [TDLEN] = e1000e_set_dlen, 3201 [RDLEN0] = e1000e_set_dlen, 3202 [RDLEN1] = e1000e_set_dlen, 3203 [TDBAL] = e1000e_set_dbal, 3204 [TDBAL1] = e1000e_set_dbal, 3205 [RDBAL0] = e1000e_set_dbal, 3206 [RDBAL1] = e1000e_set_dbal, 3207 [RDH1] = e1000e_set_16bit, 3208 [RDT1] = e1000e_set_rdt, 3209 [STATUS] = e1000e_set_status, 3210 [PBACLR] = e1000e_set_pbaclr, 3211 [CTRL_EXT] = e1000e_set_ctrlext, 3212 [FCAH] = e1000e_set_16bit, 3213 [FCT] = e1000e_set_16bit, 3214 [FCTTV] = e1000e_set_16bit, 3215 [FCRTV] = e1000e_set_16bit, 3216 [FCRTH] = e1000e_set_fcrth, 3217 [FCRTL] = e1000e_set_fcrtl, 3218 [VET] = e1000e_set_vet, 3219 [RXDCTL] = e1000e_set_rxdctl, 3220 [FLASHT] = e1000e_set_16bit, 3221 [EEWR] = e1000e_set_eewr, 3222 [CTRL_DUP] = e1000e_set_ctrl, 3223 [RFCTL] = e1000e_set_rfctl, 3224 [RA + 1] = e1000e_mac_setmacaddr, 3225 [TIMINCA] = e1000e_set_timinca, 3226 [TIMADJH] = e1000e_set_timadjh, 3227 3228 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3229 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3230 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3231 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3232 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3233 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3234 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3235 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3236 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3237 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3238 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3239 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3240 [RETA ... RETA + 31] = e1000e_mac_writereg, 3241 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3242 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3243 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3244 }; 3245 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3246 3247 enum { MAC_ACCESS_PARTIAL = 1 }; 3248 3249 /* 3250 * The array below combines alias offsets of the index values for the 3251 * MAC registers that have aliases, with the indication of not fully 3252 * implemented registers (lowest bit). This combination is possible 3253 * because all of the offsets are even. 3254 */ 3255 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3256 /* Alias index offsets */ 3257 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3258 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3259 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3260 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3261 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3262 [RA_A ... RA_A + 31] = 0x14f0, 3263 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3264 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3265 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3266 /* Access options */ 3267 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3268 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3269 [RDFPC] = MAC_ACCESS_PARTIAL, 3270 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3271 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3272 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3273 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3274 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3275 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3276 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3277 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3278 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3279 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3280 }; 3281 3282 void 3283 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3284 { 3285 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3286 3287 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3288 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3289 trace_e1000e_wrn_regs_write_trivial(index << 2); 3290 } 3291 trace_e1000e_core_write(index << 2, size, val); 3292 e1000e_macreg_writeops[index](core, index, val); 3293 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3294 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3295 } else { 3296 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3297 } 3298 } 3299 3300 uint64_t 3301 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3302 { 3303 uint64_t val; 3304 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3305 3306 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3307 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3308 trace_e1000e_wrn_regs_read_trivial(index << 2); 3309 } 3310 val = e1000e_macreg_readops[index](core, index); 3311 trace_e1000e_core_read(index << 2, size, val); 3312 return val; 3313 } else { 3314 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3315 } 3316 return 0; 3317 } 3318 3319 static inline void 3320 e1000e_autoneg_pause(E1000ECore *core) 3321 { 3322 timer_del(core->autoneg_timer); 3323 } 3324 3325 static void 3326 e1000e_autoneg_resume(E1000ECore *core) 3327 { 3328 if (e1000e_have_autoneg(core) && 3329 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3330 qemu_get_queue(core->owner_nic)->link_down = false; 3331 timer_mod(core->autoneg_timer, 3332 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3333 } 3334 } 3335 3336 static void 3337 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3338 { 3339 E1000ECore *core = opaque; 3340 3341 if (running) { 3342 trace_e1000e_vm_state_running(); 3343 e1000e_intrmgr_resume(core); 3344 e1000e_autoneg_resume(core); 3345 } else { 3346 trace_e1000e_vm_state_stopped(); 3347 e1000e_autoneg_pause(core); 3348 e1000e_intrmgr_pause(core); 3349 } 3350 } 3351 3352 void 3353 e1000e_core_pci_realize(E1000ECore *core, 3354 const uint16_t *eeprom_templ, 3355 uint32_t eeprom_size, 3356 const uint8_t *macaddr) 3357 { 3358 int i; 3359 3360 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3361 e1000e_autoneg_timer, core); 3362 e1000e_intrmgr_pci_realize(core); 3363 3364 core->vmstate = 3365 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3366 3367 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3368 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3369 } 3370 3371 net_rx_pkt_init(&core->rx_pkt); 3372 3373 e1000x_core_prepare_eeprom(core->eeprom, 3374 eeprom_templ, 3375 eeprom_size, 3376 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3377 macaddr); 3378 e1000e_update_rx_offloads(core); 3379 } 3380 3381 void 3382 e1000e_core_pci_uninit(E1000ECore *core) 3383 { 3384 int i; 3385 3386 timer_free(core->autoneg_timer); 3387 3388 e1000e_intrmgr_pci_unint(core); 3389 3390 qemu_del_vm_change_state_handler(core->vmstate); 3391 3392 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3393 net_tx_pkt_reset(core->tx[i].tx_pkt, 3394 net_tx_pkt_unmap_frag_pci, core->owner); 3395 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3396 } 3397 3398 net_rx_pkt_uninit(core->rx_pkt); 3399 } 3400 3401 static const uint16_t 3402 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3403 [0] = { 3404 [MII_BMCR] = MII_BMCR_SPEED1000 | 3405 MII_BMCR_FD | 3406 MII_BMCR_AUTOEN, 3407 3408 [MII_BMSR] = MII_BMSR_EXTCAP | 3409 MII_BMSR_LINK_ST | 3410 MII_BMSR_AUTONEG | 3411 MII_BMSR_MFPS | 3412 MII_BMSR_EXTSTAT | 3413 MII_BMSR_10T_HD | 3414 MII_BMSR_10T_FD | 3415 MII_BMSR_100TX_HD | 3416 MII_BMSR_100TX_FD, 3417 3418 [MII_PHYID1] = 0x141, 3419 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3420 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3421 MII_ANAR_10FD | MII_ANAR_TX | 3422 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3423 MII_ANAR_PAUSE_ASYM, 3424 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3425 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3426 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3427 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3428 [MII_ANNP] = 1 | MII_ANNP_MP, 3429 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3430 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3431 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3432 MII_STAT1000_ROK | MII_STAT1000_LOK, 3433 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3434 3435 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3436 BIT(12) | BIT(13), 3437 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3438 }, 3439 [2] = { 3440 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3441 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3442 }, 3443 [3] = { 3444 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3445 } 3446 }; 3447 3448 static const uint32_t e1000e_mac_reg_init[] = { 3449 [PBA] = 0x00140014, 3450 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3451 [EXTCNF_CTRL] = BIT(3), 3452 [EEMNGCTL] = BIT(31), 3453 [FLASHT] = 0x2, 3454 [FLSWCTL] = BIT(30) | BIT(31), 3455 [FLOL] = BIT(0), 3456 [RXDCTL] = BIT(16), 3457 [RXDCTL1] = BIT(16), 3458 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3459 [RXCFGL] = 0x88F7, 3460 [RXUDP] = 0x319, 3461 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3462 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3463 E1000_CTRL_ADVD3WUC, 3464 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3465 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3466 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3467 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3468 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3469 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3470 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3471 [EERD] = E1000_EERW_DONE, 3472 [EEWR] = E1000_EERW_DONE, 3473 [GCR] = E1000_L0S_ADJUST | 3474 E1000_L1_ENTRY_LATENCY_MSB | 3475 E1000_L1_ENTRY_LATENCY_LSB, 3476 [TDFH] = 0x600, 3477 [TDFT] = 0x600, 3478 [TDFHS] = 0x600, 3479 [TDFTS] = 0x600, 3480 [POEMB] = 0x30D, 3481 [PBS] = 0x028, 3482 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3483 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3484 [SWSM] = 1, 3485 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3486 [ITR] = E1000E_MIN_XITR, 3487 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3488 }; 3489 3490 static void e1000e_reset(E1000ECore *core, bool sw) 3491 { 3492 int i; 3493 3494 timer_del(core->autoneg_timer); 3495 3496 e1000e_intrmgr_reset(core); 3497 3498 memset(core->phy, 0, sizeof core->phy); 3499 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3500 3501 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3502 if (sw && (i == PBA || i == PBS || i == FLA)) { 3503 continue; 3504 } 3505 3506 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3507 e1000e_mac_reg_init[i] : 0; 3508 } 3509 3510 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3511 3512 if (qemu_get_queue(core->owner_nic)->link_down) { 3513 e1000e_link_down(core); 3514 } 3515 3516 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3517 3518 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3519 net_tx_pkt_reset(core->tx[i].tx_pkt, 3520 net_tx_pkt_unmap_frag_pci, core->owner); 3521 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3522 core->tx[i].skip_cp = false; 3523 } 3524 } 3525 3526 void 3527 e1000e_core_reset(E1000ECore *core) 3528 { 3529 e1000e_reset(core, false); 3530 } 3531 3532 void e1000e_core_pre_save(E1000ECore *core) 3533 { 3534 int i; 3535 NetClientState *nc = qemu_get_queue(core->owner_nic); 3536 3537 /* 3538 * If link is down and auto-negotiation is supported and ongoing, 3539 * complete auto-negotiation immediately. This allows us to look 3540 * at MII_BMSR_AN_COMP to infer link status on load. 3541 */ 3542 if (nc->link_down && e1000e_have_autoneg(core)) { 3543 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3544 e1000e_update_flowctl_status(core); 3545 } 3546 3547 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3548 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3549 core->tx[i].skip_cp = true; 3550 } 3551 } 3552 } 3553 3554 int 3555 e1000e_core_post_load(E1000ECore *core) 3556 { 3557 NetClientState *nc = qemu_get_queue(core->owner_nic); 3558 3559 /* 3560 * nc.link_down can't be migrated, so infer link_down according 3561 * to link status bit in core.mac[STATUS]. 3562 */ 3563 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3564 3565 return 0; 3566 } 3567