1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000_common.h" 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 55 #define E1000E_MIN_XITR (500) 56 57 #define E1000E_MAX_TX_FRAGS (64) 58 59 union e1000_rx_desc_union { 60 struct e1000_rx_desc legacy; 61 union e1000_rx_desc_extended extended; 62 union e1000_rx_desc_packet_split packet_split; 63 }; 64 65 static ssize_t 66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 67 bool has_vnet); 68 69 static inline void 70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 71 72 static void e1000e_reset(E1000ECore *core, bool sw); 73 74 static inline void 75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 76 { 77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 78 trace_e1000e_wrn_no_ts_support(); 79 } 80 } 81 82 static inline void 83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 84 { 85 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 86 trace_e1000e_wrn_no_snap_support(); 87 } 88 } 89 90 static inline void 91 e1000e_raise_legacy_irq(E1000ECore *core) 92 { 93 trace_e1000e_irq_legacy_notify(true); 94 e1000x_inc_reg_if_not_full(core->mac, IAC); 95 pci_set_irq(core->owner, 1); 96 } 97 98 static inline void 99 e1000e_lower_legacy_irq(E1000ECore *core) 100 { 101 trace_e1000e_irq_legacy_notify(false); 102 pci_set_irq(core->owner, 0); 103 } 104 105 static inline void 106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 107 { 108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 109 timer->delay_resolution_ns; 110 111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 112 113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 114 115 timer->running = true; 116 } 117 118 static void 119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 e1000e_intrmgr_rearm_timer(timer); 123 } 124 } 125 126 static void 127 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 128 { 129 if (timer->running) { 130 timer_del(timer->timer); 131 } 132 } 133 134 static inline void 135 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 136 { 137 if (timer->running) { 138 timer_del(timer->timer); 139 timer->running = false; 140 } 141 } 142 143 static inline void 144 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 145 { 146 trace_e1000e_irq_fire_delayed_interrupts(); 147 e1000e_set_interrupt_cause(core, 0); 148 } 149 150 static void 151 e1000e_intrmgr_on_timer(void *opaque) 152 { 153 E1000IntrDelayTimer *timer = opaque; 154 155 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 156 157 timer->running = false; 158 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 159 } 160 161 static void 162 e1000e_intrmgr_on_throttling_timer(void *opaque) 163 { 164 E1000IntrDelayTimer *timer = opaque; 165 166 timer->running = false; 167 168 if (timer->core->mac[IMS] & timer->core->mac[ICR]) { 169 if (msi_enabled(timer->core->owner)) { 170 trace_e1000e_irq_msi_notify_postponed(); 171 msi_notify(timer->core->owner, 0); 172 } else { 173 trace_e1000e_irq_legacy_notify_postponed(); 174 e1000e_raise_legacy_irq(timer->core); 175 } 176 } 177 } 178 179 static void 180 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 181 { 182 E1000IntrDelayTimer *timer = opaque; 183 int idx = timer - &timer->core->eitr[0]; 184 185 timer->running = false; 186 187 trace_e1000e_irq_msix_notify_postponed_vec(idx); 188 msix_notify(timer->core->owner, idx); 189 } 190 191 static void 192 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 193 { 194 int i; 195 196 core->radv.delay_reg = RADV; 197 core->rdtr.delay_reg = RDTR; 198 core->raid.delay_reg = RAID; 199 core->tadv.delay_reg = TADV; 200 core->tidv.delay_reg = TIDV; 201 202 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 207 208 core->radv.core = core; 209 core->rdtr.core = core; 210 core->raid.core = core; 211 core->tadv.core = core; 212 core->tidv.core = core; 213 214 core->itr.core = core; 215 core->itr.delay_reg = ITR; 216 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 217 218 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 219 core->eitr[i].core = core; 220 core->eitr[i].delay_reg = EITR + i; 221 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 222 } 223 224 if (!create) { 225 return; 226 } 227 228 core->radv.timer = 229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 230 core->rdtr.timer = 231 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 232 core->raid.timer = 233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 234 235 core->tadv.timer = 236 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 237 core->tidv.timer = 238 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 239 240 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 241 e1000e_intrmgr_on_throttling_timer, 242 &core->itr); 243 244 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 245 core->eitr[i].timer = 246 timer_new_ns(QEMU_CLOCK_VIRTUAL, 247 e1000e_intrmgr_on_msix_throttling_timer, 248 &core->eitr[i]); 249 } 250 } 251 252 static inline void 253 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 254 { 255 e1000e_intrmgr_stop_timer(&core->radv); 256 e1000e_intrmgr_stop_timer(&core->rdtr); 257 e1000e_intrmgr_stop_timer(&core->raid); 258 e1000e_intrmgr_stop_timer(&core->tidv); 259 e1000e_intrmgr_stop_timer(&core->tadv); 260 } 261 262 static bool 263 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 264 { 265 uint32_t delayable_causes; 266 uint32_t rdtr = core->mac[RDTR]; 267 uint32_t radv = core->mac[RADV]; 268 uint32_t raid = core->mac[RAID]; 269 270 if (msix_enabled(core->owner)) { 271 return false; 272 } 273 274 delayable_causes = E1000_ICR_RXQ0 | 275 E1000_ICR_RXQ1 | 276 E1000_ICR_RXT0; 277 278 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 279 delayable_causes |= E1000_ICR_ACK; 280 } 281 282 /* Clean up all causes that may be delayed */ 283 core->delayed_causes |= *causes & delayable_causes; 284 *causes &= ~delayable_causes; 285 286 /* 287 * Check if delayed RX interrupts disabled by client 288 * or if there are causes that cannot be delayed 289 */ 290 if ((rdtr == 0) || (*causes != 0)) { 291 return false; 292 } 293 294 /* 295 * Check if delayed RX ACK interrupts disabled by client 296 * and there is an ACK packet received 297 */ 298 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 299 return false; 300 } 301 302 /* All causes delayed */ 303 e1000e_intrmgr_rearm_timer(&core->rdtr); 304 305 if (!core->radv.running && (radv != 0)) { 306 e1000e_intrmgr_rearm_timer(&core->radv); 307 } 308 309 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 310 e1000e_intrmgr_rearm_timer(&core->raid); 311 } 312 313 return true; 314 } 315 316 static bool 317 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 318 { 319 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 320 E1000_ICR_TXQ1 | 321 E1000_ICR_TXQE | 322 E1000_ICR_TXDW; 323 324 if (msix_enabled(core->owner)) { 325 return false; 326 } 327 328 /* Clean up all causes that may be delayed */ 329 core->delayed_causes |= *causes & delayable_causes; 330 *causes &= ~delayable_causes; 331 332 /* If there are causes that cannot be delayed */ 333 if (*causes != 0) { 334 return false; 335 } 336 337 /* All causes delayed */ 338 e1000e_intrmgr_rearm_timer(&core->tidv); 339 340 if (!core->tadv.running && (core->mac[TADV] != 0)) { 341 e1000e_intrmgr_rearm_timer(&core->tadv); 342 } 343 344 return true; 345 } 346 347 static uint32_t 348 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 349 { 350 uint32_t res; 351 352 if (msix_enabled(core->owner)) { 353 assert(core->delayed_causes == 0); 354 return 0; 355 } 356 357 res = core->delayed_causes; 358 core->delayed_causes = 0; 359 360 e1000e_intrmgr_stop_delay_timers(core); 361 362 return res; 363 } 364 365 static void 366 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 367 { 368 int i; 369 370 if (core->itr.running) { 371 timer_del(core->itr.timer); 372 e1000e_intrmgr_on_throttling_timer(&core->itr); 373 } 374 375 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 376 if (core->eitr[i].running) { 377 timer_del(core->eitr[i].timer); 378 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 379 } 380 } 381 } 382 383 static void 384 e1000e_intrmgr_resume(E1000ECore *core) 385 { 386 int i; 387 388 e1000e_intmgr_timer_resume(&core->radv); 389 e1000e_intmgr_timer_resume(&core->rdtr); 390 e1000e_intmgr_timer_resume(&core->raid); 391 e1000e_intmgr_timer_resume(&core->tidv); 392 e1000e_intmgr_timer_resume(&core->tadv); 393 394 e1000e_intmgr_timer_resume(&core->itr); 395 396 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 397 e1000e_intmgr_timer_resume(&core->eitr[i]); 398 } 399 } 400 401 static void 402 e1000e_intrmgr_pause(E1000ECore *core) 403 { 404 int i; 405 406 e1000e_intmgr_timer_pause(&core->radv); 407 e1000e_intmgr_timer_pause(&core->rdtr); 408 e1000e_intmgr_timer_pause(&core->raid); 409 e1000e_intmgr_timer_pause(&core->tidv); 410 e1000e_intmgr_timer_pause(&core->tadv); 411 412 e1000e_intmgr_timer_pause(&core->itr); 413 414 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 415 e1000e_intmgr_timer_pause(&core->eitr[i]); 416 } 417 } 418 419 static void 420 e1000e_intrmgr_reset(E1000ECore *core) 421 { 422 int i; 423 424 core->delayed_causes = 0; 425 426 e1000e_intrmgr_stop_delay_timers(core); 427 428 e1000e_intrmgr_stop_timer(&core->itr); 429 430 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 431 e1000e_intrmgr_stop_timer(&core->eitr[i]); 432 } 433 } 434 435 static void 436 e1000e_intrmgr_pci_unint(E1000ECore *core) 437 { 438 int i; 439 440 timer_free(core->radv.timer); 441 timer_free(core->rdtr.timer); 442 timer_free(core->raid.timer); 443 444 timer_free(core->tadv.timer); 445 timer_free(core->tidv.timer); 446 447 timer_free(core->itr.timer); 448 449 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 450 timer_free(core->eitr[i].timer); 451 } 452 } 453 454 static void 455 e1000e_intrmgr_pci_realize(E1000ECore *core) 456 { 457 e1000e_intrmgr_initialize_all_timers(core, true); 458 } 459 460 static inline bool 461 e1000e_rx_csum_enabled(E1000ECore *core) 462 { 463 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 464 } 465 466 static inline bool 467 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 468 { 469 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 470 } 471 472 static inline bool 473 e1000e_rx_use_ps_descriptor(E1000ECore *core) 474 { 475 return !e1000e_rx_use_legacy_descriptor(core) && 476 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 477 } 478 479 static inline bool 480 e1000e_rss_enabled(E1000ECore *core) 481 { 482 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 483 !e1000e_rx_csum_enabled(core) && 484 !e1000e_rx_use_legacy_descriptor(core); 485 } 486 487 typedef struct E1000E_RSSInfo_st { 488 bool enabled; 489 uint32_t hash; 490 uint32_t queue; 491 uint32_t type; 492 } E1000E_RSSInfo; 493 494 static uint32_t 495 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 496 { 497 bool hasip4, hasip6; 498 EthL4HdrProto l4hdr_proto; 499 500 assert(e1000e_rss_enabled(core)); 501 502 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 503 504 if (hasip4) { 505 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 506 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 507 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 508 509 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 511 return E1000_MRQ_RSS_TYPE_IPV4TCP; 512 } 513 514 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 515 return E1000_MRQ_RSS_TYPE_IPV4; 516 } 517 } else if (hasip6) { 518 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 519 520 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 521 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 522 523 /* 524 * Following two traces must not be combined because resulting 525 * event will have 11 arguments totally and some trace backends 526 * (at least "ust") have limitation of maximum 10 arguments per 527 * event. Events with more arguments fail to compile for 528 * backends like these. 529 */ 530 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 531 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 532 ip6info->has_ext_hdrs, 533 ip6info->rss_ex_dst_valid, 534 ip6info->rss_ex_src_valid, 535 core->mac[MRQC], 536 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), 537 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 538 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 539 540 if ((!ex_dis || !ip6info->has_ext_hdrs) && 541 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 542 ip6info->rss_ex_src_valid))) { 543 544 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 545 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { 546 return E1000_MRQ_RSS_TYPE_IPV6TCPEX; 547 } 548 549 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 550 return E1000_MRQ_RSS_TYPE_IPV6EX; 551 } 552 553 } 554 555 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 556 return E1000_MRQ_RSS_TYPE_IPV6; 557 } 558 559 } 560 561 return E1000_MRQ_RSS_TYPE_NONE; 562 } 563 564 static uint32_t 565 e1000e_rss_calc_hash(E1000ECore *core, 566 struct NetRxPkt *pkt, 567 E1000E_RSSInfo *info) 568 { 569 NetRxPktRssType type; 570 571 assert(e1000e_rss_enabled(core)); 572 573 switch (info->type) { 574 case E1000_MRQ_RSS_TYPE_IPV4: 575 type = NetPktRssIpV4; 576 break; 577 case E1000_MRQ_RSS_TYPE_IPV4TCP: 578 type = NetPktRssIpV4Tcp; 579 break; 580 case E1000_MRQ_RSS_TYPE_IPV6TCPEX: 581 type = NetPktRssIpV6TcpEx; 582 break; 583 case E1000_MRQ_RSS_TYPE_IPV6: 584 type = NetPktRssIpV6; 585 break; 586 case E1000_MRQ_RSS_TYPE_IPV6EX: 587 type = NetPktRssIpV6Ex; 588 break; 589 default: 590 assert(false); 591 return 0; 592 } 593 594 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 595 } 596 597 static void 598 e1000e_rss_parse_packet(E1000ECore *core, 599 struct NetRxPkt *pkt, 600 E1000E_RSSInfo *info) 601 { 602 trace_e1000e_rx_rss_started(); 603 604 if (!e1000e_rss_enabled(core)) { 605 info->enabled = false; 606 info->hash = 0; 607 info->queue = 0; 608 info->type = 0; 609 trace_e1000e_rx_rss_disabled(); 610 return; 611 } 612 613 info->enabled = true; 614 615 info->type = e1000e_rss_get_hash_type(core, pkt); 616 617 trace_e1000e_rx_rss_type(info->type); 618 619 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 620 info->hash = 0; 621 info->queue = 0; 622 return; 623 } 624 625 info->hash = e1000e_rss_calc_hash(core, pkt, info); 626 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 627 } 628 629 static bool 630 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 631 { 632 if (tx->props.tse && tx->cptse) { 633 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 634 return false; 635 } 636 637 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 638 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 639 return true; 640 } 641 642 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 643 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 644 return false; 645 } 646 } 647 648 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 649 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 650 } 651 652 return true; 653 } 654 655 static void e1000e_tx_pkt_callback(void *core, 656 const struct iovec *iov, 657 int iovcnt, 658 const struct iovec *virt_iov, 659 int virt_iovcnt) 660 { 661 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 662 } 663 664 static bool 665 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 666 { 667 int target_queue = MIN(core->max_queue_num, queue_index); 668 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 669 670 if (!e1000e_setup_tx_offloads(core, tx)) { 671 return false; 672 } 673 674 net_tx_pkt_dump(tx->tx_pkt); 675 676 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 677 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 678 return net_tx_pkt_send_custom(tx->tx_pkt, false, 679 e1000e_tx_pkt_callback, core); 680 } else { 681 return net_tx_pkt_send(tx->tx_pkt, queue); 682 } 683 } 684 685 static void 686 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 687 { 688 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 689 PTC1023, PTC1522 }; 690 691 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 692 693 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 694 e1000x_inc_reg_if_not_full(core->mac, TPT); 695 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 696 697 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 698 case ETH_PKT_BCAST: 699 e1000x_inc_reg_if_not_full(core->mac, BPTC); 700 break; 701 case ETH_PKT_MCAST: 702 e1000x_inc_reg_if_not_full(core->mac, MPTC); 703 break; 704 case ETH_PKT_UCAST: 705 break; 706 default: 707 g_assert_not_reached(); 708 } 709 710 e1000x_inc_reg_if_not_full(core->mac, GPTC); 711 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 712 } 713 714 static void 715 e1000e_process_tx_desc(E1000ECore *core, 716 struct e1000e_tx *tx, 717 struct e1000_tx_desc *dp, 718 int queue_index) 719 { 720 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 721 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 722 unsigned int split_size = txd_lower & 0xffff; 723 uint64_t addr; 724 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 725 bool eop = txd_lower & E1000_TXD_CMD_EOP; 726 727 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 728 e1000x_read_tx_ctx_descr(xp, &tx->props); 729 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 730 return; 731 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 732 /* data descriptor */ 733 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 734 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 735 e1000e_process_ts_option(core, dp); 736 } else { 737 /* legacy descriptor */ 738 e1000e_process_ts_option(core, dp); 739 tx->cptse = 0; 740 } 741 742 addr = le64_to_cpu(dp->buffer_addr); 743 744 if (!tx->skip_cp) { 745 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, 746 addr, split_size)) { 747 tx->skip_cp = true; 748 } 749 } 750 751 if (eop) { 752 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 753 if (e1000x_vlan_enabled(core->mac) && 754 e1000x_is_vlan_txd(txd_lower)) { 755 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 756 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 757 } 758 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 759 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 760 } 761 } 762 763 tx->skip_cp = false; 764 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 765 766 tx->sum_needed = 0; 767 tx->cptse = 0; 768 } 769 } 770 771 static inline uint32_t 772 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 773 { 774 if (!msix_enabled(core->owner)) { 775 return E1000_ICR_TXDW; 776 } 777 778 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 779 } 780 781 static inline uint32_t 782 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 783 bool min_threshold_hit) 784 { 785 if (!msix_enabled(core->owner)) { 786 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 787 } 788 789 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 790 } 791 792 static uint32_t 793 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 794 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 795 { 796 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 797 798 if (!(txd_lower & E1000_TXD_CMD_RS) && 799 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 800 return 0; 801 } 802 803 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 804 805 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 806 807 dp->upper.data = cpu_to_le32(txd_upper); 808 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 809 &dp->upper, sizeof(dp->upper)); 810 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 811 } 812 813 typedef struct E1000E_RingInfo_st { 814 int dbah; 815 int dbal; 816 int dlen; 817 int dh; 818 int dt; 819 int idx; 820 } E1000E_RingInfo; 821 822 static inline bool 823 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 824 { 825 return core->mac[r->dh] == core->mac[r->dt] || 826 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 827 } 828 829 static inline uint64_t 830 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 831 { 832 uint64_t bah = core->mac[r->dbah]; 833 uint64_t bal = core->mac[r->dbal]; 834 835 return (bah << 32) + bal; 836 } 837 838 static inline uint64_t 839 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 840 { 841 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 842 } 843 844 static inline void 845 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 846 { 847 core->mac[r->dh] += count; 848 849 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 850 core->mac[r->dh] = 0; 851 } 852 } 853 854 static inline uint32_t 855 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 856 { 857 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 858 core->mac[r->dh], core->mac[r->dt]); 859 860 if (core->mac[r->dh] <= core->mac[r->dt]) { 861 return core->mac[r->dt] - core->mac[r->dh]; 862 } 863 864 if (core->mac[r->dh] > core->mac[r->dt]) { 865 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 866 core->mac[r->dt] - core->mac[r->dh]; 867 } 868 869 g_assert_not_reached(); 870 return 0; 871 } 872 873 static inline bool 874 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 875 { 876 return core->mac[r->dlen] > 0; 877 } 878 879 static inline uint32_t 880 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 881 { 882 return core->mac[r->dlen]; 883 } 884 885 typedef struct E1000E_TxRing_st { 886 const E1000E_RingInfo *i; 887 struct e1000e_tx *tx; 888 } E1000E_TxRing; 889 890 static inline int 891 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 892 { 893 return (reg_idx - base_reg_idx) / (0x100 >> 2); 894 } 895 896 static inline void 897 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 898 { 899 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 900 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 901 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 902 }; 903 904 assert(idx < ARRAY_SIZE(i)); 905 906 txr->i = &i[idx]; 907 txr->tx = &core->tx[idx]; 908 } 909 910 typedef struct E1000E_RxRing_st { 911 const E1000E_RingInfo *i; 912 } E1000E_RxRing; 913 914 static inline void 915 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 916 { 917 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 918 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 919 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 920 }; 921 922 assert(idx < ARRAY_SIZE(i)); 923 924 rxr->i = &i[idx]; 925 } 926 927 static void 928 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 929 { 930 dma_addr_t base; 931 struct e1000_tx_desc desc; 932 bool ide = false; 933 const E1000E_RingInfo *txi = txr->i; 934 uint32_t cause = E1000_ICS_TXQE; 935 936 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 937 trace_e1000e_tx_disabled(); 938 return; 939 } 940 941 while (!e1000e_ring_empty(core, txi)) { 942 base = e1000e_ring_head_descr(core, txi); 943 944 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 945 946 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 947 desc.lower.data, desc.upper.data); 948 949 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 950 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 951 952 e1000e_ring_advance(core, txi, 1); 953 } 954 955 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 956 e1000e_set_interrupt_cause(core, cause); 957 } 958 959 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 960 } 961 962 static bool 963 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 964 size_t total_size) 965 { 966 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 967 968 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 969 core->rx_desc_buf_size); 970 971 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 972 core->rx_desc_buf_size; 973 } 974 975 void 976 e1000e_start_recv(E1000ECore *core) 977 { 978 int i; 979 980 trace_e1000e_rx_start_recv(); 981 982 for (i = 0; i <= core->max_queue_num; i++) { 983 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 984 } 985 } 986 987 bool 988 e1000e_can_receive(E1000ECore *core) 989 { 990 int i; 991 992 if (!e1000x_rx_ready(core->owner, core->mac)) { 993 return false; 994 } 995 996 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 997 E1000E_RxRing rxr; 998 999 e1000e_rx_ring_init(core, &rxr, i); 1000 if (e1000e_ring_enabled(core, rxr.i) && 1001 e1000e_has_rxbufs(core, rxr.i, 1)) { 1002 trace_e1000e_rx_can_recv(); 1003 return true; 1004 } 1005 } 1006 1007 trace_e1000e_rx_can_recv_rings_full(); 1008 return false; 1009 } 1010 1011 ssize_t 1012 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 1013 { 1014 const struct iovec iov = { 1015 .iov_base = (uint8_t *)buf, 1016 .iov_len = size 1017 }; 1018 1019 return e1000e_receive_iov(core, &iov, 1); 1020 } 1021 1022 static inline bool 1023 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1024 { 1025 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1026 } 1027 1028 static inline bool 1029 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1030 { 1031 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1032 } 1033 1034 static bool 1035 e1000e_receive_filter(E1000ECore *core, const void *buf) 1036 { 1037 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || 1038 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && 1039 e1000x_rx_group_filter(core->mac, buf); 1040 } 1041 1042 static inline void 1043 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1044 hwaddr *buff_addr) 1045 { 1046 *buff_addr = le64_to_cpu(desc->buffer_addr); 1047 } 1048 1049 static inline void 1050 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1051 hwaddr *buff_addr) 1052 { 1053 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1054 } 1055 1056 static inline void 1057 e1000e_read_ps_rx_descr(E1000ECore *core, 1058 union e1000_rx_desc_packet_split *desc, 1059 hwaddr buff_addr[MAX_PS_BUFFERS]) 1060 { 1061 int i; 1062 1063 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1064 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1065 } 1066 1067 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1068 buff_addr[2], buff_addr[3]); 1069 } 1070 1071 static inline void 1072 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1073 hwaddr buff_addr[MAX_PS_BUFFERS]) 1074 { 1075 if (e1000e_rx_use_legacy_descriptor(core)) { 1076 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1077 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1078 } else { 1079 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1080 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1081 } else { 1082 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1083 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1084 } 1085 } 1086 } 1087 1088 static void 1089 e1000e_verify_csum_in_sw(E1000ECore *core, 1090 struct NetRxPkt *pkt, 1091 uint32_t *status_flags, 1092 EthL4HdrProto l4hdr_proto) 1093 { 1094 bool csum_valid; 1095 uint32_t csum_error; 1096 1097 if (e1000e_rx_l3_cso_enabled(core)) { 1098 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1099 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1100 } else { 1101 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1102 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1103 } 1104 } else { 1105 trace_e1000e_rx_metadata_l3_cso_disabled(); 1106 } 1107 1108 if (!e1000e_rx_l4_cso_enabled(core)) { 1109 trace_e1000e_rx_metadata_l4_cso_disabled(); 1110 return; 1111 } 1112 1113 if (l4hdr_proto != ETH_L4_HDR_PROTO_TCP && 1114 l4hdr_proto != ETH_L4_HDR_PROTO_UDP) { 1115 return; 1116 } 1117 1118 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1119 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1120 return; 1121 } 1122 1123 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1124 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1125 1126 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1127 *status_flags |= E1000_RXD_STAT_UDPCS; 1128 } 1129 } 1130 1131 static inline bool 1132 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1133 { 1134 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1135 return false; 1136 } 1137 1138 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1139 return !net_rx_pkt_has_tcp_data(rx_pkt); 1140 } 1141 1142 return true; 1143 } 1144 1145 static void 1146 e1000e_build_rx_metadata(E1000ECore *core, 1147 struct NetRxPkt *pkt, 1148 bool is_eop, 1149 const E1000E_RSSInfo *rss_info, 1150 uint32_t *rss, uint32_t *mrq, 1151 uint32_t *status_flags, 1152 uint16_t *ip_id, 1153 uint16_t *vlan_tag) 1154 { 1155 struct virtio_net_hdr *vhdr; 1156 bool hasip4, hasip6; 1157 EthL4HdrProto l4hdr_proto; 1158 uint32_t pkt_type; 1159 1160 *status_flags = E1000_RXD_STAT_DD; 1161 1162 /* No additional metadata needed for non-EOP descriptors */ 1163 if (!is_eop) { 1164 goto func_exit; 1165 } 1166 1167 *status_flags |= E1000_RXD_STAT_EOP; 1168 1169 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1170 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1171 1172 /* VLAN state */ 1173 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1174 *status_flags |= E1000_RXD_STAT_VP; 1175 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1176 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1177 } 1178 1179 /* Packet parsing results */ 1180 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1181 if (rss_info->enabled) { 1182 *rss = cpu_to_le32(rss_info->hash); 1183 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1184 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1185 } 1186 } else if (hasip4) { 1187 *status_flags |= E1000_RXD_STAT_IPIDV; 1188 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1189 trace_e1000e_rx_metadata_ip_id(*ip_id); 1190 } 1191 1192 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { 1193 *status_flags |= E1000_RXD_STAT_ACK; 1194 trace_e1000e_rx_metadata_ack(); 1195 } 1196 1197 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1198 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1199 pkt_type = E1000_RXD_PKT_MAC; 1200 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1201 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1202 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1203 } else if (hasip4 || hasip6) { 1204 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1205 } else { 1206 pkt_type = E1000_RXD_PKT_MAC; 1207 } 1208 1209 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1210 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1211 1212 /* RX CSO information */ 1213 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1214 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1215 goto func_exit; 1216 } 1217 1218 vhdr = net_rx_pkt_get_vhdr(pkt); 1219 1220 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1221 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1222 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1223 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1224 goto func_exit; 1225 } 1226 1227 if (e1000e_rx_l3_cso_enabled(core)) { 1228 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1229 } else { 1230 trace_e1000e_rx_metadata_l3_cso_disabled(); 1231 } 1232 1233 if (e1000e_rx_l4_cso_enabled(core)) { 1234 switch (l4hdr_proto) { 1235 case ETH_L4_HDR_PROTO_TCP: 1236 *status_flags |= E1000_RXD_STAT_TCPCS; 1237 break; 1238 1239 case ETH_L4_HDR_PROTO_UDP: 1240 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1241 break; 1242 1243 default: 1244 break; 1245 } 1246 } else { 1247 trace_e1000e_rx_metadata_l4_cso_disabled(); 1248 } 1249 1250 func_exit: 1251 trace_e1000e_rx_metadata_status_flags(*status_flags); 1252 *status_flags = cpu_to_le32(*status_flags); 1253 } 1254 1255 static inline void 1256 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1257 struct NetRxPkt *pkt, 1258 const E1000E_RSSInfo *rss_info, 1259 uint16_t length) 1260 { 1261 uint32_t status_flags, rss, mrq; 1262 uint16_t ip_id; 1263 1264 assert(!rss_info->enabled); 1265 1266 desc->length = cpu_to_le16(length); 1267 desc->csum = 0; 1268 1269 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1270 rss_info, 1271 &rss, &mrq, 1272 &status_flags, &ip_id, 1273 &desc->special); 1274 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1275 desc->status = (uint8_t) le32_to_cpu(status_flags); 1276 } 1277 1278 static inline void 1279 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1280 struct NetRxPkt *pkt, 1281 const E1000E_RSSInfo *rss_info, 1282 uint16_t length) 1283 { 1284 memset(&desc->wb, 0, sizeof(desc->wb)); 1285 1286 desc->wb.upper.length = cpu_to_le16(length); 1287 1288 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1289 rss_info, 1290 &desc->wb.lower.hi_dword.rss, 1291 &desc->wb.lower.mrq, 1292 &desc->wb.upper.status_error, 1293 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1294 &desc->wb.upper.vlan); 1295 } 1296 1297 static inline void 1298 e1000e_write_ps_rx_descr(E1000ECore *core, 1299 union e1000_rx_desc_packet_split *desc, 1300 struct NetRxPkt *pkt, 1301 const E1000E_RSSInfo *rss_info, 1302 size_t ps_hdr_len, 1303 uint16_t(*written)[MAX_PS_BUFFERS]) 1304 { 1305 int i; 1306 1307 memset(&desc->wb, 0, sizeof(desc->wb)); 1308 1309 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1310 1311 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1312 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1313 } 1314 1315 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1316 rss_info, 1317 &desc->wb.lower.hi_dword.rss, 1318 &desc->wb.lower.mrq, 1319 &desc->wb.middle.status_error, 1320 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1321 &desc->wb.middle.vlan); 1322 1323 desc->wb.upper.header_status = 1324 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1325 1326 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1327 (*written)[2], (*written)[3]); 1328 } 1329 1330 static inline void 1331 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1332 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1333 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1334 { 1335 if (e1000e_rx_use_legacy_descriptor(core)) { 1336 assert(ps_hdr_len == 0); 1337 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1338 (*written)[0]); 1339 } else { 1340 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1341 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1342 ps_hdr_len, written); 1343 } else { 1344 assert(ps_hdr_len == 0); 1345 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1346 (*written)[0]); 1347 } 1348 } 1349 } 1350 1351 static inline void 1352 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1353 union e1000_rx_desc_union *desc, dma_addr_t len) 1354 { 1355 PCIDevice *dev = core->owner; 1356 1357 if (e1000e_rx_use_legacy_descriptor(core)) { 1358 struct e1000_rx_desc *d = &desc->legacy; 1359 size_t offset = offsetof(struct e1000_rx_desc, status); 1360 uint8_t status = d->status; 1361 1362 d->status &= ~E1000_RXD_STAT_DD; 1363 pci_dma_write(dev, addr, desc, len); 1364 1365 if (status & E1000_RXD_STAT_DD) { 1366 d->status = status; 1367 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1368 } 1369 } else { 1370 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1371 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1372 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1373 wb.middle.status_error); 1374 uint32_t status = d->wb.middle.status_error; 1375 1376 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1377 pci_dma_write(dev, addr, desc, len); 1378 1379 if (status & E1000_RXD_STAT_DD) { 1380 d->wb.middle.status_error = status; 1381 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1382 } 1383 } else { 1384 union e1000_rx_desc_extended *d = &desc->extended; 1385 size_t offset = offsetof(union e1000_rx_desc_extended, 1386 wb.upper.status_error); 1387 uint32_t status = d->wb.upper.status_error; 1388 1389 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1390 pci_dma_write(dev, addr, desc, len); 1391 1392 if (status & E1000_RXD_STAT_DD) { 1393 d->wb.upper.status_error = status; 1394 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1395 } 1396 } 1397 } 1398 } 1399 1400 typedef struct e1000e_ba_state_st { 1401 uint16_t written[MAX_PS_BUFFERS]; 1402 uint8_t cur_idx; 1403 } e1000e_ba_state; 1404 1405 static inline void 1406 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1407 hwaddr ba[MAX_PS_BUFFERS], 1408 e1000e_ba_state *bastate, 1409 const char *data, 1410 dma_addr_t data_len) 1411 { 1412 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1413 1414 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1415 bastate->written[0] += data_len; 1416 1417 bastate->cur_idx = 1; 1418 } 1419 1420 static void 1421 e1000e_write_to_rx_buffers(E1000ECore *core, 1422 hwaddr ba[MAX_PS_BUFFERS], 1423 e1000e_ba_state *bastate, 1424 const char *data, 1425 dma_addr_t data_len) 1426 { 1427 while (data_len > 0) { 1428 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1429 uint32_t cur_buf_bytes_left = cur_buf_len - 1430 bastate->written[bastate->cur_idx]; 1431 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1432 1433 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1434 ba[bastate->cur_idx], 1435 bastate->written[bastate->cur_idx], 1436 data, 1437 bytes_to_write); 1438 1439 pci_dma_write(core->owner, 1440 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1441 data, bytes_to_write); 1442 1443 bastate->written[bastate->cur_idx] += bytes_to_write; 1444 data += bytes_to_write; 1445 data_len -= bytes_to_write; 1446 1447 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1448 bastate->cur_idx++; 1449 } 1450 1451 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1452 } 1453 } 1454 1455 static void 1456 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) 1457 { 1458 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1459 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1460 } 1461 1462 static inline bool 1463 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1464 { 1465 return e1000e_ring_free_descr_num(core, rxi) == 1466 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1467 } 1468 1469 static bool 1470 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1471 { 1472 bool hasip4, hasip6; 1473 EthL4HdrProto l4hdr_proto; 1474 bool fragment; 1475 1476 if (!e1000e_rx_use_ps_descriptor(core)) { 1477 return false; 1478 } 1479 1480 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1481 1482 if (hasip4) { 1483 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1484 } else if (hasip6) { 1485 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1486 } else { 1487 return false; 1488 } 1489 1490 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1491 return false; 1492 } 1493 1494 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1495 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1496 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1497 } else { 1498 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1499 } 1500 1501 if ((*hdr_len > core->rxbuf_sizes[0]) || 1502 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1503 return false; 1504 } 1505 1506 return true; 1507 } 1508 1509 static void 1510 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1511 const E1000E_RxRing *rxr, 1512 const E1000E_RSSInfo *rss_info) 1513 { 1514 PCIDevice *d = core->owner; 1515 dma_addr_t base; 1516 union e1000_rx_desc_union desc; 1517 size_t desc_size; 1518 size_t desc_offset = 0; 1519 size_t iov_ofs = 0; 1520 1521 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1522 size_t size = net_rx_pkt_get_total_len(pkt); 1523 size_t total_size = size + e1000x_fcs_len(core->mac); 1524 const E1000E_RingInfo *rxi; 1525 size_t ps_hdr_len = 0; 1526 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1527 bool is_first = true; 1528 1529 rxi = rxr->i; 1530 1531 do { 1532 hwaddr ba[MAX_PS_BUFFERS]; 1533 e1000e_ba_state bastate = { { 0 } }; 1534 bool is_last = false; 1535 1536 desc_size = total_size - desc_offset; 1537 1538 if (desc_size > core->rx_desc_buf_size) { 1539 desc_size = core->rx_desc_buf_size; 1540 } 1541 1542 if (e1000e_ring_empty(core, rxi)) { 1543 return; 1544 } 1545 1546 base = e1000e_ring_head_descr(core, rxi); 1547 1548 pci_dma_read(d, base, &desc, core->rx_desc_len); 1549 1550 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1551 1552 e1000e_read_rx_descr(core, &desc, ba); 1553 1554 if (ba[0]) { 1555 if (desc_offset < size) { 1556 static const uint32_t fcs_pad; 1557 size_t iov_copy; 1558 size_t copy_size = size - desc_offset; 1559 if (copy_size > core->rx_desc_buf_size) { 1560 copy_size = core->rx_desc_buf_size; 1561 } 1562 1563 /* For PS mode copy the packet header first */ 1564 if (do_ps) { 1565 if (is_first) { 1566 size_t ps_hdr_copied = 0; 1567 do { 1568 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1569 iov->iov_len - iov_ofs); 1570 1571 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1572 iov->iov_base, iov_copy); 1573 1574 copy_size -= iov_copy; 1575 ps_hdr_copied += iov_copy; 1576 1577 iov_ofs += iov_copy; 1578 if (iov_ofs == iov->iov_len) { 1579 iov++; 1580 iov_ofs = 0; 1581 } 1582 } while (ps_hdr_copied < ps_hdr_len); 1583 1584 is_first = false; 1585 } else { 1586 /* Leave buffer 0 of each descriptor except first */ 1587 /* empty as per spec 7.1.5.1 */ 1588 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1589 NULL, 0); 1590 } 1591 } 1592 1593 /* Copy packet payload */ 1594 while (copy_size) { 1595 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1596 1597 e1000e_write_to_rx_buffers(core, ba, &bastate, 1598 iov->iov_base + iov_ofs, iov_copy); 1599 1600 copy_size -= iov_copy; 1601 iov_ofs += iov_copy; 1602 if (iov_ofs == iov->iov_len) { 1603 iov++; 1604 iov_ofs = 0; 1605 } 1606 } 1607 1608 if (desc_offset + desc_size >= total_size) { 1609 /* Simulate FCS checksum presence in the last descriptor */ 1610 e1000e_write_to_rx_buffers(core, ba, &bastate, 1611 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1612 } 1613 } 1614 } else { /* as per intel docs; skip descriptors with null buf addr */ 1615 trace_e1000e_rx_null_descriptor(); 1616 } 1617 desc_offset += desc_size; 1618 if (desc_offset >= total_size) { 1619 is_last = true; 1620 } 1621 1622 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1623 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1624 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1625 1626 e1000e_ring_advance(core, rxi, 1627 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1628 1629 } while (desc_offset < total_size); 1630 1631 e1000e_update_rx_stats(core, size, total_size); 1632 } 1633 1634 static inline void 1635 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1636 { 1637 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1638 1639 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1640 net_rx_pkt_fix_l4_csum(pkt); 1641 } 1642 } 1643 1644 ssize_t 1645 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1646 { 1647 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1648 } 1649 1650 static ssize_t 1651 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1652 bool has_vnet) 1653 { 1654 uint32_t causes = 0; 1655 uint8_t buf[ETH_ZLEN]; 1656 struct iovec min_iov; 1657 size_t size, orig_size; 1658 size_t iov_ofs = 0; 1659 E1000E_RxRing rxr; 1660 E1000E_RSSInfo rss_info; 1661 size_t total_size; 1662 ssize_t retval; 1663 bool rdmts_hit; 1664 1665 trace_e1000e_rx_receive_iov(iovcnt); 1666 1667 if (!e1000x_hw_rx_enabled(core->mac)) { 1668 return -1; 1669 } 1670 1671 /* Pull virtio header in */ 1672 if (has_vnet) { 1673 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1674 iov_ofs = sizeof(struct virtio_net_hdr); 1675 } else { 1676 net_rx_pkt_unset_vhdr(core->rx_pkt); 1677 } 1678 1679 orig_size = iov_size(iov, iovcnt); 1680 size = orig_size - iov_ofs; 1681 1682 /* Pad to minimum Ethernet frame length */ 1683 if (size < sizeof(buf)) { 1684 iov_to_buf(iov, iovcnt, iov_ofs, buf, size); 1685 memset(&buf[size], 0, sizeof(buf) - size); 1686 e1000x_inc_reg_if_not_full(core->mac, RUC); 1687 min_iov.iov_base = buf; 1688 min_iov.iov_len = size = sizeof(buf); 1689 iovcnt = 1; 1690 iov = &min_iov; 1691 iov_ofs = 0; 1692 } else { 1693 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4); 1694 } 1695 1696 /* Discard oversized packets if !LPE and !SBP. */ 1697 if (e1000x_is_oversized(core->mac, size)) { 1698 return orig_size; 1699 } 1700 1701 net_rx_pkt_set_packet_type(core->rx_pkt, 1702 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1703 1704 if (!e1000e_receive_filter(core, buf)) { 1705 trace_e1000e_rx_flt_dropped(); 1706 return orig_size; 1707 } 1708 1709 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1710 e1000x_vlan_enabled(core->mac) ? 0 : -1, 1711 core->mac[VET], 0); 1712 1713 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1714 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1715 1716 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1717 e1000x_fcs_len(core->mac); 1718 1719 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1720 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1721 1722 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1723 1724 retval = orig_size; 1725 1726 /* Perform small receive detection (RSRPD) */ 1727 if (total_size < core->mac[RSRPD]) { 1728 causes |= E1000_ICS_SRPD; 1729 } 1730 1731 /* Perform ACK receive detection */ 1732 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1733 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1734 causes |= E1000_ICS_ACK; 1735 } 1736 1737 /* Check if receive descriptor minimum threshold hit */ 1738 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1739 causes |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1740 1741 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1742 } else { 1743 causes |= E1000_ICS_RXO; 1744 retval = 0; 1745 1746 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1747 } 1748 1749 if (!e1000e_intrmgr_delay_rx_causes(core, &causes)) { 1750 trace_e1000e_rx_interrupt_set(causes); 1751 e1000e_set_interrupt_cause(core, causes); 1752 } else { 1753 trace_e1000e_rx_interrupt_delayed(causes); 1754 } 1755 1756 return retval; 1757 } 1758 1759 static inline bool 1760 e1000e_have_autoneg(E1000ECore *core) 1761 { 1762 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1763 } 1764 1765 static void e1000e_update_flowctl_status(E1000ECore *core) 1766 { 1767 if (e1000e_have_autoneg(core) && 1768 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1769 trace_e1000e_link_autoneg_flowctl(true); 1770 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1771 } else { 1772 trace_e1000e_link_autoneg_flowctl(false); 1773 } 1774 } 1775 1776 static inline void 1777 e1000e_link_down(E1000ECore *core) 1778 { 1779 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1780 e1000e_update_flowctl_status(core); 1781 } 1782 1783 static inline void 1784 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1785 { 1786 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1787 core->phy[0][MII_BMCR] = val & ~(0x3f | 1788 MII_BMCR_RESET | 1789 MII_BMCR_ANRESTART); 1790 1791 if ((val & MII_BMCR_ANRESTART) && 1792 e1000e_have_autoneg(core)) { 1793 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1794 } 1795 } 1796 1797 static void 1798 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1799 { 1800 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1801 1802 if (val & BIT(10)) { 1803 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1804 } 1805 } 1806 1807 static void 1808 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1809 { 1810 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1811 } 1812 1813 void 1814 e1000e_core_set_link_status(E1000ECore *core) 1815 { 1816 NetClientState *nc = qemu_get_queue(core->owner_nic); 1817 uint32_t old_status = core->mac[STATUS]; 1818 1819 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1820 1821 if (nc->link_down) { 1822 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1823 } else { 1824 if (e1000e_have_autoneg(core) && 1825 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1826 e1000x_restart_autoneg(core->mac, core->phy[0], 1827 core->autoneg_timer); 1828 } else { 1829 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1830 e1000e_start_recv(core); 1831 } 1832 } 1833 1834 if (core->mac[STATUS] != old_status) { 1835 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1836 } 1837 } 1838 1839 static void 1840 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1841 { 1842 trace_e1000e_core_ctrl_write(index, val); 1843 1844 /* RST is self clearing */ 1845 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1846 core->mac[CTRL_DUP] = core->mac[CTRL]; 1847 1848 trace_e1000e_link_set_params( 1849 !!(val & E1000_CTRL_ASDE), 1850 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1851 !!(val & E1000_CTRL_FRCSPD), 1852 !!(val & E1000_CTRL_FRCDPX), 1853 !!(val & E1000_CTRL_RFCE), 1854 !!(val & E1000_CTRL_TFCE)); 1855 1856 if (val & E1000_CTRL_RST) { 1857 trace_e1000e_core_ctrl_sw_reset(); 1858 e1000e_reset(core, true); 1859 } 1860 1861 if (val & E1000_CTRL_PHY_RST) { 1862 trace_e1000e_core_ctrl_phy_reset(); 1863 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1864 } 1865 } 1866 1867 static void 1868 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1869 { 1870 trace_e1000e_rx_set_rfctl(val); 1871 1872 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1873 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1874 } 1875 1876 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1877 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1878 } 1879 1880 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1881 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1882 } 1883 1884 core->mac[RFCTL] = val; 1885 } 1886 1887 static void 1888 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1889 { 1890 int i; 1891 core->rx_desc_buf_size = 0; 1892 1893 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1894 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1895 } 1896 } 1897 1898 static void 1899 e1000e_parse_rxbufsize(E1000ECore *core) 1900 { 1901 uint32_t rctl = core->mac[RCTL]; 1902 1903 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1904 1905 if (rctl & E1000_RCTL_DTYP_MASK) { 1906 uint32_t bsize; 1907 1908 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1909 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1910 1911 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1912 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1913 1914 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1915 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1916 1917 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1918 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1919 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1920 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1921 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1922 } else { 1923 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1924 } 1925 1926 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1927 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1928 1929 e1000e_calc_per_desc_buf_size(core); 1930 } 1931 1932 static void 1933 e1000e_calc_rxdesclen(E1000ECore *core) 1934 { 1935 if (e1000e_rx_use_legacy_descriptor(core)) { 1936 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1937 } else { 1938 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1939 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1940 } else { 1941 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1942 } 1943 } 1944 trace_e1000e_rx_desc_len(core->rx_desc_len); 1945 } 1946 1947 static void 1948 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1949 { 1950 core->mac[RCTL] = val; 1951 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1952 1953 if (val & E1000_RCTL_EN) { 1954 e1000e_parse_rxbufsize(core); 1955 e1000e_calc_rxdesclen(core); 1956 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1957 E1000_RING_DESC_LEN_SHIFT; 1958 1959 e1000e_start_recv(core); 1960 } 1961 } 1962 1963 static 1964 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1965 (E1000ECore *, int, uint16_t) = { 1966 [0] = { 1967 [MII_BMCR] = e1000e_set_phy_ctrl, 1968 [PHY_PAGE] = e1000e_set_phy_page, 1969 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1970 } 1971 }; 1972 1973 static inline bool 1974 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 1975 { 1976 if (timer->running) { 1977 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1978 1979 return true; 1980 } 1981 1982 if (timer->core->mac[timer->delay_reg] != 0) { 1983 e1000e_intrmgr_rearm_timer(timer); 1984 } 1985 1986 return false; 1987 } 1988 1989 static inline bool 1990 e1000e_itr_should_postpone(E1000ECore *core) 1991 { 1992 return e1000e_postpone_interrupt(&core->itr); 1993 } 1994 1995 static inline bool 1996 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 1997 { 1998 return e1000e_postpone_interrupt(&core->eitr[idx]); 1999 } 2000 2001 static void 2002 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2003 { 2004 uint32_t effective_eiac; 2005 2006 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2007 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2008 if (vec < E1000E_MSIX_VEC_NUM) { 2009 if (!e1000e_eitr_should_postpone(core, vec)) { 2010 trace_e1000e_irq_msix_notify_vec(vec); 2011 msix_notify(core->owner, vec); 2012 } 2013 } else { 2014 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2015 } 2016 } else { 2017 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2018 } 2019 2020 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2021 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2022 core->mac[IAM] &= ~cause; 2023 } 2024 2025 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2026 2027 effective_eiac = core->mac[EIAC] & cause; 2028 2029 core->mac[ICR] &= ~effective_eiac; 2030 2031 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2032 core->mac[IMS] &= ~effective_eiac; 2033 } 2034 } 2035 2036 static void 2037 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2038 { 2039 if (causes & E1000_ICR_RXQ0) { 2040 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2041 E1000_IVAR_RXQ0(core->mac[IVAR])); 2042 } 2043 2044 if (causes & E1000_ICR_RXQ1) { 2045 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2046 E1000_IVAR_RXQ1(core->mac[IVAR])); 2047 } 2048 2049 if (causes & E1000_ICR_TXQ0) { 2050 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2051 E1000_IVAR_TXQ0(core->mac[IVAR])); 2052 } 2053 2054 if (causes & E1000_ICR_TXQ1) { 2055 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2056 E1000_IVAR_TXQ1(core->mac[IVAR])); 2057 } 2058 2059 if (causes & E1000_ICR_OTHER) { 2060 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2061 E1000_IVAR_OTHER(core->mac[IVAR])); 2062 } 2063 } 2064 2065 static void 2066 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2067 { 2068 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2069 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2070 if (vec < E1000E_MSIX_VEC_NUM) { 2071 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2072 msix_clr_pending(core->owner, vec); 2073 } else { 2074 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2075 } 2076 } else { 2077 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2078 } 2079 } 2080 2081 static void 2082 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2083 { 2084 if (causes & E1000_ICR_RXQ0) { 2085 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2086 E1000_IVAR_RXQ0(core->mac[IVAR])); 2087 } 2088 2089 if (causes & E1000_ICR_RXQ1) { 2090 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2091 E1000_IVAR_RXQ1(core->mac[IVAR])); 2092 } 2093 2094 if (causes & E1000_ICR_TXQ0) { 2095 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2096 E1000_IVAR_TXQ0(core->mac[IVAR])); 2097 } 2098 2099 if (causes & E1000_ICR_TXQ1) { 2100 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2101 E1000_IVAR_TXQ1(core->mac[IVAR])); 2102 } 2103 2104 if (causes & E1000_ICR_OTHER) { 2105 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2106 E1000_IVAR_OTHER(core->mac[IVAR])); 2107 } 2108 } 2109 2110 static inline void 2111 e1000e_fix_icr_asserted(E1000ECore *core) 2112 { 2113 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2114 if (core->mac[ICR]) { 2115 core->mac[ICR] |= E1000_ICR_ASSERTED; 2116 } 2117 2118 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2119 } 2120 2121 static void e1000e_raise_interrupts(E1000ECore *core, 2122 size_t index, uint32_t causes) 2123 { 2124 bool is_msix = msix_enabled(core->owner); 2125 uint32_t old_causes = core->mac[IMS] & core->mac[ICR]; 2126 uint32_t raised_causes; 2127 2128 trace_e1000e_irq_set(index << 2, 2129 core->mac[index], core->mac[index] | causes); 2130 2131 core->mac[index] |= causes; 2132 2133 /* Set ICR[OTHER] for MSI-X */ 2134 if (is_msix) { 2135 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2136 core->mac[ICR] |= E1000_ICR_OTHER; 2137 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2138 } 2139 } 2140 2141 e1000e_fix_icr_asserted(core); 2142 2143 /* 2144 * Make sure ICR and ICS registers have the same value. 2145 * The spec says that the ICS register is write-only. However in practice, 2146 * on real hardware ICS is readable, and for reads it has the same value as 2147 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2148 * 2149 * The VxWorks PRO/1000 driver uses this behaviour. 2150 */ 2151 core->mac[ICS] = core->mac[ICR]; 2152 2153 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2154 core->mac[ICR], core->mac[IMS]); 2155 2156 raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes; 2157 if (!raised_causes) { 2158 return; 2159 } 2160 2161 if (is_msix) { 2162 e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED); 2163 } else if (!e1000e_itr_should_postpone(core)) { 2164 if (msi_enabled(core->owner)) { 2165 trace_e1000e_irq_msi_notify(raised_causes); 2166 msi_notify(core->owner, 0); 2167 } else { 2168 e1000e_raise_legacy_irq(core); 2169 } 2170 } 2171 } 2172 2173 static void e1000e_lower_interrupts(E1000ECore *core, 2174 size_t index, uint32_t causes) 2175 { 2176 trace_e1000e_irq_clear(index << 2, 2177 core->mac[index], core->mac[index] & ~causes); 2178 2179 core->mac[index] &= ~causes; 2180 2181 /* 2182 * Make sure ICR and ICS registers have the same value. 2183 * The spec says that the ICS register is write-only. However in practice, 2184 * on real hardware ICS is readable, and for reads it has the same value as 2185 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2186 * 2187 * The VxWorks PRO/1000 driver uses this behaviour. 2188 */ 2189 core->mac[ICS] = core->mac[ICR]; 2190 2191 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2192 core->mac[ICR], core->mac[IMS]); 2193 2194 if (!(core->mac[IMS] & core->mac[ICR]) && 2195 !msix_enabled(core->owner) && !msi_enabled(core->owner)) { 2196 e1000e_lower_legacy_irq(core); 2197 } 2198 } 2199 2200 static void 2201 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2202 { 2203 val |= e1000e_intmgr_collect_delayed_causes(core); 2204 e1000e_raise_interrupts(core, ICR, val); 2205 } 2206 2207 static inline void 2208 e1000e_autoneg_timer(void *opaque) 2209 { 2210 E1000ECore *core = opaque; 2211 if (!qemu_get_queue(core->owner_nic)->link_down) { 2212 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2213 e1000e_start_recv(core); 2214 2215 e1000e_update_flowctl_status(core); 2216 /* signal link status change to the guest */ 2217 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2218 } 2219 } 2220 2221 static inline uint16_t 2222 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2223 { 2224 uint16_t index = (addr & 0x1ffff) >> 2; 2225 return index + (mac_reg_access[index] & 0xfffe); 2226 } 2227 2228 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2229 [0] = { 2230 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2231 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2232 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2233 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2234 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2235 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2236 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2237 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2238 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2239 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2240 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2241 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2242 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2243 2244 [PHY_COPPER_CTRL1] = PHY_RW, 2245 [PHY_COPPER_STAT1] = PHY_R, 2246 [PHY_COPPER_CTRL3] = PHY_RW, 2247 [PHY_RX_ERR_CNTR] = PHY_R, 2248 [PHY_OEM_BITS] = PHY_RW, 2249 [PHY_BIAS_1] = PHY_RW, 2250 [PHY_BIAS_2] = PHY_RW, 2251 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2252 [PHY_COPPER_STAT2] = PHY_R, 2253 [PHY_COPPER_CTRL2] = PHY_RW 2254 }, 2255 [2] = { 2256 [PHY_MAC_CTRL1] = PHY_RW, 2257 [PHY_MAC_INT_ENABLE] = PHY_RW, 2258 [PHY_MAC_STAT] = PHY_R, 2259 [PHY_MAC_CTRL2] = PHY_RW 2260 }, 2261 [3] = { 2262 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2263 [PHY_LED_03_POL_CTRL] = PHY_RW, 2264 [PHY_LED_TIMER_CTRL] = PHY_RW, 2265 [PHY_LED_45_CTRL] = PHY_RW 2266 }, 2267 [5] = { 2268 [PHY_1000T_SKEW] = PHY_R, 2269 [PHY_1000T_SWAP] = PHY_R 2270 }, 2271 [6] = { 2272 [PHY_CRC_COUNTERS] = PHY_R 2273 } 2274 }; 2275 2276 static bool 2277 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2278 char cap, uint8_t *page) 2279 { 2280 *page = 2281 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2282 : core->phy[0][PHY_PAGE]; 2283 2284 if (*page >= E1000E_PHY_PAGES) { 2285 return false; 2286 } 2287 2288 return e1000e_phy_regcap[*page][addr] & cap; 2289 } 2290 2291 static void 2292 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2293 uint32_t addr, uint16_t data) 2294 { 2295 assert(page < E1000E_PHY_PAGES); 2296 assert(addr < E1000E_PHY_PAGE_SIZE); 2297 2298 if (e1000e_phyreg_writeops[page][addr]) { 2299 e1000e_phyreg_writeops[page][addr](core, addr, data); 2300 } else { 2301 core->phy[page][addr] = data; 2302 } 2303 } 2304 2305 static void 2306 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2307 { 2308 uint32_t data = val & E1000_MDIC_DATA_MASK; 2309 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2310 uint8_t page; 2311 2312 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2313 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2314 } else if (val & E1000_MDIC_OP_READ) { 2315 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2316 trace_e1000e_core_mdic_read_unhandled(page, addr); 2317 val |= E1000_MDIC_ERROR; 2318 } else { 2319 val = (val ^ data) | core->phy[page][addr]; 2320 trace_e1000e_core_mdic_read(page, addr, val); 2321 } 2322 } else if (val & E1000_MDIC_OP_WRITE) { 2323 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2324 trace_e1000e_core_mdic_write_unhandled(page, addr); 2325 val |= E1000_MDIC_ERROR; 2326 } else { 2327 trace_e1000e_core_mdic_write(page, addr, data); 2328 e1000e_phy_reg_write(core, page, addr, data); 2329 } 2330 } 2331 core->mac[MDIC] = val | E1000_MDIC_READY; 2332 2333 if (val & E1000_MDIC_INT_EN) { 2334 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2335 } 2336 } 2337 2338 static void 2339 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2340 { 2341 core->mac[index] = val & 0xffff; 2342 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2343 e1000e_start_recv(core); 2344 } 2345 2346 static void 2347 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2348 { 2349 if ((val & E1000_STATUS_PHYRA) == 0) { 2350 core->mac[index] &= ~E1000_STATUS_PHYRA; 2351 } 2352 } 2353 2354 static void 2355 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2356 { 2357 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2358 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2359 2360 /* Zero self-clearing bits */ 2361 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2362 core->mac[CTRL_EXT] = val; 2363 } 2364 2365 static void 2366 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2367 { 2368 int i; 2369 2370 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2371 2372 if (!msix_enabled(core->owner)) { 2373 return; 2374 } 2375 2376 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2377 if (core->mac[PBACLR] & BIT(i)) { 2378 msix_clr_pending(core->owner, i); 2379 } 2380 } 2381 } 2382 2383 static void 2384 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2385 { 2386 core->mac[FCRTH] = val & 0xFFF8; 2387 } 2388 2389 static void 2390 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2391 { 2392 core->mac[FCRTL] = val & 0x8000FFF8; 2393 } 2394 2395 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2396 static void \ 2397 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2398 { \ 2399 core->mac[index] = val & (BIT(num) - 1); \ 2400 } 2401 2402 E1000E_LOW_BITS_SET_FUNC(4) 2403 E1000E_LOW_BITS_SET_FUNC(6) 2404 E1000E_LOW_BITS_SET_FUNC(11) 2405 E1000E_LOW_BITS_SET_FUNC(12) 2406 E1000E_LOW_BITS_SET_FUNC(13) 2407 E1000E_LOW_BITS_SET_FUNC(16) 2408 2409 static void 2410 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2411 { 2412 core->mac[VET] = val & 0xffff; 2413 trace_e1000e_vlan_vet(core->mac[VET]); 2414 } 2415 2416 static void 2417 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2418 { 2419 core->mac[index] = val & E1000_XDLEN_MASK; 2420 } 2421 2422 static void 2423 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2424 { 2425 core->mac[index] = val & E1000_XDBAL_MASK; 2426 } 2427 2428 static void 2429 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2430 { 2431 E1000E_TxRing txr; 2432 core->mac[index] = val; 2433 2434 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2435 e1000e_tx_ring_init(core, &txr, 0); 2436 e1000e_start_xmit(core, &txr); 2437 } 2438 2439 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2440 e1000e_tx_ring_init(core, &txr, 1); 2441 e1000e_start_xmit(core, &txr); 2442 } 2443 } 2444 2445 static void 2446 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2447 { 2448 E1000E_TxRing txr; 2449 int qidx = e1000e_mq_queue_idx(TDT, index); 2450 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2451 2452 core->mac[index] = val & 0xffff; 2453 2454 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2455 e1000e_tx_ring_init(core, &txr, qidx); 2456 e1000e_start_xmit(core, &txr); 2457 } 2458 } 2459 2460 static void 2461 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2462 { 2463 trace_e1000e_irq_write_ics(val); 2464 e1000e_set_interrupt_cause(core, val); 2465 } 2466 2467 static void 2468 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2469 { 2470 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2471 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2472 trace_e1000e_irq_icr_process_iame(); 2473 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2474 } 2475 2476 /* 2477 * Windows driver expects that the "receive overrun" bit and other 2478 * ones to be cleared when the "Other" bit (#24) is cleared. 2479 */ 2480 if (val & E1000_ICR_OTHER) { 2481 val |= E1000_ICR_OTHER_CAUSES; 2482 } 2483 e1000e_lower_interrupts(core, ICR, val); 2484 } 2485 2486 static void 2487 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2488 { 2489 trace_e1000e_irq_ims_clear_set_imc(val); 2490 e1000e_lower_interrupts(core, IMS, val); 2491 } 2492 2493 static void 2494 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2495 { 2496 static const uint32_t ims_ext_mask = 2497 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2498 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2499 E1000_IMS_OTHER; 2500 2501 static const uint32_t ims_valid_mask = 2502 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2503 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2504 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2505 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2506 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2507 E1000_IMS_OTHER; 2508 2509 uint32_t valid_val = val & ims_valid_mask; 2510 2511 if ((valid_val & ims_ext_mask) && 2512 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2513 msix_enabled(core->owner)) { 2514 e1000e_msix_clear(core, valid_val); 2515 } 2516 2517 if ((valid_val == ims_valid_mask) && 2518 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2519 trace_e1000e_irq_fire_all_timers(val); 2520 e1000e_intrmgr_fire_all_timers(core); 2521 } 2522 2523 e1000e_raise_interrupts(core, IMS, valid_val); 2524 } 2525 2526 static void 2527 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2528 { 2529 e1000e_set_16bit(core, index, val); 2530 2531 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2532 trace_e1000e_irq_rdtr_fpd_running(); 2533 e1000e_intrmgr_fire_delayed_interrupts(core); 2534 } else { 2535 trace_e1000e_irq_rdtr_fpd_not_running(); 2536 } 2537 } 2538 2539 static void 2540 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2541 { 2542 e1000e_set_16bit(core, index, val); 2543 2544 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2545 trace_e1000e_irq_tidv_fpd_running(); 2546 e1000e_intrmgr_fire_delayed_interrupts(core); 2547 } else { 2548 trace_e1000e_irq_tidv_fpd_not_running(); 2549 } 2550 } 2551 2552 static uint32_t 2553 e1000e_mac_readreg(E1000ECore *core, int index) 2554 { 2555 return core->mac[index]; 2556 } 2557 2558 static uint32_t 2559 e1000e_mac_ics_read(E1000ECore *core, int index) 2560 { 2561 trace_e1000e_irq_read_ics(core->mac[ICS]); 2562 return core->mac[ICS]; 2563 } 2564 2565 static uint32_t 2566 e1000e_mac_ims_read(E1000ECore *core, int index) 2567 { 2568 trace_e1000e_irq_read_ims(core->mac[IMS]); 2569 return core->mac[IMS]; 2570 } 2571 2572 static uint32_t 2573 e1000e_mac_swsm_read(E1000ECore *core, int index) 2574 { 2575 uint32_t val = core->mac[SWSM]; 2576 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2577 return val; 2578 } 2579 2580 static uint32_t 2581 e1000e_mac_itr_read(E1000ECore *core, int index) 2582 { 2583 return core->itr_guest_value; 2584 } 2585 2586 static uint32_t 2587 e1000e_mac_eitr_read(E1000ECore *core, int index) 2588 { 2589 return core->eitr_guest_value[index - EITR]; 2590 } 2591 2592 static uint32_t 2593 e1000e_mac_icr_read(E1000ECore *core, int index) 2594 { 2595 uint32_t ret = core->mac[ICR]; 2596 2597 if (core->mac[IMS] == 0) { 2598 trace_e1000e_irq_icr_clear_zero_ims(); 2599 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2600 } 2601 2602 if (!msix_enabled(core->owner)) { 2603 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2604 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2605 } 2606 2607 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2608 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2609 trace_e1000e_irq_icr_clear_iame(); 2610 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2611 trace_e1000e_irq_icr_process_iame(); 2612 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2613 } 2614 2615 return ret; 2616 } 2617 2618 static uint32_t 2619 e1000e_mac_read_clr4(E1000ECore *core, int index) 2620 { 2621 uint32_t ret = core->mac[index]; 2622 2623 core->mac[index] = 0; 2624 return ret; 2625 } 2626 2627 static uint32_t 2628 e1000e_mac_read_clr8(E1000ECore *core, int index) 2629 { 2630 uint32_t ret = core->mac[index]; 2631 2632 core->mac[index] = 0; 2633 core->mac[index - 1] = 0; 2634 return ret; 2635 } 2636 2637 static uint32_t 2638 e1000e_get_ctrl(E1000ECore *core, int index) 2639 { 2640 uint32_t val = core->mac[CTRL]; 2641 2642 trace_e1000e_link_read_params( 2643 !!(val & E1000_CTRL_ASDE), 2644 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2645 !!(val & E1000_CTRL_FRCSPD), 2646 !!(val & E1000_CTRL_FRCDPX), 2647 !!(val & E1000_CTRL_RFCE), 2648 !!(val & E1000_CTRL_TFCE)); 2649 2650 return val; 2651 } 2652 2653 static uint32_t 2654 e1000e_get_status(E1000ECore *core, int index) 2655 { 2656 uint32_t res = core->mac[STATUS]; 2657 2658 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2659 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2660 } 2661 2662 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2663 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2664 } else { 2665 res |= E1000_STATUS_FD; 2666 } 2667 2668 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2669 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2670 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2671 case E1000_CTRL_SPD_10: 2672 res |= E1000_STATUS_SPEED_10; 2673 break; 2674 case E1000_CTRL_SPD_100: 2675 res |= E1000_STATUS_SPEED_100; 2676 break; 2677 case E1000_CTRL_SPD_1000: 2678 default: 2679 res |= E1000_STATUS_SPEED_1000; 2680 break; 2681 } 2682 } else { 2683 res |= E1000_STATUS_SPEED_1000; 2684 } 2685 2686 trace_e1000e_link_status( 2687 !!(res & E1000_STATUS_LU), 2688 !!(res & E1000_STATUS_FD), 2689 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2690 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2691 2692 return res; 2693 } 2694 2695 static uint32_t 2696 e1000e_get_tarc(E1000ECore *core, int index) 2697 { 2698 return core->mac[index] & ((BIT(11) - 1) | 2699 BIT(27) | 2700 BIT(28) | 2701 BIT(29) | 2702 BIT(30)); 2703 } 2704 2705 static void 2706 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2707 { 2708 core->mac[index] = val; 2709 } 2710 2711 static void 2712 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2713 { 2714 uint32_t macaddr[2]; 2715 2716 core->mac[index] = val; 2717 2718 macaddr[0] = cpu_to_le32(core->mac[RA]); 2719 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2720 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2721 (uint8_t *) macaddr); 2722 2723 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2724 } 2725 2726 static void 2727 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2728 { 2729 static const uint32_t ro_bits = E1000_EECD_PRES | 2730 E1000_EECD_AUTO_RD | 2731 E1000_EECD_SIZE_EX_MASK; 2732 2733 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2734 } 2735 2736 static void 2737 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2738 { 2739 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2740 uint32_t flags = 0; 2741 uint32_t data = 0; 2742 2743 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2744 data = core->eeprom[addr]; 2745 flags = E1000_EERW_DONE; 2746 } 2747 2748 core->mac[EERD] = flags | 2749 (addr << E1000_EERW_ADDR_SHIFT) | 2750 (data << E1000_EERW_DATA_SHIFT); 2751 } 2752 2753 static void 2754 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2755 { 2756 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2757 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2758 uint32_t flags = 0; 2759 2760 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2761 core->eeprom[addr] = data; 2762 flags = E1000_EERW_DONE; 2763 } 2764 2765 core->mac[EERD] = flags | 2766 (addr << E1000_EERW_ADDR_SHIFT) | 2767 (data << E1000_EERW_DATA_SHIFT); 2768 } 2769 2770 static void 2771 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2772 { 2773 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2774 } 2775 2776 static void 2777 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2778 { 2779 uint32_t interval = val & 0xffff; 2780 2781 trace_e1000e_irq_itr_set(val); 2782 2783 core->itr_guest_value = interval; 2784 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2785 } 2786 2787 static void 2788 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2789 { 2790 uint32_t interval = val & 0xffff; 2791 uint32_t eitr_num = index - EITR; 2792 2793 trace_e1000e_irq_eitr_set(eitr_num, val); 2794 2795 core->eitr_guest_value[eitr_num] = interval; 2796 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2797 } 2798 2799 static void 2800 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2801 { 2802 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2803 2804 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2805 qemu_log_mask(LOG_GUEST_ERROR, 2806 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2807 return; 2808 } 2809 2810 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2811 qemu_log_mask(LOG_GUEST_ERROR, 2812 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2813 return; 2814 } 2815 } 2816 2817 core->mac[PSRCTL] = val; 2818 } 2819 2820 static void 2821 e1000e_update_rx_offloads(E1000ECore *core) 2822 { 2823 int cso_state = e1000e_rx_l4_cso_enabled(core); 2824 2825 trace_e1000e_rx_set_cso(cso_state); 2826 2827 if (core->has_vnet) { 2828 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2829 cso_state, 0, 0, 0, 0); 2830 } 2831 } 2832 2833 static void 2834 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2835 { 2836 core->mac[RXCSUM] = val; 2837 e1000e_update_rx_offloads(core); 2838 } 2839 2840 static void 2841 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2842 { 2843 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2844 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2845 } 2846 2847 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) 2848 { 2849 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2850 return core->mac[SYSTIML]; 2851 } 2852 2853 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) 2854 { 2855 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2856 return core->mac[RXSATRH]; 2857 } 2858 2859 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) 2860 { 2861 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2862 return core->mac[TXSTMPH]; 2863 } 2864 2865 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) 2866 { 2867 e1000x_set_timinca(core->mac, &core->timadj, val); 2868 } 2869 2870 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) 2871 { 2872 core->mac[TIMADJH] = val; 2873 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2874 } 2875 2876 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2877 typedef uint32_t (*readops)(E1000ECore *, int); 2878 static const readops e1000e_macreg_readops[] = { 2879 e1000e_getreg(PBA), 2880 e1000e_getreg(WUFC), 2881 e1000e_getreg(MANC), 2882 e1000e_getreg(TOTL), 2883 e1000e_getreg(RDT0), 2884 e1000e_getreg(RDBAH0), 2885 e1000e_getreg(TDBAL1), 2886 e1000e_getreg(RDLEN0), 2887 e1000e_getreg(RDH1), 2888 e1000e_getreg(LATECOL), 2889 e1000e_getreg(SEQEC), 2890 e1000e_getreg(XONTXC), 2891 e1000e_getreg(AIT), 2892 e1000e_getreg(TDFH), 2893 e1000e_getreg(TDFT), 2894 e1000e_getreg(TDFHS), 2895 e1000e_getreg(TDFTS), 2896 e1000e_getreg(TDFPC), 2897 e1000e_getreg(WUS), 2898 e1000e_getreg(PBS), 2899 e1000e_getreg(RDFH), 2900 e1000e_getreg(RDFT), 2901 e1000e_getreg(RDFHS), 2902 e1000e_getreg(RDFTS), 2903 e1000e_getreg(RDFPC), 2904 e1000e_getreg(GORCL), 2905 e1000e_getreg(MGTPRC), 2906 e1000e_getreg(EERD), 2907 e1000e_getreg(EIAC), 2908 e1000e_getreg(PSRCTL), 2909 e1000e_getreg(MANC2H), 2910 e1000e_getreg(RXCSUM), 2911 e1000e_getreg(GSCL_3), 2912 e1000e_getreg(GSCN_2), 2913 e1000e_getreg(RSRPD), 2914 e1000e_getreg(RDBAL1), 2915 e1000e_getreg(FCAH), 2916 e1000e_getreg(FCRTH), 2917 e1000e_getreg(FLOP), 2918 e1000e_getreg(FLASHT), 2919 e1000e_getreg(RXSTMPH), 2920 e1000e_getreg(TXSTMPL), 2921 e1000e_getreg(TIMADJL), 2922 e1000e_getreg(TXDCTL), 2923 e1000e_getreg(RDH0), 2924 e1000e_getreg(TDT1), 2925 e1000e_getreg(TNCRS), 2926 e1000e_getreg(RJC), 2927 e1000e_getreg(IAM), 2928 e1000e_getreg(GSCL_2), 2929 e1000e_getreg(RDBAH1), 2930 e1000e_getreg(FLSWDATA), 2931 e1000e_getreg(TIPG), 2932 e1000e_getreg(FLMNGCTL), 2933 e1000e_getreg(FLMNGCNT), 2934 e1000e_getreg(TSYNCTXCTL), 2935 e1000e_getreg(EXTCNF_SIZE), 2936 e1000e_getreg(EXTCNF_CTRL), 2937 e1000e_getreg(EEMNGDATA), 2938 e1000e_getreg(CTRL_EXT), 2939 e1000e_getreg(SYSTIMH), 2940 e1000e_getreg(EEMNGCTL), 2941 e1000e_getreg(FLMNGDATA), 2942 e1000e_getreg(TSYNCRXCTL), 2943 e1000e_getreg(TDH), 2944 e1000e_getreg(LEDCTL), 2945 e1000e_getreg(TCTL), 2946 e1000e_getreg(TDBAL), 2947 e1000e_getreg(TDLEN), 2948 e1000e_getreg(TDH1), 2949 e1000e_getreg(RADV), 2950 e1000e_getreg(ECOL), 2951 e1000e_getreg(DC), 2952 e1000e_getreg(RLEC), 2953 e1000e_getreg(XOFFTXC), 2954 e1000e_getreg(RFC), 2955 e1000e_getreg(RNBC), 2956 e1000e_getreg(MGTPTC), 2957 e1000e_getreg(TIMINCA), 2958 e1000e_getreg(RXCFGL), 2959 e1000e_getreg(MFUTP01), 2960 e1000e_getreg(FACTPS), 2961 e1000e_getreg(GSCL_1), 2962 e1000e_getreg(GSCN_0), 2963 e1000e_getreg(GCR2), 2964 e1000e_getreg(RDT1), 2965 e1000e_getreg(PBACLR), 2966 e1000e_getreg(FCTTV), 2967 e1000e_getreg(EEWR), 2968 e1000e_getreg(FLSWCTL), 2969 e1000e_getreg(RXDCTL1), 2970 e1000e_getreg(RXSATRL), 2971 e1000e_getreg(RXUDP), 2972 e1000e_getreg(TORL), 2973 e1000e_getreg(TDLEN1), 2974 e1000e_getreg(MCC), 2975 e1000e_getreg(WUC), 2976 e1000e_getreg(EECD), 2977 e1000e_getreg(MFUTP23), 2978 e1000e_getreg(RAID), 2979 e1000e_getreg(FCRTV), 2980 e1000e_getreg(TXDCTL1), 2981 e1000e_getreg(RCTL), 2982 e1000e_getreg(TDT), 2983 e1000e_getreg(MDIC), 2984 e1000e_getreg(FCRUC), 2985 e1000e_getreg(VET), 2986 e1000e_getreg(RDBAL0), 2987 e1000e_getreg(TDBAH1), 2988 e1000e_getreg(RDTR), 2989 e1000e_getreg(SCC), 2990 e1000e_getreg(COLC), 2991 e1000e_getreg(CEXTERR), 2992 e1000e_getreg(XOFFRXC), 2993 e1000e_getreg(IPAV), 2994 e1000e_getreg(GOTCL), 2995 e1000e_getreg(MGTPDC), 2996 e1000e_getreg(GCR), 2997 e1000e_getreg(IVAR), 2998 e1000e_getreg(POEMB), 2999 e1000e_getreg(MFVAL), 3000 e1000e_getreg(FUNCTAG), 3001 e1000e_getreg(GSCL_4), 3002 e1000e_getreg(GSCN_3), 3003 e1000e_getreg(MRQC), 3004 e1000e_getreg(RDLEN1), 3005 e1000e_getreg(FCT), 3006 e1000e_getreg(FLA), 3007 e1000e_getreg(FLOL), 3008 e1000e_getreg(RXDCTL), 3009 e1000e_getreg(RXSTMPL), 3010 e1000e_getreg(TIMADJH), 3011 e1000e_getreg(FCRTL), 3012 e1000e_getreg(TDBAH), 3013 e1000e_getreg(TADV), 3014 e1000e_getreg(XONRXC), 3015 e1000e_getreg(TSCTFC), 3016 e1000e_getreg(RFCTL), 3017 e1000e_getreg(GSCN_1), 3018 e1000e_getreg(FCAL), 3019 e1000e_getreg(FLSWCNT), 3020 3021 [TOTH] = e1000e_mac_read_clr8, 3022 [GOTCH] = e1000e_mac_read_clr8, 3023 [PRC64] = e1000e_mac_read_clr4, 3024 [PRC255] = e1000e_mac_read_clr4, 3025 [PRC1023] = e1000e_mac_read_clr4, 3026 [PTC64] = e1000e_mac_read_clr4, 3027 [PTC255] = e1000e_mac_read_clr4, 3028 [PTC1023] = e1000e_mac_read_clr4, 3029 [GPRC] = e1000e_mac_read_clr4, 3030 [TPT] = e1000e_mac_read_clr4, 3031 [RUC] = e1000e_mac_read_clr4, 3032 [BPRC] = e1000e_mac_read_clr4, 3033 [MPTC] = e1000e_mac_read_clr4, 3034 [IAC] = e1000e_mac_read_clr4, 3035 [ICR] = e1000e_mac_icr_read, 3036 [STATUS] = e1000e_get_status, 3037 [TARC0] = e1000e_get_tarc, 3038 [ICS] = e1000e_mac_ics_read, 3039 [TORH] = e1000e_mac_read_clr8, 3040 [GORCH] = e1000e_mac_read_clr8, 3041 [PRC127] = e1000e_mac_read_clr4, 3042 [PRC511] = e1000e_mac_read_clr4, 3043 [PRC1522] = e1000e_mac_read_clr4, 3044 [PTC127] = e1000e_mac_read_clr4, 3045 [PTC511] = e1000e_mac_read_clr4, 3046 [PTC1522] = e1000e_mac_read_clr4, 3047 [GPTC] = e1000e_mac_read_clr4, 3048 [TPR] = e1000e_mac_read_clr4, 3049 [ROC] = e1000e_mac_read_clr4, 3050 [MPRC] = e1000e_mac_read_clr4, 3051 [BPTC] = e1000e_mac_read_clr4, 3052 [TSCTC] = e1000e_mac_read_clr4, 3053 [ITR] = e1000e_mac_itr_read, 3054 [CTRL] = e1000e_get_ctrl, 3055 [TARC1] = e1000e_get_tarc, 3056 [SWSM] = e1000e_mac_swsm_read, 3057 [IMS] = e1000e_mac_ims_read, 3058 [SYSTIML] = e1000e_get_systiml, 3059 [RXSATRH] = e1000e_get_rxsatrh, 3060 [TXSTMPH] = e1000e_get_txstmph, 3061 3062 [CRCERRS ... MPC] = e1000e_mac_readreg, 3063 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3064 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3065 [RA ... RA + 31] = e1000e_mac_readreg, 3066 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3067 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3068 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3069 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3070 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3071 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3072 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3073 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3074 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3075 [RETA ... RETA + 31] = e1000e_mac_readreg, 3076 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3077 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3078 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3079 }; 3080 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3081 3082 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3083 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3084 static const writeops e1000e_macreg_writeops[] = { 3085 e1000e_putreg(PBA), 3086 e1000e_putreg(SWSM), 3087 e1000e_putreg(WUFC), 3088 e1000e_putreg(RDBAH1), 3089 e1000e_putreg(TDBAH), 3090 e1000e_putreg(TXDCTL), 3091 e1000e_putreg(RDBAH0), 3092 e1000e_putreg(LEDCTL), 3093 e1000e_putreg(FCAL), 3094 e1000e_putreg(FCRUC), 3095 e1000e_putreg(WUC), 3096 e1000e_putreg(WUS), 3097 e1000e_putreg(IPAV), 3098 e1000e_putreg(TDBAH1), 3099 e1000e_putreg(IAM), 3100 e1000e_putreg(EIAC), 3101 e1000e_putreg(IVAR), 3102 e1000e_putreg(TARC0), 3103 e1000e_putreg(TARC1), 3104 e1000e_putreg(FLSWDATA), 3105 e1000e_putreg(POEMB), 3106 e1000e_putreg(MFUTP01), 3107 e1000e_putreg(MFUTP23), 3108 e1000e_putreg(MANC), 3109 e1000e_putreg(MANC2H), 3110 e1000e_putreg(MFVAL), 3111 e1000e_putreg(EXTCNF_CTRL), 3112 e1000e_putreg(FACTPS), 3113 e1000e_putreg(FUNCTAG), 3114 e1000e_putreg(GSCL_1), 3115 e1000e_putreg(GSCL_2), 3116 e1000e_putreg(GSCL_3), 3117 e1000e_putreg(GSCL_4), 3118 e1000e_putreg(GSCN_0), 3119 e1000e_putreg(GSCN_1), 3120 e1000e_putreg(GSCN_2), 3121 e1000e_putreg(GSCN_3), 3122 e1000e_putreg(GCR2), 3123 e1000e_putreg(MRQC), 3124 e1000e_putreg(FLOP), 3125 e1000e_putreg(FLOL), 3126 e1000e_putreg(FLSWCTL), 3127 e1000e_putreg(FLSWCNT), 3128 e1000e_putreg(FLA), 3129 e1000e_putreg(RXDCTL1), 3130 e1000e_putreg(TXDCTL1), 3131 e1000e_putreg(TIPG), 3132 e1000e_putreg(RXSTMPH), 3133 e1000e_putreg(RXSTMPL), 3134 e1000e_putreg(RXSATRL), 3135 e1000e_putreg(RXSATRH), 3136 e1000e_putreg(TXSTMPL), 3137 e1000e_putreg(TXSTMPH), 3138 e1000e_putreg(SYSTIML), 3139 e1000e_putreg(SYSTIMH), 3140 e1000e_putreg(TIMADJL), 3141 e1000e_putreg(RXUDP), 3142 e1000e_putreg(RXCFGL), 3143 e1000e_putreg(TSYNCRXCTL), 3144 e1000e_putreg(TSYNCTXCTL), 3145 e1000e_putreg(EXTCNF_SIZE), 3146 e1000e_putreg(EEMNGCTL), 3147 e1000e_putreg(RA), 3148 3149 [TDH1] = e1000e_set_16bit, 3150 [TDT1] = e1000e_set_tdt, 3151 [TCTL] = e1000e_set_tctl, 3152 [TDT] = e1000e_set_tdt, 3153 [MDIC] = e1000e_set_mdic, 3154 [ICS] = e1000e_set_ics, 3155 [TDH] = e1000e_set_16bit, 3156 [RDH0] = e1000e_set_16bit, 3157 [RDT0] = e1000e_set_rdt, 3158 [IMC] = e1000e_set_imc, 3159 [IMS] = e1000e_set_ims, 3160 [ICR] = e1000e_set_icr, 3161 [EECD] = e1000e_set_eecd, 3162 [RCTL] = e1000e_set_rx_control, 3163 [CTRL] = e1000e_set_ctrl, 3164 [RDTR] = e1000e_set_rdtr, 3165 [RADV] = e1000e_set_16bit, 3166 [TADV] = e1000e_set_16bit, 3167 [ITR] = e1000e_set_itr, 3168 [EERD] = e1000e_set_eerd, 3169 [AIT] = e1000e_set_16bit, 3170 [TDFH] = e1000e_set_13bit, 3171 [TDFT] = e1000e_set_13bit, 3172 [TDFHS] = e1000e_set_13bit, 3173 [TDFTS] = e1000e_set_13bit, 3174 [TDFPC] = e1000e_set_13bit, 3175 [RDFH] = e1000e_set_13bit, 3176 [RDFHS] = e1000e_set_13bit, 3177 [RDFT] = e1000e_set_13bit, 3178 [RDFTS] = e1000e_set_13bit, 3179 [RDFPC] = e1000e_set_13bit, 3180 [PBS] = e1000e_set_6bit, 3181 [GCR] = e1000e_set_gcr, 3182 [PSRCTL] = e1000e_set_psrctl, 3183 [RXCSUM] = e1000e_set_rxcsum, 3184 [RAID] = e1000e_set_16bit, 3185 [RSRPD] = e1000e_set_12bit, 3186 [TIDV] = e1000e_set_tidv, 3187 [TDLEN1] = e1000e_set_dlen, 3188 [TDLEN] = e1000e_set_dlen, 3189 [RDLEN0] = e1000e_set_dlen, 3190 [RDLEN1] = e1000e_set_dlen, 3191 [TDBAL] = e1000e_set_dbal, 3192 [TDBAL1] = e1000e_set_dbal, 3193 [RDBAL0] = e1000e_set_dbal, 3194 [RDBAL1] = e1000e_set_dbal, 3195 [RDH1] = e1000e_set_16bit, 3196 [RDT1] = e1000e_set_rdt, 3197 [STATUS] = e1000e_set_status, 3198 [PBACLR] = e1000e_set_pbaclr, 3199 [CTRL_EXT] = e1000e_set_ctrlext, 3200 [FCAH] = e1000e_set_16bit, 3201 [FCT] = e1000e_set_16bit, 3202 [FCTTV] = e1000e_set_16bit, 3203 [FCRTV] = e1000e_set_16bit, 3204 [FCRTH] = e1000e_set_fcrth, 3205 [FCRTL] = e1000e_set_fcrtl, 3206 [VET] = e1000e_set_vet, 3207 [RXDCTL] = e1000e_set_rxdctl, 3208 [FLASHT] = e1000e_set_16bit, 3209 [EEWR] = e1000e_set_eewr, 3210 [CTRL_DUP] = e1000e_set_ctrl, 3211 [RFCTL] = e1000e_set_rfctl, 3212 [RA + 1] = e1000e_mac_setmacaddr, 3213 [TIMINCA] = e1000e_set_timinca, 3214 [TIMADJH] = e1000e_set_timadjh, 3215 3216 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3217 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3218 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3219 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3220 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3221 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3222 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3223 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3224 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3225 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3226 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3227 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3228 [RETA ... RETA + 31] = e1000e_mac_writereg, 3229 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3230 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3231 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3232 }; 3233 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3234 3235 enum { MAC_ACCESS_PARTIAL = 1 }; 3236 3237 /* 3238 * The array below combines alias offsets of the index values for the 3239 * MAC registers that have aliases, with the indication of not fully 3240 * implemented registers (lowest bit). This combination is possible 3241 * because all of the offsets are even. 3242 */ 3243 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3244 /* Alias index offsets */ 3245 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3246 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3247 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3248 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3249 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3250 [RA_A ... RA_A + 31] = 0x14f0, 3251 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3252 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3253 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3254 /* Access options */ 3255 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3256 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3257 [RDFPC] = MAC_ACCESS_PARTIAL, 3258 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3259 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3260 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3261 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3262 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3263 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3264 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3265 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3266 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3267 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3268 }; 3269 3270 void 3271 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3272 { 3273 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3274 3275 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3276 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3277 trace_e1000e_wrn_regs_write_trivial(index << 2); 3278 } 3279 trace_e1000e_core_write(index << 2, size, val); 3280 e1000e_macreg_writeops[index](core, index, val); 3281 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3282 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3283 } else { 3284 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3285 } 3286 } 3287 3288 uint64_t 3289 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3290 { 3291 uint64_t val; 3292 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3293 3294 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3295 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3296 trace_e1000e_wrn_regs_read_trivial(index << 2); 3297 } 3298 val = e1000e_macreg_readops[index](core, index); 3299 trace_e1000e_core_read(index << 2, size, val); 3300 return val; 3301 } else { 3302 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3303 } 3304 return 0; 3305 } 3306 3307 static inline void 3308 e1000e_autoneg_pause(E1000ECore *core) 3309 { 3310 timer_del(core->autoneg_timer); 3311 } 3312 3313 static void 3314 e1000e_autoneg_resume(E1000ECore *core) 3315 { 3316 if (e1000e_have_autoneg(core) && 3317 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3318 qemu_get_queue(core->owner_nic)->link_down = false; 3319 timer_mod(core->autoneg_timer, 3320 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3321 } 3322 } 3323 3324 static void 3325 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3326 { 3327 E1000ECore *core = opaque; 3328 3329 if (running) { 3330 trace_e1000e_vm_state_running(); 3331 e1000e_intrmgr_resume(core); 3332 e1000e_autoneg_resume(core); 3333 } else { 3334 trace_e1000e_vm_state_stopped(); 3335 e1000e_autoneg_pause(core); 3336 e1000e_intrmgr_pause(core); 3337 } 3338 } 3339 3340 void 3341 e1000e_core_pci_realize(E1000ECore *core, 3342 const uint16_t *eeprom_templ, 3343 uint32_t eeprom_size, 3344 const uint8_t *macaddr) 3345 { 3346 int i; 3347 3348 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3349 e1000e_autoneg_timer, core); 3350 e1000e_intrmgr_pci_realize(core); 3351 3352 core->vmstate = 3353 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3354 3355 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3356 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3357 } 3358 3359 net_rx_pkt_init(&core->rx_pkt); 3360 3361 e1000x_core_prepare_eeprom(core->eeprom, 3362 eeprom_templ, 3363 eeprom_size, 3364 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3365 macaddr); 3366 e1000e_update_rx_offloads(core); 3367 } 3368 3369 void 3370 e1000e_core_pci_uninit(E1000ECore *core) 3371 { 3372 int i; 3373 3374 timer_free(core->autoneg_timer); 3375 3376 e1000e_intrmgr_pci_unint(core); 3377 3378 qemu_del_vm_change_state_handler(core->vmstate); 3379 3380 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3381 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3382 } 3383 3384 net_rx_pkt_uninit(core->rx_pkt); 3385 } 3386 3387 static const uint16_t 3388 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3389 [0] = { 3390 [MII_BMCR] = MII_BMCR_SPEED1000 | 3391 MII_BMCR_FD | 3392 MII_BMCR_AUTOEN, 3393 3394 [MII_BMSR] = MII_BMSR_EXTCAP | 3395 MII_BMSR_LINK_ST | 3396 MII_BMSR_AUTONEG | 3397 MII_BMSR_MFPS | 3398 MII_BMSR_EXTSTAT | 3399 MII_BMSR_10T_HD | 3400 MII_BMSR_10T_FD | 3401 MII_BMSR_100TX_HD | 3402 MII_BMSR_100TX_FD, 3403 3404 [MII_PHYID1] = 0x141, 3405 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3406 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3407 MII_ANAR_10FD | MII_ANAR_TX | 3408 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3409 MII_ANAR_PAUSE_ASYM, 3410 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3411 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3412 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3413 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3414 [MII_ANNP] = 1 | MII_ANNP_MP, 3415 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3416 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3417 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3418 MII_STAT1000_ROK | MII_STAT1000_LOK, 3419 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3420 3421 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3422 BIT(12) | BIT(13), 3423 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3424 }, 3425 [2] = { 3426 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3427 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3428 }, 3429 [3] = { 3430 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3431 } 3432 }; 3433 3434 static const uint32_t e1000e_mac_reg_init[] = { 3435 [PBA] = 0x00140014, 3436 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3437 [EXTCNF_CTRL] = BIT(3), 3438 [EEMNGCTL] = BIT(31), 3439 [FLASHT] = 0x2, 3440 [FLSWCTL] = BIT(30) | BIT(31), 3441 [FLOL] = BIT(0), 3442 [RXDCTL] = BIT(16), 3443 [RXDCTL1] = BIT(16), 3444 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3445 [RXCFGL] = 0x88F7, 3446 [RXUDP] = 0x319, 3447 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3448 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3449 E1000_CTRL_ADVD3WUC, 3450 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3451 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3452 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3453 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3454 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3455 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3456 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3457 [EERD] = E1000_EERW_DONE, 3458 [EEWR] = E1000_EERW_DONE, 3459 [GCR] = E1000_L0S_ADJUST | 3460 E1000_L1_ENTRY_LATENCY_MSB | 3461 E1000_L1_ENTRY_LATENCY_LSB, 3462 [TDFH] = 0x600, 3463 [TDFT] = 0x600, 3464 [TDFHS] = 0x600, 3465 [TDFTS] = 0x600, 3466 [POEMB] = 0x30D, 3467 [PBS] = 0x028, 3468 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3469 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3470 [SWSM] = 1, 3471 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3472 [ITR] = E1000E_MIN_XITR, 3473 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3474 }; 3475 3476 static void e1000e_reset(E1000ECore *core, bool sw) 3477 { 3478 int i; 3479 3480 timer_del(core->autoneg_timer); 3481 3482 e1000e_intrmgr_reset(core); 3483 3484 memset(core->phy, 0, sizeof core->phy); 3485 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3486 3487 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3488 if (sw && (i == PBA || i == PBS || i == FLA)) { 3489 continue; 3490 } 3491 3492 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3493 e1000e_mac_reg_init[i] : 0; 3494 } 3495 3496 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3497 3498 if (qemu_get_queue(core->owner_nic)->link_down) { 3499 e1000e_link_down(core); 3500 } 3501 3502 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3503 3504 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3505 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3506 core->tx[i].skip_cp = false; 3507 } 3508 } 3509 3510 void 3511 e1000e_core_reset(E1000ECore *core) 3512 { 3513 e1000e_reset(core, false); 3514 } 3515 3516 void e1000e_core_pre_save(E1000ECore *core) 3517 { 3518 int i; 3519 NetClientState *nc = qemu_get_queue(core->owner_nic); 3520 3521 /* 3522 * If link is down and auto-negotiation is supported and ongoing, 3523 * complete auto-negotiation immediately. This allows us to look 3524 * at MII_BMSR_AN_COMP to infer link status on load. 3525 */ 3526 if (nc->link_down && e1000e_have_autoneg(core)) { 3527 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3528 e1000e_update_flowctl_status(core); 3529 } 3530 3531 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3532 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3533 core->tx[i].skip_cp = true; 3534 } 3535 } 3536 } 3537 3538 int 3539 e1000e_core_post_load(E1000ECore *core) 3540 { 3541 NetClientState *nc = qemu_get_queue(core->owner_nic); 3542 3543 /* 3544 * nc.link_down can't be migrated, so infer link_down according 3545 * to link status bit in core.mac[STATUS]. 3546 */ 3547 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3548 3549 return 0; 3550 } 3551