1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "system/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000_common.h" 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 55 #define E1000E_MIN_XITR (500) 56 57 #define E1000E_MAX_TX_FRAGS (64) 58 59 union e1000_rx_desc_union { 60 struct e1000_rx_desc legacy; 61 union e1000_rx_desc_extended extended; 62 union e1000_rx_desc_packet_split packet_split; 63 }; 64 65 static ssize_t 66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 67 bool has_vnet); 68 69 static inline void 70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 71 72 static void e1000e_reset(E1000ECore *core, bool sw); 73 74 static inline void 75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 76 { 77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 78 trace_e1000e_wrn_no_ts_support(); 79 } 80 } 81 82 static inline void 83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 84 { 85 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 86 trace_e1000e_wrn_no_snap_support(); 87 } 88 } 89 90 static inline void 91 e1000e_raise_legacy_irq(E1000ECore *core) 92 { 93 trace_e1000e_irq_legacy_notify(true); 94 e1000x_inc_reg_if_not_full(core->mac, IAC); 95 pci_set_irq(core->owner, 1); 96 } 97 98 static inline void 99 e1000e_lower_legacy_irq(E1000ECore *core) 100 { 101 trace_e1000e_irq_legacy_notify(false); 102 pci_set_irq(core->owner, 0); 103 } 104 105 static inline void 106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 107 { 108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 109 timer->delay_resolution_ns; 110 111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 112 113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 114 115 timer->running = true; 116 } 117 118 static void 119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 e1000e_intrmgr_rearm_timer(timer); 123 } 124 } 125 126 static inline void 127 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 128 { 129 if (timer->running) { 130 timer_del(timer->timer); 131 timer->running = false; 132 } 133 } 134 135 static inline void 136 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 137 { 138 trace_e1000e_irq_fire_delayed_interrupts(); 139 e1000e_set_interrupt_cause(core, 0); 140 } 141 142 static void 143 e1000e_intrmgr_on_timer(void *opaque) 144 { 145 E1000IntrDelayTimer *timer = opaque; 146 147 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 148 149 timer->running = false; 150 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 151 } 152 153 static void 154 e1000e_intrmgr_on_throttling_timer(void *opaque) 155 { 156 E1000IntrDelayTimer *timer = opaque; 157 158 timer->running = false; 159 160 if (timer->core->mac[IMS] & timer->core->mac[ICR]) { 161 if (msi_enabled(timer->core->owner)) { 162 trace_e1000e_irq_msi_notify_postponed(); 163 msi_notify(timer->core->owner, 0); 164 } else { 165 trace_e1000e_irq_legacy_notify_postponed(); 166 e1000e_raise_legacy_irq(timer->core); 167 } 168 } 169 } 170 171 static void 172 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 173 { 174 E1000IntrDelayTimer *timer = opaque; 175 int idx = timer - &timer->core->eitr[0]; 176 177 timer->running = false; 178 179 trace_e1000e_irq_msix_notify_postponed_vec(idx); 180 msix_notify(timer->core->owner, idx); 181 } 182 183 static void 184 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 185 { 186 int i; 187 188 core->radv.delay_reg = RADV; 189 core->rdtr.delay_reg = RDTR; 190 core->raid.delay_reg = RAID; 191 core->tadv.delay_reg = TADV; 192 core->tidv.delay_reg = TIDV; 193 194 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 195 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 196 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 197 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 198 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 199 200 core->radv.core = core; 201 core->rdtr.core = core; 202 core->raid.core = core; 203 core->tadv.core = core; 204 core->tidv.core = core; 205 206 core->itr.core = core; 207 core->itr.delay_reg = ITR; 208 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 209 210 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 211 core->eitr[i].core = core; 212 core->eitr[i].delay_reg = EITR + i; 213 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 214 } 215 216 if (!create) { 217 return; 218 } 219 220 core->radv.timer = 221 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 222 core->rdtr.timer = 223 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 224 core->raid.timer = 225 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 226 227 core->tadv.timer = 228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 229 core->tidv.timer = 230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 231 232 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 233 e1000e_intrmgr_on_throttling_timer, 234 &core->itr); 235 236 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 237 core->eitr[i].timer = 238 timer_new_ns(QEMU_CLOCK_VIRTUAL, 239 e1000e_intrmgr_on_msix_throttling_timer, 240 &core->eitr[i]); 241 } 242 } 243 244 static inline void 245 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 246 { 247 e1000e_intrmgr_stop_timer(&core->radv); 248 e1000e_intrmgr_stop_timer(&core->rdtr); 249 e1000e_intrmgr_stop_timer(&core->raid); 250 e1000e_intrmgr_stop_timer(&core->tidv); 251 e1000e_intrmgr_stop_timer(&core->tadv); 252 } 253 254 static bool 255 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 256 { 257 uint32_t delayable_causes; 258 uint32_t rdtr = core->mac[RDTR]; 259 uint32_t radv = core->mac[RADV]; 260 uint32_t raid = core->mac[RAID]; 261 262 if (msix_enabled(core->owner)) { 263 return false; 264 } 265 266 delayable_causes = E1000_ICR_RXQ0 | 267 E1000_ICR_RXQ1 | 268 E1000_ICR_RXT0; 269 270 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 271 delayable_causes |= E1000_ICR_ACK; 272 } 273 274 /* Clean up all causes that may be delayed */ 275 core->delayed_causes |= *causes & delayable_causes; 276 *causes &= ~delayable_causes; 277 278 /* 279 * Check if delayed RX interrupts disabled by client 280 * or if there are causes that cannot be delayed 281 */ 282 if ((rdtr == 0) || (*causes != 0)) { 283 return false; 284 } 285 286 /* 287 * Check if delayed RX ACK interrupts disabled by client 288 * and there is an ACK packet received 289 */ 290 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 291 return false; 292 } 293 294 /* All causes delayed */ 295 e1000e_intrmgr_rearm_timer(&core->rdtr); 296 297 if (!core->radv.running && (radv != 0)) { 298 e1000e_intrmgr_rearm_timer(&core->radv); 299 } 300 301 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 302 e1000e_intrmgr_rearm_timer(&core->raid); 303 } 304 305 return true; 306 } 307 308 static bool 309 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 310 { 311 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 312 E1000_ICR_TXQ1 | 313 E1000_ICR_TXQE | 314 E1000_ICR_TXDW; 315 316 if (msix_enabled(core->owner)) { 317 return false; 318 } 319 320 /* Clean up all causes that may be delayed */ 321 core->delayed_causes |= *causes & delayable_causes; 322 *causes &= ~delayable_causes; 323 324 /* If there are causes that cannot be delayed */ 325 if (*causes != 0) { 326 return false; 327 } 328 329 /* All causes delayed */ 330 e1000e_intrmgr_rearm_timer(&core->tidv); 331 332 if (!core->tadv.running && (core->mac[TADV] != 0)) { 333 e1000e_intrmgr_rearm_timer(&core->tadv); 334 } 335 336 return true; 337 } 338 339 static uint32_t 340 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 341 { 342 uint32_t res; 343 344 res = core->delayed_causes; 345 core->delayed_causes = 0; 346 347 e1000e_intrmgr_stop_delay_timers(core); 348 349 return res; 350 } 351 352 static void 353 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 354 { 355 int i; 356 357 if (core->itr.running) { 358 timer_del(core->itr.timer); 359 e1000e_intrmgr_on_throttling_timer(&core->itr); 360 } 361 362 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 363 if (core->eitr[i].running) { 364 timer_del(core->eitr[i].timer); 365 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 366 } 367 } 368 } 369 370 static void 371 e1000e_intrmgr_resume(E1000ECore *core) 372 { 373 int i; 374 375 e1000e_intmgr_timer_resume(&core->radv); 376 e1000e_intmgr_timer_resume(&core->rdtr); 377 e1000e_intmgr_timer_resume(&core->raid); 378 e1000e_intmgr_timer_resume(&core->tidv); 379 e1000e_intmgr_timer_resume(&core->tadv); 380 381 e1000e_intmgr_timer_resume(&core->itr); 382 383 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 384 e1000e_intmgr_timer_resume(&core->eitr[i]); 385 } 386 } 387 388 static void 389 e1000e_intrmgr_reset(E1000ECore *core) 390 { 391 int i; 392 393 core->delayed_causes = 0; 394 395 e1000e_intrmgr_stop_delay_timers(core); 396 397 e1000e_intrmgr_stop_timer(&core->itr); 398 399 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 400 e1000e_intrmgr_stop_timer(&core->eitr[i]); 401 } 402 } 403 404 static void 405 e1000e_intrmgr_pci_unint(E1000ECore *core) 406 { 407 int i; 408 409 timer_free(core->radv.timer); 410 timer_free(core->rdtr.timer); 411 timer_free(core->raid.timer); 412 413 timer_free(core->tadv.timer); 414 timer_free(core->tidv.timer); 415 416 timer_free(core->itr.timer); 417 418 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 419 timer_free(core->eitr[i].timer); 420 } 421 } 422 423 static void 424 e1000e_intrmgr_pci_realize(E1000ECore *core) 425 { 426 e1000e_intrmgr_initialize_all_timers(core, true); 427 } 428 429 static inline bool 430 e1000e_rx_csum_enabled(E1000ECore *core) 431 { 432 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 433 } 434 435 static inline bool 436 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 437 { 438 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 439 } 440 441 static inline bool 442 e1000e_rx_use_ps_descriptor(E1000ECore *core) 443 { 444 return !e1000e_rx_use_legacy_descriptor(core) && 445 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 446 } 447 448 static inline bool 449 e1000e_rss_enabled(E1000ECore *core) 450 { 451 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 452 !e1000e_rx_csum_enabled(core) && 453 !e1000e_rx_use_legacy_descriptor(core); 454 } 455 456 typedef struct E1000E_RSSInfo_st { 457 bool enabled; 458 uint32_t hash; 459 uint32_t queue; 460 uint32_t type; 461 } E1000E_RSSInfo; 462 463 static uint32_t 464 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 465 { 466 bool hasip4, hasip6; 467 EthL4HdrProto l4hdr_proto; 468 469 assert(e1000e_rss_enabled(core)); 470 471 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 472 473 if (hasip4) { 474 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 475 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 476 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 477 478 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 479 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 480 return E1000_MRQ_RSS_TYPE_IPV4TCP; 481 } 482 483 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 484 return E1000_MRQ_RSS_TYPE_IPV4; 485 } 486 } else if (hasip6) { 487 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 488 489 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 490 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 491 492 /* 493 * Following two traces must not be combined because resulting 494 * event will have 11 arguments totally and some trace backends 495 * (at least "ust") have limitation of maximum 10 arguments per 496 * event. Events with more arguments fail to compile for 497 * backends like these. 498 */ 499 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 500 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 501 ip6info->has_ext_hdrs, 502 ip6info->rss_ex_dst_valid, 503 ip6info->rss_ex_src_valid, 504 core->mac[MRQC], 505 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), 506 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 507 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 508 509 if ((!ex_dis || !ip6info->has_ext_hdrs) && 510 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 511 ip6info->rss_ex_src_valid))) { 512 513 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 514 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { 515 return E1000_MRQ_RSS_TYPE_IPV6TCPEX; 516 } 517 518 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 519 return E1000_MRQ_RSS_TYPE_IPV6EX; 520 } 521 522 } 523 524 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 525 return E1000_MRQ_RSS_TYPE_IPV6; 526 } 527 528 } 529 530 return E1000_MRQ_RSS_TYPE_NONE; 531 } 532 533 static uint32_t 534 e1000e_rss_calc_hash(E1000ECore *core, 535 struct NetRxPkt *pkt, 536 E1000E_RSSInfo *info) 537 { 538 NetRxPktRssType type; 539 540 assert(e1000e_rss_enabled(core)); 541 542 switch (info->type) { 543 case E1000_MRQ_RSS_TYPE_IPV4: 544 type = NetPktRssIpV4; 545 break; 546 case E1000_MRQ_RSS_TYPE_IPV4TCP: 547 type = NetPktRssIpV4Tcp; 548 break; 549 case E1000_MRQ_RSS_TYPE_IPV6TCPEX: 550 type = NetPktRssIpV6TcpEx; 551 break; 552 case E1000_MRQ_RSS_TYPE_IPV6: 553 type = NetPktRssIpV6; 554 break; 555 case E1000_MRQ_RSS_TYPE_IPV6EX: 556 type = NetPktRssIpV6Ex; 557 break; 558 default: 559 g_assert_not_reached(); 560 } 561 562 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 563 } 564 565 static void 566 e1000e_rss_parse_packet(E1000ECore *core, 567 struct NetRxPkt *pkt, 568 E1000E_RSSInfo *info) 569 { 570 trace_e1000e_rx_rss_started(); 571 572 if (!e1000e_rss_enabled(core)) { 573 info->enabled = false; 574 info->hash = 0; 575 info->queue = 0; 576 info->type = 0; 577 trace_e1000e_rx_rss_disabled(); 578 return; 579 } 580 581 info->enabled = true; 582 583 info->type = e1000e_rss_get_hash_type(core, pkt); 584 585 trace_e1000e_rx_rss_type(info->type); 586 587 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 588 info->hash = 0; 589 info->queue = 0; 590 return; 591 } 592 593 info->hash = e1000e_rss_calc_hash(core, pkt, info); 594 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 595 } 596 597 static bool 598 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 599 { 600 if (tx->props.tse && tx->cptse) { 601 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 602 return false; 603 } 604 605 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 606 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 607 return true; 608 } 609 610 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 611 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 612 return false; 613 } 614 } 615 616 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 617 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 618 } 619 620 return true; 621 } 622 623 static void e1000e_tx_pkt_callback(void *core, 624 const struct iovec *iov, 625 int iovcnt, 626 const struct iovec *virt_iov, 627 int virt_iovcnt) 628 { 629 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 630 } 631 632 static bool 633 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 634 { 635 int target_queue = MIN(core->max_queue_num, queue_index); 636 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 637 638 if (!e1000e_setup_tx_offloads(core, tx)) { 639 return false; 640 } 641 642 net_tx_pkt_dump(tx->tx_pkt); 643 644 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 645 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 646 return net_tx_pkt_send_custom(tx->tx_pkt, false, 647 e1000e_tx_pkt_callback, core); 648 } else { 649 return net_tx_pkt_send(tx->tx_pkt, queue); 650 } 651 } 652 653 static void 654 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 655 { 656 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 657 PTC1023, PTC1522 }; 658 659 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 660 661 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 662 e1000x_inc_reg_if_not_full(core->mac, TPT); 663 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 664 665 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 666 case ETH_PKT_BCAST: 667 e1000x_inc_reg_if_not_full(core->mac, BPTC); 668 break; 669 case ETH_PKT_MCAST: 670 e1000x_inc_reg_if_not_full(core->mac, MPTC); 671 break; 672 case ETH_PKT_UCAST: 673 break; 674 default: 675 g_assert_not_reached(); 676 } 677 678 e1000x_inc_reg_if_not_full(core->mac, GPTC); 679 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 680 } 681 682 static void 683 e1000e_process_tx_desc(E1000ECore *core, 684 struct e1000e_tx *tx, 685 struct e1000_tx_desc *dp, 686 int queue_index) 687 { 688 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 689 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 690 unsigned int split_size = txd_lower & 0xffff; 691 uint64_t addr; 692 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 693 bool eop = txd_lower & E1000_TXD_CMD_EOP; 694 695 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 696 e1000x_read_tx_ctx_descr(xp, &tx->props); 697 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 698 return; 699 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 700 /* data descriptor */ 701 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 702 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 703 e1000e_process_ts_option(core, dp); 704 } else { 705 /* legacy descriptor */ 706 e1000e_process_ts_option(core, dp); 707 tx->cptse = 0; 708 } 709 710 addr = le64_to_cpu(dp->buffer_addr); 711 712 if (!tx->skip_cp) { 713 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, 714 addr, split_size)) { 715 tx->skip_cp = true; 716 } 717 } 718 719 if (eop) { 720 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 721 if (e1000x_vlan_enabled(core->mac) && 722 e1000x_is_vlan_txd(txd_lower)) { 723 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 724 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 725 } 726 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 727 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 728 } 729 } 730 731 tx->skip_cp = false; 732 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 733 734 tx->sum_needed = 0; 735 tx->cptse = 0; 736 } 737 } 738 739 static inline uint32_t 740 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 741 { 742 if (!msix_enabled(core->owner)) { 743 return E1000_ICR_TXDW; 744 } 745 746 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 747 } 748 749 static inline uint32_t 750 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 751 bool min_threshold_hit) 752 { 753 if (!msix_enabled(core->owner)) { 754 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 755 } 756 757 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 758 } 759 760 static uint32_t 761 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 762 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 763 { 764 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 765 766 if (!(txd_lower & E1000_TXD_CMD_RS) && 767 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 768 return 0; 769 } 770 771 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 772 773 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 774 775 dp->upper.data = cpu_to_le32(txd_upper); 776 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 777 &dp->upper, sizeof(dp->upper)); 778 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 779 } 780 781 typedef struct E1000ERingInfo { 782 int dbah; 783 int dbal; 784 int dlen; 785 int dh; 786 int dt; 787 int idx; 788 } E1000ERingInfo; 789 790 static inline bool 791 e1000e_ring_empty(E1000ECore *core, const E1000ERingInfo *r) 792 { 793 return core->mac[r->dh] == core->mac[r->dt] || 794 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 795 } 796 797 static inline uint64_t 798 e1000e_ring_base(E1000ECore *core, const E1000ERingInfo *r) 799 { 800 uint64_t bah = core->mac[r->dbah]; 801 uint64_t bal = core->mac[r->dbal]; 802 803 return (bah << 32) + bal; 804 } 805 806 static inline uint64_t 807 e1000e_ring_head_descr(E1000ECore *core, const E1000ERingInfo *r) 808 { 809 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 810 } 811 812 static inline void 813 e1000e_ring_advance(E1000ECore *core, const E1000ERingInfo *r, uint32_t count) 814 { 815 core->mac[r->dh] += count; 816 817 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 818 core->mac[r->dh] = 0; 819 } 820 } 821 822 static inline uint32_t 823 e1000e_ring_free_descr_num(E1000ECore *core, const E1000ERingInfo *r) 824 { 825 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 826 core->mac[r->dh], core->mac[r->dt]); 827 828 if (core->mac[r->dh] <= core->mac[r->dt]) { 829 return core->mac[r->dt] - core->mac[r->dh]; 830 } 831 832 if (core->mac[r->dh] > core->mac[r->dt]) { 833 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 834 core->mac[r->dt] - core->mac[r->dh]; 835 } 836 837 g_assert_not_reached(); 838 } 839 840 static inline bool 841 e1000e_ring_enabled(E1000ECore *core, const E1000ERingInfo *r) 842 { 843 return core->mac[r->dlen] > 0; 844 } 845 846 static inline uint32_t 847 e1000e_ring_len(E1000ECore *core, const E1000ERingInfo *r) 848 { 849 return core->mac[r->dlen]; 850 } 851 852 typedef struct E1000E_TxRing_st { 853 const E1000ERingInfo *i; 854 struct e1000e_tx *tx; 855 } E1000E_TxRing; 856 857 static inline int 858 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 859 { 860 return (reg_idx - base_reg_idx) / (0x100 >> 2); 861 } 862 863 static inline void 864 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 865 { 866 static const E1000ERingInfo i[E1000E_NUM_QUEUES] = { 867 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 868 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 869 }; 870 871 assert(idx < ARRAY_SIZE(i)); 872 873 txr->i = &i[idx]; 874 txr->tx = &core->tx[idx]; 875 } 876 877 typedef struct E1000E_RxRing_st { 878 const E1000ERingInfo *i; 879 } E1000E_RxRing; 880 881 static inline void 882 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 883 { 884 static const E1000ERingInfo i[E1000E_NUM_QUEUES] = { 885 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 886 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 887 }; 888 889 assert(idx < ARRAY_SIZE(i)); 890 891 rxr->i = &i[idx]; 892 } 893 894 static void 895 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 896 { 897 dma_addr_t base; 898 struct e1000_tx_desc desc; 899 bool ide = false; 900 const E1000ERingInfo *txi = txr->i; 901 uint32_t cause = E1000_ICS_TXQE; 902 903 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 904 trace_e1000e_tx_disabled(); 905 return; 906 } 907 908 while (!e1000e_ring_empty(core, txi)) { 909 base = e1000e_ring_head_descr(core, txi); 910 911 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 912 913 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 914 desc.lower.data, desc.upper.data); 915 916 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 917 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 918 919 e1000e_ring_advance(core, txi, 1); 920 } 921 922 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 923 e1000e_set_interrupt_cause(core, cause); 924 } 925 926 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 927 } 928 929 static bool 930 e1000e_has_rxbufs(E1000ECore *core, const E1000ERingInfo *r, 931 size_t total_size) 932 { 933 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 934 935 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 936 core->rx_desc_buf_size); 937 938 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 939 core->rx_desc_buf_size; 940 } 941 942 void 943 e1000e_start_recv(E1000ECore *core) 944 { 945 int i; 946 947 trace_e1000e_rx_start_recv(); 948 949 for (i = 0; i <= core->max_queue_num; i++) { 950 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 951 } 952 } 953 954 bool 955 e1000e_can_receive(E1000ECore *core) 956 { 957 int i; 958 959 if (!e1000x_rx_ready(core->owner, core->mac)) { 960 return false; 961 } 962 963 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 964 E1000E_RxRing rxr; 965 966 e1000e_rx_ring_init(core, &rxr, i); 967 if (e1000e_ring_enabled(core, rxr.i) && 968 e1000e_has_rxbufs(core, rxr.i, 1)) { 969 trace_e1000e_rx_can_recv(); 970 return true; 971 } 972 } 973 974 trace_e1000e_rx_can_recv_rings_full(); 975 return false; 976 } 977 978 ssize_t 979 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 980 { 981 const struct iovec iov = { 982 .iov_base = (uint8_t *)buf, 983 .iov_len = size 984 }; 985 986 return e1000e_receive_iov(core, &iov, 1); 987 } 988 989 static inline bool 990 e1000e_rx_l3_cso_enabled(E1000ECore *core) 991 { 992 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 993 } 994 995 static inline bool 996 e1000e_rx_l4_cso_enabled(E1000ECore *core) 997 { 998 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 999 } 1000 1001 static bool 1002 e1000e_receive_filter(E1000ECore *core, const void *buf) 1003 { 1004 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || 1005 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && 1006 e1000x_rx_group_filter(core->mac, buf); 1007 } 1008 1009 static inline void 1010 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1011 hwaddr *buff_addr) 1012 { 1013 *buff_addr = le64_to_cpu(desc->buffer_addr); 1014 } 1015 1016 static inline void 1017 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1018 hwaddr *buff_addr) 1019 { 1020 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1021 } 1022 1023 static inline void 1024 e1000e_read_ps_rx_descr(E1000ECore *core, 1025 union e1000_rx_desc_packet_split *desc, 1026 hwaddr buff_addr[MAX_PS_BUFFERS]) 1027 { 1028 int i; 1029 1030 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1031 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1032 } 1033 1034 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1035 buff_addr[2], buff_addr[3]); 1036 } 1037 1038 static inline void 1039 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1040 hwaddr buff_addr[MAX_PS_BUFFERS]) 1041 { 1042 if (e1000e_rx_use_legacy_descriptor(core)) { 1043 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1044 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1045 } else { 1046 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1047 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1048 } else { 1049 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1050 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1051 } 1052 } 1053 } 1054 1055 static void 1056 e1000e_verify_csum_in_sw(E1000ECore *core, 1057 struct NetRxPkt *pkt, 1058 uint32_t *status_flags, 1059 EthL4HdrProto l4hdr_proto) 1060 { 1061 bool csum_valid; 1062 uint32_t csum_error; 1063 1064 if (e1000e_rx_l3_cso_enabled(core)) { 1065 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1066 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1067 } else { 1068 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1069 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1070 } 1071 } else { 1072 trace_e1000e_rx_metadata_l3_cso_disabled(); 1073 } 1074 1075 if (!e1000e_rx_l4_cso_enabled(core)) { 1076 trace_e1000e_rx_metadata_l4_cso_disabled(); 1077 return; 1078 } 1079 1080 if (l4hdr_proto != ETH_L4_HDR_PROTO_TCP && 1081 l4hdr_proto != ETH_L4_HDR_PROTO_UDP) { 1082 return; 1083 } 1084 1085 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1086 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1087 return; 1088 } 1089 1090 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1091 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1092 1093 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1094 *status_flags |= E1000_RXD_STAT_UDPCS; 1095 } 1096 } 1097 1098 static inline bool 1099 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1100 { 1101 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1102 return false; 1103 } 1104 1105 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1106 return !net_rx_pkt_has_tcp_data(rx_pkt); 1107 } 1108 1109 return true; 1110 } 1111 1112 static void 1113 e1000e_build_rx_metadata(E1000ECore *core, 1114 struct NetRxPkt *pkt, 1115 bool is_eop, 1116 const E1000E_RSSInfo *rss_info, 1117 uint32_t *rss, uint32_t *mrq, 1118 uint32_t *status_flags, 1119 uint16_t *ip_id, 1120 uint16_t *vlan_tag) 1121 { 1122 struct virtio_net_hdr *vhdr; 1123 bool hasip4, hasip6; 1124 EthL4HdrProto l4hdr_proto; 1125 uint32_t pkt_type; 1126 1127 *status_flags = E1000_RXD_STAT_DD; 1128 1129 /* No additional metadata needed for non-EOP descriptors */ 1130 if (!is_eop) { 1131 goto func_exit; 1132 } 1133 1134 *status_flags |= E1000_RXD_STAT_EOP; 1135 1136 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1137 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1138 1139 /* VLAN state */ 1140 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1141 *status_flags |= E1000_RXD_STAT_VP; 1142 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1143 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1144 } 1145 1146 /* Packet parsing results */ 1147 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1148 if (rss_info->enabled) { 1149 *rss = cpu_to_le32(rss_info->hash); 1150 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1151 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1152 } 1153 } else if (hasip4) { 1154 *status_flags |= E1000_RXD_STAT_IPIDV; 1155 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1156 trace_e1000e_rx_metadata_ip_id(*ip_id); 1157 } 1158 1159 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { 1160 *status_flags |= E1000_RXD_STAT_ACK; 1161 trace_e1000e_rx_metadata_ack(); 1162 } 1163 1164 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1165 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1166 pkt_type = E1000_RXD_PKT_MAC; 1167 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1168 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1169 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1170 } else if (hasip4 || hasip6) { 1171 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1172 } else { 1173 pkt_type = E1000_RXD_PKT_MAC; 1174 } 1175 1176 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1177 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1178 1179 /* RX CSO information */ 1180 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1181 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1182 goto func_exit; 1183 } 1184 1185 vhdr = net_rx_pkt_get_vhdr(pkt); 1186 1187 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1188 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1189 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1190 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1191 goto func_exit; 1192 } 1193 1194 if (e1000e_rx_l3_cso_enabled(core)) { 1195 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1196 } else { 1197 trace_e1000e_rx_metadata_l3_cso_disabled(); 1198 } 1199 1200 if (e1000e_rx_l4_cso_enabled(core)) { 1201 switch (l4hdr_proto) { 1202 case ETH_L4_HDR_PROTO_TCP: 1203 *status_flags |= E1000_RXD_STAT_TCPCS; 1204 break; 1205 1206 case ETH_L4_HDR_PROTO_UDP: 1207 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1208 break; 1209 1210 default: 1211 break; 1212 } 1213 } else { 1214 trace_e1000e_rx_metadata_l4_cso_disabled(); 1215 } 1216 1217 func_exit: 1218 trace_e1000e_rx_metadata_status_flags(*status_flags); 1219 *status_flags = cpu_to_le32(*status_flags); 1220 } 1221 1222 static inline void 1223 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1224 struct NetRxPkt *pkt, 1225 const E1000E_RSSInfo *rss_info, 1226 uint16_t length) 1227 { 1228 uint32_t status_flags, rss, mrq; 1229 uint16_t ip_id; 1230 1231 assert(!rss_info->enabled); 1232 1233 desc->length = cpu_to_le16(length); 1234 desc->csum = 0; 1235 1236 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1237 rss_info, 1238 &rss, &mrq, 1239 &status_flags, &ip_id, 1240 &desc->special); 1241 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1242 desc->status = (uint8_t) le32_to_cpu(status_flags); 1243 } 1244 1245 static inline void 1246 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1247 struct NetRxPkt *pkt, 1248 const E1000E_RSSInfo *rss_info, 1249 uint16_t length) 1250 { 1251 memset(&desc->wb, 0, sizeof(desc->wb)); 1252 1253 desc->wb.upper.length = cpu_to_le16(length); 1254 1255 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1256 rss_info, 1257 &desc->wb.lower.hi_dword.rss, 1258 &desc->wb.lower.mrq, 1259 &desc->wb.upper.status_error, 1260 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1261 &desc->wb.upper.vlan); 1262 } 1263 1264 static inline void 1265 e1000e_write_ps_rx_descr(E1000ECore *core, 1266 union e1000_rx_desc_packet_split *desc, 1267 struct NetRxPkt *pkt, 1268 const E1000E_RSSInfo *rss_info, 1269 size_t ps_hdr_len, 1270 uint16_t(*written)[MAX_PS_BUFFERS]) 1271 { 1272 int i; 1273 1274 memset(&desc->wb, 0, sizeof(desc->wb)); 1275 1276 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1277 1278 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1279 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1280 } 1281 1282 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1283 rss_info, 1284 &desc->wb.lower.hi_dword.rss, 1285 &desc->wb.lower.mrq, 1286 &desc->wb.middle.status_error, 1287 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1288 &desc->wb.middle.vlan); 1289 1290 desc->wb.upper.header_status = 1291 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1292 1293 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1294 (*written)[2], (*written)[3]); 1295 } 1296 1297 static inline void 1298 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1299 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1300 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1301 { 1302 if (e1000e_rx_use_legacy_descriptor(core)) { 1303 assert(ps_hdr_len == 0); 1304 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1305 (*written)[0]); 1306 } else { 1307 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1308 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1309 ps_hdr_len, written); 1310 } else { 1311 assert(ps_hdr_len == 0); 1312 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1313 (*written)[0]); 1314 } 1315 } 1316 } 1317 1318 static inline void 1319 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1320 union e1000_rx_desc_union *desc, dma_addr_t len) 1321 { 1322 PCIDevice *dev = core->owner; 1323 1324 if (e1000e_rx_use_legacy_descriptor(core)) { 1325 struct e1000_rx_desc *d = &desc->legacy; 1326 size_t offset = offsetof(struct e1000_rx_desc, status); 1327 uint8_t status = d->status; 1328 1329 d->status &= ~E1000_RXD_STAT_DD; 1330 pci_dma_write(dev, addr, desc, len); 1331 1332 if (status & E1000_RXD_STAT_DD) { 1333 d->status = status; 1334 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1335 } 1336 } else { 1337 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1338 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1339 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1340 wb.middle.status_error); 1341 uint32_t status = d->wb.middle.status_error; 1342 1343 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1344 pci_dma_write(dev, addr, desc, len); 1345 1346 if (status & E1000_RXD_STAT_DD) { 1347 d->wb.middle.status_error = status; 1348 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1349 } 1350 } else { 1351 union e1000_rx_desc_extended *d = &desc->extended; 1352 size_t offset = offsetof(union e1000_rx_desc_extended, 1353 wb.upper.status_error); 1354 uint32_t status = d->wb.upper.status_error; 1355 1356 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1357 pci_dma_write(dev, addr, desc, len); 1358 1359 if (status & E1000_RXD_STAT_DD) { 1360 d->wb.upper.status_error = status; 1361 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1362 } 1363 } 1364 } 1365 } 1366 1367 typedef struct E1000EBAState { 1368 uint16_t written[MAX_PS_BUFFERS]; 1369 uint8_t cur_idx; 1370 } E1000EBAState; 1371 1372 static inline void 1373 e1000e_write_hdr_frag_to_rx_buffers(E1000ECore *core, 1374 hwaddr ba[MAX_PS_BUFFERS], 1375 E1000EBAState *bastate, 1376 const char *data, 1377 dma_addr_t data_len) 1378 { 1379 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1380 1381 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1382 bastate->written[0] += data_len; 1383 1384 bastate->cur_idx = 1; 1385 } 1386 1387 static void 1388 e1000e_write_payload_frag_to_rx_buffers(E1000ECore *core, 1389 hwaddr ba[MAX_PS_BUFFERS], 1390 E1000EBAState *bastate, 1391 const char *data, 1392 dma_addr_t data_len) 1393 { 1394 while (data_len > 0) { 1395 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1396 uint32_t cur_buf_bytes_left = cur_buf_len - 1397 bastate->written[bastate->cur_idx]; 1398 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1399 1400 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1401 ba[bastate->cur_idx], 1402 bastate->written[bastate->cur_idx], 1403 data, 1404 bytes_to_write); 1405 1406 pci_dma_write(core->owner, 1407 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1408 data, bytes_to_write); 1409 1410 bastate->written[bastate->cur_idx] += bytes_to_write; 1411 data += bytes_to_write; 1412 data_len -= bytes_to_write; 1413 1414 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1415 bastate->cur_idx++; 1416 } 1417 1418 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1419 } 1420 } 1421 1422 static void 1423 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) 1424 { 1425 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1426 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1427 } 1428 1429 static inline bool 1430 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000ERingInfo *rxi) 1431 { 1432 return e1000e_ring_free_descr_num(core, rxi) == 1433 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1434 } 1435 1436 static bool 1437 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1438 { 1439 bool hasip4, hasip6; 1440 EthL4HdrProto l4hdr_proto; 1441 bool fragment; 1442 1443 if (!e1000e_rx_use_ps_descriptor(core)) { 1444 return false; 1445 } 1446 1447 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1448 1449 if (hasip4) { 1450 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1451 } else if (hasip6) { 1452 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1453 } else { 1454 return false; 1455 } 1456 1457 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1458 return false; 1459 } 1460 1461 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1462 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1463 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1464 } else { 1465 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1466 } 1467 1468 if ((*hdr_len > core->rxbuf_sizes[0]) || 1469 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1470 return false; 1471 } 1472 1473 return true; 1474 } 1475 1476 static void 1477 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1478 const E1000E_RxRing *rxr, 1479 const E1000E_RSSInfo *rss_info) 1480 { 1481 PCIDevice *d = core->owner; 1482 dma_addr_t base; 1483 union e1000_rx_desc_union desc; 1484 size_t desc_size; 1485 size_t desc_offset = 0; 1486 size_t iov_ofs = 0; 1487 1488 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1489 size_t size = net_rx_pkt_get_total_len(pkt); 1490 size_t total_size = size + e1000x_fcs_len(core->mac); 1491 const E1000ERingInfo *rxi; 1492 size_t ps_hdr_len = 0; 1493 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1494 bool is_first = true; 1495 1496 rxi = rxr->i; 1497 1498 do { 1499 hwaddr ba[MAX_PS_BUFFERS]; 1500 E1000EBAState bastate = { { 0 } }; 1501 bool is_last = false; 1502 1503 desc_size = total_size - desc_offset; 1504 1505 if (desc_size > core->rx_desc_buf_size) { 1506 desc_size = core->rx_desc_buf_size; 1507 } 1508 1509 if (e1000e_ring_empty(core, rxi)) { 1510 return; 1511 } 1512 1513 base = e1000e_ring_head_descr(core, rxi); 1514 1515 pci_dma_read(d, base, &desc, core->rx_desc_len); 1516 1517 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1518 1519 e1000e_read_rx_descr(core, &desc, ba); 1520 1521 if (ba[0]) { 1522 if (desc_offset < size) { 1523 static const uint32_t fcs_pad; 1524 size_t iov_copy; 1525 size_t copy_size = size - desc_offset; 1526 if (copy_size > core->rx_desc_buf_size) { 1527 copy_size = core->rx_desc_buf_size; 1528 } 1529 1530 /* For PS mode copy the packet header first */ 1531 if (do_ps) { 1532 if (is_first) { 1533 size_t ps_hdr_copied = 0; 1534 do { 1535 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1536 iov->iov_len - iov_ofs); 1537 1538 e1000e_write_hdr_frag_to_rx_buffers(core, ba, 1539 &bastate, 1540 iov->iov_base, 1541 iov_copy); 1542 1543 copy_size -= iov_copy; 1544 ps_hdr_copied += iov_copy; 1545 1546 iov_ofs += iov_copy; 1547 if (iov_ofs == iov->iov_len) { 1548 iov++; 1549 iov_ofs = 0; 1550 } 1551 } while (ps_hdr_copied < ps_hdr_len); 1552 1553 is_first = false; 1554 } else { 1555 /* Leave buffer 0 of each descriptor except first */ 1556 /* empty as per spec 7.1.5.1 */ 1557 e1000e_write_hdr_frag_to_rx_buffers(core, ba, &bastate, 1558 NULL, 0); 1559 } 1560 } 1561 1562 /* Copy packet payload */ 1563 while (copy_size) { 1564 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1565 1566 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, 1567 iov->iov_base + 1568 iov_ofs, 1569 iov_copy); 1570 1571 copy_size -= iov_copy; 1572 iov_ofs += iov_copy; 1573 if (iov_ofs == iov->iov_len) { 1574 iov++; 1575 iov_ofs = 0; 1576 } 1577 } 1578 1579 if (desc_offset + desc_size >= total_size) { 1580 /* Simulate FCS checksum presence in the last descriptor */ 1581 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, 1582 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1583 } 1584 } 1585 } else { /* as per intel docs; skip descriptors with null buf addr */ 1586 trace_e1000e_rx_null_descriptor(); 1587 } 1588 desc_offset += desc_size; 1589 if (desc_offset >= total_size) { 1590 is_last = true; 1591 } 1592 1593 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1594 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1595 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1596 1597 e1000e_ring_advance(core, rxi, 1598 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1599 1600 } while (desc_offset < total_size); 1601 1602 e1000e_update_rx_stats(core, size, total_size); 1603 } 1604 1605 static inline void 1606 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1607 { 1608 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1609 1610 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1611 net_rx_pkt_fix_l4_csum(pkt); 1612 } 1613 } 1614 1615 ssize_t 1616 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1617 { 1618 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1619 } 1620 1621 static ssize_t 1622 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1623 bool has_vnet) 1624 { 1625 uint32_t causes = 0; 1626 uint8_t buf[ETH_ZLEN]; 1627 struct iovec min_iov; 1628 size_t size, orig_size; 1629 size_t iov_ofs = 0; 1630 E1000E_RxRing rxr; 1631 E1000E_RSSInfo rss_info; 1632 size_t total_size; 1633 ssize_t retval; 1634 bool rdmts_hit; 1635 1636 trace_e1000e_rx_receive_iov(iovcnt); 1637 1638 if (!e1000x_hw_rx_enabled(core->mac)) { 1639 return -1; 1640 } 1641 1642 /* Pull virtio header in */ 1643 if (has_vnet) { 1644 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1645 iov_ofs = sizeof(struct virtio_net_hdr); 1646 } else { 1647 net_rx_pkt_unset_vhdr(core->rx_pkt); 1648 } 1649 1650 orig_size = iov_size(iov, iovcnt); 1651 size = orig_size - iov_ofs; 1652 1653 /* Pad to minimum Ethernet frame length */ 1654 if (size < sizeof(buf)) { 1655 iov_to_buf(iov, iovcnt, iov_ofs, buf, size); 1656 memset(&buf[size], 0, sizeof(buf) - size); 1657 e1000x_inc_reg_if_not_full(core->mac, RUC); 1658 min_iov.iov_base = buf; 1659 min_iov.iov_len = size = sizeof(buf); 1660 iovcnt = 1; 1661 iov = &min_iov; 1662 iov_ofs = 0; 1663 } else { 1664 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4); 1665 } 1666 1667 /* Discard oversized packets if !LPE and !SBP. */ 1668 if (e1000x_is_oversized(core->mac, size)) { 1669 return orig_size; 1670 } 1671 1672 net_rx_pkt_set_packet_type(core->rx_pkt, 1673 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1674 1675 if (!e1000e_receive_filter(core, buf)) { 1676 trace_e1000e_rx_flt_dropped(); 1677 return orig_size; 1678 } 1679 1680 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1681 e1000x_vlan_enabled(core->mac) ? 0 : -1, 1682 core->mac[VET], 0); 1683 1684 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1685 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1686 1687 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1688 e1000x_fcs_len(core->mac); 1689 1690 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1691 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1692 1693 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1694 1695 retval = orig_size; 1696 1697 /* Perform small receive detection (RSRPD) */ 1698 if (total_size < core->mac[RSRPD]) { 1699 causes |= E1000_ICS_SRPD; 1700 } 1701 1702 /* Perform ACK receive detection */ 1703 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1704 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1705 causes |= E1000_ICS_ACK; 1706 } 1707 1708 /* Check if receive descriptor minimum threshold hit */ 1709 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1710 causes |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1711 1712 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1713 } else { 1714 causes |= E1000_ICS_RXO; 1715 retval = 0; 1716 1717 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1718 } 1719 1720 if (!e1000e_intrmgr_delay_rx_causes(core, &causes)) { 1721 trace_e1000e_rx_interrupt_set(causes); 1722 e1000e_set_interrupt_cause(core, causes); 1723 } else { 1724 trace_e1000e_rx_interrupt_delayed(causes); 1725 } 1726 1727 return retval; 1728 } 1729 1730 static inline bool 1731 e1000e_have_autoneg(E1000ECore *core) 1732 { 1733 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1734 } 1735 1736 static void e1000e_update_flowctl_status(E1000ECore *core) 1737 { 1738 if (e1000e_have_autoneg(core) && 1739 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1740 trace_e1000e_link_autoneg_flowctl(true); 1741 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1742 } else { 1743 trace_e1000e_link_autoneg_flowctl(false); 1744 } 1745 } 1746 1747 static inline void 1748 e1000e_link_down(E1000ECore *core) 1749 { 1750 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1751 e1000e_update_flowctl_status(core); 1752 } 1753 1754 static inline void 1755 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1756 { 1757 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1758 core->phy[0][MII_BMCR] = val & ~(0x3f | 1759 MII_BMCR_RESET | 1760 MII_BMCR_ANRESTART); 1761 1762 if ((val & MII_BMCR_ANRESTART) && 1763 e1000e_have_autoneg(core)) { 1764 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1765 } 1766 } 1767 1768 static void 1769 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1770 { 1771 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1772 1773 if (val & BIT(10)) { 1774 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1775 } 1776 } 1777 1778 static void 1779 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1780 { 1781 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1782 } 1783 1784 void 1785 e1000e_core_set_link_status(E1000ECore *core) 1786 { 1787 NetClientState *nc = qemu_get_queue(core->owner_nic); 1788 uint32_t old_status = core->mac[STATUS]; 1789 1790 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1791 1792 if (nc->link_down) { 1793 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1794 } else { 1795 if (e1000e_have_autoneg(core) && 1796 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1797 e1000x_restart_autoneg(core->mac, core->phy[0], 1798 core->autoneg_timer); 1799 } else { 1800 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1801 e1000e_start_recv(core); 1802 } 1803 } 1804 1805 if (core->mac[STATUS] != old_status) { 1806 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1807 } 1808 } 1809 1810 static void 1811 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1812 { 1813 trace_e1000e_core_ctrl_write(index, val); 1814 1815 /* RST is self clearing */ 1816 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1817 core->mac[CTRL_DUP] = core->mac[CTRL]; 1818 1819 trace_e1000e_link_set_params( 1820 !!(val & E1000_CTRL_ASDE), 1821 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1822 !!(val & E1000_CTRL_FRCSPD), 1823 !!(val & E1000_CTRL_FRCDPX), 1824 !!(val & E1000_CTRL_RFCE), 1825 !!(val & E1000_CTRL_TFCE)); 1826 1827 if (val & E1000_CTRL_RST) { 1828 trace_e1000e_core_ctrl_sw_reset(); 1829 e1000e_reset(core, true); 1830 } 1831 1832 if (val & E1000_CTRL_PHY_RST) { 1833 trace_e1000e_core_ctrl_phy_reset(); 1834 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1835 } 1836 } 1837 1838 static void 1839 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1840 { 1841 trace_e1000e_rx_set_rfctl(val); 1842 1843 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1844 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1845 } 1846 1847 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1848 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1849 } 1850 1851 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1852 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1853 } 1854 1855 core->mac[RFCTL] = val; 1856 } 1857 1858 static void 1859 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1860 { 1861 int i; 1862 core->rx_desc_buf_size = 0; 1863 1864 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1865 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1866 } 1867 } 1868 1869 static void 1870 e1000e_parse_rxbufsize(E1000ECore *core) 1871 { 1872 uint32_t rctl = core->mac[RCTL]; 1873 1874 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1875 1876 if (rctl & E1000_RCTL_DTYP_MASK) { 1877 uint32_t bsize; 1878 1879 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1880 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1881 1882 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1883 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1884 1885 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1886 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1887 1888 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1889 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1890 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1891 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1892 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1893 } else { 1894 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1895 } 1896 1897 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1898 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1899 1900 e1000e_calc_per_desc_buf_size(core); 1901 } 1902 1903 static void 1904 e1000e_calc_rxdesclen(E1000ECore *core) 1905 { 1906 if (e1000e_rx_use_legacy_descriptor(core)) { 1907 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1908 } else { 1909 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1910 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1911 } else { 1912 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1913 } 1914 } 1915 trace_e1000e_rx_desc_len(core->rx_desc_len); 1916 } 1917 1918 static void 1919 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1920 { 1921 core->mac[RCTL] = val; 1922 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1923 1924 if (val & E1000_RCTL_EN) { 1925 e1000e_parse_rxbufsize(core); 1926 e1000e_calc_rxdesclen(core); 1927 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1928 E1000_RING_DESC_LEN_SHIFT; 1929 1930 e1000e_start_recv(core); 1931 } 1932 } 1933 1934 static 1935 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1936 (E1000ECore *, int, uint16_t) = { 1937 [0] = { 1938 [MII_BMCR] = e1000e_set_phy_ctrl, 1939 [PHY_PAGE] = e1000e_set_phy_page, 1940 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1941 } 1942 }; 1943 1944 static inline bool 1945 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 1946 { 1947 if (timer->running) { 1948 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1949 1950 return true; 1951 } 1952 1953 if (timer->core->mac[timer->delay_reg] != 0) { 1954 e1000e_intrmgr_rearm_timer(timer); 1955 } 1956 1957 return false; 1958 } 1959 1960 static inline bool 1961 e1000e_itr_should_postpone(E1000ECore *core) 1962 { 1963 return e1000e_postpone_interrupt(&core->itr); 1964 } 1965 1966 static inline bool 1967 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 1968 { 1969 return e1000e_postpone_interrupt(&core->eitr[idx]); 1970 } 1971 1972 static void 1973 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 1974 { 1975 uint32_t effective_eiac; 1976 1977 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 1978 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 1979 if (vec < E1000E_MSIX_VEC_NUM) { 1980 if (!e1000e_eitr_should_postpone(core, vec)) { 1981 trace_e1000e_irq_msix_notify_vec(vec); 1982 msix_notify(core->owner, vec); 1983 } 1984 } else { 1985 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 1986 } 1987 } else { 1988 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 1989 } 1990 1991 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 1992 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 1993 core->mac[IAM] &= ~cause; 1994 } 1995 1996 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 1997 1998 effective_eiac = core->mac[EIAC] & cause; 1999 2000 core->mac[ICR] &= ~effective_eiac; 2001 2002 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2003 core->mac[IMS] &= ~effective_eiac; 2004 } 2005 } 2006 2007 static void 2008 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2009 { 2010 if (causes & E1000_ICR_RXQ0) { 2011 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2012 E1000_IVAR_RXQ0(core->mac[IVAR])); 2013 } 2014 2015 if (causes & E1000_ICR_RXQ1) { 2016 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2017 E1000_IVAR_RXQ1(core->mac[IVAR])); 2018 } 2019 2020 if (causes & E1000_ICR_TXQ0) { 2021 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2022 E1000_IVAR_TXQ0(core->mac[IVAR])); 2023 } 2024 2025 if (causes & E1000_ICR_TXQ1) { 2026 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2027 E1000_IVAR_TXQ1(core->mac[IVAR])); 2028 } 2029 2030 if (causes & E1000_ICR_OTHER) { 2031 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2032 E1000_IVAR_OTHER(core->mac[IVAR])); 2033 } 2034 } 2035 2036 static void 2037 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2038 { 2039 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2040 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2041 if (vec < E1000E_MSIX_VEC_NUM) { 2042 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2043 msix_clr_pending(core->owner, vec); 2044 } else { 2045 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2046 } 2047 } else { 2048 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2049 } 2050 } 2051 2052 static void 2053 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2054 { 2055 if (causes & E1000_ICR_RXQ0) { 2056 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2057 E1000_IVAR_RXQ0(core->mac[IVAR])); 2058 } 2059 2060 if (causes & E1000_ICR_RXQ1) { 2061 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2062 E1000_IVAR_RXQ1(core->mac[IVAR])); 2063 } 2064 2065 if (causes & E1000_ICR_TXQ0) { 2066 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2067 E1000_IVAR_TXQ0(core->mac[IVAR])); 2068 } 2069 2070 if (causes & E1000_ICR_TXQ1) { 2071 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2072 E1000_IVAR_TXQ1(core->mac[IVAR])); 2073 } 2074 2075 if (causes & E1000_ICR_OTHER) { 2076 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2077 E1000_IVAR_OTHER(core->mac[IVAR])); 2078 } 2079 } 2080 2081 static inline void 2082 e1000e_fix_icr_asserted(E1000ECore *core) 2083 { 2084 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2085 if (core->mac[ICR]) { 2086 core->mac[ICR] |= E1000_ICR_ASSERTED; 2087 } 2088 2089 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2090 } 2091 2092 static void e1000e_raise_interrupts(E1000ECore *core, 2093 size_t index, uint32_t causes) 2094 { 2095 bool is_msix = msix_enabled(core->owner); 2096 uint32_t old_causes = core->mac[IMS] & core->mac[ICR]; 2097 uint32_t raised_causes; 2098 2099 trace_e1000e_irq_set(index << 2, 2100 core->mac[index], core->mac[index] | causes); 2101 2102 core->mac[index] |= causes; 2103 2104 /* Set ICR[OTHER] for MSI-X */ 2105 if (is_msix) { 2106 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2107 core->mac[ICR] |= E1000_ICR_OTHER; 2108 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2109 } 2110 } 2111 2112 e1000e_fix_icr_asserted(core); 2113 2114 /* 2115 * Make sure ICR and ICS registers have the same value. 2116 * The spec says that the ICS register is write-only. However in practice, 2117 * on real hardware ICS is readable, and for reads it has the same value as 2118 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2119 * 2120 * The VxWorks PRO/1000 driver uses this behaviour. 2121 */ 2122 core->mac[ICS] = core->mac[ICR]; 2123 2124 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2125 core->mac[ICR], core->mac[IMS]); 2126 2127 raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes; 2128 if (!raised_causes) { 2129 return; 2130 } 2131 2132 if (is_msix) { 2133 e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED); 2134 } else if (!e1000e_itr_should_postpone(core)) { 2135 if (msi_enabled(core->owner)) { 2136 trace_e1000e_irq_msi_notify(raised_causes); 2137 msi_notify(core->owner, 0); 2138 } else { 2139 e1000e_raise_legacy_irq(core); 2140 } 2141 } 2142 } 2143 2144 static void e1000e_lower_interrupts(E1000ECore *core, 2145 size_t index, uint32_t causes) 2146 { 2147 trace_e1000e_irq_clear(index << 2, 2148 core->mac[index], core->mac[index] & ~causes); 2149 2150 core->mac[index] &= ~causes; 2151 2152 /* 2153 * Make sure ICR and ICS registers have the same value. 2154 * The spec says that the ICS register is write-only. However in practice, 2155 * on real hardware ICS is readable, and for reads it has the same value as 2156 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2157 * 2158 * The VxWorks PRO/1000 driver uses this behaviour. 2159 */ 2160 core->mac[ICS] = core->mac[ICR]; 2161 2162 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2163 core->mac[ICR], core->mac[IMS]); 2164 2165 if (!(core->mac[IMS] & core->mac[ICR]) && 2166 !msix_enabled(core->owner) && !msi_enabled(core->owner)) { 2167 e1000e_lower_legacy_irq(core); 2168 } 2169 } 2170 2171 static void 2172 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2173 { 2174 val |= e1000e_intmgr_collect_delayed_causes(core); 2175 e1000e_raise_interrupts(core, ICR, val); 2176 } 2177 2178 static inline void 2179 e1000e_autoneg_timer(void *opaque) 2180 { 2181 E1000ECore *core = opaque; 2182 if (!qemu_get_queue(core->owner_nic)->link_down) { 2183 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2184 e1000e_start_recv(core); 2185 2186 e1000e_update_flowctl_status(core); 2187 /* signal link status change to the guest */ 2188 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2189 } 2190 } 2191 2192 static inline uint16_t 2193 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2194 { 2195 uint16_t index = (addr & 0x1ffff) >> 2; 2196 return index + (mac_reg_access[index] & 0xfffe); 2197 } 2198 2199 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2200 [0] = { 2201 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2202 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2203 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2204 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2205 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2206 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2207 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2208 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2209 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2210 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2211 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2212 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2213 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2214 2215 [PHY_COPPER_CTRL1] = PHY_RW, 2216 [PHY_COPPER_STAT1] = PHY_R, 2217 [PHY_COPPER_CTRL3] = PHY_RW, 2218 [PHY_RX_ERR_CNTR] = PHY_R, 2219 [PHY_OEM_BITS] = PHY_RW, 2220 [PHY_BIAS_1] = PHY_RW, 2221 [PHY_BIAS_2] = PHY_RW, 2222 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2223 [PHY_COPPER_STAT2] = PHY_R, 2224 [PHY_COPPER_CTRL2] = PHY_RW 2225 }, 2226 [2] = { 2227 [PHY_MAC_CTRL1] = PHY_RW, 2228 [PHY_MAC_INT_ENABLE] = PHY_RW, 2229 [PHY_MAC_STAT] = PHY_R, 2230 [PHY_MAC_CTRL2] = PHY_RW 2231 }, 2232 [3] = { 2233 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2234 [PHY_LED_03_POL_CTRL] = PHY_RW, 2235 [PHY_LED_TIMER_CTRL] = PHY_RW, 2236 [PHY_LED_45_CTRL] = PHY_RW 2237 }, 2238 [5] = { 2239 [PHY_1000T_SKEW] = PHY_R, 2240 [PHY_1000T_SWAP] = PHY_R 2241 }, 2242 [6] = { 2243 [PHY_CRC_COUNTERS] = PHY_R 2244 } 2245 }; 2246 2247 static bool 2248 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2249 char cap, uint8_t *page) 2250 { 2251 *page = 2252 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2253 : core->phy[0][PHY_PAGE]; 2254 2255 if (*page >= E1000E_PHY_PAGES) { 2256 return false; 2257 } 2258 2259 return e1000e_phy_regcap[*page][addr] & cap; 2260 } 2261 2262 static void 2263 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2264 uint32_t addr, uint16_t data) 2265 { 2266 assert(page < E1000E_PHY_PAGES); 2267 assert(addr < E1000E_PHY_PAGE_SIZE); 2268 2269 if (e1000e_phyreg_writeops[page][addr]) { 2270 e1000e_phyreg_writeops[page][addr](core, addr, data); 2271 } else { 2272 core->phy[page][addr] = data; 2273 } 2274 } 2275 2276 static void 2277 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2278 { 2279 uint32_t data = val & E1000_MDIC_DATA_MASK; 2280 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2281 uint8_t page; 2282 2283 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2284 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2285 } else if (val & E1000_MDIC_OP_READ) { 2286 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2287 trace_e1000e_core_mdic_read_unhandled(page, addr); 2288 val |= E1000_MDIC_ERROR; 2289 } else { 2290 val = (val ^ data) | core->phy[page][addr]; 2291 trace_e1000e_core_mdic_read(page, addr, val); 2292 } 2293 } else if (val & E1000_MDIC_OP_WRITE) { 2294 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2295 trace_e1000e_core_mdic_write_unhandled(page, addr); 2296 val |= E1000_MDIC_ERROR; 2297 } else { 2298 trace_e1000e_core_mdic_write(page, addr, data); 2299 e1000e_phy_reg_write(core, page, addr, data); 2300 } 2301 } 2302 core->mac[MDIC] = val | E1000_MDIC_READY; 2303 2304 if (val & E1000_MDIC_INT_EN) { 2305 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2306 } 2307 } 2308 2309 static void 2310 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2311 { 2312 core->mac[index] = val & 0xffff; 2313 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2314 e1000e_start_recv(core); 2315 } 2316 2317 static void 2318 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2319 { 2320 if ((val & E1000_STATUS_PHYRA) == 0) { 2321 core->mac[index] &= ~E1000_STATUS_PHYRA; 2322 } 2323 } 2324 2325 static void 2326 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2327 { 2328 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2329 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2330 2331 /* Zero self-clearing bits */ 2332 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2333 core->mac[CTRL_EXT] = val; 2334 } 2335 2336 static void 2337 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2338 { 2339 int i; 2340 2341 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2342 2343 if (!msix_enabled(core->owner)) { 2344 return; 2345 } 2346 2347 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2348 if (core->mac[PBACLR] & BIT(i)) { 2349 msix_clr_pending(core->owner, i); 2350 } 2351 } 2352 } 2353 2354 static void 2355 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2356 { 2357 core->mac[FCRTH] = val & 0xFFF8; 2358 } 2359 2360 static void 2361 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2362 { 2363 core->mac[FCRTL] = val & 0x8000FFF8; 2364 } 2365 2366 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2367 static void \ 2368 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2369 { \ 2370 core->mac[index] = val & (BIT(num) - 1); \ 2371 } 2372 2373 E1000E_LOW_BITS_SET_FUNC(4) 2374 E1000E_LOW_BITS_SET_FUNC(6) 2375 E1000E_LOW_BITS_SET_FUNC(11) 2376 E1000E_LOW_BITS_SET_FUNC(12) 2377 E1000E_LOW_BITS_SET_FUNC(13) 2378 E1000E_LOW_BITS_SET_FUNC(16) 2379 2380 static void 2381 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2382 { 2383 core->mac[VET] = val & 0xffff; 2384 trace_e1000e_vlan_vet(core->mac[VET]); 2385 } 2386 2387 static void 2388 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2389 { 2390 core->mac[index] = val & E1000_XDLEN_MASK; 2391 } 2392 2393 static void 2394 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2395 { 2396 core->mac[index] = val & E1000_XDBAL_MASK; 2397 } 2398 2399 static void 2400 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2401 { 2402 E1000E_TxRing txr; 2403 core->mac[index] = val; 2404 2405 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2406 e1000e_tx_ring_init(core, &txr, 0); 2407 e1000e_start_xmit(core, &txr); 2408 } 2409 2410 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2411 e1000e_tx_ring_init(core, &txr, 1); 2412 e1000e_start_xmit(core, &txr); 2413 } 2414 } 2415 2416 static void 2417 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2418 { 2419 E1000E_TxRing txr; 2420 int qidx = e1000e_mq_queue_idx(TDT, index); 2421 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2422 2423 core->mac[index] = val & 0xffff; 2424 2425 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2426 e1000e_tx_ring_init(core, &txr, qidx); 2427 e1000e_start_xmit(core, &txr); 2428 } 2429 } 2430 2431 static void 2432 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2433 { 2434 trace_e1000e_irq_write_ics(val); 2435 e1000e_set_interrupt_cause(core, val); 2436 } 2437 2438 static void 2439 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2440 { 2441 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2442 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2443 trace_e1000e_irq_icr_process_iame(); 2444 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2445 } 2446 2447 /* 2448 * Windows driver expects that the "receive overrun" bit and other 2449 * ones to be cleared when the "Other" bit (#24) is cleared. 2450 */ 2451 if (val & E1000_ICR_OTHER) { 2452 val |= E1000_ICR_OTHER_CAUSES; 2453 } 2454 e1000e_lower_interrupts(core, ICR, val); 2455 } 2456 2457 static void 2458 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2459 { 2460 trace_e1000e_irq_ims_clear_set_imc(val); 2461 e1000e_lower_interrupts(core, IMS, val); 2462 } 2463 2464 static void 2465 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2466 { 2467 static const uint32_t ims_ext_mask = 2468 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2469 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2470 E1000_IMS_OTHER; 2471 2472 static const uint32_t ims_valid_mask = 2473 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2474 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2475 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2476 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2477 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2478 E1000_IMS_OTHER; 2479 2480 uint32_t valid_val = val & ims_valid_mask; 2481 2482 if ((valid_val & ims_ext_mask) && 2483 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2484 msix_enabled(core->owner)) { 2485 e1000e_msix_clear(core, valid_val); 2486 } 2487 2488 if ((valid_val == ims_valid_mask) && 2489 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2490 trace_e1000e_irq_fire_all_timers(val); 2491 e1000e_intrmgr_fire_all_timers(core); 2492 } 2493 2494 e1000e_raise_interrupts(core, IMS, valid_val); 2495 } 2496 2497 static void 2498 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2499 { 2500 e1000e_set_16bit(core, index, val); 2501 2502 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2503 trace_e1000e_irq_rdtr_fpd_running(); 2504 e1000e_intrmgr_fire_delayed_interrupts(core); 2505 } else { 2506 trace_e1000e_irq_rdtr_fpd_not_running(); 2507 } 2508 } 2509 2510 static void 2511 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2512 { 2513 e1000e_set_16bit(core, index, val); 2514 2515 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2516 trace_e1000e_irq_tidv_fpd_running(); 2517 e1000e_intrmgr_fire_delayed_interrupts(core); 2518 } else { 2519 trace_e1000e_irq_tidv_fpd_not_running(); 2520 } 2521 } 2522 2523 static uint32_t 2524 e1000e_mac_readreg(E1000ECore *core, int index) 2525 { 2526 return core->mac[index]; 2527 } 2528 2529 static uint32_t 2530 e1000e_mac_ics_read(E1000ECore *core, int index) 2531 { 2532 trace_e1000e_irq_read_ics(core->mac[ICS]); 2533 return core->mac[ICS]; 2534 } 2535 2536 static uint32_t 2537 e1000e_mac_ims_read(E1000ECore *core, int index) 2538 { 2539 trace_e1000e_irq_read_ims(core->mac[IMS]); 2540 return core->mac[IMS]; 2541 } 2542 2543 static uint32_t 2544 e1000e_mac_swsm_read(E1000ECore *core, int index) 2545 { 2546 uint32_t val = core->mac[SWSM]; 2547 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2548 return val; 2549 } 2550 2551 static uint32_t 2552 e1000e_mac_itr_read(E1000ECore *core, int index) 2553 { 2554 return core->itr_guest_value; 2555 } 2556 2557 static uint32_t 2558 e1000e_mac_eitr_read(E1000ECore *core, int index) 2559 { 2560 return core->eitr_guest_value[index - EITR]; 2561 } 2562 2563 static uint32_t 2564 e1000e_mac_icr_read(E1000ECore *core, int index) 2565 { 2566 uint32_t ret = core->mac[ICR]; 2567 2568 if (core->mac[IMS] == 0) { 2569 trace_e1000e_irq_icr_clear_zero_ims(); 2570 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2571 } 2572 2573 if (!msix_enabled(core->owner)) { 2574 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2575 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2576 } 2577 2578 if (core->mac[ICR] & E1000_ICR_ASSERTED) { 2579 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) { 2580 trace_e1000e_irq_icr_clear_iame(); 2581 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2582 trace_e1000e_irq_icr_process_iame(); 2583 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2584 } 2585 2586 /* 2587 * The datasheet does not say what happens when interrupt was asserted 2588 * (ICR.INT_ASSERT=1) and auto mask is *not* active. 2589 * However, section of 13.3.27 the PCIe* GbE Controllers Open Source 2590 * Software Developer’s Manual, which were written for older devices, 2591 * namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI & 2592 * 82573E/82573V/82573L, does say: 2593 * > If IMS = 0b, then the ICR register is always clear-on-read. If IMS 2594 * > is not 0b, but some ICR bit is set where the corresponding IMS bit 2595 * > is not set, then a read does not clear the ICR register. For 2596 * > example, if IMS = 10101010b and ICR = 01010101b, then a read to the 2597 * > ICR register does not clear it. If IMS = 10101010b and 2598 * > ICR = 0101011b, then a read to the ICR register clears it entirely 2599 * > (ICR.INT_ASSERTED = 1b). 2600 * 2601 * Linux does no longer activate auto mask since commit 2602 * 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware 2603 * clears ICR even in such a case so we also should do so. 2604 */ 2605 if (core->mac[ICR] & core->mac[IMS]) { 2606 trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR], 2607 core->mac[IMS]); 2608 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2609 } 2610 } 2611 2612 return ret; 2613 } 2614 2615 static uint32_t 2616 e1000e_mac_read_clr4(E1000ECore *core, int index) 2617 { 2618 uint32_t ret = core->mac[index]; 2619 2620 core->mac[index] = 0; 2621 return ret; 2622 } 2623 2624 static uint32_t 2625 e1000e_mac_read_clr8(E1000ECore *core, int index) 2626 { 2627 uint32_t ret = core->mac[index]; 2628 2629 core->mac[index] = 0; 2630 core->mac[index - 1] = 0; 2631 return ret; 2632 } 2633 2634 static uint32_t 2635 e1000e_get_ctrl(E1000ECore *core, int index) 2636 { 2637 uint32_t val = core->mac[CTRL]; 2638 2639 trace_e1000e_link_read_params( 2640 !!(val & E1000_CTRL_ASDE), 2641 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2642 !!(val & E1000_CTRL_FRCSPD), 2643 !!(val & E1000_CTRL_FRCDPX), 2644 !!(val & E1000_CTRL_RFCE), 2645 !!(val & E1000_CTRL_TFCE)); 2646 2647 return val; 2648 } 2649 2650 static uint32_t 2651 e1000e_get_status(E1000ECore *core, int index) 2652 { 2653 uint32_t res = core->mac[STATUS]; 2654 2655 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2656 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2657 } 2658 2659 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2660 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2661 } else { 2662 res |= E1000_STATUS_FD; 2663 } 2664 2665 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2666 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2667 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2668 case E1000_CTRL_SPD_10: 2669 res |= E1000_STATUS_SPEED_10; 2670 break; 2671 case E1000_CTRL_SPD_100: 2672 res |= E1000_STATUS_SPEED_100; 2673 break; 2674 case E1000_CTRL_SPD_1000: 2675 default: 2676 res |= E1000_STATUS_SPEED_1000; 2677 break; 2678 } 2679 } else { 2680 res |= E1000_STATUS_SPEED_1000; 2681 } 2682 2683 trace_e1000e_link_status( 2684 !!(res & E1000_STATUS_LU), 2685 !!(res & E1000_STATUS_FD), 2686 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2687 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2688 2689 return res; 2690 } 2691 2692 static uint32_t 2693 e1000e_get_tarc(E1000ECore *core, int index) 2694 { 2695 return core->mac[index] & ((BIT(11) - 1) | 2696 BIT(27) | 2697 BIT(28) | 2698 BIT(29) | 2699 BIT(30)); 2700 } 2701 2702 static void 2703 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2704 { 2705 core->mac[index] = val; 2706 } 2707 2708 static void 2709 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2710 { 2711 uint32_t macaddr[2]; 2712 2713 core->mac[index] = val; 2714 2715 macaddr[0] = cpu_to_le32(core->mac[RA]); 2716 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2717 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2718 (uint8_t *) macaddr); 2719 2720 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2721 } 2722 2723 static void 2724 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2725 { 2726 static const uint32_t ro_bits = E1000_EECD_PRES | 2727 E1000_EECD_AUTO_RD | 2728 E1000_EECD_SIZE_EX_MASK; 2729 2730 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2731 } 2732 2733 static void 2734 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2735 { 2736 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2737 uint32_t flags = 0; 2738 uint32_t data = 0; 2739 2740 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2741 data = core->eeprom[addr]; 2742 flags = E1000_EERW_DONE; 2743 } 2744 2745 core->mac[EERD] = flags | 2746 (addr << E1000_EERW_ADDR_SHIFT) | 2747 (data << E1000_EERW_DATA_SHIFT); 2748 } 2749 2750 static void 2751 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2752 { 2753 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2754 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2755 uint32_t flags = 0; 2756 2757 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2758 core->eeprom[addr] = data; 2759 flags = E1000_EERW_DONE; 2760 } 2761 2762 core->mac[EERD] = flags | 2763 (addr << E1000_EERW_ADDR_SHIFT) | 2764 (data << E1000_EERW_DATA_SHIFT); 2765 } 2766 2767 static void 2768 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2769 { 2770 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2771 } 2772 2773 static void 2774 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2775 { 2776 uint32_t interval = val & 0xffff; 2777 2778 trace_e1000e_irq_itr_set(val); 2779 2780 core->itr_guest_value = interval; 2781 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2782 } 2783 2784 static void 2785 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2786 { 2787 uint32_t interval = val & 0xffff; 2788 uint32_t eitr_num = index - EITR; 2789 2790 trace_e1000e_irq_eitr_set(eitr_num, val); 2791 2792 core->eitr_guest_value[eitr_num] = interval; 2793 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2794 } 2795 2796 static void 2797 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2798 { 2799 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2800 2801 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2802 qemu_log_mask(LOG_GUEST_ERROR, 2803 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2804 return; 2805 } 2806 2807 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2808 qemu_log_mask(LOG_GUEST_ERROR, 2809 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2810 return; 2811 } 2812 } 2813 2814 core->mac[PSRCTL] = val; 2815 } 2816 2817 static void 2818 e1000e_update_rx_offloads(E1000ECore *core) 2819 { 2820 int cso_state = e1000e_rx_l4_cso_enabled(core); 2821 2822 trace_e1000e_rx_set_cso(cso_state); 2823 2824 if (core->has_vnet) { 2825 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2826 cso_state, 0, 0, 0, 0, 0, 0); 2827 } 2828 } 2829 2830 static void 2831 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2832 { 2833 core->mac[RXCSUM] = val; 2834 e1000e_update_rx_offloads(core); 2835 } 2836 2837 static void 2838 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2839 { 2840 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2841 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2842 } 2843 2844 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) 2845 { 2846 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2847 return core->mac[SYSTIML]; 2848 } 2849 2850 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) 2851 { 2852 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2853 return core->mac[RXSATRH]; 2854 } 2855 2856 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) 2857 { 2858 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2859 return core->mac[TXSTMPH]; 2860 } 2861 2862 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) 2863 { 2864 e1000x_set_timinca(core->mac, &core->timadj, val); 2865 } 2866 2867 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) 2868 { 2869 core->mac[TIMADJH] = val; 2870 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2871 } 2872 2873 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2874 typedef uint32_t (*readops)(E1000ECore *, int); 2875 static const readops e1000e_macreg_readops[] = { 2876 e1000e_getreg(PBA), 2877 e1000e_getreg(WUFC), 2878 e1000e_getreg(MANC), 2879 e1000e_getreg(TOTL), 2880 e1000e_getreg(RDT0), 2881 e1000e_getreg(RDBAH0), 2882 e1000e_getreg(TDBAL1), 2883 e1000e_getreg(RDLEN0), 2884 e1000e_getreg(RDH1), 2885 e1000e_getreg(LATECOL), 2886 e1000e_getreg(SEQEC), 2887 e1000e_getreg(XONTXC), 2888 e1000e_getreg(AIT), 2889 e1000e_getreg(TDFH), 2890 e1000e_getreg(TDFT), 2891 e1000e_getreg(TDFHS), 2892 e1000e_getreg(TDFTS), 2893 e1000e_getreg(TDFPC), 2894 e1000e_getreg(WUS), 2895 e1000e_getreg(PBS), 2896 e1000e_getreg(RDFH), 2897 e1000e_getreg(RDFT), 2898 e1000e_getreg(RDFHS), 2899 e1000e_getreg(RDFTS), 2900 e1000e_getreg(RDFPC), 2901 e1000e_getreg(GORCL), 2902 e1000e_getreg(MGTPRC), 2903 e1000e_getreg(EERD), 2904 e1000e_getreg(EIAC), 2905 e1000e_getreg(PSRCTL), 2906 e1000e_getreg(MANC2H), 2907 e1000e_getreg(RXCSUM), 2908 e1000e_getreg(GSCL_3), 2909 e1000e_getreg(GSCN_2), 2910 e1000e_getreg(RSRPD), 2911 e1000e_getreg(RDBAL1), 2912 e1000e_getreg(FCAH), 2913 e1000e_getreg(FCRTH), 2914 e1000e_getreg(FLOP), 2915 e1000e_getreg(FLASHT), 2916 e1000e_getreg(RXSTMPH), 2917 e1000e_getreg(TXSTMPL), 2918 e1000e_getreg(TIMADJL), 2919 e1000e_getreg(TXDCTL), 2920 e1000e_getreg(RDH0), 2921 e1000e_getreg(TDT1), 2922 e1000e_getreg(TNCRS), 2923 e1000e_getreg(RJC), 2924 e1000e_getreg(IAM), 2925 e1000e_getreg(GSCL_2), 2926 e1000e_getreg(RDBAH1), 2927 e1000e_getreg(FLSWDATA), 2928 e1000e_getreg(TIPG), 2929 e1000e_getreg(FLMNGCTL), 2930 e1000e_getreg(FLMNGCNT), 2931 e1000e_getreg(TSYNCTXCTL), 2932 e1000e_getreg(EXTCNF_SIZE), 2933 e1000e_getreg(EXTCNF_CTRL), 2934 e1000e_getreg(EEMNGDATA), 2935 e1000e_getreg(CTRL_EXT), 2936 e1000e_getreg(SYSTIMH), 2937 e1000e_getreg(EEMNGCTL), 2938 e1000e_getreg(FLMNGDATA), 2939 e1000e_getreg(TSYNCRXCTL), 2940 e1000e_getreg(TDH), 2941 e1000e_getreg(LEDCTL), 2942 e1000e_getreg(TCTL), 2943 e1000e_getreg(TDBAL), 2944 e1000e_getreg(TDLEN), 2945 e1000e_getreg(TDH1), 2946 e1000e_getreg(RADV), 2947 e1000e_getreg(ECOL), 2948 e1000e_getreg(DC), 2949 e1000e_getreg(RLEC), 2950 e1000e_getreg(XOFFTXC), 2951 e1000e_getreg(RFC), 2952 e1000e_getreg(RNBC), 2953 e1000e_getreg(MGTPTC), 2954 e1000e_getreg(TIMINCA), 2955 e1000e_getreg(RXCFGL), 2956 e1000e_getreg(MFUTP01), 2957 e1000e_getreg(FACTPS), 2958 e1000e_getreg(GSCL_1), 2959 e1000e_getreg(GSCN_0), 2960 e1000e_getreg(GCR2), 2961 e1000e_getreg(RDT1), 2962 e1000e_getreg(PBACLR), 2963 e1000e_getreg(FCTTV), 2964 e1000e_getreg(EEWR), 2965 e1000e_getreg(FLSWCTL), 2966 e1000e_getreg(RXDCTL1), 2967 e1000e_getreg(RXSATRL), 2968 e1000e_getreg(RXUDP), 2969 e1000e_getreg(TORL), 2970 e1000e_getreg(TDLEN1), 2971 e1000e_getreg(MCC), 2972 e1000e_getreg(WUC), 2973 e1000e_getreg(EECD), 2974 e1000e_getreg(MFUTP23), 2975 e1000e_getreg(RAID), 2976 e1000e_getreg(FCRTV), 2977 e1000e_getreg(TXDCTL1), 2978 e1000e_getreg(RCTL), 2979 e1000e_getreg(TDT), 2980 e1000e_getreg(MDIC), 2981 e1000e_getreg(FCRUC), 2982 e1000e_getreg(VET), 2983 e1000e_getreg(RDBAL0), 2984 e1000e_getreg(TDBAH1), 2985 e1000e_getreg(RDTR), 2986 e1000e_getreg(SCC), 2987 e1000e_getreg(COLC), 2988 e1000e_getreg(CEXTERR), 2989 e1000e_getreg(XOFFRXC), 2990 e1000e_getreg(IPAV), 2991 e1000e_getreg(GOTCL), 2992 e1000e_getreg(MGTPDC), 2993 e1000e_getreg(GCR), 2994 e1000e_getreg(IVAR), 2995 e1000e_getreg(POEMB), 2996 e1000e_getreg(MFVAL), 2997 e1000e_getreg(FUNCTAG), 2998 e1000e_getreg(GSCL_4), 2999 e1000e_getreg(GSCN_3), 3000 e1000e_getreg(MRQC), 3001 e1000e_getreg(RDLEN1), 3002 e1000e_getreg(FCT), 3003 e1000e_getreg(FLA), 3004 e1000e_getreg(FLOL), 3005 e1000e_getreg(RXDCTL), 3006 e1000e_getreg(RXSTMPL), 3007 e1000e_getreg(TIMADJH), 3008 e1000e_getreg(FCRTL), 3009 e1000e_getreg(TDBAH), 3010 e1000e_getreg(TADV), 3011 e1000e_getreg(XONRXC), 3012 e1000e_getreg(TSCTFC), 3013 e1000e_getreg(RFCTL), 3014 e1000e_getreg(GSCN_1), 3015 e1000e_getreg(FCAL), 3016 e1000e_getreg(FLSWCNT), 3017 3018 [TOTH] = e1000e_mac_read_clr8, 3019 [GOTCH] = e1000e_mac_read_clr8, 3020 [PRC64] = e1000e_mac_read_clr4, 3021 [PRC255] = e1000e_mac_read_clr4, 3022 [PRC1023] = e1000e_mac_read_clr4, 3023 [PTC64] = e1000e_mac_read_clr4, 3024 [PTC255] = e1000e_mac_read_clr4, 3025 [PTC1023] = e1000e_mac_read_clr4, 3026 [GPRC] = e1000e_mac_read_clr4, 3027 [TPT] = e1000e_mac_read_clr4, 3028 [RUC] = e1000e_mac_read_clr4, 3029 [BPRC] = e1000e_mac_read_clr4, 3030 [MPTC] = e1000e_mac_read_clr4, 3031 [IAC] = e1000e_mac_read_clr4, 3032 [ICR] = e1000e_mac_icr_read, 3033 [STATUS] = e1000e_get_status, 3034 [TARC0] = e1000e_get_tarc, 3035 [ICS] = e1000e_mac_ics_read, 3036 [TORH] = e1000e_mac_read_clr8, 3037 [GORCH] = e1000e_mac_read_clr8, 3038 [PRC127] = e1000e_mac_read_clr4, 3039 [PRC511] = e1000e_mac_read_clr4, 3040 [PRC1522] = e1000e_mac_read_clr4, 3041 [PTC127] = e1000e_mac_read_clr4, 3042 [PTC511] = e1000e_mac_read_clr4, 3043 [PTC1522] = e1000e_mac_read_clr4, 3044 [GPTC] = e1000e_mac_read_clr4, 3045 [TPR] = e1000e_mac_read_clr4, 3046 [ROC] = e1000e_mac_read_clr4, 3047 [MPRC] = e1000e_mac_read_clr4, 3048 [BPTC] = e1000e_mac_read_clr4, 3049 [TSCTC] = e1000e_mac_read_clr4, 3050 [ITR] = e1000e_mac_itr_read, 3051 [CTRL] = e1000e_get_ctrl, 3052 [TARC1] = e1000e_get_tarc, 3053 [SWSM] = e1000e_mac_swsm_read, 3054 [IMS] = e1000e_mac_ims_read, 3055 [SYSTIML] = e1000e_get_systiml, 3056 [RXSATRH] = e1000e_get_rxsatrh, 3057 [TXSTMPH] = e1000e_get_txstmph, 3058 3059 [CRCERRS ... MPC] = e1000e_mac_readreg, 3060 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3061 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3062 [RA ... RA + 31] = e1000e_mac_readreg, 3063 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3064 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3065 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3066 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3067 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3068 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3069 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3070 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3071 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3072 [RETA ... RETA + 31] = e1000e_mac_readreg, 3073 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3074 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3075 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3076 }; 3077 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3078 3079 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3080 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3081 static const writeops e1000e_macreg_writeops[] = { 3082 e1000e_putreg(PBA), 3083 e1000e_putreg(SWSM), 3084 e1000e_putreg(WUFC), 3085 e1000e_putreg(RDBAH1), 3086 e1000e_putreg(TDBAH), 3087 e1000e_putreg(TXDCTL), 3088 e1000e_putreg(RDBAH0), 3089 e1000e_putreg(LEDCTL), 3090 e1000e_putreg(FCAL), 3091 e1000e_putreg(FCRUC), 3092 e1000e_putreg(WUC), 3093 e1000e_putreg(WUS), 3094 e1000e_putreg(IPAV), 3095 e1000e_putreg(TDBAH1), 3096 e1000e_putreg(IAM), 3097 e1000e_putreg(EIAC), 3098 e1000e_putreg(IVAR), 3099 e1000e_putreg(TARC0), 3100 e1000e_putreg(TARC1), 3101 e1000e_putreg(FLSWDATA), 3102 e1000e_putreg(POEMB), 3103 e1000e_putreg(MFUTP01), 3104 e1000e_putreg(MFUTP23), 3105 e1000e_putreg(MANC), 3106 e1000e_putreg(MANC2H), 3107 e1000e_putreg(MFVAL), 3108 e1000e_putreg(EXTCNF_CTRL), 3109 e1000e_putreg(FACTPS), 3110 e1000e_putreg(FUNCTAG), 3111 e1000e_putreg(GSCL_1), 3112 e1000e_putreg(GSCL_2), 3113 e1000e_putreg(GSCL_3), 3114 e1000e_putreg(GSCL_4), 3115 e1000e_putreg(GSCN_0), 3116 e1000e_putreg(GSCN_1), 3117 e1000e_putreg(GSCN_2), 3118 e1000e_putreg(GSCN_3), 3119 e1000e_putreg(GCR2), 3120 e1000e_putreg(MRQC), 3121 e1000e_putreg(FLOP), 3122 e1000e_putreg(FLOL), 3123 e1000e_putreg(FLSWCTL), 3124 e1000e_putreg(FLSWCNT), 3125 e1000e_putreg(FLA), 3126 e1000e_putreg(RXDCTL1), 3127 e1000e_putreg(TXDCTL1), 3128 e1000e_putreg(TIPG), 3129 e1000e_putreg(RXSTMPH), 3130 e1000e_putreg(RXSTMPL), 3131 e1000e_putreg(RXSATRL), 3132 e1000e_putreg(RXSATRH), 3133 e1000e_putreg(TXSTMPL), 3134 e1000e_putreg(TXSTMPH), 3135 e1000e_putreg(SYSTIML), 3136 e1000e_putreg(SYSTIMH), 3137 e1000e_putreg(TIMADJL), 3138 e1000e_putreg(RXUDP), 3139 e1000e_putreg(RXCFGL), 3140 e1000e_putreg(TSYNCRXCTL), 3141 e1000e_putreg(TSYNCTXCTL), 3142 e1000e_putreg(EXTCNF_SIZE), 3143 e1000e_putreg(EEMNGCTL), 3144 e1000e_putreg(RA), 3145 3146 [TDH1] = e1000e_set_16bit, 3147 [TDT1] = e1000e_set_tdt, 3148 [TCTL] = e1000e_set_tctl, 3149 [TDT] = e1000e_set_tdt, 3150 [MDIC] = e1000e_set_mdic, 3151 [ICS] = e1000e_set_ics, 3152 [TDH] = e1000e_set_16bit, 3153 [RDH0] = e1000e_set_16bit, 3154 [RDT0] = e1000e_set_rdt, 3155 [IMC] = e1000e_set_imc, 3156 [IMS] = e1000e_set_ims, 3157 [ICR] = e1000e_set_icr, 3158 [EECD] = e1000e_set_eecd, 3159 [RCTL] = e1000e_set_rx_control, 3160 [CTRL] = e1000e_set_ctrl, 3161 [RDTR] = e1000e_set_rdtr, 3162 [RADV] = e1000e_set_16bit, 3163 [TADV] = e1000e_set_16bit, 3164 [ITR] = e1000e_set_itr, 3165 [EERD] = e1000e_set_eerd, 3166 [AIT] = e1000e_set_16bit, 3167 [TDFH] = e1000e_set_13bit, 3168 [TDFT] = e1000e_set_13bit, 3169 [TDFHS] = e1000e_set_13bit, 3170 [TDFTS] = e1000e_set_13bit, 3171 [TDFPC] = e1000e_set_13bit, 3172 [RDFH] = e1000e_set_13bit, 3173 [RDFHS] = e1000e_set_13bit, 3174 [RDFT] = e1000e_set_13bit, 3175 [RDFTS] = e1000e_set_13bit, 3176 [RDFPC] = e1000e_set_13bit, 3177 [PBS] = e1000e_set_6bit, 3178 [GCR] = e1000e_set_gcr, 3179 [PSRCTL] = e1000e_set_psrctl, 3180 [RXCSUM] = e1000e_set_rxcsum, 3181 [RAID] = e1000e_set_16bit, 3182 [RSRPD] = e1000e_set_12bit, 3183 [TIDV] = e1000e_set_tidv, 3184 [TDLEN1] = e1000e_set_dlen, 3185 [TDLEN] = e1000e_set_dlen, 3186 [RDLEN0] = e1000e_set_dlen, 3187 [RDLEN1] = e1000e_set_dlen, 3188 [TDBAL] = e1000e_set_dbal, 3189 [TDBAL1] = e1000e_set_dbal, 3190 [RDBAL0] = e1000e_set_dbal, 3191 [RDBAL1] = e1000e_set_dbal, 3192 [RDH1] = e1000e_set_16bit, 3193 [RDT1] = e1000e_set_rdt, 3194 [STATUS] = e1000e_set_status, 3195 [PBACLR] = e1000e_set_pbaclr, 3196 [CTRL_EXT] = e1000e_set_ctrlext, 3197 [FCAH] = e1000e_set_16bit, 3198 [FCT] = e1000e_set_16bit, 3199 [FCTTV] = e1000e_set_16bit, 3200 [FCRTV] = e1000e_set_16bit, 3201 [FCRTH] = e1000e_set_fcrth, 3202 [FCRTL] = e1000e_set_fcrtl, 3203 [VET] = e1000e_set_vet, 3204 [RXDCTL] = e1000e_set_rxdctl, 3205 [FLASHT] = e1000e_set_16bit, 3206 [EEWR] = e1000e_set_eewr, 3207 [CTRL_DUP] = e1000e_set_ctrl, 3208 [RFCTL] = e1000e_set_rfctl, 3209 [RA + 1] = e1000e_mac_setmacaddr, 3210 [TIMINCA] = e1000e_set_timinca, 3211 [TIMADJH] = e1000e_set_timadjh, 3212 3213 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3214 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3215 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3216 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3217 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3218 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3219 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3220 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3221 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3222 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3223 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3224 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3225 [RETA ... RETA + 31] = e1000e_mac_writereg, 3226 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3227 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3228 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3229 }; 3230 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3231 3232 enum { MAC_ACCESS_PARTIAL = 1 }; 3233 3234 /* 3235 * The array below combines alias offsets of the index values for the 3236 * MAC registers that have aliases, with the indication of not fully 3237 * implemented registers (lowest bit). This combination is possible 3238 * because all of the offsets are even. 3239 */ 3240 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3241 /* Alias index offsets */ 3242 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3243 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3244 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3245 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3246 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3247 [RA_A ... RA_A + 31] = 0x14f0, 3248 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3249 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3250 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3251 /* Access options */ 3252 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3253 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3254 [RDFPC] = MAC_ACCESS_PARTIAL, 3255 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3256 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3257 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3258 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3259 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3260 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3261 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3262 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3263 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3264 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3265 }; 3266 3267 void 3268 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3269 { 3270 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3271 3272 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3273 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3274 trace_e1000e_wrn_regs_write_trivial(index << 2); 3275 } 3276 trace_e1000e_core_write(index << 2, size, val); 3277 e1000e_macreg_writeops[index](core, index, val); 3278 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3279 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3280 } else { 3281 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3282 } 3283 } 3284 3285 uint64_t 3286 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3287 { 3288 uint64_t val; 3289 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3290 3291 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3292 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3293 trace_e1000e_wrn_regs_read_trivial(index << 2); 3294 } 3295 val = e1000e_macreg_readops[index](core, index); 3296 trace_e1000e_core_read(index << 2, size, val); 3297 return val; 3298 } else { 3299 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3300 } 3301 return 0; 3302 } 3303 3304 static void 3305 e1000e_autoneg_resume(E1000ECore *core) 3306 { 3307 if (e1000e_have_autoneg(core) && 3308 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3309 qemu_get_queue(core->owner_nic)->link_down = false; 3310 timer_mod(core->autoneg_timer, 3311 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3312 } 3313 } 3314 3315 void 3316 e1000e_core_pci_realize(E1000ECore *core, 3317 const uint16_t *eeprom_templ, 3318 uint32_t eeprom_size, 3319 const uint8_t *macaddr) 3320 { 3321 int i; 3322 3323 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3324 e1000e_autoneg_timer, core); 3325 e1000e_intrmgr_pci_realize(core); 3326 3327 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3328 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3329 } 3330 3331 net_rx_pkt_init(&core->rx_pkt); 3332 3333 e1000x_core_prepare_eeprom(core->eeprom, 3334 eeprom_templ, 3335 eeprom_size, 3336 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3337 macaddr); 3338 e1000e_update_rx_offloads(core); 3339 } 3340 3341 void 3342 e1000e_core_pci_uninit(E1000ECore *core) 3343 { 3344 int i; 3345 3346 timer_free(core->autoneg_timer); 3347 3348 e1000e_intrmgr_pci_unint(core); 3349 3350 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3351 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3352 } 3353 3354 net_rx_pkt_uninit(core->rx_pkt); 3355 } 3356 3357 static const uint16_t 3358 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3359 [0] = { 3360 [MII_BMCR] = MII_BMCR_SPEED1000 | 3361 MII_BMCR_FD | 3362 MII_BMCR_AUTOEN, 3363 3364 [MII_BMSR] = MII_BMSR_EXTCAP | 3365 MII_BMSR_LINK_ST | 3366 MII_BMSR_AUTONEG | 3367 MII_BMSR_MFPS | 3368 MII_BMSR_EXTSTAT | 3369 MII_BMSR_10T_HD | 3370 MII_BMSR_10T_FD | 3371 MII_BMSR_100TX_HD | 3372 MII_BMSR_100TX_FD, 3373 3374 [MII_PHYID1] = 0x141, 3375 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3376 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3377 MII_ANAR_10FD | MII_ANAR_TX | 3378 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3379 MII_ANAR_PAUSE_ASYM, 3380 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3381 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3382 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3383 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3384 [MII_ANNP] = 1 | MII_ANNP_MP, 3385 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3386 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3387 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3388 MII_STAT1000_ROK | MII_STAT1000_LOK, 3389 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3390 3391 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3392 BIT(12) | BIT(13), 3393 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3394 }, 3395 [2] = { 3396 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3397 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3398 }, 3399 [3] = { 3400 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3401 } 3402 }; 3403 3404 static const uint32_t e1000e_mac_reg_init[] = { 3405 [PBA] = 0x00140014, 3406 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3407 [EXTCNF_CTRL] = BIT(3), 3408 [EEMNGCTL] = BIT(31), 3409 [FLASHT] = 0x2, 3410 [FLSWCTL] = BIT(30) | BIT(31), 3411 [FLOL] = BIT(0), 3412 [RXDCTL] = BIT(16), 3413 [RXDCTL1] = BIT(16), 3414 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3415 [RXCFGL] = 0x88F7, 3416 [RXUDP] = 0x319, 3417 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3418 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3419 E1000_CTRL_ADVD3WUC, 3420 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3421 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3422 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3423 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3424 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3425 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3426 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3427 [EERD] = E1000_EERW_DONE, 3428 [EEWR] = E1000_EERW_DONE, 3429 [GCR] = E1000_L0S_ADJUST | 3430 E1000_L1_ENTRY_LATENCY_MSB | 3431 E1000_L1_ENTRY_LATENCY_LSB, 3432 [TDFH] = 0x600, 3433 [TDFT] = 0x600, 3434 [TDFHS] = 0x600, 3435 [TDFTS] = 0x600, 3436 [POEMB] = 0x30D, 3437 [PBS] = 0x028, 3438 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3439 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3440 [SWSM] = 1, 3441 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3442 [ITR] = E1000E_MIN_XITR, 3443 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3444 }; 3445 3446 static void e1000e_reset(E1000ECore *core, bool sw) 3447 { 3448 int i; 3449 3450 timer_del(core->autoneg_timer); 3451 3452 e1000e_intrmgr_reset(core); 3453 3454 memset(core->phy, 0, sizeof core->phy); 3455 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3456 3457 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3458 if (sw && (i == PBA || i == PBS || i == FLA)) { 3459 continue; 3460 } 3461 3462 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3463 e1000e_mac_reg_init[i] : 0; 3464 } 3465 3466 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3467 3468 if (qemu_get_queue(core->owner_nic)->link_down) { 3469 e1000e_link_down(core); 3470 } 3471 3472 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3473 3474 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3475 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3476 core->tx[i].skip_cp = false; 3477 } 3478 } 3479 3480 void 3481 e1000e_core_reset(E1000ECore *core) 3482 { 3483 e1000e_reset(core, false); 3484 } 3485 3486 void e1000e_core_pre_save(E1000ECore *core) 3487 { 3488 int i; 3489 NetClientState *nc = qemu_get_queue(core->owner_nic); 3490 3491 /* 3492 * If link is down and auto-negotiation is supported and ongoing, 3493 * complete auto-negotiation immediately. This allows us to look 3494 * at MII_BMSR_AN_COMP to infer link status on load. 3495 */ 3496 if (nc->link_down && e1000e_have_autoneg(core)) { 3497 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3498 e1000e_update_flowctl_status(core); 3499 } 3500 3501 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3502 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3503 core->tx[i].skip_cp = true; 3504 } 3505 } 3506 } 3507 3508 int 3509 e1000e_core_post_load(E1000ECore *core) 3510 { 3511 NetClientState *nc = qemu_get_queue(core->owner_nic); 3512 3513 /* 3514 * nc.link_down can't be migrated, so infer link_down according 3515 * to link status bit in core.mac[STATUS]. 3516 */ 3517 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3518 3519 /* 3520 * we need to restart intrmgr timers, as an older version of 3521 * QEMU can have stopped them before migration 3522 */ 3523 e1000e_intrmgr_resume(core); 3524 e1000e_autoneg_resume(core); 3525 3526 return 0; 3527 } 3528