1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000x_common.h" 49 #include "e1000e_core.h" 50 51 #include "trace.h" 52 53 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 54 #define E1000E_MIN_XITR (500) 55 56 #define E1000E_MAX_TX_FRAGS (64) 57 58 union e1000_rx_desc_union { 59 struct e1000_rx_desc legacy; 60 union e1000_rx_desc_extended extended; 61 union e1000_rx_desc_packet_split packet_split; 62 }; 63 64 static ssize_t 65 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 66 bool has_vnet); 67 68 static inline void 69 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 70 71 static void e1000e_reset(E1000ECore *core, bool sw); 72 73 static inline void 74 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 75 { 76 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 77 trace_e1000e_wrn_no_ts_support(); 78 } 79 } 80 81 static inline void 82 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 83 { 84 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 85 trace_e1000e_wrn_no_snap_support(); 86 } 87 } 88 89 static inline void 90 e1000e_raise_legacy_irq(E1000ECore *core) 91 { 92 trace_e1000e_irq_legacy_notify(true); 93 e1000x_inc_reg_if_not_full(core->mac, IAC); 94 pci_set_irq(core->owner, 1); 95 } 96 97 static inline void 98 e1000e_lower_legacy_irq(E1000ECore *core) 99 { 100 trace_e1000e_irq_legacy_notify(false); 101 pci_set_irq(core->owner, 0); 102 } 103 104 static inline void 105 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 106 { 107 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 108 timer->delay_resolution_ns; 109 110 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 111 112 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 113 114 timer->running = true; 115 } 116 117 static void 118 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 119 { 120 if (timer->running) { 121 e1000e_intrmgr_rearm_timer(timer); 122 } 123 } 124 125 static void 126 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 127 { 128 if (timer->running) { 129 timer_del(timer->timer); 130 } 131 } 132 133 static inline void 134 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 135 { 136 if (timer->running) { 137 timer_del(timer->timer); 138 timer->running = false; 139 } 140 } 141 142 static inline void 143 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 144 { 145 trace_e1000e_irq_fire_delayed_interrupts(); 146 e1000e_set_interrupt_cause(core, 0); 147 } 148 149 static void 150 e1000e_intrmgr_on_timer(void *opaque) 151 { 152 E1000IntrDelayTimer *timer = opaque; 153 154 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 155 156 timer->running = false; 157 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 158 } 159 160 static void 161 e1000e_intrmgr_on_throttling_timer(void *opaque) 162 { 163 E1000IntrDelayTimer *timer = opaque; 164 165 timer->running = false; 166 167 if (msi_enabled(timer->core->owner)) { 168 trace_e1000e_irq_msi_notify_postponed(); 169 /* Clear msi_causes_pending to fire MSI eventually */ 170 timer->core->msi_causes_pending = 0; 171 e1000e_set_interrupt_cause(timer->core, 0); 172 } else { 173 trace_e1000e_irq_legacy_notify_postponed(); 174 e1000e_set_interrupt_cause(timer->core, 0); 175 } 176 } 177 178 static void 179 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 180 { 181 E1000IntrDelayTimer *timer = opaque; 182 int idx = timer - &timer->core->eitr[0]; 183 184 timer->running = false; 185 186 trace_e1000e_irq_msix_notify_postponed_vec(idx); 187 msix_notify(timer->core->owner, idx); 188 } 189 190 static void 191 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 192 { 193 int i; 194 195 core->radv.delay_reg = RADV; 196 core->rdtr.delay_reg = RDTR; 197 core->raid.delay_reg = RAID; 198 core->tadv.delay_reg = TADV; 199 core->tidv.delay_reg = TIDV; 200 201 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 202 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 207 core->radv.core = core; 208 core->rdtr.core = core; 209 core->raid.core = core; 210 core->tadv.core = core; 211 core->tidv.core = core; 212 213 core->itr.core = core; 214 core->itr.delay_reg = ITR; 215 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 216 217 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 218 core->eitr[i].core = core; 219 core->eitr[i].delay_reg = EITR + i; 220 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 221 } 222 223 if (!create) { 224 return; 225 } 226 227 core->radv.timer = 228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 229 core->rdtr.timer = 230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 231 core->raid.timer = 232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 233 234 core->tadv.timer = 235 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 236 core->tidv.timer = 237 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 238 239 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 240 e1000e_intrmgr_on_throttling_timer, 241 &core->itr); 242 243 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 244 core->eitr[i].timer = 245 timer_new_ns(QEMU_CLOCK_VIRTUAL, 246 e1000e_intrmgr_on_msix_throttling_timer, 247 &core->eitr[i]); 248 } 249 } 250 251 static inline void 252 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 253 { 254 e1000e_intrmgr_stop_timer(&core->radv); 255 e1000e_intrmgr_stop_timer(&core->rdtr); 256 e1000e_intrmgr_stop_timer(&core->raid); 257 e1000e_intrmgr_stop_timer(&core->tidv); 258 e1000e_intrmgr_stop_timer(&core->tadv); 259 } 260 261 static bool 262 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 263 { 264 uint32_t delayable_causes; 265 uint32_t rdtr = core->mac[RDTR]; 266 uint32_t radv = core->mac[RADV]; 267 uint32_t raid = core->mac[RAID]; 268 269 if (msix_enabled(core->owner)) { 270 return false; 271 } 272 273 delayable_causes = E1000_ICR_RXQ0 | 274 E1000_ICR_RXQ1 | 275 E1000_ICR_RXT0; 276 277 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 278 delayable_causes |= E1000_ICR_ACK; 279 } 280 281 /* Clean up all causes that may be delayed */ 282 core->delayed_causes |= *causes & delayable_causes; 283 *causes &= ~delayable_causes; 284 285 /* 286 * Check if delayed RX interrupts disabled by client 287 * or if there are causes that cannot be delayed 288 */ 289 if ((rdtr == 0) || (*causes != 0)) { 290 return false; 291 } 292 293 /* 294 * Check if delayed RX ACK interrupts disabled by client 295 * and there is an ACK packet received 296 */ 297 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 298 return false; 299 } 300 301 /* All causes delayed */ 302 e1000e_intrmgr_rearm_timer(&core->rdtr); 303 304 if (!core->radv.running && (radv != 0)) { 305 e1000e_intrmgr_rearm_timer(&core->radv); 306 } 307 308 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 309 e1000e_intrmgr_rearm_timer(&core->raid); 310 } 311 312 return true; 313 } 314 315 static bool 316 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 317 { 318 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 319 E1000_ICR_TXQ1 | 320 E1000_ICR_TXQE | 321 E1000_ICR_TXDW; 322 323 if (msix_enabled(core->owner)) { 324 return false; 325 } 326 327 /* Clean up all causes that may be delayed */ 328 core->delayed_causes |= *causes & delayable_causes; 329 *causes &= ~delayable_causes; 330 331 /* If there are causes that cannot be delayed */ 332 if (*causes != 0) { 333 return false; 334 } 335 336 /* All causes delayed */ 337 e1000e_intrmgr_rearm_timer(&core->tidv); 338 339 if (!core->tadv.running && (core->mac[TADV] != 0)) { 340 e1000e_intrmgr_rearm_timer(&core->tadv); 341 } 342 343 return true; 344 } 345 346 static uint32_t 347 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 348 { 349 uint32_t res; 350 351 if (msix_enabled(core->owner)) { 352 assert(core->delayed_causes == 0); 353 return 0; 354 } 355 356 res = core->delayed_causes; 357 core->delayed_causes = 0; 358 359 e1000e_intrmgr_stop_delay_timers(core); 360 361 return res; 362 } 363 364 static void 365 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 366 { 367 int i; 368 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 369 370 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 371 core->mac[ICR] |= val; 372 373 if (core->itr.running) { 374 timer_del(core->itr.timer); 375 e1000e_intrmgr_on_throttling_timer(&core->itr); 376 } 377 378 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 379 if (core->eitr[i].running) { 380 timer_del(core->eitr[i].timer); 381 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 382 } 383 } 384 } 385 386 static void 387 e1000e_intrmgr_resume(E1000ECore *core) 388 { 389 int i; 390 391 e1000e_intmgr_timer_resume(&core->radv); 392 e1000e_intmgr_timer_resume(&core->rdtr); 393 e1000e_intmgr_timer_resume(&core->raid); 394 e1000e_intmgr_timer_resume(&core->tidv); 395 e1000e_intmgr_timer_resume(&core->tadv); 396 397 e1000e_intmgr_timer_resume(&core->itr); 398 399 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 400 e1000e_intmgr_timer_resume(&core->eitr[i]); 401 } 402 } 403 404 static void 405 e1000e_intrmgr_pause(E1000ECore *core) 406 { 407 int i; 408 409 e1000e_intmgr_timer_pause(&core->radv); 410 e1000e_intmgr_timer_pause(&core->rdtr); 411 e1000e_intmgr_timer_pause(&core->raid); 412 e1000e_intmgr_timer_pause(&core->tidv); 413 e1000e_intmgr_timer_pause(&core->tadv); 414 415 e1000e_intmgr_timer_pause(&core->itr); 416 417 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 418 e1000e_intmgr_timer_pause(&core->eitr[i]); 419 } 420 } 421 422 static void 423 e1000e_intrmgr_reset(E1000ECore *core) 424 { 425 int i; 426 427 core->delayed_causes = 0; 428 429 e1000e_intrmgr_stop_delay_timers(core); 430 431 e1000e_intrmgr_stop_timer(&core->itr); 432 433 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 434 e1000e_intrmgr_stop_timer(&core->eitr[i]); 435 } 436 } 437 438 static void 439 e1000e_intrmgr_pci_unint(E1000ECore *core) 440 { 441 int i; 442 443 timer_free(core->radv.timer); 444 timer_free(core->rdtr.timer); 445 timer_free(core->raid.timer); 446 447 timer_free(core->tadv.timer); 448 timer_free(core->tidv.timer); 449 450 timer_free(core->itr.timer); 451 452 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 453 timer_free(core->eitr[i].timer); 454 } 455 } 456 457 static void 458 e1000e_intrmgr_pci_realize(E1000ECore *core) 459 { 460 e1000e_intrmgr_initialize_all_timers(core, true); 461 } 462 463 static inline bool 464 e1000e_rx_csum_enabled(E1000ECore *core) 465 { 466 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 467 } 468 469 static inline bool 470 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 471 { 472 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 473 } 474 475 static inline bool 476 e1000e_rx_use_ps_descriptor(E1000ECore *core) 477 { 478 return !e1000e_rx_use_legacy_descriptor(core) && 479 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 480 } 481 482 static inline bool 483 e1000e_rss_enabled(E1000ECore *core) 484 { 485 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 486 !e1000e_rx_csum_enabled(core) && 487 !e1000e_rx_use_legacy_descriptor(core); 488 } 489 490 typedef struct E1000E_RSSInfo_st { 491 bool enabled; 492 uint32_t hash; 493 uint32_t queue; 494 uint32_t type; 495 } E1000E_RSSInfo; 496 497 static uint32_t 498 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 499 { 500 bool isip4, isip6, isudp, istcp; 501 502 assert(e1000e_rss_enabled(core)); 503 504 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 505 506 if (isip4) { 507 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 508 509 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC], 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 511 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 512 513 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 514 return E1000_MRQ_RSS_TYPE_IPV4TCP; 515 } 516 517 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 518 return E1000_MRQ_RSS_TYPE_IPV4; 519 } 520 } else if (isip6) { 521 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 522 523 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 524 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 525 526 /* 527 * Following two traces must not be combined because resulting 528 * event will have 11 arguments totally and some trace backends 529 * (at least "ust") have limitation of maximum 10 arguments per 530 * event. Events with more arguments fail to compile for 531 * backends like these. 532 */ 533 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 534 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp, 535 ip6info->has_ext_hdrs, 536 ip6info->rss_ex_dst_valid, 537 ip6info->rss_ex_src_valid, 538 core->mac[MRQC], 539 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 540 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 541 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 542 543 if ((!ex_dis || !ip6info->has_ext_hdrs) && 544 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 545 ip6info->rss_ex_src_valid))) { 546 547 if (istcp && !ip6info->fragment && 548 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 549 return E1000_MRQ_RSS_TYPE_IPV6TCP; 550 } 551 552 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 553 return E1000_MRQ_RSS_TYPE_IPV6EX; 554 } 555 556 } 557 558 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 559 return E1000_MRQ_RSS_TYPE_IPV6; 560 } 561 562 } 563 564 return E1000_MRQ_RSS_TYPE_NONE; 565 } 566 567 static uint32_t 568 e1000e_rss_calc_hash(E1000ECore *core, 569 struct NetRxPkt *pkt, 570 E1000E_RSSInfo *info) 571 { 572 NetRxPktRssType type; 573 574 assert(e1000e_rss_enabled(core)); 575 576 switch (info->type) { 577 case E1000_MRQ_RSS_TYPE_IPV4: 578 type = NetPktRssIpV4; 579 break; 580 case E1000_MRQ_RSS_TYPE_IPV4TCP: 581 type = NetPktRssIpV4Tcp; 582 break; 583 case E1000_MRQ_RSS_TYPE_IPV6TCP: 584 type = NetPktRssIpV6TcpEx; 585 break; 586 case E1000_MRQ_RSS_TYPE_IPV6: 587 type = NetPktRssIpV6; 588 break; 589 case E1000_MRQ_RSS_TYPE_IPV6EX: 590 type = NetPktRssIpV6Ex; 591 break; 592 default: 593 assert(false); 594 return 0; 595 } 596 597 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 598 } 599 600 static void 601 e1000e_rss_parse_packet(E1000ECore *core, 602 struct NetRxPkt *pkt, 603 E1000E_RSSInfo *info) 604 { 605 trace_e1000e_rx_rss_started(); 606 607 if (!e1000e_rss_enabled(core)) { 608 info->enabled = false; 609 info->hash = 0; 610 info->queue = 0; 611 info->type = 0; 612 trace_e1000e_rx_rss_disabled(); 613 return; 614 } 615 616 info->enabled = true; 617 618 info->type = e1000e_rss_get_hash_type(core, pkt); 619 620 trace_e1000e_rx_rss_type(info->type); 621 622 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 623 info->hash = 0; 624 info->queue = 0; 625 return; 626 } 627 628 info->hash = e1000e_rss_calc_hash(core, pkt, info); 629 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 630 } 631 632 static bool 633 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 634 { 635 if (tx->props.tse && tx->cptse) { 636 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 637 return false; 638 } 639 640 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 641 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 642 return true; 643 } 644 645 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 646 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 647 return false; 648 } 649 } 650 651 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 652 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 653 } 654 655 return true; 656 } 657 658 static void e1000e_tx_pkt_callback(void *core, 659 const struct iovec *iov, 660 int iovcnt, 661 const struct iovec *virt_iov, 662 int virt_iovcnt) 663 { 664 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 665 } 666 667 static bool 668 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 669 { 670 int target_queue = MIN(core->max_queue_num, queue_index); 671 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 672 673 if (!e1000e_setup_tx_offloads(core, tx)) { 674 return false; 675 } 676 677 net_tx_pkt_dump(tx->tx_pkt); 678 679 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 680 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 681 return net_tx_pkt_send_custom(tx->tx_pkt, false, 682 e1000e_tx_pkt_callback, core); 683 } else { 684 return net_tx_pkt_send(tx->tx_pkt, queue); 685 } 686 } 687 688 static void 689 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 690 { 691 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 692 PTC1023, PTC1522 }; 693 694 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt); 695 696 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 697 e1000x_inc_reg_if_not_full(core->mac, TPT); 698 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 699 700 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 701 case ETH_PKT_BCAST: 702 e1000x_inc_reg_if_not_full(core->mac, BPTC); 703 break; 704 case ETH_PKT_MCAST: 705 e1000x_inc_reg_if_not_full(core->mac, MPTC); 706 break; 707 case ETH_PKT_UCAST: 708 break; 709 default: 710 g_assert_not_reached(); 711 } 712 713 core->mac[GPTC] = core->mac[TPT]; 714 core->mac[GOTCL] = core->mac[TOTL]; 715 core->mac[GOTCH] = core->mac[TOTH]; 716 } 717 718 static void 719 e1000e_process_tx_desc(E1000ECore *core, 720 struct e1000e_tx *tx, 721 struct e1000_tx_desc *dp, 722 int queue_index) 723 { 724 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 725 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 726 unsigned int split_size = txd_lower & 0xffff; 727 uint64_t addr; 728 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 729 bool eop = txd_lower & E1000_TXD_CMD_EOP; 730 731 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 732 e1000x_read_tx_ctx_descr(xp, &tx->props); 733 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 734 return; 735 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 736 /* data descriptor */ 737 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 738 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 739 e1000e_process_ts_option(core, dp); 740 } else { 741 /* legacy descriptor */ 742 e1000e_process_ts_option(core, dp); 743 tx->cptse = 0; 744 } 745 746 addr = le64_to_cpu(dp->buffer_addr); 747 748 if (!tx->skip_cp) { 749 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) { 750 tx->skip_cp = true; 751 } 752 } 753 754 if (eop) { 755 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 756 if (e1000x_vlan_enabled(core->mac) && 757 e1000x_is_vlan_txd(txd_lower)) { 758 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 759 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 760 } 761 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 762 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 763 } 764 } 765 766 tx->skip_cp = false; 767 net_tx_pkt_reset(tx->tx_pkt); 768 769 tx->sum_needed = 0; 770 tx->cptse = 0; 771 } 772 } 773 774 static inline uint32_t 775 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 776 { 777 if (!msix_enabled(core->owner)) { 778 return E1000_ICR_TXDW; 779 } 780 781 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 782 } 783 784 static inline uint32_t 785 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 786 bool min_threshold_hit) 787 { 788 if (!msix_enabled(core->owner)) { 789 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 790 } 791 792 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 793 } 794 795 static uint32_t 796 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 797 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 798 { 799 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 800 801 if (!(txd_lower & E1000_TXD_CMD_RS) && 802 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 803 return 0; 804 } 805 806 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 807 808 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 809 810 dp->upper.data = cpu_to_le32(txd_upper); 811 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 812 &dp->upper, sizeof(dp->upper)); 813 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 814 } 815 816 typedef struct E1000E_RingInfo_st { 817 int dbah; 818 int dbal; 819 int dlen; 820 int dh; 821 int dt; 822 int idx; 823 } E1000E_RingInfo; 824 825 static inline bool 826 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 827 { 828 return core->mac[r->dh] == core->mac[r->dt] || 829 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 830 } 831 832 static inline uint64_t 833 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 834 { 835 uint64_t bah = core->mac[r->dbah]; 836 uint64_t bal = core->mac[r->dbal]; 837 838 return (bah << 32) + bal; 839 } 840 841 static inline uint64_t 842 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 843 { 844 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 845 } 846 847 static inline void 848 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 849 { 850 core->mac[r->dh] += count; 851 852 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 853 core->mac[r->dh] = 0; 854 } 855 } 856 857 static inline uint32_t 858 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 859 { 860 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 861 core->mac[r->dh], core->mac[r->dt]); 862 863 if (core->mac[r->dh] <= core->mac[r->dt]) { 864 return core->mac[r->dt] - core->mac[r->dh]; 865 } 866 867 if (core->mac[r->dh] > core->mac[r->dt]) { 868 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 869 core->mac[r->dt] - core->mac[r->dh]; 870 } 871 872 g_assert_not_reached(); 873 return 0; 874 } 875 876 static inline bool 877 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 878 { 879 return core->mac[r->dlen] > 0; 880 } 881 882 static inline uint32_t 883 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 884 { 885 return core->mac[r->dlen]; 886 } 887 888 typedef struct E1000E_TxRing_st { 889 const E1000E_RingInfo *i; 890 struct e1000e_tx *tx; 891 } E1000E_TxRing; 892 893 static inline int 894 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 895 { 896 return (reg_idx - base_reg_idx) / (0x100 >> 2); 897 } 898 899 static inline void 900 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 901 { 902 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 903 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 904 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 905 }; 906 907 assert(idx < ARRAY_SIZE(i)); 908 909 txr->i = &i[idx]; 910 txr->tx = &core->tx[idx]; 911 } 912 913 typedef struct E1000E_RxRing_st { 914 const E1000E_RingInfo *i; 915 } E1000E_RxRing; 916 917 static inline void 918 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 919 { 920 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 921 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 922 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 923 }; 924 925 assert(idx < ARRAY_SIZE(i)); 926 927 rxr->i = &i[idx]; 928 } 929 930 static void 931 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 932 { 933 dma_addr_t base; 934 struct e1000_tx_desc desc; 935 bool ide = false; 936 const E1000E_RingInfo *txi = txr->i; 937 uint32_t cause = E1000_ICS_TXQE; 938 939 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 940 trace_e1000e_tx_disabled(); 941 return; 942 } 943 944 while (!e1000e_ring_empty(core, txi)) { 945 base = e1000e_ring_head_descr(core, txi); 946 947 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 948 949 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 950 desc.lower.data, desc.upper.data); 951 952 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 953 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 954 955 e1000e_ring_advance(core, txi, 1); 956 } 957 958 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 959 e1000e_set_interrupt_cause(core, cause); 960 } 961 } 962 963 static bool 964 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 965 size_t total_size) 966 { 967 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 968 969 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 970 core->rx_desc_buf_size); 971 972 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 973 core->rx_desc_buf_size; 974 } 975 976 void 977 e1000e_start_recv(E1000ECore *core) 978 { 979 int i; 980 981 trace_e1000e_rx_start_recv(); 982 983 for (i = 0; i <= core->max_queue_num; i++) { 984 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 985 } 986 } 987 988 bool 989 e1000e_can_receive(E1000ECore *core) 990 { 991 int i; 992 993 if (!e1000x_rx_ready(core->owner, core->mac)) { 994 return false; 995 } 996 997 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 998 E1000E_RxRing rxr; 999 1000 e1000e_rx_ring_init(core, &rxr, i); 1001 if (e1000e_ring_enabled(core, rxr.i) && 1002 e1000e_has_rxbufs(core, rxr.i, 1)) { 1003 trace_e1000e_rx_can_recv(); 1004 return true; 1005 } 1006 } 1007 1008 trace_e1000e_rx_can_recv_rings_full(); 1009 return false; 1010 } 1011 1012 ssize_t 1013 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 1014 { 1015 const struct iovec iov = { 1016 .iov_base = (uint8_t *)buf, 1017 .iov_len = size 1018 }; 1019 1020 return e1000e_receive_iov(core, &iov, 1); 1021 } 1022 1023 static inline bool 1024 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1025 { 1026 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1027 } 1028 1029 static inline bool 1030 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1031 { 1032 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1033 } 1034 1035 static bool 1036 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size) 1037 { 1038 uint32_t rctl = core->mac[RCTL]; 1039 1040 if (e1000x_is_vlan_packet(buf, core->mac[VET]) && 1041 e1000x_vlan_rx_filter_enabled(core->mac)) { 1042 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(buf)->h_tci); 1043 uint32_t vfta = 1044 ldl_le_p((uint32_t *)(core->mac + VFTA) + 1045 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK)); 1046 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) { 1047 trace_e1000e_rx_flt_vlan_mismatch(vid); 1048 return false; 1049 } else { 1050 trace_e1000e_rx_flt_vlan_match(vid); 1051 } 1052 } 1053 1054 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1055 case ETH_PKT_UCAST: 1056 if (rctl & E1000_RCTL_UPE) { 1057 return true; /* promiscuous ucast */ 1058 } 1059 break; 1060 1061 case ETH_PKT_BCAST: 1062 if (rctl & E1000_RCTL_BAM) { 1063 return true; /* broadcast enabled */ 1064 } 1065 break; 1066 1067 case ETH_PKT_MCAST: 1068 if (rctl & E1000_RCTL_MPE) { 1069 return true; /* promiscuous mcast */ 1070 } 1071 break; 1072 1073 default: 1074 g_assert_not_reached(); 1075 } 1076 1077 return e1000x_rx_group_filter(core->mac, buf); 1078 } 1079 1080 static inline void 1081 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1082 hwaddr *buff_addr) 1083 { 1084 *buff_addr = le64_to_cpu(desc->buffer_addr); 1085 } 1086 1087 static inline void 1088 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1089 hwaddr *buff_addr) 1090 { 1091 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1092 } 1093 1094 static inline void 1095 e1000e_read_ps_rx_descr(E1000ECore *core, 1096 union e1000_rx_desc_packet_split *desc, 1097 hwaddr buff_addr[MAX_PS_BUFFERS]) 1098 { 1099 int i; 1100 1101 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1102 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1103 } 1104 1105 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1106 buff_addr[2], buff_addr[3]); 1107 } 1108 1109 static inline void 1110 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1111 hwaddr buff_addr[MAX_PS_BUFFERS]) 1112 { 1113 if (e1000e_rx_use_legacy_descriptor(core)) { 1114 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1115 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1116 } else { 1117 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1118 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1119 } else { 1120 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1121 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1122 } 1123 } 1124 } 1125 1126 static void 1127 e1000e_verify_csum_in_sw(E1000ECore *core, 1128 struct NetRxPkt *pkt, 1129 uint32_t *status_flags, 1130 bool istcp, bool isudp) 1131 { 1132 bool csum_valid; 1133 uint32_t csum_error; 1134 1135 if (e1000e_rx_l3_cso_enabled(core)) { 1136 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1137 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1138 } else { 1139 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1140 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1141 } 1142 } else { 1143 trace_e1000e_rx_metadata_l3_cso_disabled(); 1144 } 1145 1146 if (!e1000e_rx_l4_cso_enabled(core)) { 1147 trace_e1000e_rx_metadata_l4_cso_disabled(); 1148 return; 1149 } 1150 1151 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1152 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1153 return; 1154 } 1155 1156 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1157 1158 if (istcp) { 1159 *status_flags |= E1000_RXD_STAT_TCPCS | 1160 csum_error; 1161 } else if (isudp) { 1162 *status_flags |= E1000_RXD_STAT_TCPCS | 1163 E1000_RXD_STAT_UDPCS | 1164 csum_error; 1165 } 1166 } 1167 1168 static inline bool 1169 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1170 { 1171 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1172 return false; 1173 } 1174 1175 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1176 return !net_rx_pkt_has_tcp_data(rx_pkt); 1177 } 1178 1179 return true; 1180 } 1181 1182 static void 1183 e1000e_build_rx_metadata(E1000ECore *core, 1184 struct NetRxPkt *pkt, 1185 bool is_eop, 1186 const E1000E_RSSInfo *rss_info, 1187 uint32_t *rss, uint32_t *mrq, 1188 uint32_t *status_flags, 1189 uint16_t *ip_id, 1190 uint16_t *vlan_tag) 1191 { 1192 struct virtio_net_hdr *vhdr; 1193 bool isip4, isip6, istcp, isudp; 1194 uint32_t pkt_type; 1195 1196 *status_flags = E1000_RXD_STAT_DD; 1197 1198 /* No additional metadata needed for non-EOP descriptors */ 1199 if (!is_eop) { 1200 goto func_exit; 1201 } 1202 1203 *status_flags |= E1000_RXD_STAT_EOP; 1204 1205 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1206 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp); 1207 1208 /* VLAN state */ 1209 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1210 *status_flags |= E1000_RXD_STAT_VP; 1211 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1212 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1213 } 1214 1215 /* Packet parsing results */ 1216 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1217 if (rss_info->enabled) { 1218 *rss = cpu_to_le32(rss_info->hash); 1219 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1220 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1221 } 1222 } else if (isip4) { 1223 *status_flags |= E1000_RXD_STAT_IPIDV; 1224 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1225 trace_e1000e_rx_metadata_ip_id(*ip_id); 1226 } 1227 1228 if (istcp && e1000e_is_tcp_ack(core, pkt)) { 1229 *status_flags |= E1000_RXD_STAT_ACK; 1230 trace_e1000e_rx_metadata_ack(); 1231 } 1232 1233 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1234 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1235 pkt_type = E1000_RXD_PKT_MAC; 1236 } else if (istcp || isudp) { 1237 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1238 } else if (isip4 || isip6) { 1239 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1240 } else { 1241 pkt_type = E1000_RXD_PKT_MAC; 1242 } 1243 1244 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1245 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1246 1247 /* RX CSO information */ 1248 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1249 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1250 goto func_exit; 1251 } 1252 1253 vhdr = net_rx_pkt_get_vhdr(pkt); 1254 1255 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1256 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1257 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1258 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp); 1259 goto func_exit; 1260 } 1261 1262 if (e1000e_rx_l3_cso_enabled(core)) { 1263 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0; 1264 } else { 1265 trace_e1000e_rx_metadata_l3_cso_disabled(); 1266 } 1267 1268 if (e1000e_rx_l4_cso_enabled(core)) { 1269 if (istcp) { 1270 *status_flags |= E1000_RXD_STAT_TCPCS; 1271 } else if (isudp) { 1272 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1273 } 1274 } else { 1275 trace_e1000e_rx_metadata_l4_cso_disabled(); 1276 } 1277 1278 trace_e1000e_rx_metadata_status_flags(*status_flags); 1279 1280 func_exit: 1281 *status_flags = cpu_to_le32(*status_flags); 1282 } 1283 1284 static inline void 1285 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1286 struct NetRxPkt *pkt, 1287 const E1000E_RSSInfo *rss_info, 1288 uint16_t length) 1289 { 1290 uint32_t status_flags, rss, mrq; 1291 uint16_t ip_id; 1292 1293 assert(!rss_info->enabled); 1294 1295 desc->length = cpu_to_le16(length); 1296 desc->csum = 0; 1297 1298 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1299 rss_info, 1300 &rss, &mrq, 1301 &status_flags, &ip_id, 1302 &desc->special); 1303 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1304 desc->status = (uint8_t) le32_to_cpu(status_flags); 1305 } 1306 1307 static inline void 1308 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1309 struct NetRxPkt *pkt, 1310 const E1000E_RSSInfo *rss_info, 1311 uint16_t length) 1312 { 1313 memset(&desc->wb, 0, sizeof(desc->wb)); 1314 1315 desc->wb.upper.length = cpu_to_le16(length); 1316 1317 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1318 rss_info, 1319 &desc->wb.lower.hi_dword.rss, 1320 &desc->wb.lower.mrq, 1321 &desc->wb.upper.status_error, 1322 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1323 &desc->wb.upper.vlan); 1324 } 1325 1326 static inline void 1327 e1000e_write_ps_rx_descr(E1000ECore *core, 1328 union e1000_rx_desc_packet_split *desc, 1329 struct NetRxPkt *pkt, 1330 const E1000E_RSSInfo *rss_info, 1331 size_t ps_hdr_len, 1332 uint16_t(*written)[MAX_PS_BUFFERS]) 1333 { 1334 int i; 1335 1336 memset(&desc->wb, 0, sizeof(desc->wb)); 1337 1338 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1339 1340 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1341 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1342 } 1343 1344 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1345 rss_info, 1346 &desc->wb.lower.hi_dword.rss, 1347 &desc->wb.lower.mrq, 1348 &desc->wb.middle.status_error, 1349 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1350 &desc->wb.middle.vlan); 1351 1352 desc->wb.upper.header_status = 1353 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1354 1355 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1356 (*written)[2], (*written)[3]); 1357 } 1358 1359 static inline void 1360 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1361 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1362 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1363 { 1364 if (e1000e_rx_use_legacy_descriptor(core)) { 1365 assert(ps_hdr_len == 0); 1366 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1367 (*written)[0]); 1368 } else { 1369 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1370 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1371 ps_hdr_len, written); 1372 } else { 1373 assert(ps_hdr_len == 0); 1374 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1375 (*written)[0]); 1376 } 1377 } 1378 } 1379 1380 static inline void 1381 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1382 union e1000_rx_desc_union *desc, dma_addr_t len) 1383 { 1384 PCIDevice *dev = core->owner; 1385 1386 if (e1000e_rx_use_legacy_descriptor(core)) { 1387 struct e1000_rx_desc *d = &desc->legacy; 1388 size_t offset = offsetof(struct e1000_rx_desc, status); 1389 uint8_t status = d->status; 1390 1391 d->status &= ~E1000_RXD_STAT_DD; 1392 pci_dma_write(dev, addr, desc, len); 1393 1394 if (status & E1000_RXD_STAT_DD) { 1395 d->status = status; 1396 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1397 } 1398 } else { 1399 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1400 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1401 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1402 wb.middle.status_error); 1403 uint32_t status = d->wb.middle.status_error; 1404 1405 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1406 pci_dma_write(dev, addr, desc, len); 1407 1408 if (status & E1000_RXD_STAT_DD) { 1409 d->wb.middle.status_error = status; 1410 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1411 } 1412 } else { 1413 union e1000_rx_desc_extended *d = &desc->extended; 1414 size_t offset = offsetof(union e1000_rx_desc_extended, 1415 wb.upper.status_error); 1416 uint32_t status = d->wb.upper.status_error; 1417 1418 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1419 pci_dma_write(dev, addr, desc, len); 1420 1421 if (status & E1000_RXD_STAT_DD) { 1422 d->wb.upper.status_error = status; 1423 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1424 } 1425 } 1426 } 1427 } 1428 1429 typedef struct e1000e_ba_state_st { 1430 uint16_t written[MAX_PS_BUFFERS]; 1431 uint8_t cur_idx; 1432 } e1000e_ba_state; 1433 1434 static inline void 1435 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1436 hwaddr ba[MAX_PS_BUFFERS], 1437 e1000e_ba_state *bastate, 1438 const char *data, 1439 dma_addr_t data_len) 1440 { 1441 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1442 1443 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1444 bastate->written[0] += data_len; 1445 1446 bastate->cur_idx = 1; 1447 } 1448 1449 static void 1450 e1000e_write_to_rx_buffers(E1000ECore *core, 1451 hwaddr ba[MAX_PS_BUFFERS], 1452 e1000e_ba_state *bastate, 1453 const char *data, 1454 dma_addr_t data_len) 1455 { 1456 while (data_len > 0) { 1457 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1458 uint32_t cur_buf_bytes_left = cur_buf_len - 1459 bastate->written[bastate->cur_idx]; 1460 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1461 1462 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1463 ba[bastate->cur_idx], 1464 bastate->written[bastate->cur_idx], 1465 data, 1466 bytes_to_write); 1467 1468 pci_dma_write(core->owner, 1469 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1470 data, bytes_to_write); 1471 1472 bastate->written[bastate->cur_idx] += bytes_to_write; 1473 data += bytes_to_write; 1474 data_len -= bytes_to_write; 1475 1476 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1477 bastate->cur_idx++; 1478 } 1479 1480 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1481 } 1482 } 1483 1484 static void 1485 e1000e_update_rx_stats(E1000ECore *core, 1486 size_t data_size, 1487 size_t data_fcs_size) 1488 { 1489 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1490 1491 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1492 case ETH_PKT_BCAST: 1493 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1494 break; 1495 1496 case ETH_PKT_MCAST: 1497 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1498 break; 1499 1500 default: 1501 break; 1502 } 1503 } 1504 1505 static inline bool 1506 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1507 { 1508 return e1000e_ring_free_descr_num(core, rxi) == 1509 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1510 } 1511 1512 static bool 1513 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1514 { 1515 bool isip4, isip6, isudp, istcp; 1516 bool fragment; 1517 1518 if (!e1000e_rx_use_ps_descriptor(core)) { 1519 return false; 1520 } 1521 1522 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1523 1524 if (isip4) { 1525 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1526 } else if (isip6) { 1527 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1528 } else { 1529 return false; 1530 } 1531 1532 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1533 return false; 1534 } 1535 1536 if (!fragment && (isudp || istcp)) { 1537 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1538 } else { 1539 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1540 } 1541 1542 if ((*hdr_len > core->rxbuf_sizes[0]) || 1543 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1544 return false; 1545 } 1546 1547 return true; 1548 } 1549 1550 static void 1551 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1552 const E1000E_RxRing *rxr, 1553 const E1000E_RSSInfo *rss_info) 1554 { 1555 PCIDevice *d = core->owner; 1556 dma_addr_t base; 1557 union e1000_rx_desc_union desc; 1558 size_t desc_size; 1559 size_t desc_offset = 0; 1560 size_t iov_ofs = 0; 1561 1562 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1563 size_t size = net_rx_pkt_get_total_len(pkt); 1564 size_t total_size = size + e1000x_fcs_len(core->mac); 1565 const E1000E_RingInfo *rxi; 1566 size_t ps_hdr_len = 0; 1567 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1568 bool is_first = true; 1569 1570 rxi = rxr->i; 1571 1572 do { 1573 hwaddr ba[MAX_PS_BUFFERS]; 1574 e1000e_ba_state bastate = { { 0 } }; 1575 bool is_last = false; 1576 1577 desc_size = total_size - desc_offset; 1578 1579 if (desc_size > core->rx_desc_buf_size) { 1580 desc_size = core->rx_desc_buf_size; 1581 } 1582 1583 if (e1000e_ring_empty(core, rxi)) { 1584 return; 1585 } 1586 1587 base = e1000e_ring_head_descr(core, rxi); 1588 1589 pci_dma_read(d, base, &desc, core->rx_desc_len); 1590 1591 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1592 1593 e1000e_read_rx_descr(core, &desc, ba); 1594 1595 if (ba[0]) { 1596 if (desc_offset < size) { 1597 static const uint32_t fcs_pad; 1598 size_t iov_copy; 1599 size_t copy_size = size - desc_offset; 1600 if (copy_size > core->rx_desc_buf_size) { 1601 copy_size = core->rx_desc_buf_size; 1602 } 1603 1604 /* For PS mode copy the packet header first */ 1605 if (do_ps) { 1606 if (is_first) { 1607 size_t ps_hdr_copied = 0; 1608 do { 1609 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1610 iov->iov_len - iov_ofs); 1611 1612 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1613 iov->iov_base, iov_copy); 1614 1615 copy_size -= iov_copy; 1616 ps_hdr_copied += iov_copy; 1617 1618 iov_ofs += iov_copy; 1619 if (iov_ofs == iov->iov_len) { 1620 iov++; 1621 iov_ofs = 0; 1622 } 1623 } while (ps_hdr_copied < ps_hdr_len); 1624 1625 is_first = false; 1626 } else { 1627 /* Leave buffer 0 of each descriptor except first */ 1628 /* empty as per spec 7.1.5.1 */ 1629 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1630 NULL, 0); 1631 } 1632 } 1633 1634 /* Copy packet payload */ 1635 while (copy_size) { 1636 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1637 1638 e1000e_write_to_rx_buffers(core, ba, &bastate, 1639 iov->iov_base + iov_ofs, iov_copy); 1640 1641 copy_size -= iov_copy; 1642 iov_ofs += iov_copy; 1643 if (iov_ofs == iov->iov_len) { 1644 iov++; 1645 iov_ofs = 0; 1646 } 1647 } 1648 1649 if (desc_offset + desc_size >= total_size) { 1650 /* Simulate FCS checksum presence in the last descriptor */ 1651 e1000e_write_to_rx_buffers(core, ba, &bastate, 1652 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1653 } 1654 } 1655 } else { /* as per intel docs; skip descriptors with null buf addr */ 1656 trace_e1000e_rx_null_descriptor(); 1657 } 1658 desc_offset += desc_size; 1659 if (desc_offset >= total_size) { 1660 is_last = true; 1661 } 1662 1663 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1664 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1665 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1666 1667 e1000e_ring_advance(core, rxi, 1668 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1669 1670 } while (desc_offset < total_size); 1671 1672 e1000e_update_rx_stats(core, size, total_size); 1673 } 1674 1675 static inline void 1676 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1677 { 1678 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1679 1680 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1681 net_rx_pkt_fix_l4_csum(pkt); 1682 } 1683 } 1684 1685 ssize_t 1686 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1687 { 1688 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1689 } 1690 1691 static ssize_t 1692 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1693 bool has_vnet) 1694 { 1695 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4); 1696 1697 uint32_t n = 0; 1698 uint8_t min_buf[ETH_ZLEN]; 1699 struct iovec min_iov; 1700 uint8_t *filter_buf; 1701 size_t size, orig_size; 1702 size_t iov_ofs = 0; 1703 E1000E_RxRing rxr; 1704 E1000E_RSSInfo rss_info; 1705 size_t total_size; 1706 ssize_t retval; 1707 bool rdmts_hit; 1708 1709 trace_e1000e_rx_receive_iov(iovcnt); 1710 1711 if (!e1000x_hw_rx_enabled(core->mac)) { 1712 return -1; 1713 } 1714 1715 /* Pull virtio header in */ 1716 if (has_vnet) { 1717 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1718 iov_ofs = sizeof(struct virtio_net_hdr); 1719 } else { 1720 net_rx_pkt_unset_vhdr(core->rx_pkt); 1721 } 1722 1723 filter_buf = iov->iov_base + iov_ofs; 1724 orig_size = iov_size(iov, iovcnt); 1725 size = orig_size - iov_ofs; 1726 1727 /* Pad to minimum Ethernet frame length */ 1728 if (size < sizeof(min_buf)) { 1729 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1730 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1731 e1000x_inc_reg_if_not_full(core->mac, RUC); 1732 min_iov.iov_base = filter_buf = min_buf; 1733 min_iov.iov_len = size = sizeof(min_buf); 1734 iovcnt = 1; 1735 iov = &min_iov; 1736 iov_ofs = 0; 1737 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1738 /* This is very unlikely, but may happen. */ 1739 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1740 filter_buf = min_buf; 1741 } 1742 1743 /* Discard oversized packets if !LPE and !SBP. */ 1744 if (e1000x_is_oversized(core->mac, size)) { 1745 return orig_size; 1746 } 1747 1748 net_rx_pkt_set_packet_type(core->rx_pkt, 1749 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf))); 1750 1751 if (!e1000e_receive_filter(core, filter_buf, size)) { 1752 trace_e1000e_rx_flt_dropped(); 1753 return orig_size; 1754 } 1755 1756 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1757 e1000x_vlan_enabled(core->mac), core->mac[VET]); 1758 1759 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1760 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1761 1762 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1763 e1000x_fcs_len(core->mac); 1764 1765 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1766 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1767 1768 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1769 1770 retval = orig_size; 1771 1772 /* Perform small receive detection (RSRPD) */ 1773 if (total_size < core->mac[RSRPD]) { 1774 n |= E1000_ICS_SRPD; 1775 } 1776 1777 /* Perform ACK receive detection */ 1778 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1779 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1780 n |= E1000_ICS_ACK; 1781 } 1782 1783 /* Check if receive descriptor minimum threshold hit */ 1784 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1785 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1786 1787 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1788 } else { 1789 n |= E1000_ICS_RXO; 1790 retval = 0; 1791 1792 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1793 } 1794 1795 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1796 trace_e1000e_rx_interrupt_set(n); 1797 e1000e_set_interrupt_cause(core, n); 1798 } else { 1799 trace_e1000e_rx_interrupt_delayed(n); 1800 } 1801 1802 return retval; 1803 } 1804 1805 static inline bool 1806 e1000e_have_autoneg(E1000ECore *core) 1807 { 1808 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1809 } 1810 1811 static void e1000e_update_flowctl_status(E1000ECore *core) 1812 { 1813 if (e1000e_have_autoneg(core) && 1814 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1815 trace_e1000e_link_autoneg_flowctl(true); 1816 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1817 } else { 1818 trace_e1000e_link_autoneg_flowctl(false); 1819 } 1820 } 1821 1822 static inline void 1823 e1000e_link_down(E1000ECore *core) 1824 { 1825 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1826 e1000e_update_flowctl_status(core); 1827 } 1828 1829 static inline void 1830 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1831 { 1832 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1833 core->phy[0][MII_BMCR] = val & ~(0x3f | 1834 MII_BMCR_RESET | 1835 MII_BMCR_ANRESTART); 1836 1837 if ((val & MII_BMCR_ANRESTART) && 1838 e1000e_have_autoneg(core)) { 1839 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1840 } 1841 } 1842 1843 static void 1844 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1845 { 1846 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1847 1848 if (val & BIT(10)) { 1849 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1850 } 1851 } 1852 1853 static void 1854 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1855 { 1856 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1857 } 1858 1859 void 1860 e1000e_core_set_link_status(E1000ECore *core) 1861 { 1862 NetClientState *nc = qemu_get_queue(core->owner_nic); 1863 uint32_t old_status = core->mac[STATUS]; 1864 1865 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1866 1867 if (nc->link_down) { 1868 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1869 } else { 1870 if (e1000e_have_autoneg(core) && 1871 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1872 e1000x_restart_autoneg(core->mac, core->phy[0], 1873 core->autoneg_timer); 1874 } else { 1875 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1876 e1000e_start_recv(core); 1877 } 1878 } 1879 1880 if (core->mac[STATUS] != old_status) { 1881 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1882 } 1883 } 1884 1885 static void 1886 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1887 { 1888 trace_e1000e_core_ctrl_write(index, val); 1889 1890 /* RST is self clearing */ 1891 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1892 core->mac[CTRL_DUP] = core->mac[CTRL]; 1893 1894 trace_e1000e_link_set_params( 1895 !!(val & E1000_CTRL_ASDE), 1896 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1897 !!(val & E1000_CTRL_FRCSPD), 1898 !!(val & E1000_CTRL_FRCDPX), 1899 !!(val & E1000_CTRL_RFCE), 1900 !!(val & E1000_CTRL_TFCE)); 1901 1902 if (val & E1000_CTRL_RST) { 1903 trace_e1000e_core_ctrl_sw_reset(); 1904 e1000e_reset(core, true); 1905 } 1906 1907 if (val & E1000_CTRL_PHY_RST) { 1908 trace_e1000e_core_ctrl_phy_reset(); 1909 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1910 } 1911 } 1912 1913 static void 1914 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1915 { 1916 trace_e1000e_rx_set_rfctl(val); 1917 1918 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1919 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1920 } 1921 1922 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1923 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1924 } 1925 1926 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1927 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1928 } 1929 1930 core->mac[RFCTL] = val; 1931 } 1932 1933 static void 1934 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1935 { 1936 int i; 1937 core->rx_desc_buf_size = 0; 1938 1939 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1940 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1941 } 1942 } 1943 1944 static void 1945 e1000e_parse_rxbufsize(E1000ECore *core) 1946 { 1947 uint32_t rctl = core->mac[RCTL]; 1948 1949 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1950 1951 if (rctl & E1000_RCTL_DTYP_MASK) { 1952 uint32_t bsize; 1953 1954 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1955 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1956 1957 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1958 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1959 1960 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1961 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1962 1963 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1964 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1965 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1966 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1967 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1968 } else { 1969 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1970 } 1971 1972 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1973 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1974 1975 e1000e_calc_per_desc_buf_size(core); 1976 } 1977 1978 static void 1979 e1000e_calc_rxdesclen(E1000ECore *core) 1980 { 1981 if (e1000e_rx_use_legacy_descriptor(core)) { 1982 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1983 } else { 1984 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1985 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1986 } else { 1987 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1988 } 1989 } 1990 trace_e1000e_rx_desc_len(core->rx_desc_len); 1991 } 1992 1993 static void 1994 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1995 { 1996 core->mac[RCTL] = val; 1997 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1998 1999 if (val & E1000_RCTL_EN) { 2000 e1000e_parse_rxbufsize(core); 2001 e1000e_calc_rxdesclen(core); 2002 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 2003 E1000_RING_DESC_LEN_SHIFT; 2004 2005 e1000e_start_recv(core); 2006 } 2007 } 2008 2009 static 2010 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 2011 (E1000ECore *, int, uint16_t) = { 2012 [0] = { 2013 [MII_BMCR] = e1000e_set_phy_ctrl, 2014 [PHY_PAGE] = e1000e_set_phy_page, 2015 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 2016 } 2017 }; 2018 2019 static inline void 2020 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 2021 { 2022 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 2023 core->mac[IMS] &= ~bits; 2024 } 2025 2026 static inline bool 2027 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 2028 { 2029 if (timer->running) { 2030 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 2031 2032 return true; 2033 } 2034 2035 if (timer->core->mac[timer->delay_reg] != 0) { 2036 e1000e_intrmgr_rearm_timer(timer); 2037 } 2038 2039 return false; 2040 } 2041 2042 static inline bool 2043 e1000e_itr_should_postpone(E1000ECore *core) 2044 { 2045 return e1000e_postpone_interrupt(&core->itr); 2046 } 2047 2048 static inline bool 2049 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 2050 { 2051 return e1000e_postpone_interrupt(&core->eitr[idx]); 2052 } 2053 2054 static void 2055 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2056 { 2057 uint32_t effective_eiac; 2058 2059 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2060 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2061 if (vec < E1000E_MSIX_VEC_NUM) { 2062 if (!e1000e_eitr_should_postpone(core, vec)) { 2063 trace_e1000e_irq_msix_notify_vec(vec); 2064 msix_notify(core->owner, vec); 2065 } 2066 } else { 2067 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2068 } 2069 } else { 2070 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2071 } 2072 2073 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2074 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2075 core->mac[IAM] &= ~cause; 2076 } 2077 2078 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2079 2080 effective_eiac = core->mac[EIAC] & cause; 2081 2082 core->mac[ICR] &= ~effective_eiac; 2083 core->msi_causes_pending &= ~effective_eiac; 2084 2085 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2086 core->mac[IMS] &= ~effective_eiac; 2087 } 2088 } 2089 2090 static void 2091 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2092 { 2093 if (causes & E1000_ICR_RXQ0) { 2094 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2095 E1000_IVAR_RXQ0(core->mac[IVAR])); 2096 } 2097 2098 if (causes & E1000_ICR_RXQ1) { 2099 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2100 E1000_IVAR_RXQ1(core->mac[IVAR])); 2101 } 2102 2103 if (causes & E1000_ICR_TXQ0) { 2104 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2105 E1000_IVAR_TXQ0(core->mac[IVAR])); 2106 } 2107 2108 if (causes & E1000_ICR_TXQ1) { 2109 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2110 E1000_IVAR_TXQ1(core->mac[IVAR])); 2111 } 2112 2113 if (causes & E1000_ICR_OTHER) { 2114 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2115 E1000_IVAR_OTHER(core->mac[IVAR])); 2116 } 2117 } 2118 2119 static void 2120 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2121 { 2122 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2123 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2124 if (vec < E1000E_MSIX_VEC_NUM) { 2125 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2126 msix_clr_pending(core->owner, vec); 2127 } else { 2128 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2129 } 2130 } else { 2131 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2132 } 2133 } 2134 2135 static void 2136 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2137 { 2138 if (causes & E1000_ICR_RXQ0) { 2139 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2140 E1000_IVAR_RXQ0(core->mac[IVAR])); 2141 } 2142 2143 if (causes & E1000_ICR_RXQ1) { 2144 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2145 E1000_IVAR_RXQ1(core->mac[IVAR])); 2146 } 2147 2148 if (causes & E1000_ICR_TXQ0) { 2149 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2150 E1000_IVAR_TXQ0(core->mac[IVAR])); 2151 } 2152 2153 if (causes & E1000_ICR_TXQ1) { 2154 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2155 E1000_IVAR_TXQ1(core->mac[IVAR])); 2156 } 2157 2158 if (causes & E1000_ICR_OTHER) { 2159 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2160 E1000_IVAR_OTHER(core->mac[IVAR])); 2161 } 2162 } 2163 2164 static inline void 2165 e1000e_fix_icr_asserted(E1000ECore *core) 2166 { 2167 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2168 if (core->mac[ICR]) { 2169 core->mac[ICR] |= E1000_ICR_ASSERTED; 2170 } 2171 2172 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2173 } 2174 2175 static void 2176 e1000e_send_msi(E1000ECore *core, bool msix) 2177 { 2178 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2179 2180 core->msi_causes_pending &= causes; 2181 causes ^= core->msi_causes_pending; 2182 if (causes == 0) { 2183 return; 2184 } 2185 core->msi_causes_pending |= causes; 2186 2187 if (msix) { 2188 e1000e_msix_notify(core, causes); 2189 } else { 2190 if (!e1000e_itr_should_postpone(core)) { 2191 trace_e1000e_irq_msi_notify(causes); 2192 msi_notify(core->owner, 0); 2193 } 2194 } 2195 } 2196 2197 static void 2198 e1000e_update_interrupt_state(E1000ECore *core) 2199 { 2200 bool interrupts_pending; 2201 bool is_msix = msix_enabled(core->owner); 2202 2203 /* Set ICR[OTHER] for MSI-X */ 2204 if (is_msix) { 2205 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2206 core->mac[ICR] |= E1000_ICR_OTHER; 2207 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2208 } 2209 } 2210 2211 e1000e_fix_icr_asserted(core); 2212 2213 /* 2214 * Make sure ICR and ICS registers have the same value. 2215 * The spec says that the ICS register is write-only. However in practice, 2216 * on real hardware ICS is readable, and for reads it has the same value as 2217 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2218 * 2219 * The VxWorks PRO/1000 driver uses this behaviour. 2220 */ 2221 core->mac[ICS] = core->mac[ICR]; 2222 2223 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2224 if (!interrupts_pending) { 2225 core->msi_causes_pending = 0; 2226 } 2227 2228 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2229 core->mac[ICR], core->mac[IMS]); 2230 2231 if (is_msix || msi_enabled(core->owner)) { 2232 if (interrupts_pending) { 2233 e1000e_send_msi(core, is_msix); 2234 } 2235 } else { 2236 if (interrupts_pending) { 2237 if (!e1000e_itr_should_postpone(core)) { 2238 e1000e_raise_legacy_irq(core); 2239 } 2240 } else { 2241 e1000e_lower_legacy_irq(core); 2242 } 2243 } 2244 } 2245 2246 static void 2247 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2248 { 2249 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2250 2251 val |= e1000e_intmgr_collect_delayed_causes(core); 2252 core->mac[ICR] |= val; 2253 2254 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2255 2256 e1000e_update_interrupt_state(core); 2257 } 2258 2259 static inline void 2260 e1000e_autoneg_timer(void *opaque) 2261 { 2262 E1000ECore *core = opaque; 2263 if (!qemu_get_queue(core->owner_nic)->link_down) { 2264 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2265 e1000e_start_recv(core); 2266 2267 e1000e_update_flowctl_status(core); 2268 /* signal link status change to the guest */ 2269 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2270 } 2271 } 2272 2273 static inline uint16_t 2274 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2275 { 2276 uint16_t index = (addr & 0x1ffff) >> 2; 2277 return index + (mac_reg_access[index] & 0xfffe); 2278 } 2279 2280 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2281 [0] = { 2282 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2283 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2284 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2285 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2286 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2287 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2288 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2289 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2290 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2291 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2292 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2293 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2294 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2295 2296 [PHY_COPPER_CTRL1] = PHY_RW, 2297 [PHY_COPPER_STAT1] = PHY_R, 2298 [PHY_COPPER_CTRL3] = PHY_RW, 2299 [PHY_RX_ERR_CNTR] = PHY_R, 2300 [PHY_OEM_BITS] = PHY_RW, 2301 [PHY_BIAS_1] = PHY_RW, 2302 [PHY_BIAS_2] = PHY_RW, 2303 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2304 [PHY_COPPER_STAT2] = PHY_R, 2305 [PHY_COPPER_CTRL2] = PHY_RW 2306 }, 2307 [2] = { 2308 [PHY_MAC_CTRL1] = PHY_RW, 2309 [PHY_MAC_INT_ENABLE] = PHY_RW, 2310 [PHY_MAC_STAT] = PHY_R, 2311 [PHY_MAC_CTRL2] = PHY_RW 2312 }, 2313 [3] = { 2314 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2315 [PHY_LED_03_POL_CTRL] = PHY_RW, 2316 [PHY_LED_TIMER_CTRL] = PHY_RW, 2317 [PHY_LED_45_CTRL] = PHY_RW 2318 }, 2319 [5] = { 2320 [PHY_1000T_SKEW] = PHY_R, 2321 [PHY_1000T_SWAP] = PHY_R 2322 }, 2323 [6] = { 2324 [PHY_CRC_COUNTERS] = PHY_R 2325 } 2326 }; 2327 2328 static bool 2329 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2330 char cap, uint8_t *page) 2331 { 2332 *page = 2333 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2334 : core->phy[0][PHY_PAGE]; 2335 2336 if (*page >= E1000E_PHY_PAGES) { 2337 return false; 2338 } 2339 2340 return e1000e_phy_regcap[*page][addr] & cap; 2341 } 2342 2343 static void 2344 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2345 uint32_t addr, uint16_t data) 2346 { 2347 assert(page < E1000E_PHY_PAGES); 2348 assert(addr < E1000E_PHY_PAGE_SIZE); 2349 2350 if (e1000e_phyreg_writeops[page][addr]) { 2351 e1000e_phyreg_writeops[page][addr](core, addr, data); 2352 } else { 2353 core->phy[page][addr] = data; 2354 } 2355 } 2356 2357 static void 2358 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2359 { 2360 uint32_t data = val & E1000_MDIC_DATA_MASK; 2361 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2362 uint8_t page; 2363 2364 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2365 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2366 } else if (val & E1000_MDIC_OP_READ) { 2367 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2368 trace_e1000e_core_mdic_read_unhandled(page, addr); 2369 val |= E1000_MDIC_ERROR; 2370 } else { 2371 val = (val ^ data) | core->phy[page][addr]; 2372 trace_e1000e_core_mdic_read(page, addr, val); 2373 } 2374 } else if (val & E1000_MDIC_OP_WRITE) { 2375 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2376 trace_e1000e_core_mdic_write_unhandled(page, addr); 2377 val |= E1000_MDIC_ERROR; 2378 } else { 2379 trace_e1000e_core_mdic_write(page, addr, data); 2380 e1000e_phy_reg_write(core, page, addr, data); 2381 } 2382 } 2383 core->mac[MDIC] = val | E1000_MDIC_READY; 2384 2385 if (val & E1000_MDIC_INT_EN) { 2386 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2387 } 2388 } 2389 2390 static void 2391 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2392 { 2393 core->mac[index] = val & 0xffff; 2394 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2395 e1000e_start_recv(core); 2396 } 2397 2398 static void 2399 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2400 { 2401 if ((val & E1000_STATUS_PHYRA) == 0) { 2402 core->mac[index] &= ~E1000_STATUS_PHYRA; 2403 } 2404 } 2405 2406 static void 2407 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2408 { 2409 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2410 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2411 2412 /* Zero self-clearing bits */ 2413 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2414 core->mac[CTRL_EXT] = val; 2415 } 2416 2417 static void 2418 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2419 { 2420 int i; 2421 2422 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2423 2424 if (!msix_enabled(core->owner)) { 2425 return; 2426 } 2427 2428 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2429 if (core->mac[PBACLR] & BIT(i)) { 2430 msix_clr_pending(core->owner, i); 2431 } 2432 } 2433 } 2434 2435 static void 2436 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2437 { 2438 core->mac[FCRTH] = val & 0xFFF8; 2439 } 2440 2441 static void 2442 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2443 { 2444 core->mac[FCRTL] = val & 0x8000FFF8; 2445 } 2446 2447 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2448 static void \ 2449 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2450 { \ 2451 core->mac[index] = val & (BIT(num) - 1); \ 2452 } 2453 2454 E1000E_LOW_BITS_SET_FUNC(4) 2455 E1000E_LOW_BITS_SET_FUNC(6) 2456 E1000E_LOW_BITS_SET_FUNC(11) 2457 E1000E_LOW_BITS_SET_FUNC(12) 2458 E1000E_LOW_BITS_SET_FUNC(13) 2459 E1000E_LOW_BITS_SET_FUNC(16) 2460 2461 static void 2462 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2463 { 2464 core->mac[VET] = val & 0xffff; 2465 trace_e1000e_vlan_vet(core->mac[VET]); 2466 } 2467 2468 static void 2469 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2470 { 2471 core->mac[index] = val & E1000_XDLEN_MASK; 2472 } 2473 2474 static void 2475 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2476 { 2477 core->mac[index] = val & E1000_XDBAL_MASK; 2478 } 2479 2480 static void 2481 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2482 { 2483 E1000E_TxRing txr; 2484 core->mac[index] = val; 2485 2486 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2487 e1000e_tx_ring_init(core, &txr, 0); 2488 e1000e_start_xmit(core, &txr); 2489 } 2490 2491 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2492 e1000e_tx_ring_init(core, &txr, 1); 2493 e1000e_start_xmit(core, &txr); 2494 } 2495 } 2496 2497 static void 2498 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2499 { 2500 E1000E_TxRing txr; 2501 int qidx = e1000e_mq_queue_idx(TDT, index); 2502 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2503 2504 core->mac[index] = val & 0xffff; 2505 2506 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2507 e1000e_tx_ring_init(core, &txr, qidx); 2508 e1000e_start_xmit(core, &txr); 2509 } 2510 } 2511 2512 static void 2513 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2514 { 2515 trace_e1000e_irq_write_ics(val); 2516 e1000e_set_interrupt_cause(core, val); 2517 } 2518 2519 static void 2520 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2521 { 2522 uint32_t icr = 0; 2523 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2524 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2525 trace_e1000e_irq_icr_process_iame(); 2526 e1000e_clear_ims_bits(core, core->mac[IAM]); 2527 } 2528 2529 icr = core->mac[ICR] & ~val; 2530 /* 2531 * Windows driver expects that the "receive overrun" bit and other 2532 * ones to be cleared when the "Other" bit (#24) is cleared. 2533 */ 2534 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr; 2535 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); 2536 core->mac[ICR] = icr; 2537 e1000e_update_interrupt_state(core); 2538 } 2539 2540 static void 2541 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2542 { 2543 trace_e1000e_irq_ims_clear_set_imc(val); 2544 e1000e_clear_ims_bits(core, val); 2545 e1000e_update_interrupt_state(core); 2546 } 2547 2548 static void 2549 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2550 { 2551 static const uint32_t ims_ext_mask = 2552 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2553 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2554 E1000_IMS_OTHER; 2555 2556 static const uint32_t ims_valid_mask = 2557 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2558 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2559 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2560 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2561 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2562 E1000_IMS_OTHER; 2563 2564 uint32_t valid_val = val & ims_valid_mask; 2565 2566 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2567 core->mac[IMS] |= valid_val; 2568 2569 if ((valid_val & ims_ext_mask) && 2570 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2571 msix_enabled(core->owner)) { 2572 e1000e_msix_clear(core, valid_val); 2573 } 2574 2575 if ((valid_val == ims_valid_mask) && 2576 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2577 trace_e1000e_irq_fire_all_timers(val); 2578 e1000e_intrmgr_fire_all_timers(core); 2579 } 2580 2581 e1000e_update_interrupt_state(core); 2582 } 2583 2584 static void 2585 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2586 { 2587 e1000e_set_16bit(core, index, val); 2588 2589 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2590 trace_e1000e_irq_rdtr_fpd_running(); 2591 e1000e_intrmgr_fire_delayed_interrupts(core); 2592 } else { 2593 trace_e1000e_irq_rdtr_fpd_not_running(); 2594 } 2595 } 2596 2597 static void 2598 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2599 { 2600 e1000e_set_16bit(core, index, val); 2601 2602 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2603 trace_e1000e_irq_tidv_fpd_running(); 2604 e1000e_intrmgr_fire_delayed_interrupts(core); 2605 } else { 2606 trace_e1000e_irq_tidv_fpd_not_running(); 2607 } 2608 } 2609 2610 static uint32_t 2611 e1000e_mac_readreg(E1000ECore *core, int index) 2612 { 2613 return core->mac[index]; 2614 } 2615 2616 static uint32_t 2617 e1000e_mac_ics_read(E1000ECore *core, int index) 2618 { 2619 trace_e1000e_irq_read_ics(core->mac[ICS]); 2620 return core->mac[ICS]; 2621 } 2622 2623 static uint32_t 2624 e1000e_mac_ims_read(E1000ECore *core, int index) 2625 { 2626 trace_e1000e_irq_read_ims(core->mac[IMS]); 2627 return core->mac[IMS]; 2628 } 2629 2630 static uint32_t 2631 e1000e_mac_swsm_read(E1000ECore *core, int index) 2632 { 2633 uint32_t val = core->mac[SWSM]; 2634 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2635 return val; 2636 } 2637 2638 static uint32_t 2639 e1000e_mac_itr_read(E1000ECore *core, int index) 2640 { 2641 return core->itr_guest_value; 2642 } 2643 2644 static uint32_t 2645 e1000e_mac_eitr_read(E1000ECore *core, int index) 2646 { 2647 return core->eitr_guest_value[index - EITR]; 2648 } 2649 2650 static uint32_t 2651 e1000e_mac_icr_read(E1000ECore *core, int index) 2652 { 2653 uint32_t ret = core->mac[ICR]; 2654 trace_e1000e_irq_icr_read_entry(ret); 2655 2656 if (core->mac[IMS] == 0) { 2657 trace_e1000e_irq_icr_clear_zero_ims(); 2658 core->mac[ICR] = 0; 2659 } 2660 2661 if (!msix_enabled(core->owner)) { 2662 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2663 core->mac[ICR] = 0; 2664 } 2665 2666 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2667 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2668 trace_e1000e_irq_icr_clear_iame(); 2669 core->mac[ICR] = 0; 2670 trace_e1000e_irq_icr_process_iame(); 2671 e1000e_clear_ims_bits(core, core->mac[IAM]); 2672 } 2673 2674 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2675 e1000e_update_interrupt_state(core); 2676 return ret; 2677 } 2678 2679 static uint32_t 2680 e1000e_mac_read_clr4(E1000ECore *core, int index) 2681 { 2682 uint32_t ret = core->mac[index]; 2683 2684 core->mac[index] = 0; 2685 return ret; 2686 } 2687 2688 static uint32_t 2689 e1000e_mac_read_clr8(E1000ECore *core, int index) 2690 { 2691 uint32_t ret = core->mac[index]; 2692 2693 core->mac[index] = 0; 2694 core->mac[index - 1] = 0; 2695 return ret; 2696 } 2697 2698 static uint32_t 2699 e1000e_get_ctrl(E1000ECore *core, int index) 2700 { 2701 uint32_t val = core->mac[CTRL]; 2702 2703 trace_e1000e_link_read_params( 2704 !!(val & E1000_CTRL_ASDE), 2705 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2706 !!(val & E1000_CTRL_FRCSPD), 2707 !!(val & E1000_CTRL_FRCDPX), 2708 !!(val & E1000_CTRL_RFCE), 2709 !!(val & E1000_CTRL_TFCE)); 2710 2711 return val; 2712 } 2713 2714 static uint32_t 2715 e1000e_get_status(E1000ECore *core, int index) 2716 { 2717 uint32_t res = core->mac[STATUS]; 2718 2719 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2720 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2721 } 2722 2723 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2724 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2725 } else { 2726 res |= E1000_STATUS_FD; 2727 } 2728 2729 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2730 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2731 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2732 case E1000_CTRL_SPD_10: 2733 res |= E1000_STATUS_SPEED_10; 2734 break; 2735 case E1000_CTRL_SPD_100: 2736 res |= E1000_STATUS_SPEED_100; 2737 break; 2738 case E1000_CTRL_SPD_1000: 2739 default: 2740 res |= E1000_STATUS_SPEED_1000; 2741 break; 2742 } 2743 } else { 2744 res |= E1000_STATUS_SPEED_1000; 2745 } 2746 2747 trace_e1000e_link_status( 2748 !!(res & E1000_STATUS_LU), 2749 !!(res & E1000_STATUS_FD), 2750 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2751 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2752 2753 return res; 2754 } 2755 2756 static uint32_t 2757 e1000e_get_tarc(E1000ECore *core, int index) 2758 { 2759 return core->mac[index] & ((BIT(11) - 1) | 2760 BIT(27) | 2761 BIT(28) | 2762 BIT(29) | 2763 BIT(30)); 2764 } 2765 2766 static void 2767 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2768 { 2769 core->mac[index] = val; 2770 } 2771 2772 static void 2773 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2774 { 2775 uint32_t macaddr[2]; 2776 2777 core->mac[index] = val; 2778 2779 macaddr[0] = cpu_to_le32(core->mac[RA]); 2780 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2781 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2782 (uint8_t *) macaddr); 2783 2784 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2785 } 2786 2787 static void 2788 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2789 { 2790 static const uint32_t ro_bits = E1000_EECD_PRES | 2791 E1000_EECD_AUTO_RD | 2792 E1000_EECD_SIZE_EX_MASK; 2793 2794 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2795 } 2796 2797 static void 2798 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2799 { 2800 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2801 uint32_t flags = 0; 2802 uint32_t data = 0; 2803 2804 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2805 data = core->eeprom[addr]; 2806 flags = E1000_EERW_DONE; 2807 } 2808 2809 core->mac[EERD] = flags | 2810 (addr << E1000_EERW_ADDR_SHIFT) | 2811 (data << E1000_EERW_DATA_SHIFT); 2812 } 2813 2814 static void 2815 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2816 { 2817 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2818 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2819 uint32_t flags = 0; 2820 2821 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2822 core->eeprom[addr] = data; 2823 flags = E1000_EERW_DONE; 2824 } 2825 2826 core->mac[EERD] = flags | 2827 (addr << E1000_EERW_ADDR_SHIFT) | 2828 (data << E1000_EERW_DATA_SHIFT); 2829 } 2830 2831 static void 2832 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2833 { 2834 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2835 } 2836 2837 static void 2838 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2839 { 2840 uint32_t interval = val & 0xffff; 2841 2842 trace_e1000e_irq_itr_set(val); 2843 2844 core->itr_guest_value = interval; 2845 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2846 } 2847 2848 static void 2849 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2850 { 2851 uint32_t interval = val & 0xffff; 2852 uint32_t eitr_num = index - EITR; 2853 2854 trace_e1000e_irq_eitr_set(eitr_num, val); 2855 2856 core->eitr_guest_value[eitr_num] = interval; 2857 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2858 } 2859 2860 static void 2861 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2862 { 2863 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2864 2865 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2866 qemu_log_mask(LOG_GUEST_ERROR, 2867 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2868 return; 2869 } 2870 2871 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2872 qemu_log_mask(LOG_GUEST_ERROR, 2873 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2874 return; 2875 } 2876 } 2877 2878 core->mac[PSRCTL] = val; 2879 } 2880 2881 static void 2882 e1000e_update_rx_offloads(E1000ECore *core) 2883 { 2884 int cso_state = e1000e_rx_l4_cso_enabled(core); 2885 2886 trace_e1000e_rx_set_cso(cso_state); 2887 2888 if (core->has_vnet) { 2889 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2890 cso_state, 0, 0, 0, 0); 2891 } 2892 } 2893 2894 static void 2895 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2896 { 2897 core->mac[RXCSUM] = val; 2898 e1000e_update_rx_offloads(core); 2899 } 2900 2901 static void 2902 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2903 { 2904 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2905 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2906 } 2907 2908 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2909 typedef uint32_t (*readops)(E1000ECore *, int); 2910 static const readops e1000e_macreg_readops[] = { 2911 e1000e_getreg(PBA), 2912 e1000e_getreg(WUFC), 2913 e1000e_getreg(MANC), 2914 e1000e_getreg(TOTL), 2915 e1000e_getreg(RDT0), 2916 e1000e_getreg(RDBAH0), 2917 e1000e_getreg(TDBAL1), 2918 e1000e_getreg(RDLEN0), 2919 e1000e_getreg(RDH1), 2920 e1000e_getreg(LATECOL), 2921 e1000e_getreg(SEQEC), 2922 e1000e_getreg(XONTXC), 2923 e1000e_getreg(AIT), 2924 e1000e_getreg(TDFH), 2925 e1000e_getreg(TDFT), 2926 e1000e_getreg(TDFHS), 2927 e1000e_getreg(TDFTS), 2928 e1000e_getreg(TDFPC), 2929 e1000e_getreg(WUS), 2930 e1000e_getreg(PBS), 2931 e1000e_getreg(RDFH), 2932 e1000e_getreg(RDFT), 2933 e1000e_getreg(RDFHS), 2934 e1000e_getreg(RDFTS), 2935 e1000e_getreg(RDFPC), 2936 e1000e_getreg(GORCL), 2937 e1000e_getreg(MGTPRC), 2938 e1000e_getreg(EERD), 2939 e1000e_getreg(EIAC), 2940 e1000e_getreg(PSRCTL), 2941 e1000e_getreg(MANC2H), 2942 e1000e_getreg(RXCSUM), 2943 e1000e_getreg(GSCL_3), 2944 e1000e_getreg(GSCN_2), 2945 e1000e_getreg(RSRPD), 2946 e1000e_getreg(RDBAL1), 2947 e1000e_getreg(FCAH), 2948 e1000e_getreg(FCRTH), 2949 e1000e_getreg(FLOP), 2950 e1000e_getreg(FLASHT), 2951 e1000e_getreg(RXSTMPH), 2952 e1000e_getreg(TXSTMPL), 2953 e1000e_getreg(TIMADJL), 2954 e1000e_getreg(TXDCTL), 2955 e1000e_getreg(RDH0), 2956 e1000e_getreg(TDT1), 2957 e1000e_getreg(TNCRS), 2958 e1000e_getreg(RJC), 2959 e1000e_getreg(IAM), 2960 e1000e_getreg(GSCL_2), 2961 e1000e_getreg(RDBAH1), 2962 e1000e_getreg(FLSWDATA), 2963 e1000e_getreg(RXSATRH), 2964 e1000e_getreg(TIPG), 2965 e1000e_getreg(FLMNGCTL), 2966 e1000e_getreg(FLMNGCNT), 2967 e1000e_getreg(TSYNCTXCTL), 2968 e1000e_getreg(EXTCNF_SIZE), 2969 e1000e_getreg(EXTCNF_CTRL), 2970 e1000e_getreg(EEMNGDATA), 2971 e1000e_getreg(CTRL_EXT), 2972 e1000e_getreg(SYSTIMH), 2973 e1000e_getreg(EEMNGCTL), 2974 e1000e_getreg(FLMNGDATA), 2975 e1000e_getreg(TSYNCRXCTL), 2976 e1000e_getreg(TDH), 2977 e1000e_getreg(LEDCTL), 2978 e1000e_getreg(TCTL), 2979 e1000e_getreg(TDBAL), 2980 e1000e_getreg(TDLEN), 2981 e1000e_getreg(TDH1), 2982 e1000e_getreg(RADV), 2983 e1000e_getreg(ECOL), 2984 e1000e_getreg(DC), 2985 e1000e_getreg(RLEC), 2986 e1000e_getreg(XOFFTXC), 2987 e1000e_getreg(RFC), 2988 e1000e_getreg(RNBC), 2989 e1000e_getreg(MGTPTC), 2990 e1000e_getreg(TIMINCA), 2991 e1000e_getreg(RXCFGL), 2992 e1000e_getreg(MFUTP01), 2993 e1000e_getreg(FACTPS), 2994 e1000e_getreg(GSCL_1), 2995 e1000e_getreg(GSCN_0), 2996 e1000e_getreg(GCR2), 2997 e1000e_getreg(RDT1), 2998 e1000e_getreg(PBACLR), 2999 e1000e_getreg(FCTTV), 3000 e1000e_getreg(EEWR), 3001 e1000e_getreg(FLSWCTL), 3002 e1000e_getreg(RXDCTL1), 3003 e1000e_getreg(RXSATRL), 3004 e1000e_getreg(SYSTIML), 3005 e1000e_getreg(RXUDP), 3006 e1000e_getreg(TORL), 3007 e1000e_getreg(TDLEN1), 3008 e1000e_getreg(MCC), 3009 e1000e_getreg(WUC), 3010 e1000e_getreg(EECD), 3011 e1000e_getreg(MFUTP23), 3012 e1000e_getreg(RAID), 3013 e1000e_getreg(FCRTV), 3014 e1000e_getreg(TXDCTL1), 3015 e1000e_getreg(RCTL), 3016 e1000e_getreg(TDT), 3017 e1000e_getreg(MDIC), 3018 e1000e_getreg(FCRUC), 3019 e1000e_getreg(VET), 3020 e1000e_getreg(RDBAL0), 3021 e1000e_getreg(TDBAH1), 3022 e1000e_getreg(RDTR), 3023 e1000e_getreg(SCC), 3024 e1000e_getreg(COLC), 3025 e1000e_getreg(CEXTERR), 3026 e1000e_getreg(XOFFRXC), 3027 e1000e_getreg(IPAV), 3028 e1000e_getreg(GOTCL), 3029 e1000e_getreg(MGTPDC), 3030 e1000e_getreg(GCR), 3031 e1000e_getreg(IVAR), 3032 e1000e_getreg(POEMB), 3033 e1000e_getreg(MFVAL), 3034 e1000e_getreg(FUNCTAG), 3035 e1000e_getreg(GSCL_4), 3036 e1000e_getreg(GSCN_3), 3037 e1000e_getreg(MRQC), 3038 e1000e_getreg(RDLEN1), 3039 e1000e_getreg(FCT), 3040 e1000e_getreg(FLA), 3041 e1000e_getreg(FLOL), 3042 e1000e_getreg(RXDCTL), 3043 e1000e_getreg(RXSTMPL), 3044 e1000e_getreg(TXSTMPH), 3045 e1000e_getreg(TIMADJH), 3046 e1000e_getreg(FCRTL), 3047 e1000e_getreg(TDBAH), 3048 e1000e_getreg(TADV), 3049 e1000e_getreg(XONRXC), 3050 e1000e_getreg(TSCTFC), 3051 e1000e_getreg(RFCTL), 3052 e1000e_getreg(GSCN_1), 3053 e1000e_getreg(FCAL), 3054 e1000e_getreg(FLSWCNT), 3055 3056 [TOTH] = e1000e_mac_read_clr8, 3057 [GOTCH] = e1000e_mac_read_clr8, 3058 [PRC64] = e1000e_mac_read_clr4, 3059 [PRC255] = e1000e_mac_read_clr4, 3060 [PRC1023] = e1000e_mac_read_clr4, 3061 [PTC64] = e1000e_mac_read_clr4, 3062 [PTC255] = e1000e_mac_read_clr4, 3063 [PTC1023] = e1000e_mac_read_clr4, 3064 [GPRC] = e1000e_mac_read_clr4, 3065 [TPT] = e1000e_mac_read_clr4, 3066 [RUC] = e1000e_mac_read_clr4, 3067 [BPRC] = e1000e_mac_read_clr4, 3068 [MPTC] = e1000e_mac_read_clr4, 3069 [IAC] = e1000e_mac_read_clr4, 3070 [ICR] = e1000e_mac_icr_read, 3071 [STATUS] = e1000e_get_status, 3072 [TARC0] = e1000e_get_tarc, 3073 [ICS] = e1000e_mac_ics_read, 3074 [TORH] = e1000e_mac_read_clr8, 3075 [GORCH] = e1000e_mac_read_clr8, 3076 [PRC127] = e1000e_mac_read_clr4, 3077 [PRC511] = e1000e_mac_read_clr4, 3078 [PRC1522] = e1000e_mac_read_clr4, 3079 [PTC127] = e1000e_mac_read_clr4, 3080 [PTC511] = e1000e_mac_read_clr4, 3081 [PTC1522] = e1000e_mac_read_clr4, 3082 [GPTC] = e1000e_mac_read_clr4, 3083 [TPR] = e1000e_mac_read_clr4, 3084 [ROC] = e1000e_mac_read_clr4, 3085 [MPRC] = e1000e_mac_read_clr4, 3086 [BPTC] = e1000e_mac_read_clr4, 3087 [TSCTC] = e1000e_mac_read_clr4, 3088 [ITR] = e1000e_mac_itr_read, 3089 [CTRL] = e1000e_get_ctrl, 3090 [TARC1] = e1000e_get_tarc, 3091 [SWSM] = e1000e_mac_swsm_read, 3092 [IMS] = e1000e_mac_ims_read, 3093 3094 [CRCERRS ... MPC] = e1000e_mac_readreg, 3095 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3096 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3097 [RA ... RA + 31] = e1000e_mac_readreg, 3098 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3099 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3100 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3101 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3102 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3103 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3104 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3105 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3106 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3107 [RETA ... RETA + 31] = e1000e_mac_readreg, 3108 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3109 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3110 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3111 }; 3112 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3113 3114 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3115 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3116 static const writeops e1000e_macreg_writeops[] = { 3117 e1000e_putreg(PBA), 3118 e1000e_putreg(SWSM), 3119 e1000e_putreg(WUFC), 3120 e1000e_putreg(RDBAH1), 3121 e1000e_putreg(TDBAH), 3122 e1000e_putreg(TXDCTL), 3123 e1000e_putreg(RDBAH0), 3124 e1000e_putreg(LEDCTL), 3125 e1000e_putreg(FCAL), 3126 e1000e_putreg(FCRUC), 3127 e1000e_putreg(WUC), 3128 e1000e_putreg(WUS), 3129 e1000e_putreg(IPAV), 3130 e1000e_putreg(TDBAH1), 3131 e1000e_putreg(TIMINCA), 3132 e1000e_putreg(IAM), 3133 e1000e_putreg(EIAC), 3134 e1000e_putreg(IVAR), 3135 e1000e_putreg(TARC0), 3136 e1000e_putreg(TARC1), 3137 e1000e_putreg(FLSWDATA), 3138 e1000e_putreg(POEMB), 3139 e1000e_putreg(MFUTP01), 3140 e1000e_putreg(MFUTP23), 3141 e1000e_putreg(MANC), 3142 e1000e_putreg(MANC2H), 3143 e1000e_putreg(MFVAL), 3144 e1000e_putreg(EXTCNF_CTRL), 3145 e1000e_putreg(FACTPS), 3146 e1000e_putreg(FUNCTAG), 3147 e1000e_putreg(GSCL_1), 3148 e1000e_putreg(GSCL_2), 3149 e1000e_putreg(GSCL_3), 3150 e1000e_putreg(GSCL_4), 3151 e1000e_putreg(GSCN_0), 3152 e1000e_putreg(GSCN_1), 3153 e1000e_putreg(GSCN_2), 3154 e1000e_putreg(GSCN_3), 3155 e1000e_putreg(GCR2), 3156 e1000e_putreg(MRQC), 3157 e1000e_putreg(FLOP), 3158 e1000e_putreg(FLOL), 3159 e1000e_putreg(FLSWCTL), 3160 e1000e_putreg(FLSWCNT), 3161 e1000e_putreg(FLA), 3162 e1000e_putreg(RXDCTL1), 3163 e1000e_putreg(TXDCTL1), 3164 e1000e_putreg(TIPG), 3165 e1000e_putreg(RXSTMPH), 3166 e1000e_putreg(RXSTMPL), 3167 e1000e_putreg(RXSATRL), 3168 e1000e_putreg(RXSATRH), 3169 e1000e_putreg(TXSTMPL), 3170 e1000e_putreg(TXSTMPH), 3171 e1000e_putreg(SYSTIML), 3172 e1000e_putreg(SYSTIMH), 3173 e1000e_putreg(TIMADJL), 3174 e1000e_putreg(TIMADJH), 3175 e1000e_putreg(RXUDP), 3176 e1000e_putreg(RXCFGL), 3177 e1000e_putreg(TSYNCRXCTL), 3178 e1000e_putreg(TSYNCTXCTL), 3179 e1000e_putreg(EXTCNF_SIZE), 3180 e1000e_putreg(EEMNGCTL), 3181 e1000e_putreg(RA), 3182 3183 [TDH1] = e1000e_set_16bit, 3184 [TDT1] = e1000e_set_tdt, 3185 [TCTL] = e1000e_set_tctl, 3186 [TDT] = e1000e_set_tdt, 3187 [MDIC] = e1000e_set_mdic, 3188 [ICS] = e1000e_set_ics, 3189 [TDH] = e1000e_set_16bit, 3190 [RDH0] = e1000e_set_16bit, 3191 [RDT0] = e1000e_set_rdt, 3192 [IMC] = e1000e_set_imc, 3193 [IMS] = e1000e_set_ims, 3194 [ICR] = e1000e_set_icr, 3195 [EECD] = e1000e_set_eecd, 3196 [RCTL] = e1000e_set_rx_control, 3197 [CTRL] = e1000e_set_ctrl, 3198 [RDTR] = e1000e_set_rdtr, 3199 [RADV] = e1000e_set_16bit, 3200 [TADV] = e1000e_set_16bit, 3201 [ITR] = e1000e_set_itr, 3202 [EERD] = e1000e_set_eerd, 3203 [AIT] = e1000e_set_16bit, 3204 [TDFH] = e1000e_set_13bit, 3205 [TDFT] = e1000e_set_13bit, 3206 [TDFHS] = e1000e_set_13bit, 3207 [TDFTS] = e1000e_set_13bit, 3208 [TDFPC] = e1000e_set_13bit, 3209 [RDFH] = e1000e_set_13bit, 3210 [RDFHS] = e1000e_set_13bit, 3211 [RDFT] = e1000e_set_13bit, 3212 [RDFTS] = e1000e_set_13bit, 3213 [RDFPC] = e1000e_set_13bit, 3214 [PBS] = e1000e_set_6bit, 3215 [GCR] = e1000e_set_gcr, 3216 [PSRCTL] = e1000e_set_psrctl, 3217 [RXCSUM] = e1000e_set_rxcsum, 3218 [RAID] = e1000e_set_16bit, 3219 [RSRPD] = e1000e_set_12bit, 3220 [TIDV] = e1000e_set_tidv, 3221 [TDLEN1] = e1000e_set_dlen, 3222 [TDLEN] = e1000e_set_dlen, 3223 [RDLEN0] = e1000e_set_dlen, 3224 [RDLEN1] = e1000e_set_dlen, 3225 [TDBAL] = e1000e_set_dbal, 3226 [TDBAL1] = e1000e_set_dbal, 3227 [RDBAL0] = e1000e_set_dbal, 3228 [RDBAL1] = e1000e_set_dbal, 3229 [RDH1] = e1000e_set_16bit, 3230 [RDT1] = e1000e_set_rdt, 3231 [STATUS] = e1000e_set_status, 3232 [PBACLR] = e1000e_set_pbaclr, 3233 [CTRL_EXT] = e1000e_set_ctrlext, 3234 [FCAH] = e1000e_set_16bit, 3235 [FCT] = e1000e_set_16bit, 3236 [FCTTV] = e1000e_set_16bit, 3237 [FCRTV] = e1000e_set_16bit, 3238 [FCRTH] = e1000e_set_fcrth, 3239 [FCRTL] = e1000e_set_fcrtl, 3240 [VET] = e1000e_set_vet, 3241 [RXDCTL] = e1000e_set_rxdctl, 3242 [FLASHT] = e1000e_set_16bit, 3243 [EEWR] = e1000e_set_eewr, 3244 [CTRL_DUP] = e1000e_set_ctrl, 3245 [RFCTL] = e1000e_set_rfctl, 3246 [RA + 1] = e1000e_mac_setmacaddr, 3247 3248 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3249 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3250 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3251 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3252 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3253 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3254 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3255 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3256 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3257 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3258 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3259 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3260 [RETA ... RETA + 31] = e1000e_mac_writereg, 3261 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3262 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3263 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3264 }; 3265 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3266 3267 enum { MAC_ACCESS_PARTIAL = 1 }; 3268 3269 /* 3270 * The array below combines alias offsets of the index values for the 3271 * MAC registers that have aliases, with the indication of not fully 3272 * implemented registers (lowest bit). This combination is possible 3273 * because all of the offsets are even. 3274 */ 3275 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3276 /* Alias index offsets */ 3277 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3278 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3279 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3280 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3281 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3282 [RA_A ... RA_A + 31] = 0x14f0, 3283 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3284 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3285 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3286 /* Access options */ 3287 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3288 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3289 [RDFPC] = MAC_ACCESS_PARTIAL, 3290 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3291 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3292 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3293 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3294 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3295 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3296 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3297 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3298 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3299 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3300 }; 3301 3302 void 3303 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3304 { 3305 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3306 3307 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3308 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3309 trace_e1000e_wrn_regs_write_trivial(index << 2); 3310 } 3311 trace_e1000e_core_write(index << 2, size, val); 3312 e1000e_macreg_writeops[index](core, index, val); 3313 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3314 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3315 } else { 3316 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3317 } 3318 } 3319 3320 uint64_t 3321 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3322 { 3323 uint64_t val; 3324 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3325 3326 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3327 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3328 trace_e1000e_wrn_regs_read_trivial(index << 2); 3329 } 3330 val = e1000e_macreg_readops[index](core, index); 3331 trace_e1000e_core_read(index << 2, size, val); 3332 return val; 3333 } else { 3334 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3335 } 3336 return 0; 3337 } 3338 3339 static inline void 3340 e1000e_autoneg_pause(E1000ECore *core) 3341 { 3342 timer_del(core->autoneg_timer); 3343 } 3344 3345 static void 3346 e1000e_autoneg_resume(E1000ECore *core) 3347 { 3348 if (e1000e_have_autoneg(core) && 3349 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3350 qemu_get_queue(core->owner_nic)->link_down = false; 3351 timer_mod(core->autoneg_timer, 3352 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3353 } 3354 } 3355 3356 static void 3357 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3358 { 3359 E1000ECore *core = opaque; 3360 3361 if (running) { 3362 trace_e1000e_vm_state_running(); 3363 e1000e_intrmgr_resume(core); 3364 e1000e_autoneg_resume(core); 3365 } else { 3366 trace_e1000e_vm_state_stopped(); 3367 e1000e_autoneg_pause(core); 3368 e1000e_intrmgr_pause(core); 3369 } 3370 } 3371 3372 void 3373 e1000e_core_pci_realize(E1000ECore *core, 3374 const uint16_t *eeprom_templ, 3375 uint32_t eeprom_size, 3376 const uint8_t *macaddr) 3377 { 3378 int i; 3379 3380 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3381 e1000e_autoneg_timer, core); 3382 e1000e_intrmgr_pci_realize(core); 3383 3384 core->vmstate = 3385 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3386 3387 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3388 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner, E1000E_MAX_TX_FRAGS); 3389 } 3390 3391 net_rx_pkt_init(&core->rx_pkt); 3392 3393 e1000x_core_prepare_eeprom(core->eeprom, 3394 eeprom_templ, 3395 eeprom_size, 3396 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3397 macaddr); 3398 e1000e_update_rx_offloads(core); 3399 } 3400 3401 void 3402 e1000e_core_pci_uninit(E1000ECore *core) 3403 { 3404 int i; 3405 3406 timer_free(core->autoneg_timer); 3407 3408 e1000e_intrmgr_pci_unint(core); 3409 3410 qemu_del_vm_change_state_handler(core->vmstate); 3411 3412 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3413 net_tx_pkt_reset(core->tx[i].tx_pkt); 3414 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3415 } 3416 3417 net_rx_pkt_uninit(core->rx_pkt); 3418 } 3419 3420 static const uint16_t 3421 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3422 [0] = { 3423 [MII_BMCR] = MII_BMCR_SPEED1000 | 3424 MII_BMCR_FD | 3425 MII_BMCR_AUTOEN, 3426 3427 [MII_BMSR] = MII_BMSR_EXTCAP | 3428 MII_BMSR_LINK_ST | 3429 MII_BMSR_AUTONEG | 3430 MII_BMSR_MFPS | 3431 MII_BMSR_EXTSTAT | 3432 MII_BMSR_10T_HD | 3433 MII_BMSR_10T_FD | 3434 MII_BMSR_100TX_HD | 3435 MII_BMSR_100TX_FD, 3436 3437 [MII_PHYID1] = 0x141, 3438 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3439 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3440 MII_ANAR_10FD | MII_ANAR_TX | 3441 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3442 MII_ANAR_PAUSE_ASYM, 3443 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3444 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3445 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3446 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3447 [MII_ANNP] = 1 | MII_ANNP_MP, 3448 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3449 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3450 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3451 MII_STAT1000_ROK | MII_STAT1000_LOK, 3452 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3453 3454 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3455 BIT(12) | BIT(13), 3456 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3457 }, 3458 [2] = { 3459 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3460 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3461 }, 3462 [3] = { 3463 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3464 } 3465 }; 3466 3467 static const uint32_t e1000e_mac_reg_init[] = { 3468 [PBA] = 0x00140014, 3469 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3470 [EXTCNF_CTRL] = BIT(3), 3471 [EEMNGCTL] = BIT(31), 3472 [FLASHT] = 0x2, 3473 [FLSWCTL] = BIT(30) | BIT(31), 3474 [FLOL] = BIT(0), 3475 [RXDCTL] = BIT(16), 3476 [RXDCTL1] = BIT(16), 3477 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3478 [RXCFGL] = 0x88F7, 3479 [RXUDP] = 0x319, 3480 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3481 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3482 E1000_CTRL_ADVD3WUC, 3483 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3484 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3485 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3486 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3487 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3488 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3489 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3490 [EERD] = E1000_EERW_DONE, 3491 [EEWR] = E1000_EERW_DONE, 3492 [GCR] = E1000_L0S_ADJUST | 3493 E1000_L1_ENTRY_LATENCY_MSB | 3494 E1000_L1_ENTRY_LATENCY_LSB, 3495 [TDFH] = 0x600, 3496 [TDFT] = 0x600, 3497 [TDFHS] = 0x600, 3498 [TDFTS] = 0x600, 3499 [POEMB] = 0x30D, 3500 [PBS] = 0x028, 3501 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3502 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3503 [SWSM] = 1, 3504 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3505 [ITR] = E1000E_MIN_XITR, 3506 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3507 }; 3508 3509 static void e1000e_reset(E1000ECore *core, bool sw) 3510 { 3511 int i; 3512 3513 timer_del(core->autoneg_timer); 3514 3515 e1000e_intrmgr_reset(core); 3516 3517 memset(core->phy, 0, sizeof core->phy); 3518 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3519 3520 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3521 if (sw && (i == PBA || i == PBS || i == FLA)) { 3522 continue; 3523 } 3524 3525 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3526 e1000e_mac_reg_init[i] : 0; 3527 } 3528 3529 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3530 3531 if (qemu_get_queue(core->owner_nic)->link_down) { 3532 e1000e_link_down(core); 3533 } 3534 3535 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3536 3537 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3538 net_tx_pkt_reset(core->tx[i].tx_pkt); 3539 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3540 core->tx[i].skip_cp = false; 3541 } 3542 } 3543 3544 void 3545 e1000e_core_reset(E1000ECore *core) 3546 { 3547 e1000e_reset(core, false); 3548 } 3549 3550 void e1000e_core_pre_save(E1000ECore *core) 3551 { 3552 int i; 3553 NetClientState *nc = qemu_get_queue(core->owner_nic); 3554 3555 /* 3556 * If link is down and auto-negotiation is supported and ongoing, 3557 * complete auto-negotiation immediately. This allows us to look 3558 * at MII_BMSR_AN_COMP to infer link status on load. 3559 */ 3560 if (nc->link_down && e1000e_have_autoneg(core)) { 3561 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3562 e1000e_update_flowctl_status(core); 3563 } 3564 3565 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3566 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3567 core->tx[i].skip_cp = true; 3568 } 3569 } 3570 } 3571 3572 int 3573 e1000e_core_post_load(E1000ECore *core) 3574 { 3575 NetClientState *nc = qemu_get_queue(core->owner_nic); 3576 3577 /* 3578 * nc.link_down can't be migrated, so infer link_down according 3579 * to link status bit in core.mac[STATUS]. 3580 */ 3581 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3582 3583 return 0; 3584 } 3585