1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000x_common.h" 49 #include "e1000e_core.h" 50 51 #include "trace.h" 52 53 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 54 #define E1000E_MIN_XITR (500) 55 56 #define E1000E_MAX_TX_FRAGS (64) 57 58 static inline void 59 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 60 61 static inline void 62 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 63 { 64 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 65 trace_e1000e_wrn_no_ts_support(); 66 } 67 } 68 69 static inline void 70 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 71 { 72 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 73 trace_e1000e_wrn_no_snap_support(); 74 } 75 } 76 77 static inline void 78 e1000e_raise_legacy_irq(E1000ECore *core) 79 { 80 trace_e1000e_irq_legacy_notify(true); 81 e1000x_inc_reg_if_not_full(core->mac, IAC); 82 pci_set_irq(core->owner, 1); 83 } 84 85 static inline void 86 e1000e_lower_legacy_irq(E1000ECore *core) 87 { 88 trace_e1000e_irq_legacy_notify(false); 89 pci_set_irq(core->owner, 0); 90 } 91 92 static inline void 93 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 94 { 95 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 96 timer->delay_resolution_ns; 97 98 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 99 100 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 101 102 timer->running = true; 103 } 104 105 static void 106 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 107 { 108 if (timer->running) { 109 e1000e_intrmgr_rearm_timer(timer); 110 } 111 } 112 113 static void 114 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 115 { 116 if (timer->running) { 117 timer_del(timer->timer); 118 } 119 } 120 121 static inline void 122 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 123 { 124 if (timer->running) { 125 timer_del(timer->timer); 126 timer->running = false; 127 } 128 } 129 130 static inline void 131 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 132 { 133 trace_e1000e_irq_fire_delayed_interrupts(); 134 e1000e_set_interrupt_cause(core, 0); 135 } 136 137 static void 138 e1000e_intrmgr_on_timer(void *opaque) 139 { 140 E1000IntrDelayTimer *timer = opaque; 141 142 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 143 144 timer->running = false; 145 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 146 } 147 148 static void 149 e1000e_intrmgr_on_throttling_timer(void *opaque) 150 { 151 E1000IntrDelayTimer *timer = opaque; 152 153 assert(!msix_enabled(timer->core->owner)); 154 155 timer->running = false; 156 157 if (!timer->core->itr_intr_pending) { 158 trace_e1000e_irq_throttling_no_pending_interrupts(); 159 return; 160 } 161 162 if (msi_enabled(timer->core->owner)) { 163 trace_e1000e_irq_msi_notify_postponed(); 164 /* Clear msi_causes_pending to fire MSI eventually */ 165 timer->core->msi_causes_pending = 0; 166 e1000e_set_interrupt_cause(timer->core, 0); 167 } else { 168 trace_e1000e_irq_legacy_notify_postponed(); 169 e1000e_set_interrupt_cause(timer->core, 0); 170 } 171 } 172 173 static void 174 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 175 { 176 E1000IntrDelayTimer *timer = opaque; 177 int idx = timer - &timer->core->eitr[0]; 178 179 assert(msix_enabled(timer->core->owner)); 180 181 timer->running = false; 182 183 if (!timer->core->eitr_intr_pending[idx]) { 184 trace_e1000e_irq_throttling_no_pending_vec(idx); 185 return; 186 } 187 188 trace_e1000e_irq_msix_notify_postponed_vec(idx); 189 msix_notify(timer->core->owner, idx); 190 } 191 192 static void 193 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 194 { 195 int i; 196 197 core->radv.delay_reg = RADV; 198 core->rdtr.delay_reg = RDTR; 199 core->raid.delay_reg = RAID; 200 core->tadv.delay_reg = TADV; 201 core->tidv.delay_reg = TIDV; 202 203 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 207 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 208 209 core->radv.core = core; 210 core->rdtr.core = core; 211 core->raid.core = core; 212 core->tadv.core = core; 213 core->tidv.core = core; 214 215 core->itr.core = core; 216 core->itr.delay_reg = ITR; 217 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 218 219 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 220 core->eitr[i].core = core; 221 core->eitr[i].delay_reg = EITR + i; 222 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 223 } 224 225 if (!create) { 226 return; 227 } 228 229 core->radv.timer = 230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 231 core->rdtr.timer = 232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 233 core->raid.timer = 234 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 235 236 core->tadv.timer = 237 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 238 core->tidv.timer = 239 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 240 241 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 242 e1000e_intrmgr_on_throttling_timer, 243 &core->itr); 244 245 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 246 core->eitr[i].timer = 247 timer_new_ns(QEMU_CLOCK_VIRTUAL, 248 e1000e_intrmgr_on_msix_throttling_timer, 249 &core->eitr[i]); 250 } 251 } 252 253 static inline void 254 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 255 { 256 e1000e_intrmgr_stop_timer(&core->radv); 257 e1000e_intrmgr_stop_timer(&core->rdtr); 258 e1000e_intrmgr_stop_timer(&core->raid); 259 e1000e_intrmgr_stop_timer(&core->tidv); 260 e1000e_intrmgr_stop_timer(&core->tadv); 261 } 262 263 static bool 264 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 265 { 266 uint32_t delayable_causes; 267 uint32_t rdtr = core->mac[RDTR]; 268 uint32_t radv = core->mac[RADV]; 269 uint32_t raid = core->mac[RAID]; 270 271 if (msix_enabled(core->owner)) { 272 return false; 273 } 274 275 delayable_causes = E1000_ICR_RXQ0 | 276 E1000_ICR_RXQ1 | 277 E1000_ICR_RXT0; 278 279 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 280 delayable_causes |= E1000_ICR_ACK; 281 } 282 283 /* Clean up all causes that may be delayed */ 284 core->delayed_causes |= *causes & delayable_causes; 285 *causes &= ~delayable_causes; 286 287 /* 288 * Check if delayed RX interrupts disabled by client 289 * or if there are causes that cannot be delayed 290 */ 291 if ((rdtr == 0) || (*causes != 0)) { 292 return false; 293 } 294 295 /* 296 * Check if delayed RX ACK interrupts disabled by client 297 * and there is an ACK packet received 298 */ 299 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 300 return false; 301 } 302 303 /* All causes delayed */ 304 e1000e_intrmgr_rearm_timer(&core->rdtr); 305 306 if (!core->radv.running && (radv != 0)) { 307 e1000e_intrmgr_rearm_timer(&core->radv); 308 } 309 310 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 311 e1000e_intrmgr_rearm_timer(&core->raid); 312 } 313 314 return true; 315 } 316 317 static bool 318 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 319 { 320 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 321 E1000_ICR_TXQ1 | 322 E1000_ICR_TXQE | 323 E1000_ICR_TXDW; 324 325 if (msix_enabled(core->owner)) { 326 return false; 327 } 328 329 /* Clean up all causes that may be delayed */ 330 core->delayed_causes |= *causes & delayable_causes; 331 *causes &= ~delayable_causes; 332 333 /* If there are causes that cannot be delayed */ 334 if (*causes != 0) { 335 return false; 336 } 337 338 /* All causes delayed */ 339 e1000e_intrmgr_rearm_timer(&core->tidv); 340 341 if (!core->tadv.running && (core->mac[TADV] != 0)) { 342 e1000e_intrmgr_rearm_timer(&core->tadv); 343 } 344 345 return true; 346 } 347 348 static uint32_t 349 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 350 { 351 uint32_t res; 352 353 if (msix_enabled(core->owner)) { 354 assert(core->delayed_causes == 0); 355 return 0; 356 } 357 358 res = core->delayed_causes; 359 core->delayed_causes = 0; 360 361 e1000e_intrmgr_stop_delay_timers(core); 362 363 return res; 364 } 365 366 static void 367 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 368 { 369 int i; 370 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 371 372 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 373 core->mac[ICR] |= val; 374 375 if (core->itr.running) { 376 timer_del(core->itr.timer); 377 e1000e_intrmgr_on_throttling_timer(&core->itr); 378 } 379 380 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 381 if (core->eitr[i].running) { 382 timer_del(core->eitr[i].timer); 383 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 384 } 385 } 386 } 387 388 static void 389 e1000e_intrmgr_resume(E1000ECore *core) 390 { 391 int i; 392 393 e1000e_intmgr_timer_resume(&core->radv); 394 e1000e_intmgr_timer_resume(&core->rdtr); 395 e1000e_intmgr_timer_resume(&core->raid); 396 e1000e_intmgr_timer_resume(&core->tidv); 397 e1000e_intmgr_timer_resume(&core->tadv); 398 399 e1000e_intmgr_timer_resume(&core->itr); 400 401 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 402 e1000e_intmgr_timer_resume(&core->eitr[i]); 403 } 404 } 405 406 static void 407 e1000e_intrmgr_pause(E1000ECore *core) 408 { 409 int i; 410 411 e1000e_intmgr_timer_pause(&core->radv); 412 e1000e_intmgr_timer_pause(&core->rdtr); 413 e1000e_intmgr_timer_pause(&core->raid); 414 e1000e_intmgr_timer_pause(&core->tidv); 415 e1000e_intmgr_timer_pause(&core->tadv); 416 417 e1000e_intmgr_timer_pause(&core->itr); 418 419 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 420 e1000e_intmgr_timer_pause(&core->eitr[i]); 421 } 422 } 423 424 static void 425 e1000e_intrmgr_reset(E1000ECore *core) 426 { 427 int i; 428 429 core->delayed_causes = 0; 430 431 e1000e_intrmgr_stop_delay_timers(core); 432 433 e1000e_intrmgr_stop_timer(&core->itr); 434 435 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 436 e1000e_intrmgr_stop_timer(&core->eitr[i]); 437 } 438 } 439 440 static void 441 e1000e_intrmgr_pci_unint(E1000ECore *core) 442 { 443 int i; 444 445 timer_free(core->radv.timer); 446 timer_free(core->rdtr.timer); 447 timer_free(core->raid.timer); 448 449 timer_free(core->tadv.timer); 450 timer_free(core->tidv.timer); 451 452 timer_free(core->itr.timer); 453 454 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 455 timer_free(core->eitr[i].timer); 456 } 457 } 458 459 static void 460 e1000e_intrmgr_pci_realize(E1000ECore *core) 461 { 462 e1000e_intrmgr_initialize_all_timers(core, true); 463 } 464 465 static inline bool 466 e1000e_rx_csum_enabled(E1000ECore *core) 467 { 468 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 469 } 470 471 static inline bool 472 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 473 { 474 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 475 } 476 477 static inline bool 478 e1000e_rx_use_ps_descriptor(E1000ECore *core) 479 { 480 return !e1000e_rx_use_legacy_descriptor(core) && 481 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 482 } 483 484 static inline bool 485 e1000e_rss_enabled(E1000ECore *core) 486 { 487 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 488 !e1000e_rx_csum_enabled(core) && 489 !e1000e_rx_use_legacy_descriptor(core); 490 } 491 492 typedef struct E1000E_RSSInfo_st { 493 bool enabled; 494 uint32_t hash; 495 uint32_t queue; 496 uint32_t type; 497 } E1000E_RSSInfo; 498 499 static uint32_t 500 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 501 { 502 bool isip4, isip6, isudp, istcp; 503 504 assert(e1000e_rss_enabled(core)); 505 506 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 507 508 if (isip4) { 509 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 510 511 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC], 512 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 513 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 514 515 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 516 return E1000_MRQ_RSS_TYPE_IPV4TCP; 517 } 518 519 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 520 return E1000_MRQ_RSS_TYPE_IPV4; 521 } 522 } else if (isip6) { 523 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 524 525 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 526 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 527 528 /* 529 * Following two traces must not be combined because resulting 530 * event will have 11 arguments totally and some trace backends 531 * (at least "ust") have limitation of maximum 10 arguments per 532 * event. Events with more arguments fail to compile for 533 * backends like these. 534 */ 535 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 536 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp, 537 ip6info->has_ext_hdrs, 538 ip6info->rss_ex_dst_valid, 539 ip6info->rss_ex_src_valid, 540 core->mac[MRQC], 541 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 542 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 543 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 544 545 if ((!ex_dis || !ip6info->has_ext_hdrs) && 546 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 547 ip6info->rss_ex_src_valid))) { 548 549 if (istcp && !ip6info->fragment && 550 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 551 return E1000_MRQ_RSS_TYPE_IPV6TCP; 552 } 553 554 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 555 return E1000_MRQ_RSS_TYPE_IPV6EX; 556 } 557 558 } 559 560 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 561 return E1000_MRQ_RSS_TYPE_IPV6; 562 } 563 564 } 565 566 return E1000_MRQ_RSS_TYPE_NONE; 567 } 568 569 static uint32_t 570 e1000e_rss_calc_hash(E1000ECore *core, 571 struct NetRxPkt *pkt, 572 E1000E_RSSInfo *info) 573 { 574 NetRxPktRssType type; 575 576 assert(e1000e_rss_enabled(core)); 577 578 switch (info->type) { 579 case E1000_MRQ_RSS_TYPE_IPV4: 580 type = NetPktRssIpV4; 581 break; 582 case E1000_MRQ_RSS_TYPE_IPV4TCP: 583 type = NetPktRssIpV4Tcp; 584 break; 585 case E1000_MRQ_RSS_TYPE_IPV6TCP: 586 type = NetPktRssIpV6TcpEx; 587 break; 588 case E1000_MRQ_RSS_TYPE_IPV6: 589 type = NetPktRssIpV6; 590 break; 591 case E1000_MRQ_RSS_TYPE_IPV6EX: 592 type = NetPktRssIpV6Ex; 593 break; 594 default: 595 assert(false); 596 return 0; 597 } 598 599 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 600 } 601 602 static void 603 e1000e_rss_parse_packet(E1000ECore *core, 604 struct NetRxPkt *pkt, 605 E1000E_RSSInfo *info) 606 { 607 trace_e1000e_rx_rss_started(); 608 609 if (!e1000e_rss_enabled(core)) { 610 info->enabled = false; 611 info->hash = 0; 612 info->queue = 0; 613 info->type = 0; 614 trace_e1000e_rx_rss_disabled(); 615 return; 616 } 617 618 info->enabled = true; 619 620 info->type = e1000e_rss_get_hash_type(core, pkt); 621 622 trace_e1000e_rx_rss_type(info->type); 623 624 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 625 info->hash = 0; 626 info->queue = 0; 627 return; 628 } 629 630 info->hash = e1000e_rss_calc_hash(core, pkt, info); 631 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 632 } 633 634 static void 635 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 636 { 637 if (tx->props.tse && tx->cptse) { 638 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss); 639 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 640 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 641 return; 642 } 643 644 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 645 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0); 646 } 647 648 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 649 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 650 } 651 } 652 653 static bool 654 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 655 { 656 int target_queue = MIN(core->max_queue_num, queue_index); 657 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 658 659 e1000e_setup_tx_offloads(core, tx); 660 661 net_tx_pkt_dump(tx->tx_pkt); 662 663 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 664 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 665 return net_tx_pkt_send_loopback(tx->tx_pkt, queue); 666 } else { 667 return net_tx_pkt_send(tx->tx_pkt, queue); 668 } 669 } 670 671 static void 672 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 673 { 674 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 675 PTC1023, PTC1522 }; 676 677 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt); 678 679 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 680 e1000x_inc_reg_if_not_full(core->mac, TPT); 681 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 682 683 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 684 case ETH_PKT_BCAST: 685 e1000x_inc_reg_if_not_full(core->mac, BPTC); 686 break; 687 case ETH_PKT_MCAST: 688 e1000x_inc_reg_if_not_full(core->mac, MPTC); 689 break; 690 case ETH_PKT_UCAST: 691 break; 692 default: 693 g_assert_not_reached(); 694 } 695 696 core->mac[GPTC] = core->mac[TPT]; 697 core->mac[GOTCL] = core->mac[TOTL]; 698 core->mac[GOTCH] = core->mac[TOTH]; 699 } 700 701 static void 702 e1000e_process_tx_desc(E1000ECore *core, 703 struct e1000e_tx *tx, 704 struct e1000_tx_desc *dp, 705 int queue_index) 706 { 707 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 708 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 709 unsigned int split_size = txd_lower & 0xffff; 710 uint64_t addr; 711 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 712 bool eop = txd_lower & E1000_TXD_CMD_EOP; 713 714 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 715 e1000x_read_tx_ctx_descr(xp, &tx->props); 716 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 717 return; 718 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 719 /* data descriptor */ 720 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 721 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 722 e1000e_process_ts_option(core, dp); 723 } else { 724 /* legacy descriptor */ 725 e1000e_process_ts_option(core, dp); 726 tx->cptse = 0; 727 } 728 729 addr = le64_to_cpu(dp->buffer_addr); 730 731 if (!tx->skip_cp) { 732 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) { 733 tx->skip_cp = true; 734 } 735 } 736 737 if (eop) { 738 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 739 if (e1000x_vlan_enabled(core->mac) && 740 e1000x_is_vlan_txd(txd_lower)) { 741 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 742 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 743 } 744 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 745 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 746 } 747 } 748 749 tx->skip_cp = false; 750 net_tx_pkt_reset(tx->tx_pkt); 751 752 tx->sum_needed = 0; 753 tx->cptse = 0; 754 } 755 } 756 757 static inline uint32_t 758 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 759 { 760 if (!msix_enabled(core->owner)) { 761 return E1000_ICR_TXDW; 762 } 763 764 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 765 } 766 767 static inline uint32_t 768 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 769 bool min_threshold_hit) 770 { 771 if (!msix_enabled(core->owner)) { 772 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 773 } 774 775 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 776 } 777 778 static uint32_t 779 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 780 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 781 { 782 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 783 784 if (!(txd_lower & E1000_TXD_CMD_RS) && 785 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 786 return 0; 787 } 788 789 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 790 791 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 792 793 dp->upper.data = cpu_to_le32(txd_upper); 794 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 795 &dp->upper, sizeof(dp->upper)); 796 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 797 } 798 799 typedef struct E1000E_RingInfo_st { 800 int dbah; 801 int dbal; 802 int dlen; 803 int dh; 804 int dt; 805 int idx; 806 } E1000E_RingInfo; 807 808 static inline bool 809 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 810 { 811 return core->mac[r->dh] == core->mac[r->dt] || 812 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 813 } 814 815 static inline uint64_t 816 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 817 { 818 uint64_t bah = core->mac[r->dbah]; 819 uint64_t bal = core->mac[r->dbal]; 820 821 return (bah << 32) + bal; 822 } 823 824 static inline uint64_t 825 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 826 { 827 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 828 } 829 830 static inline void 831 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 832 { 833 core->mac[r->dh] += count; 834 835 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 836 core->mac[r->dh] = 0; 837 } 838 } 839 840 static inline uint32_t 841 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 842 { 843 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 844 core->mac[r->dh], core->mac[r->dt]); 845 846 if (core->mac[r->dh] <= core->mac[r->dt]) { 847 return core->mac[r->dt] - core->mac[r->dh]; 848 } 849 850 if (core->mac[r->dh] > core->mac[r->dt]) { 851 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 852 core->mac[r->dt] - core->mac[r->dh]; 853 } 854 855 g_assert_not_reached(); 856 return 0; 857 } 858 859 static inline bool 860 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 861 { 862 return core->mac[r->dlen] > 0; 863 } 864 865 static inline uint32_t 866 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 867 { 868 return core->mac[r->dlen]; 869 } 870 871 typedef struct E1000E_TxRing_st { 872 const E1000E_RingInfo *i; 873 struct e1000e_tx *tx; 874 } E1000E_TxRing; 875 876 static inline int 877 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 878 { 879 return (reg_idx - base_reg_idx) / (0x100 >> 2); 880 } 881 882 static inline void 883 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 884 { 885 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 886 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 887 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 888 }; 889 890 assert(idx < ARRAY_SIZE(i)); 891 892 txr->i = &i[idx]; 893 txr->tx = &core->tx[idx]; 894 } 895 896 typedef struct E1000E_RxRing_st { 897 const E1000E_RingInfo *i; 898 } E1000E_RxRing; 899 900 static inline void 901 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 902 { 903 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 904 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 905 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 906 }; 907 908 assert(idx < ARRAY_SIZE(i)); 909 910 rxr->i = &i[idx]; 911 } 912 913 static void 914 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 915 { 916 dma_addr_t base; 917 struct e1000_tx_desc desc; 918 bool ide = false; 919 const E1000E_RingInfo *txi = txr->i; 920 uint32_t cause = E1000_ICS_TXQE; 921 922 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 923 trace_e1000e_tx_disabled(); 924 return; 925 } 926 927 while (!e1000e_ring_empty(core, txi)) { 928 base = e1000e_ring_head_descr(core, txi); 929 930 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 931 932 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 933 desc.lower.data, desc.upper.data); 934 935 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 936 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 937 938 e1000e_ring_advance(core, txi, 1); 939 } 940 941 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 942 e1000e_set_interrupt_cause(core, cause); 943 } 944 } 945 946 static bool 947 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 948 size_t total_size) 949 { 950 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 951 952 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 953 core->rx_desc_buf_size); 954 955 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 956 core->rx_desc_buf_size; 957 } 958 959 void 960 e1000e_start_recv(E1000ECore *core) 961 { 962 int i; 963 964 trace_e1000e_rx_start_recv(); 965 966 for (i = 0; i <= core->max_queue_num; i++) { 967 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 968 } 969 } 970 971 bool 972 e1000e_can_receive(E1000ECore *core) 973 { 974 int i; 975 976 if (!e1000x_rx_ready(core->owner, core->mac)) { 977 return false; 978 } 979 980 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 981 E1000E_RxRing rxr; 982 983 e1000e_rx_ring_init(core, &rxr, i); 984 if (e1000e_ring_enabled(core, rxr.i) && 985 e1000e_has_rxbufs(core, rxr.i, 1)) { 986 trace_e1000e_rx_can_recv(); 987 return true; 988 } 989 } 990 991 trace_e1000e_rx_can_recv_rings_full(); 992 return false; 993 } 994 995 ssize_t 996 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 997 { 998 const struct iovec iov = { 999 .iov_base = (uint8_t *)buf, 1000 .iov_len = size 1001 }; 1002 1003 return e1000e_receive_iov(core, &iov, 1); 1004 } 1005 1006 static inline bool 1007 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1008 { 1009 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1010 } 1011 1012 static inline bool 1013 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1014 { 1015 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1016 } 1017 1018 static bool 1019 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size) 1020 { 1021 uint32_t rctl = core->mac[RCTL]; 1022 1023 if (e1000x_is_vlan_packet(buf, core->mac[VET]) && 1024 e1000x_vlan_rx_filter_enabled(core->mac)) { 1025 uint16_t vid = lduw_be_p(buf + 14); 1026 uint32_t vfta = ldl_le_p((uint32_t *)(core->mac + VFTA) + 1027 ((vid >> 5) & 0x7f)); 1028 if ((vfta & (1 << (vid & 0x1f))) == 0) { 1029 trace_e1000e_rx_flt_vlan_mismatch(vid); 1030 return false; 1031 } else { 1032 trace_e1000e_rx_flt_vlan_match(vid); 1033 } 1034 } 1035 1036 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1037 case ETH_PKT_UCAST: 1038 if (rctl & E1000_RCTL_UPE) { 1039 return true; /* promiscuous ucast */ 1040 } 1041 break; 1042 1043 case ETH_PKT_BCAST: 1044 if (rctl & E1000_RCTL_BAM) { 1045 return true; /* broadcast enabled */ 1046 } 1047 break; 1048 1049 case ETH_PKT_MCAST: 1050 if (rctl & E1000_RCTL_MPE) { 1051 return true; /* promiscuous mcast */ 1052 } 1053 break; 1054 1055 default: 1056 g_assert_not_reached(); 1057 } 1058 1059 return e1000x_rx_group_filter(core->mac, buf); 1060 } 1061 1062 static inline void 1063 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr) 1064 { 1065 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc; 1066 *buff_addr = le64_to_cpu(d->buffer_addr); 1067 } 1068 1069 static inline void 1070 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr) 1071 { 1072 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc; 1073 *buff_addr = le64_to_cpu(d->read.buffer_addr); 1074 } 1075 1076 static inline void 1077 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc, 1078 hwaddr (*buff_addr)[MAX_PS_BUFFERS]) 1079 { 1080 int i; 1081 union e1000_rx_desc_packet_split *d = 1082 (union e1000_rx_desc_packet_split *) desc; 1083 1084 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1085 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]); 1086 } 1087 1088 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1], 1089 (*buff_addr)[2], (*buff_addr)[3]); 1090 } 1091 1092 static inline void 1093 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc, 1094 hwaddr (*buff_addr)[MAX_PS_BUFFERS]) 1095 { 1096 if (e1000e_rx_use_legacy_descriptor(core)) { 1097 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]); 1098 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0; 1099 } else { 1100 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1101 e1000e_read_ps_rx_descr(core, desc, buff_addr); 1102 } else { 1103 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]); 1104 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0; 1105 } 1106 } 1107 } 1108 1109 static void 1110 e1000e_verify_csum_in_sw(E1000ECore *core, 1111 struct NetRxPkt *pkt, 1112 uint32_t *status_flags, 1113 bool istcp, bool isudp) 1114 { 1115 bool csum_valid; 1116 uint32_t csum_error; 1117 1118 if (e1000e_rx_l3_cso_enabled(core)) { 1119 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1120 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1121 } else { 1122 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1123 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1124 } 1125 } else { 1126 trace_e1000e_rx_metadata_l3_cso_disabled(); 1127 } 1128 1129 if (!e1000e_rx_l4_cso_enabled(core)) { 1130 trace_e1000e_rx_metadata_l4_cso_disabled(); 1131 return; 1132 } 1133 1134 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1135 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1136 return; 1137 } 1138 1139 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1140 1141 if (istcp) { 1142 *status_flags |= E1000_RXD_STAT_TCPCS | 1143 csum_error; 1144 } else if (isudp) { 1145 *status_flags |= E1000_RXD_STAT_TCPCS | 1146 E1000_RXD_STAT_UDPCS | 1147 csum_error; 1148 } 1149 } 1150 1151 static inline bool 1152 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1153 { 1154 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1155 return false; 1156 } 1157 1158 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1159 return !net_rx_pkt_has_tcp_data(rx_pkt); 1160 } 1161 1162 return true; 1163 } 1164 1165 static void 1166 e1000e_build_rx_metadata(E1000ECore *core, 1167 struct NetRxPkt *pkt, 1168 bool is_eop, 1169 const E1000E_RSSInfo *rss_info, 1170 uint32_t *rss, uint32_t *mrq, 1171 uint32_t *status_flags, 1172 uint16_t *ip_id, 1173 uint16_t *vlan_tag) 1174 { 1175 struct virtio_net_hdr *vhdr; 1176 bool isip4, isip6, istcp, isudp; 1177 uint32_t pkt_type; 1178 1179 *status_flags = E1000_RXD_STAT_DD; 1180 1181 /* No additional metadata needed for non-EOP descriptors */ 1182 if (!is_eop) { 1183 goto func_exit; 1184 } 1185 1186 *status_flags |= E1000_RXD_STAT_EOP; 1187 1188 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1189 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp); 1190 1191 /* VLAN state */ 1192 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1193 *status_flags |= E1000_RXD_STAT_VP; 1194 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1195 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1196 } 1197 1198 /* Packet parsing results */ 1199 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1200 if (rss_info->enabled) { 1201 *rss = cpu_to_le32(rss_info->hash); 1202 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1203 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1204 } 1205 } else if (isip4) { 1206 *status_flags |= E1000_RXD_STAT_IPIDV; 1207 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1208 trace_e1000e_rx_metadata_ip_id(*ip_id); 1209 } 1210 1211 if (istcp && e1000e_is_tcp_ack(core, pkt)) { 1212 *status_flags |= E1000_RXD_STAT_ACK; 1213 trace_e1000e_rx_metadata_ack(); 1214 } 1215 1216 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1217 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1218 pkt_type = E1000_RXD_PKT_MAC; 1219 } else if (istcp || isudp) { 1220 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1221 } else if (isip4 || isip6) { 1222 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1223 } else { 1224 pkt_type = E1000_RXD_PKT_MAC; 1225 } 1226 1227 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1228 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1229 1230 /* RX CSO information */ 1231 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1232 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1233 goto func_exit; 1234 } 1235 1236 if (!net_rx_pkt_has_virt_hdr(pkt)) { 1237 trace_e1000e_rx_metadata_no_virthdr(); 1238 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp); 1239 goto func_exit; 1240 } 1241 1242 vhdr = net_rx_pkt_get_vhdr(pkt); 1243 1244 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1245 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1246 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1247 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp); 1248 goto func_exit; 1249 } 1250 1251 if (e1000e_rx_l3_cso_enabled(core)) { 1252 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0; 1253 } else { 1254 trace_e1000e_rx_metadata_l3_cso_disabled(); 1255 } 1256 1257 if (e1000e_rx_l4_cso_enabled(core)) { 1258 if (istcp) { 1259 *status_flags |= E1000_RXD_STAT_TCPCS; 1260 } else if (isudp) { 1261 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1262 } 1263 } else { 1264 trace_e1000e_rx_metadata_l4_cso_disabled(); 1265 } 1266 1267 trace_e1000e_rx_metadata_status_flags(*status_flags); 1268 1269 func_exit: 1270 *status_flags = cpu_to_le32(*status_flags); 1271 } 1272 1273 static inline void 1274 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, 1275 struct NetRxPkt *pkt, 1276 const E1000E_RSSInfo *rss_info, 1277 uint16_t length) 1278 { 1279 uint32_t status_flags, rss, mrq; 1280 uint16_t ip_id; 1281 1282 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc; 1283 1284 assert(!rss_info->enabled); 1285 1286 d->length = cpu_to_le16(length); 1287 d->csum = 0; 1288 1289 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1290 rss_info, 1291 &rss, &mrq, 1292 &status_flags, &ip_id, 1293 &d->special); 1294 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1295 d->status = (uint8_t) le32_to_cpu(status_flags); 1296 } 1297 1298 static inline void 1299 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc, 1300 struct NetRxPkt *pkt, 1301 const E1000E_RSSInfo *rss_info, 1302 uint16_t length) 1303 { 1304 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc; 1305 1306 memset(&d->wb, 0, sizeof(d->wb)); 1307 1308 d->wb.upper.length = cpu_to_le16(length); 1309 1310 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1311 rss_info, 1312 &d->wb.lower.hi_dword.rss, 1313 &d->wb.lower.mrq, 1314 &d->wb.upper.status_error, 1315 &d->wb.lower.hi_dword.csum_ip.ip_id, 1316 &d->wb.upper.vlan); 1317 } 1318 1319 static inline void 1320 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc, 1321 struct NetRxPkt *pkt, 1322 const E1000E_RSSInfo *rss_info, 1323 size_t ps_hdr_len, 1324 uint16_t(*written)[MAX_PS_BUFFERS]) 1325 { 1326 int i; 1327 union e1000_rx_desc_packet_split *d = 1328 (union e1000_rx_desc_packet_split *) desc; 1329 1330 memset(&d->wb, 0, sizeof(d->wb)); 1331 1332 d->wb.middle.length0 = cpu_to_le16((*written)[0]); 1333 1334 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1335 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1336 } 1337 1338 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1339 rss_info, 1340 &d->wb.lower.hi_dword.rss, 1341 &d->wb.lower.mrq, 1342 &d->wb.middle.status_error, 1343 &d->wb.lower.hi_dword.csum_ip.ip_id, 1344 &d->wb.middle.vlan); 1345 1346 d->wb.upper.header_status = 1347 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1348 1349 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1350 (*written)[2], (*written)[3]); 1351 } 1352 1353 static inline void 1354 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc, 1355 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1356 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1357 { 1358 if (e1000e_rx_use_legacy_descriptor(core)) { 1359 assert(ps_hdr_len == 0); 1360 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]); 1361 } else { 1362 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1363 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info, 1364 ps_hdr_len, written); 1365 } else { 1366 assert(ps_hdr_len == 0); 1367 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info, 1368 (*written)[0]); 1369 } 1370 } 1371 } 1372 1373 static inline void 1374 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1375 uint8_t *desc, dma_addr_t len) 1376 { 1377 PCIDevice *dev = core->owner; 1378 1379 if (e1000e_rx_use_legacy_descriptor(core)) { 1380 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc; 1381 size_t offset = offsetof(struct e1000_rx_desc, status); 1382 uint8_t status = d->status; 1383 1384 d->status &= ~E1000_RXD_STAT_DD; 1385 pci_dma_write(dev, addr, desc, len); 1386 1387 if (status & E1000_RXD_STAT_DD) { 1388 d->status = status; 1389 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1390 } 1391 } else { 1392 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1393 union e1000_rx_desc_packet_split *d = 1394 (union e1000_rx_desc_packet_split *) desc; 1395 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1396 wb.middle.status_error); 1397 uint32_t status = d->wb.middle.status_error; 1398 1399 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1400 pci_dma_write(dev, addr, desc, len); 1401 1402 if (status & E1000_RXD_STAT_DD) { 1403 d->wb.middle.status_error = status; 1404 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1405 } 1406 } else { 1407 union e1000_rx_desc_extended *d = 1408 (union e1000_rx_desc_extended *) desc; 1409 size_t offset = offsetof(union e1000_rx_desc_extended, 1410 wb.upper.status_error); 1411 uint32_t status = d->wb.upper.status_error; 1412 1413 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1414 pci_dma_write(dev, addr, desc, len); 1415 1416 if (status & E1000_RXD_STAT_DD) { 1417 d->wb.upper.status_error = status; 1418 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1419 } 1420 } 1421 } 1422 } 1423 1424 typedef struct e1000e_ba_state_st { 1425 uint16_t written[MAX_PS_BUFFERS]; 1426 uint8_t cur_idx; 1427 } e1000e_ba_state; 1428 1429 static inline void 1430 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1431 hwaddr (*ba)[MAX_PS_BUFFERS], 1432 e1000e_ba_state *bastate, 1433 const char *data, 1434 dma_addr_t data_len) 1435 { 1436 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1437 1438 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len); 1439 bastate->written[0] += data_len; 1440 1441 bastate->cur_idx = 1; 1442 } 1443 1444 static void 1445 e1000e_write_to_rx_buffers(E1000ECore *core, 1446 hwaddr (*ba)[MAX_PS_BUFFERS], 1447 e1000e_ba_state *bastate, 1448 const char *data, 1449 dma_addr_t data_len) 1450 { 1451 while (data_len > 0) { 1452 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1453 uint32_t cur_buf_bytes_left = cur_buf_len - 1454 bastate->written[bastate->cur_idx]; 1455 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1456 1457 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1458 (*ba)[bastate->cur_idx], 1459 bastate->written[bastate->cur_idx], 1460 data, 1461 bytes_to_write); 1462 1463 pci_dma_write(core->owner, 1464 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1465 data, bytes_to_write); 1466 1467 bastate->written[bastate->cur_idx] += bytes_to_write; 1468 data += bytes_to_write; 1469 data_len -= bytes_to_write; 1470 1471 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1472 bastate->cur_idx++; 1473 } 1474 1475 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1476 } 1477 } 1478 1479 static void 1480 e1000e_update_rx_stats(E1000ECore *core, 1481 size_t data_size, 1482 size_t data_fcs_size) 1483 { 1484 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1485 1486 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1487 case ETH_PKT_BCAST: 1488 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1489 break; 1490 1491 case ETH_PKT_MCAST: 1492 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1493 break; 1494 1495 default: 1496 break; 1497 } 1498 } 1499 1500 static inline bool 1501 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1502 { 1503 return e1000e_ring_free_descr_num(core, rxi) == 1504 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1505 } 1506 1507 static bool 1508 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1509 { 1510 bool isip4, isip6, isudp, istcp; 1511 bool fragment; 1512 1513 if (!e1000e_rx_use_ps_descriptor(core)) { 1514 return false; 1515 } 1516 1517 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1518 1519 if (isip4) { 1520 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1521 } else if (isip6) { 1522 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1523 } else { 1524 return false; 1525 } 1526 1527 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1528 return false; 1529 } 1530 1531 if (!fragment && (isudp || istcp)) { 1532 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1533 } else { 1534 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1535 } 1536 1537 if ((*hdr_len > core->rxbuf_sizes[0]) || 1538 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1539 return false; 1540 } 1541 1542 return true; 1543 } 1544 1545 static void 1546 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1547 const E1000E_RxRing *rxr, 1548 const E1000E_RSSInfo *rss_info) 1549 { 1550 PCIDevice *d = core->owner; 1551 dma_addr_t base; 1552 uint8_t desc[E1000_MAX_RX_DESC_LEN]; 1553 size_t desc_size; 1554 size_t desc_offset = 0; 1555 size_t iov_ofs = 0; 1556 1557 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1558 size_t size = net_rx_pkt_get_total_len(pkt); 1559 size_t total_size = size + e1000x_fcs_len(core->mac); 1560 const E1000E_RingInfo *rxi; 1561 size_t ps_hdr_len = 0; 1562 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1563 bool is_first = true; 1564 1565 rxi = rxr->i; 1566 1567 do { 1568 hwaddr ba[MAX_PS_BUFFERS]; 1569 e1000e_ba_state bastate = { { 0 } }; 1570 bool is_last = false; 1571 1572 desc_size = total_size - desc_offset; 1573 1574 if (desc_size > core->rx_desc_buf_size) { 1575 desc_size = core->rx_desc_buf_size; 1576 } 1577 1578 if (e1000e_ring_empty(core, rxi)) { 1579 return; 1580 } 1581 1582 base = e1000e_ring_head_descr(core, rxi); 1583 1584 pci_dma_read(d, base, &desc, core->rx_desc_len); 1585 1586 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1587 1588 e1000e_read_rx_descr(core, desc, &ba); 1589 1590 if (ba[0]) { 1591 if (desc_offset < size) { 1592 static const uint32_t fcs_pad; 1593 size_t iov_copy; 1594 size_t copy_size = size - desc_offset; 1595 if (copy_size > core->rx_desc_buf_size) { 1596 copy_size = core->rx_desc_buf_size; 1597 } 1598 1599 /* For PS mode copy the packet header first */ 1600 if (do_ps) { 1601 if (is_first) { 1602 size_t ps_hdr_copied = 0; 1603 do { 1604 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1605 iov->iov_len - iov_ofs); 1606 1607 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate, 1608 iov->iov_base, iov_copy); 1609 1610 copy_size -= iov_copy; 1611 ps_hdr_copied += iov_copy; 1612 1613 iov_ofs += iov_copy; 1614 if (iov_ofs == iov->iov_len) { 1615 iov++; 1616 iov_ofs = 0; 1617 } 1618 } while (ps_hdr_copied < ps_hdr_len); 1619 1620 is_first = false; 1621 } else { 1622 /* Leave buffer 0 of each descriptor except first */ 1623 /* empty as per spec 7.1.5.1 */ 1624 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate, 1625 NULL, 0); 1626 } 1627 } 1628 1629 /* Copy packet payload */ 1630 while (copy_size) { 1631 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1632 1633 e1000e_write_to_rx_buffers(core, &ba, &bastate, 1634 iov->iov_base + iov_ofs, iov_copy); 1635 1636 copy_size -= iov_copy; 1637 iov_ofs += iov_copy; 1638 if (iov_ofs == iov->iov_len) { 1639 iov++; 1640 iov_ofs = 0; 1641 } 1642 } 1643 1644 if (desc_offset + desc_size >= total_size) { 1645 /* Simulate FCS checksum presence in the last descriptor */ 1646 e1000e_write_to_rx_buffers(core, &ba, &bastate, 1647 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1648 } 1649 } 1650 } else { /* as per intel docs; skip descriptors with null buf addr */ 1651 trace_e1000e_rx_null_descriptor(); 1652 } 1653 desc_offset += desc_size; 1654 if (desc_offset >= total_size) { 1655 is_last = true; 1656 } 1657 1658 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL, 1659 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1660 e1000e_pci_dma_write_rx_desc(core, base, desc, core->rx_desc_len); 1661 1662 e1000e_ring_advance(core, rxi, 1663 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1664 1665 } while (desc_offset < total_size); 1666 1667 e1000e_update_rx_stats(core, size, total_size); 1668 } 1669 1670 static inline void 1671 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1672 { 1673 if (net_rx_pkt_has_virt_hdr(pkt)) { 1674 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1675 1676 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1677 net_rx_pkt_fix_l4_csum(pkt); 1678 } 1679 } 1680 } 1681 1682 /* Min. octets in an ethernet frame sans FCS */ 1683 #define MIN_BUF_SIZE 60 1684 1685 ssize_t 1686 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1687 { 1688 static const int maximum_ethernet_hdr_len = (14 + 4); 1689 1690 uint32_t n = 0; 1691 uint8_t min_buf[MIN_BUF_SIZE]; 1692 struct iovec min_iov; 1693 uint8_t *filter_buf; 1694 size_t size, orig_size; 1695 size_t iov_ofs = 0; 1696 E1000E_RxRing rxr; 1697 E1000E_RSSInfo rss_info; 1698 size_t total_size; 1699 ssize_t retval; 1700 bool rdmts_hit; 1701 1702 trace_e1000e_rx_receive_iov(iovcnt); 1703 1704 if (!e1000x_hw_rx_enabled(core->mac)) { 1705 return -1; 1706 } 1707 1708 /* Pull virtio header in */ 1709 if (core->has_vnet) { 1710 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1711 iov_ofs = sizeof(struct virtio_net_hdr); 1712 } 1713 1714 filter_buf = iov->iov_base + iov_ofs; 1715 orig_size = iov_size(iov, iovcnt); 1716 size = orig_size - iov_ofs; 1717 1718 /* Pad to minimum Ethernet frame length */ 1719 if (size < sizeof(min_buf)) { 1720 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1721 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1722 e1000x_inc_reg_if_not_full(core->mac, RUC); 1723 min_iov.iov_base = filter_buf = min_buf; 1724 min_iov.iov_len = size = sizeof(min_buf); 1725 iovcnt = 1; 1726 iov = &min_iov; 1727 iov_ofs = 0; 1728 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1729 /* This is very unlikely, but may happen. */ 1730 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1731 filter_buf = min_buf; 1732 } 1733 1734 /* Discard oversized packets if !LPE and !SBP. */ 1735 if (e1000x_is_oversized(core->mac, size)) { 1736 return orig_size; 1737 } 1738 1739 net_rx_pkt_set_packet_type(core->rx_pkt, 1740 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf))); 1741 1742 if (!e1000e_receive_filter(core, filter_buf, size)) { 1743 trace_e1000e_rx_flt_dropped(); 1744 return orig_size; 1745 } 1746 1747 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1748 e1000x_vlan_enabled(core->mac), core->mac[VET]); 1749 1750 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1751 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1752 1753 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx); 1754 1755 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1756 e1000x_fcs_len(core->mac); 1757 1758 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1759 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1760 1761 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1762 1763 retval = orig_size; 1764 1765 /* Perform small receive detection (RSRPD) */ 1766 if (total_size < core->mac[RSRPD]) { 1767 n |= E1000_ICS_SRPD; 1768 } 1769 1770 /* Perform ACK receive detection */ 1771 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1772 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1773 n |= E1000_ICS_ACK; 1774 } 1775 1776 /* Check if receive descriptor minimum threshold hit */ 1777 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1778 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1779 1780 trace_e1000e_rx_written_to_guest(n); 1781 } else { 1782 n |= E1000_ICS_RXO; 1783 retval = 0; 1784 1785 trace_e1000e_rx_not_written_to_guest(n); 1786 } 1787 1788 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1789 trace_e1000e_rx_interrupt_set(n); 1790 e1000e_set_interrupt_cause(core, n); 1791 } else { 1792 trace_e1000e_rx_interrupt_delayed(n); 1793 } 1794 1795 return retval; 1796 } 1797 1798 static inline bool 1799 e1000e_have_autoneg(E1000ECore *core) 1800 { 1801 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1802 } 1803 1804 static void e1000e_update_flowctl_status(E1000ECore *core) 1805 { 1806 if (e1000e_have_autoneg(core) && 1807 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1808 trace_e1000e_link_autoneg_flowctl(true); 1809 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1810 } else { 1811 trace_e1000e_link_autoneg_flowctl(false); 1812 } 1813 } 1814 1815 static inline void 1816 e1000e_link_down(E1000ECore *core) 1817 { 1818 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1819 e1000e_update_flowctl_status(core); 1820 } 1821 1822 static inline void 1823 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1824 { 1825 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1826 core->phy[0][MII_BMCR] = val & ~(0x3f | 1827 MII_BMCR_RESET | 1828 MII_BMCR_ANRESTART); 1829 1830 if ((val & MII_BMCR_ANRESTART) && 1831 e1000e_have_autoneg(core)) { 1832 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1833 } 1834 } 1835 1836 static void 1837 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1838 { 1839 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1840 1841 if (val & BIT(10)) { 1842 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1843 } 1844 } 1845 1846 static void 1847 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1848 { 1849 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1850 } 1851 1852 void 1853 e1000e_core_set_link_status(E1000ECore *core) 1854 { 1855 NetClientState *nc = qemu_get_queue(core->owner_nic); 1856 uint32_t old_status = core->mac[STATUS]; 1857 1858 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1859 1860 if (nc->link_down) { 1861 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1862 } else { 1863 if (e1000e_have_autoneg(core) && 1864 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1865 e1000x_restart_autoneg(core->mac, core->phy[0], 1866 core->autoneg_timer); 1867 } else { 1868 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1869 e1000e_start_recv(core); 1870 } 1871 } 1872 1873 if (core->mac[STATUS] != old_status) { 1874 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1875 } 1876 } 1877 1878 static void 1879 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1880 { 1881 trace_e1000e_core_ctrl_write(index, val); 1882 1883 /* RST is self clearing */ 1884 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1885 core->mac[CTRL_DUP] = core->mac[CTRL]; 1886 1887 trace_e1000e_link_set_params( 1888 !!(val & E1000_CTRL_ASDE), 1889 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1890 !!(val & E1000_CTRL_FRCSPD), 1891 !!(val & E1000_CTRL_FRCDPX), 1892 !!(val & E1000_CTRL_RFCE), 1893 !!(val & E1000_CTRL_TFCE)); 1894 1895 if (val & E1000_CTRL_RST) { 1896 trace_e1000e_core_ctrl_sw_reset(); 1897 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 1898 } 1899 1900 if (val & E1000_CTRL_PHY_RST) { 1901 trace_e1000e_core_ctrl_phy_reset(); 1902 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1903 } 1904 } 1905 1906 static void 1907 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1908 { 1909 trace_e1000e_rx_set_rfctl(val); 1910 1911 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1912 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1913 } 1914 1915 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1916 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1917 } 1918 1919 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1920 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1921 } 1922 1923 core->mac[RFCTL] = val; 1924 } 1925 1926 static void 1927 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1928 { 1929 int i; 1930 core->rx_desc_buf_size = 0; 1931 1932 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1933 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1934 } 1935 } 1936 1937 static void 1938 e1000e_parse_rxbufsize(E1000ECore *core) 1939 { 1940 uint32_t rctl = core->mac[RCTL]; 1941 1942 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1943 1944 if (rctl & E1000_RCTL_DTYP_MASK) { 1945 uint32_t bsize; 1946 1947 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1948 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1949 1950 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1951 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1952 1953 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1954 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1955 1956 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1957 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1958 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1959 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1960 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1961 } else { 1962 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1963 } 1964 1965 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1966 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1967 1968 e1000e_calc_per_desc_buf_size(core); 1969 } 1970 1971 static void 1972 e1000e_calc_rxdesclen(E1000ECore *core) 1973 { 1974 if (e1000e_rx_use_legacy_descriptor(core)) { 1975 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1976 } else { 1977 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1978 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1979 } else { 1980 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1981 } 1982 } 1983 trace_e1000e_rx_desc_len(core->rx_desc_len); 1984 } 1985 1986 static void 1987 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1988 { 1989 core->mac[RCTL] = val; 1990 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1991 1992 if (val & E1000_RCTL_EN) { 1993 e1000e_parse_rxbufsize(core); 1994 e1000e_calc_rxdesclen(core); 1995 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1996 E1000_RING_DESC_LEN_SHIFT; 1997 1998 e1000e_start_recv(core); 1999 } 2000 } 2001 2002 static 2003 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 2004 (E1000ECore *, int, uint16_t) = { 2005 [0] = { 2006 [MII_BMCR] = e1000e_set_phy_ctrl, 2007 [PHY_PAGE] = e1000e_set_phy_page, 2008 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 2009 } 2010 }; 2011 2012 static inline void 2013 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 2014 { 2015 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 2016 core->mac[IMS] &= ~bits; 2017 } 2018 2019 static inline bool 2020 e1000e_postpone_interrupt(bool *interrupt_pending, 2021 E1000IntrDelayTimer *timer) 2022 { 2023 if (timer->running) { 2024 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 2025 2026 *interrupt_pending = true; 2027 return true; 2028 } 2029 2030 if (timer->core->mac[timer->delay_reg] != 0) { 2031 e1000e_intrmgr_rearm_timer(timer); 2032 } 2033 2034 return false; 2035 } 2036 2037 static inline bool 2038 e1000e_itr_should_postpone(E1000ECore *core) 2039 { 2040 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr); 2041 } 2042 2043 static inline bool 2044 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 2045 { 2046 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx], 2047 &core->eitr[idx]); 2048 } 2049 2050 static void 2051 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2052 { 2053 uint32_t effective_eiac; 2054 2055 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2056 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2057 if (vec < E1000E_MSIX_VEC_NUM) { 2058 if (!e1000e_eitr_should_postpone(core, vec)) { 2059 trace_e1000e_irq_msix_notify_vec(vec); 2060 msix_notify(core->owner, vec); 2061 } 2062 } else { 2063 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2064 } 2065 } else { 2066 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2067 } 2068 2069 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2070 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2071 core->mac[IAM] &= ~cause; 2072 } 2073 2074 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2075 2076 effective_eiac = core->mac[EIAC] & cause; 2077 2078 core->mac[ICR] &= ~effective_eiac; 2079 core->msi_causes_pending &= ~effective_eiac; 2080 2081 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2082 core->mac[IMS] &= ~effective_eiac; 2083 } 2084 } 2085 2086 static void 2087 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2088 { 2089 if (causes & E1000_ICR_RXQ0) { 2090 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2091 E1000_IVAR_RXQ0(core->mac[IVAR])); 2092 } 2093 2094 if (causes & E1000_ICR_RXQ1) { 2095 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2096 E1000_IVAR_RXQ1(core->mac[IVAR])); 2097 } 2098 2099 if (causes & E1000_ICR_TXQ0) { 2100 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2101 E1000_IVAR_TXQ0(core->mac[IVAR])); 2102 } 2103 2104 if (causes & E1000_ICR_TXQ1) { 2105 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2106 E1000_IVAR_TXQ1(core->mac[IVAR])); 2107 } 2108 2109 if (causes & E1000_ICR_OTHER) { 2110 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2111 E1000_IVAR_OTHER(core->mac[IVAR])); 2112 } 2113 } 2114 2115 static void 2116 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2117 { 2118 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2119 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2120 if (vec < E1000E_MSIX_VEC_NUM) { 2121 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2122 msix_clr_pending(core->owner, vec); 2123 } else { 2124 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2125 } 2126 } else { 2127 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2128 } 2129 } 2130 2131 static void 2132 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2133 { 2134 if (causes & E1000_ICR_RXQ0) { 2135 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2136 E1000_IVAR_RXQ0(core->mac[IVAR])); 2137 } 2138 2139 if (causes & E1000_ICR_RXQ1) { 2140 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2141 E1000_IVAR_RXQ1(core->mac[IVAR])); 2142 } 2143 2144 if (causes & E1000_ICR_TXQ0) { 2145 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2146 E1000_IVAR_TXQ0(core->mac[IVAR])); 2147 } 2148 2149 if (causes & E1000_ICR_TXQ1) { 2150 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2151 E1000_IVAR_TXQ1(core->mac[IVAR])); 2152 } 2153 2154 if (causes & E1000_ICR_OTHER) { 2155 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2156 E1000_IVAR_OTHER(core->mac[IVAR])); 2157 } 2158 } 2159 2160 static inline void 2161 e1000e_fix_icr_asserted(E1000ECore *core) 2162 { 2163 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2164 if (core->mac[ICR]) { 2165 core->mac[ICR] |= E1000_ICR_ASSERTED; 2166 } 2167 2168 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2169 } 2170 2171 static void 2172 e1000e_send_msi(E1000ECore *core, bool msix) 2173 { 2174 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2175 2176 core->msi_causes_pending &= causes; 2177 causes ^= core->msi_causes_pending; 2178 if (causes == 0) { 2179 return; 2180 } 2181 core->msi_causes_pending |= causes; 2182 2183 if (msix) { 2184 e1000e_msix_notify(core, causes); 2185 } else { 2186 if (!e1000e_itr_should_postpone(core)) { 2187 trace_e1000e_irq_msi_notify(causes); 2188 msi_notify(core->owner, 0); 2189 } 2190 } 2191 } 2192 2193 static void 2194 e1000e_update_interrupt_state(E1000ECore *core) 2195 { 2196 bool interrupts_pending; 2197 bool is_msix = msix_enabled(core->owner); 2198 2199 /* Set ICR[OTHER] for MSI-X */ 2200 if (is_msix) { 2201 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2202 core->mac[ICR] |= E1000_ICR_OTHER; 2203 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2204 } 2205 } 2206 2207 e1000e_fix_icr_asserted(core); 2208 2209 /* 2210 * Make sure ICR and ICS registers have the same value. 2211 * The spec says that the ICS register is write-only. However in practice, 2212 * on real hardware ICS is readable, and for reads it has the same value as 2213 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2214 * 2215 * The VxWorks PRO/1000 driver uses this behaviour. 2216 */ 2217 core->mac[ICS] = core->mac[ICR]; 2218 2219 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2220 if (!interrupts_pending) { 2221 core->msi_causes_pending = 0; 2222 } 2223 2224 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2225 core->mac[ICR], core->mac[IMS]); 2226 2227 if (is_msix || msi_enabled(core->owner)) { 2228 if (interrupts_pending) { 2229 e1000e_send_msi(core, is_msix); 2230 } 2231 } else { 2232 if (interrupts_pending) { 2233 if (!e1000e_itr_should_postpone(core)) { 2234 e1000e_raise_legacy_irq(core); 2235 } 2236 } else { 2237 e1000e_lower_legacy_irq(core); 2238 } 2239 } 2240 } 2241 2242 static void 2243 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2244 { 2245 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2246 2247 val |= e1000e_intmgr_collect_delayed_causes(core); 2248 core->mac[ICR] |= val; 2249 2250 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2251 2252 e1000e_update_interrupt_state(core); 2253 } 2254 2255 static inline void 2256 e1000e_autoneg_timer(void *opaque) 2257 { 2258 E1000ECore *core = opaque; 2259 if (!qemu_get_queue(core->owner_nic)->link_down) { 2260 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2261 e1000e_start_recv(core); 2262 2263 e1000e_update_flowctl_status(core); 2264 /* signal link status change to the guest */ 2265 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2266 } 2267 } 2268 2269 static inline uint16_t 2270 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2271 { 2272 uint16_t index = (addr & 0x1ffff) >> 2; 2273 return index + (mac_reg_access[index] & 0xfffe); 2274 } 2275 2276 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2277 [0] = { 2278 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2279 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2280 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2281 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2282 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2283 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2284 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2285 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2286 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2287 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2288 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2289 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2290 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2291 2292 [PHY_COPPER_CTRL1] = PHY_RW, 2293 [PHY_COPPER_STAT1] = PHY_R, 2294 [PHY_COPPER_CTRL3] = PHY_RW, 2295 [PHY_RX_ERR_CNTR] = PHY_R, 2296 [PHY_OEM_BITS] = PHY_RW, 2297 [PHY_BIAS_1] = PHY_RW, 2298 [PHY_BIAS_2] = PHY_RW, 2299 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2300 [PHY_COPPER_STAT2] = PHY_R, 2301 [PHY_COPPER_CTRL2] = PHY_RW 2302 }, 2303 [2] = { 2304 [PHY_MAC_CTRL1] = PHY_RW, 2305 [PHY_MAC_INT_ENABLE] = PHY_RW, 2306 [PHY_MAC_STAT] = PHY_R, 2307 [PHY_MAC_CTRL2] = PHY_RW 2308 }, 2309 [3] = { 2310 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2311 [PHY_LED_03_POL_CTRL] = PHY_RW, 2312 [PHY_LED_TIMER_CTRL] = PHY_RW, 2313 [PHY_LED_45_CTRL] = PHY_RW 2314 }, 2315 [5] = { 2316 [PHY_1000T_SKEW] = PHY_R, 2317 [PHY_1000T_SWAP] = PHY_R 2318 }, 2319 [6] = { 2320 [PHY_CRC_COUNTERS] = PHY_R 2321 } 2322 }; 2323 2324 static bool 2325 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2326 char cap, uint8_t *page) 2327 { 2328 *page = 2329 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2330 : core->phy[0][PHY_PAGE]; 2331 2332 if (*page >= E1000E_PHY_PAGES) { 2333 return false; 2334 } 2335 2336 return e1000e_phy_regcap[*page][addr] & cap; 2337 } 2338 2339 static void 2340 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2341 uint32_t addr, uint16_t data) 2342 { 2343 assert(page < E1000E_PHY_PAGES); 2344 assert(addr < E1000E_PHY_PAGE_SIZE); 2345 2346 if (e1000e_phyreg_writeops[page][addr]) { 2347 e1000e_phyreg_writeops[page][addr](core, addr, data); 2348 } else { 2349 core->phy[page][addr] = data; 2350 } 2351 } 2352 2353 static void 2354 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2355 { 2356 uint32_t data = val & E1000_MDIC_DATA_MASK; 2357 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2358 uint8_t page; 2359 2360 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2361 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2362 } else if (val & E1000_MDIC_OP_READ) { 2363 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2364 trace_e1000e_core_mdic_read_unhandled(page, addr); 2365 val |= E1000_MDIC_ERROR; 2366 } else { 2367 val = (val ^ data) | core->phy[page][addr]; 2368 trace_e1000e_core_mdic_read(page, addr, val); 2369 } 2370 } else if (val & E1000_MDIC_OP_WRITE) { 2371 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2372 trace_e1000e_core_mdic_write_unhandled(page, addr); 2373 val |= E1000_MDIC_ERROR; 2374 } else { 2375 trace_e1000e_core_mdic_write(page, addr, data); 2376 e1000e_phy_reg_write(core, page, addr, data); 2377 } 2378 } 2379 core->mac[MDIC] = val | E1000_MDIC_READY; 2380 2381 if (val & E1000_MDIC_INT_EN) { 2382 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2383 } 2384 } 2385 2386 static void 2387 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2388 { 2389 core->mac[index] = val & 0xffff; 2390 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2391 e1000e_start_recv(core); 2392 } 2393 2394 static void 2395 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2396 { 2397 if ((val & E1000_STATUS_PHYRA) == 0) { 2398 core->mac[index] &= ~E1000_STATUS_PHYRA; 2399 } 2400 } 2401 2402 static void 2403 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2404 { 2405 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2406 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2407 2408 /* Zero self-clearing bits */ 2409 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2410 core->mac[CTRL_EXT] = val; 2411 } 2412 2413 static void 2414 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2415 { 2416 int i; 2417 2418 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2419 2420 if (!msix_enabled(core->owner)) { 2421 return; 2422 } 2423 2424 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2425 if (core->mac[PBACLR] & BIT(i)) { 2426 msix_clr_pending(core->owner, i); 2427 } 2428 } 2429 } 2430 2431 static void 2432 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2433 { 2434 core->mac[FCRTH] = val & 0xFFF8; 2435 } 2436 2437 static void 2438 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2439 { 2440 core->mac[FCRTL] = val & 0x8000FFF8; 2441 } 2442 2443 static inline void 2444 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val) 2445 { 2446 core->mac[index] = val & 0xffff; 2447 } 2448 2449 static void 2450 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val) 2451 { 2452 core->mac[index] = val & 0xfff; 2453 } 2454 2455 static void 2456 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2457 { 2458 core->mac[VET] = val & 0xffff; 2459 trace_e1000e_vlan_vet(core->mac[VET]); 2460 } 2461 2462 static void 2463 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2464 { 2465 core->mac[index] = val & E1000_XDLEN_MASK; 2466 } 2467 2468 static void 2469 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2470 { 2471 core->mac[index] = val & E1000_XDBAL_MASK; 2472 } 2473 2474 static void 2475 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2476 { 2477 E1000E_TxRing txr; 2478 core->mac[index] = val; 2479 2480 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2481 e1000e_tx_ring_init(core, &txr, 0); 2482 e1000e_start_xmit(core, &txr); 2483 } 2484 2485 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2486 e1000e_tx_ring_init(core, &txr, 1); 2487 e1000e_start_xmit(core, &txr); 2488 } 2489 } 2490 2491 static void 2492 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2493 { 2494 E1000E_TxRing txr; 2495 int qidx = e1000e_mq_queue_idx(TDT, index); 2496 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2497 2498 core->mac[index] = val & 0xffff; 2499 2500 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2501 e1000e_tx_ring_init(core, &txr, qidx); 2502 e1000e_start_xmit(core, &txr); 2503 } 2504 } 2505 2506 static void 2507 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2508 { 2509 trace_e1000e_irq_write_ics(val); 2510 e1000e_set_interrupt_cause(core, val); 2511 } 2512 2513 static void 2514 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2515 { 2516 uint32_t icr = 0; 2517 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2518 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2519 trace_e1000e_irq_icr_process_iame(); 2520 e1000e_clear_ims_bits(core, core->mac[IAM]); 2521 } 2522 2523 icr = core->mac[ICR] & ~val; 2524 /* 2525 * Windows driver expects that the "receive overrun" bit and other 2526 * ones to be cleared when the "Other" bit (#24) is cleared. 2527 */ 2528 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr; 2529 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); 2530 core->mac[ICR] = icr; 2531 e1000e_update_interrupt_state(core); 2532 } 2533 2534 static void 2535 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2536 { 2537 trace_e1000e_irq_ims_clear_set_imc(val); 2538 e1000e_clear_ims_bits(core, val); 2539 e1000e_update_interrupt_state(core); 2540 } 2541 2542 static void 2543 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2544 { 2545 static const uint32_t ims_ext_mask = 2546 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2547 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2548 E1000_IMS_OTHER; 2549 2550 static const uint32_t ims_valid_mask = 2551 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2552 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2553 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2554 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2555 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2556 E1000_IMS_OTHER; 2557 2558 uint32_t valid_val = val & ims_valid_mask; 2559 2560 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2561 core->mac[IMS] |= valid_val; 2562 2563 if ((valid_val & ims_ext_mask) && 2564 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2565 msix_enabled(core->owner)) { 2566 e1000e_msix_clear(core, valid_val); 2567 } 2568 2569 if ((valid_val == ims_valid_mask) && 2570 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2571 trace_e1000e_irq_fire_all_timers(val); 2572 e1000e_intrmgr_fire_all_timers(core); 2573 } 2574 2575 e1000e_update_interrupt_state(core); 2576 } 2577 2578 static void 2579 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2580 { 2581 e1000e_set_16bit(core, index, val); 2582 2583 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2584 trace_e1000e_irq_rdtr_fpd_running(); 2585 e1000e_intrmgr_fire_delayed_interrupts(core); 2586 } else { 2587 trace_e1000e_irq_rdtr_fpd_not_running(); 2588 } 2589 } 2590 2591 static void 2592 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2593 { 2594 e1000e_set_16bit(core, index, val); 2595 2596 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2597 trace_e1000e_irq_tidv_fpd_running(); 2598 e1000e_intrmgr_fire_delayed_interrupts(core); 2599 } else { 2600 trace_e1000e_irq_tidv_fpd_not_running(); 2601 } 2602 } 2603 2604 static uint32_t 2605 e1000e_mac_readreg(E1000ECore *core, int index) 2606 { 2607 return core->mac[index]; 2608 } 2609 2610 static uint32_t 2611 e1000e_mac_ics_read(E1000ECore *core, int index) 2612 { 2613 trace_e1000e_irq_read_ics(core->mac[ICS]); 2614 return core->mac[ICS]; 2615 } 2616 2617 static uint32_t 2618 e1000e_mac_ims_read(E1000ECore *core, int index) 2619 { 2620 trace_e1000e_irq_read_ims(core->mac[IMS]); 2621 return core->mac[IMS]; 2622 } 2623 2624 #define E1000E_LOW_BITS_READ_FUNC(num) \ 2625 static uint32_t \ 2626 e1000e_mac_low##num##_read(E1000ECore *core, int index) \ 2627 { \ 2628 return core->mac[index] & (BIT(num) - 1); \ 2629 } \ 2630 2631 #define E1000E_LOW_BITS_READ(num) \ 2632 e1000e_mac_low##num##_read 2633 2634 E1000E_LOW_BITS_READ_FUNC(4); 2635 E1000E_LOW_BITS_READ_FUNC(6); 2636 E1000E_LOW_BITS_READ_FUNC(11); 2637 E1000E_LOW_BITS_READ_FUNC(13); 2638 E1000E_LOW_BITS_READ_FUNC(16); 2639 2640 static uint32_t 2641 e1000e_mac_swsm_read(E1000ECore *core, int index) 2642 { 2643 uint32_t val = core->mac[SWSM]; 2644 core->mac[SWSM] = val | 1; 2645 return val; 2646 } 2647 2648 static uint32_t 2649 e1000e_mac_itr_read(E1000ECore *core, int index) 2650 { 2651 return core->itr_guest_value; 2652 } 2653 2654 static uint32_t 2655 e1000e_mac_eitr_read(E1000ECore *core, int index) 2656 { 2657 return core->eitr_guest_value[index - EITR]; 2658 } 2659 2660 static uint32_t 2661 e1000e_mac_icr_read(E1000ECore *core, int index) 2662 { 2663 uint32_t ret = core->mac[ICR]; 2664 trace_e1000e_irq_icr_read_entry(ret); 2665 2666 if (core->mac[IMS] == 0) { 2667 trace_e1000e_irq_icr_clear_zero_ims(); 2668 core->mac[ICR] = 0; 2669 } 2670 2671 if (!msix_enabled(core->owner)) { 2672 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2673 core->mac[ICR] = 0; 2674 } 2675 2676 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2677 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2678 trace_e1000e_irq_icr_clear_iame(); 2679 core->mac[ICR] = 0; 2680 trace_e1000e_irq_icr_process_iame(); 2681 e1000e_clear_ims_bits(core, core->mac[IAM]); 2682 } 2683 2684 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2685 e1000e_update_interrupt_state(core); 2686 return ret; 2687 } 2688 2689 static uint32_t 2690 e1000e_mac_read_clr4(E1000ECore *core, int index) 2691 { 2692 uint32_t ret = core->mac[index]; 2693 2694 core->mac[index] = 0; 2695 return ret; 2696 } 2697 2698 static uint32_t 2699 e1000e_mac_read_clr8(E1000ECore *core, int index) 2700 { 2701 uint32_t ret = core->mac[index]; 2702 2703 core->mac[index] = 0; 2704 core->mac[index - 1] = 0; 2705 return ret; 2706 } 2707 2708 static uint32_t 2709 e1000e_get_ctrl(E1000ECore *core, int index) 2710 { 2711 uint32_t val = core->mac[CTRL]; 2712 2713 trace_e1000e_link_read_params( 2714 !!(val & E1000_CTRL_ASDE), 2715 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2716 !!(val & E1000_CTRL_FRCSPD), 2717 !!(val & E1000_CTRL_FRCDPX), 2718 !!(val & E1000_CTRL_RFCE), 2719 !!(val & E1000_CTRL_TFCE)); 2720 2721 return val; 2722 } 2723 2724 static uint32_t 2725 e1000e_get_status(E1000ECore *core, int index) 2726 { 2727 uint32_t res = core->mac[STATUS]; 2728 2729 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2730 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2731 } 2732 2733 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2734 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2735 } else { 2736 res |= E1000_STATUS_FD; 2737 } 2738 2739 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2740 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2741 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2742 case E1000_CTRL_SPD_10: 2743 res |= E1000_STATUS_SPEED_10; 2744 break; 2745 case E1000_CTRL_SPD_100: 2746 res |= E1000_STATUS_SPEED_100; 2747 break; 2748 case E1000_CTRL_SPD_1000: 2749 default: 2750 res |= E1000_STATUS_SPEED_1000; 2751 break; 2752 } 2753 } else { 2754 res |= E1000_STATUS_SPEED_1000; 2755 } 2756 2757 trace_e1000e_link_status( 2758 !!(res & E1000_STATUS_LU), 2759 !!(res & E1000_STATUS_FD), 2760 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2761 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2762 2763 return res; 2764 } 2765 2766 static uint32_t 2767 e1000e_get_tarc(E1000ECore *core, int index) 2768 { 2769 return core->mac[index] & ((BIT(11) - 1) | 2770 BIT(27) | 2771 BIT(28) | 2772 BIT(29) | 2773 BIT(30)); 2774 } 2775 2776 static void 2777 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2778 { 2779 core->mac[index] = val; 2780 } 2781 2782 static void 2783 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2784 { 2785 uint32_t macaddr[2]; 2786 2787 core->mac[index] = val; 2788 2789 macaddr[0] = cpu_to_le32(core->mac[RA]); 2790 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2791 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2792 (uint8_t *) macaddr); 2793 2794 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2795 } 2796 2797 static void 2798 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2799 { 2800 static const uint32_t ro_bits = E1000_EECD_PRES | 2801 E1000_EECD_AUTO_RD | 2802 E1000_EECD_SIZE_EX_MASK; 2803 2804 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2805 } 2806 2807 static void 2808 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2809 { 2810 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2811 uint32_t flags = 0; 2812 uint32_t data = 0; 2813 2814 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2815 data = core->eeprom[addr]; 2816 flags = E1000_EERW_DONE; 2817 } 2818 2819 core->mac[EERD] = flags | 2820 (addr << E1000_EERW_ADDR_SHIFT) | 2821 (data << E1000_EERW_DATA_SHIFT); 2822 } 2823 2824 static void 2825 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2826 { 2827 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2828 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2829 uint32_t flags = 0; 2830 2831 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2832 core->eeprom[addr] = data; 2833 flags = E1000_EERW_DONE; 2834 } 2835 2836 core->mac[EERD] = flags | 2837 (addr << E1000_EERW_ADDR_SHIFT) | 2838 (data << E1000_EERW_DATA_SHIFT); 2839 } 2840 2841 static void 2842 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2843 { 2844 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2845 } 2846 2847 static void 2848 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2849 { 2850 uint32_t interval = val & 0xffff; 2851 2852 trace_e1000e_irq_itr_set(val); 2853 2854 core->itr_guest_value = interval; 2855 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2856 } 2857 2858 static void 2859 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2860 { 2861 uint32_t interval = val & 0xffff; 2862 uint32_t eitr_num = index - EITR; 2863 2864 trace_e1000e_irq_eitr_set(eitr_num, val); 2865 2866 core->eitr_guest_value[eitr_num] = interval; 2867 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2868 } 2869 2870 static void 2871 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2872 { 2873 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2874 2875 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2876 qemu_log_mask(LOG_GUEST_ERROR, 2877 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2878 return; 2879 } 2880 2881 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2882 qemu_log_mask(LOG_GUEST_ERROR, 2883 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2884 return; 2885 } 2886 } 2887 2888 core->mac[PSRCTL] = val; 2889 } 2890 2891 static void 2892 e1000e_update_rx_offloads(E1000ECore *core) 2893 { 2894 int cso_state = e1000e_rx_l4_cso_enabled(core); 2895 2896 trace_e1000e_rx_set_cso(cso_state); 2897 2898 if (core->has_vnet) { 2899 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2900 cso_state, 0, 0, 0, 0); 2901 } 2902 } 2903 2904 static void 2905 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2906 { 2907 core->mac[RXCSUM] = val; 2908 e1000e_update_rx_offloads(core); 2909 } 2910 2911 static void 2912 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2913 { 2914 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2915 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2916 } 2917 2918 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2919 typedef uint32_t (*readops)(E1000ECore *, int); 2920 static const readops e1000e_macreg_readops[] = { 2921 e1000e_getreg(PBA), 2922 e1000e_getreg(WUFC), 2923 e1000e_getreg(MANC), 2924 e1000e_getreg(TOTL), 2925 e1000e_getreg(RDT0), 2926 e1000e_getreg(RDBAH0), 2927 e1000e_getreg(TDBAL1), 2928 e1000e_getreg(RDLEN0), 2929 e1000e_getreg(RDH1), 2930 e1000e_getreg(LATECOL), 2931 e1000e_getreg(SEQEC), 2932 e1000e_getreg(XONTXC), 2933 e1000e_getreg(WUS), 2934 e1000e_getreg(GORCL), 2935 e1000e_getreg(MGTPRC), 2936 e1000e_getreg(EERD), 2937 e1000e_getreg(EIAC), 2938 e1000e_getreg(PSRCTL), 2939 e1000e_getreg(MANC2H), 2940 e1000e_getreg(RXCSUM), 2941 e1000e_getreg(GSCL_3), 2942 e1000e_getreg(GSCN_2), 2943 e1000e_getreg(RSRPD), 2944 e1000e_getreg(RDBAL1), 2945 e1000e_getreg(FCAH), 2946 e1000e_getreg(FCRTH), 2947 e1000e_getreg(FLOP), 2948 e1000e_getreg(FLASHT), 2949 e1000e_getreg(RXSTMPH), 2950 e1000e_getreg(TXSTMPL), 2951 e1000e_getreg(TIMADJL), 2952 e1000e_getreg(TXDCTL), 2953 e1000e_getreg(RDH0), 2954 e1000e_getreg(TDT1), 2955 e1000e_getreg(TNCRS), 2956 e1000e_getreg(RJC), 2957 e1000e_getreg(IAM), 2958 e1000e_getreg(GSCL_2), 2959 e1000e_getreg(RDBAH1), 2960 e1000e_getreg(FLSWDATA), 2961 e1000e_getreg(RXSATRH), 2962 e1000e_getreg(TIPG), 2963 e1000e_getreg(FLMNGCTL), 2964 e1000e_getreg(FLMNGCNT), 2965 e1000e_getreg(TSYNCTXCTL), 2966 e1000e_getreg(EXTCNF_SIZE), 2967 e1000e_getreg(EXTCNF_CTRL), 2968 e1000e_getreg(EEMNGDATA), 2969 e1000e_getreg(CTRL_EXT), 2970 e1000e_getreg(SYSTIMH), 2971 e1000e_getreg(EEMNGCTL), 2972 e1000e_getreg(FLMNGDATA), 2973 e1000e_getreg(TSYNCRXCTL), 2974 e1000e_getreg(TDH), 2975 e1000e_getreg(LEDCTL), 2976 e1000e_getreg(TCTL), 2977 e1000e_getreg(TDBAL), 2978 e1000e_getreg(TDLEN), 2979 e1000e_getreg(TDH1), 2980 e1000e_getreg(RADV), 2981 e1000e_getreg(ECOL), 2982 e1000e_getreg(DC), 2983 e1000e_getreg(RLEC), 2984 e1000e_getreg(XOFFTXC), 2985 e1000e_getreg(RFC), 2986 e1000e_getreg(RNBC), 2987 e1000e_getreg(MGTPTC), 2988 e1000e_getreg(TIMINCA), 2989 e1000e_getreg(RXCFGL), 2990 e1000e_getreg(MFUTP01), 2991 e1000e_getreg(FACTPS), 2992 e1000e_getreg(GSCL_1), 2993 e1000e_getreg(GSCN_0), 2994 e1000e_getreg(GCR2), 2995 e1000e_getreg(RDT1), 2996 e1000e_getreg(PBACLR), 2997 e1000e_getreg(FCTTV), 2998 e1000e_getreg(EEWR), 2999 e1000e_getreg(FLSWCTL), 3000 e1000e_getreg(RXDCTL1), 3001 e1000e_getreg(RXSATRL), 3002 e1000e_getreg(SYSTIML), 3003 e1000e_getreg(RXUDP), 3004 e1000e_getreg(TORL), 3005 e1000e_getreg(TDLEN1), 3006 e1000e_getreg(MCC), 3007 e1000e_getreg(WUC), 3008 e1000e_getreg(EECD), 3009 e1000e_getreg(MFUTP23), 3010 e1000e_getreg(RAID), 3011 e1000e_getreg(FCRTV), 3012 e1000e_getreg(TXDCTL1), 3013 e1000e_getreg(RCTL), 3014 e1000e_getreg(TDT), 3015 e1000e_getreg(MDIC), 3016 e1000e_getreg(FCRUC), 3017 e1000e_getreg(VET), 3018 e1000e_getreg(RDBAL0), 3019 e1000e_getreg(TDBAH1), 3020 e1000e_getreg(RDTR), 3021 e1000e_getreg(SCC), 3022 e1000e_getreg(COLC), 3023 e1000e_getreg(CEXTERR), 3024 e1000e_getreg(XOFFRXC), 3025 e1000e_getreg(IPAV), 3026 e1000e_getreg(GOTCL), 3027 e1000e_getreg(MGTPDC), 3028 e1000e_getreg(GCR), 3029 e1000e_getreg(IVAR), 3030 e1000e_getreg(POEMB), 3031 e1000e_getreg(MFVAL), 3032 e1000e_getreg(FUNCTAG), 3033 e1000e_getreg(GSCL_4), 3034 e1000e_getreg(GSCN_3), 3035 e1000e_getreg(MRQC), 3036 e1000e_getreg(RDLEN1), 3037 e1000e_getreg(FCT), 3038 e1000e_getreg(FLA), 3039 e1000e_getreg(FLOL), 3040 e1000e_getreg(RXDCTL), 3041 e1000e_getreg(RXSTMPL), 3042 e1000e_getreg(TXSTMPH), 3043 e1000e_getreg(TIMADJH), 3044 e1000e_getreg(FCRTL), 3045 e1000e_getreg(TDBAH), 3046 e1000e_getreg(TADV), 3047 e1000e_getreg(XONRXC), 3048 e1000e_getreg(TSCTFC), 3049 e1000e_getreg(RFCTL), 3050 e1000e_getreg(GSCN_1), 3051 e1000e_getreg(FCAL), 3052 e1000e_getreg(FLSWCNT), 3053 3054 [TOTH] = e1000e_mac_read_clr8, 3055 [GOTCH] = e1000e_mac_read_clr8, 3056 [PRC64] = e1000e_mac_read_clr4, 3057 [PRC255] = e1000e_mac_read_clr4, 3058 [PRC1023] = e1000e_mac_read_clr4, 3059 [PTC64] = e1000e_mac_read_clr4, 3060 [PTC255] = e1000e_mac_read_clr4, 3061 [PTC1023] = e1000e_mac_read_clr4, 3062 [GPRC] = e1000e_mac_read_clr4, 3063 [TPT] = e1000e_mac_read_clr4, 3064 [RUC] = e1000e_mac_read_clr4, 3065 [BPRC] = e1000e_mac_read_clr4, 3066 [MPTC] = e1000e_mac_read_clr4, 3067 [IAC] = e1000e_mac_read_clr4, 3068 [ICR] = e1000e_mac_icr_read, 3069 [RDFH] = E1000E_LOW_BITS_READ(13), 3070 [RDFHS] = E1000E_LOW_BITS_READ(13), 3071 [RDFPC] = E1000E_LOW_BITS_READ(13), 3072 [TDFH] = E1000E_LOW_BITS_READ(13), 3073 [TDFHS] = E1000E_LOW_BITS_READ(13), 3074 [STATUS] = e1000e_get_status, 3075 [TARC0] = e1000e_get_tarc, 3076 [PBS] = E1000E_LOW_BITS_READ(6), 3077 [ICS] = e1000e_mac_ics_read, 3078 [AIT] = E1000E_LOW_BITS_READ(16), 3079 [TORH] = e1000e_mac_read_clr8, 3080 [GORCH] = e1000e_mac_read_clr8, 3081 [PRC127] = e1000e_mac_read_clr4, 3082 [PRC511] = e1000e_mac_read_clr4, 3083 [PRC1522] = e1000e_mac_read_clr4, 3084 [PTC127] = e1000e_mac_read_clr4, 3085 [PTC511] = e1000e_mac_read_clr4, 3086 [PTC1522] = e1000e_mac_read_clr4, 3087 [GPTC] = e1000e_mac_read_clr4, 3088 [TPR] = e1000e_mac_read_clr4, 3089 [ROC] = e1000e_mac_read_clr4, 3090 [MPRC] = e1000e_mac_read_clr4, 3091 [BPTC] = e1000e_mac_read_clr4, 3092 [TSCTC] = e1000e_mac_read_clr4, 3093 [ITR] = e1000e_mac_itr_read, 3094 [RDFT] = E1000E_LOW_BITS_READ(13), 3095 [RDFTS] = E1000E_LOW_BITS_READ(13), 3096 [TDFPC] = E1000E_LOW_BITS_READ(13), 3097 [TDFT] = E1000E_LOW_BITS_READ(13), 3098 [TDFTS] = E1000E_LOW_BITS_READ(13), 3099 [CTRL] = e1000e_get_ctrl, 3100 [TARC1] = e1000e_get_tarc, 3101 [SWSM] = e1000e_mac_swsm_read, 3102 [IMS] = e1000e_mac_ims_read, 3103 3104 [CRCERRS ... MPC] = e1000e_mac_readreg, 3105 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3106 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3107 [RA ... RA + 31] = e1000e_mac_readreg, 3108 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3109 [MTA ... MTA + 127] = e1000e_mac_readreg, 3110 [VFTA ... VFTA + 127] = e1000e_mac_readreg, 3111 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4), 3112 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3113 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3114 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11), 3115 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3116 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3117 [RETA ... RETA + 31] = e1000e_mac_readreg, 3118 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3119 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3120 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3121 }; 3122 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3123 3124 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3125 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3126 static const writeops e1000e_macreg_writeops[] = { 3127 e1000e_putreg(PBA), 3128 e1000e_putreg(SWSM), 3129 e1000e_putreg(WUFC), 3130 e1000e_putreg(RDBAH1), 3131 e1000e_putreg(TDBAH), 3132 e1000e_putreg(TXDCTL), 3133 e1000e_putreg(RDBAH0), 3134 e1000e_putreg(LEDCTL), 3135 e1000e_putreg(FCAL), 3136 e1000e_putreg(FCRUC), 3137 e1000e_putreg(AIT), 3138 e1000e_putreg(TDFH), 3139 e1000e_putreg(TDFT), 3140 e1000e_putreg(TDFHS), 3141 e1000e_putreg(TDFTS), 3142 e1000e_putreg(TDFPC), 3143 e1000e_putreg(WUC), 3144 e1000e_putreg(WUS), 3145 e1000e_putreg(RDFH), 3146 e1000e_putreg(RDFT), 3147 e1000e_putreg(RDFHS), 3148 e1000e_putreg(RDFTS), 3149 e1000e_putreg(RDFPC), 3150 e1000e_putreg(IPAV), 3151 e1000e_putreg(TDBAH1), 3152 e1000e_putreg(TIMINCA), 3153 e1000e_putreg(IAM), 3154 e1000e_putreg(EIAC), 3155 e1000e_putreg(IVAR), 3156 e1000e_putreg(TARC0), 3157 e1000e_putreg(TARC1), 3158 e1000e_putreg(FLSWDATA), 3159 e1000e_putreg(POEMB), 3160 e1000e_putreg(PBS), 3161 e1000e_putreg(MFUTP01), 3162 e1000e_putreg(MFUTP23), 3163 e1000e_putreg(MANC), 3164 e1000e_putreg(MANC2H), 3165 e1000e_putreg(MFVAL), 3166 e1000e_putreg(EXTCNF_CTRL), 3167 e1000e_putreg(FACTPS), 3168 e1000e_putreg(FUNCTAG), 3169 e1000e_putreg(GSCL_1), 3170 e1000e_putreg(GSCL_2), 3171 e1000e_putreg(GSCL_3), 3172 e1000e_putreg(GSCL_4), 3173 e1000e_putreg(GSCN_0), 3174 e1000e_putreg(GSCN_1), 3175 e1000e_putreg(GSCN_2), 3176 e1000e_putreg(GSCN_3), 3177 e1000e_putreg(GCR2), 3178 e1000e_putreg(MRQC), 3179 e1000e_putreg(FLOP), 3180 e1000e_putreg(FLOL), 3181 e1000e_putreg(FLSWCTL), 3182 e1000e_putreg(FLSWCNT), 3183 e1000e_putreg(FLA), 3184 e1000e_putreg(RXDCTL1), 3185 e1000e_putreg(TXDCTL1), 3186 e1000e_putreg(TIPG), 3187 e1000e_putreg(RXSTMPH), 3188 e1000e_putreg(RXSTMPL), 3189 e1000e_putreg(RXSATRL), 3190 e1000e_putreg(RXSATRH), 3191 e1000e_putreg(TXSTMPL), 3192 e1000e_putreg(TXSTMPH), 3193 e1000e_putreg(SYSTIML), 3194 e1000e_putreg(SYSTIMH), 3195 e1000e_putreg(TIMADJL), 3196 e1000e_putreg(TIMADJH), 3197 e1000e_putreg(RXUDP), 3198 e1000e_putreg(RXCFGL), 3199 e1000e_putreg(TSYNCRXCTL), 3200 e1000e_putreg(TSYNCTXCTL), 3201 e1000e_putreg(EXTCNF_SIZE), 3202 e1000e_putreg(EEMNGCTL), 3203 e1000e_putreg(RA), 3204 3205 [TDH1] = e1000e_set_16bit, 3206 [TDT1] = e1000e_set_tdt, 3207 [TCTL] = e1000e_set_tctl, 3208 [TDT] = e1000e_set_tdt, 3209 [MDIC] = e1000e_set_mdic, 3210 [ICS] = e1000e_set_ics, 3211 [TDH] = e1000e_set_16bit, 3212 [RDH0] = e1000e_set_16bit, 3213 [RDT0] = e1000e_set_rdt, 3214 [IMC] = e1000e_set_imc, 3215 [IMS] = e1000e_set_ims, 3216 [ICR] = e1000e_set_icr, 3217 [EECD] = e1000e_set_eecd, 3218 [RCTL] = e1000e_set_rx_control, 3219 [CTRL] = e1000e_set_ctrl, 3220 [RDTR] = e1000e_set_rdtr, 3221 [RADV] = e1000e_set_16bit, 3222 [TADV] = e1000e_set_16bit, 3223 [ITR] = e1000e_set_itr, 3224 [EERD] = e1000e_set_eerd, 3225 [GCR] = e1000e_set_gcr, 3226 [PSRCTL] = e1000e_set_psrctl, 3227 [RXCSUM] = e1000e_set_rxcsum, 3228 [RAID] = e1000e_set_16bit, 3229 [RSRPD] = e1000e_set_12bit, 3230 [TIDV] = e1000e_set_tidv, 3231 [TDLEN1] = e1000e_set_dlen, 3232 [TDLEN] = e1000e_set_dlen, 3233 [RDLEN0] = e1000e_set_dlen, 3234 [RDLEN1] = e1000e_set_dlen, 3235 [TDBAL] = e1000e_set_dbal, 3236 [TDBAL1] = e1000e_set_dbal, 3237 [RDBAL0] = e1000e_set_dbal, 3238 [RDBAL1] = e1000e_set_dbal, 3239 [RDH1] = e1000e_set_16bit, 3240 [RDT1] = e1000e_set_rdt, 3241 [STATUS] = e1000e_set_status, 3242 [PBACLR] = e1000e_set_pbaclr, 3243 [CTRL_EXT] = e1000e_set_ctrlext, 3244 [FCAH] = e1000e_set_16bit, 3245 [FCT] = e1000e_set_16bit, 3246 [FCTTV] = e1000e_set_16bit, 3247 [FCRTV] = e1000e_set_16bit, 3248 [FCRTH] = e1000e_set_fcrth, 3249 [FCRTL] = e1000e_set_fcrtl, 3250 [VET] = e1000e_set_vet, 3251 [RXDCTL] = e1000e_set_rxdctl, 3252 [FLASHT] = e1000e_set_16bit, 3253 [EEWR] = e1000e_set_eewr, 3254 [CTRL_DUP] = e1000e_set_ctrl, 3255 [RFCTL] = e1000e_set_rfctl, 3256 [RA + 1] = e1000e_mac_setmacaddr, 3257 3258 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3259 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3260 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3261 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3262 [MTA ... MTA + 127] = e1000e_mac_writereg, 3263 [VFTA ... VFTA + 127] = e1000e_mac_writereg, 3264 [FFMT ... FFMT + 254] = e1000e_mac_writereg, 3265 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3266 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3267 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3268 [FFLT ... FFLT + 10] = e1000e_mac_writereg, 3269 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3270 [RETA ... RETA + 31] = e1000e_mac_writereg, 3271 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3272 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3273 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3274 }; 3275 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3276 3277 enum { MAC_ACCESS_PARTIAL = 1 }; 3278 3279 /* 3280 * The array below combines alias offsets of the index values for the 3281 * MAC registers that have aliases, with the indication of not fully 3282 * implemented registers (lowest bit). This combination is possible 3283 * because all of the offsets are even. 3284 */ 3285 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3286 /* Alias index offsets */ 3287 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3288 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3289 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3290 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3291 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3292 [RA_A ... RA_A + 31] = 0x14f0, 3293 [VFTA_A ... VFTA_A + 127] = 0x1400, 3294 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3295 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3296 /* Access options */ 3297 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3298 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3299 [RDFPC] = MAC_ACCESS_PARTIAL, 3300 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3301 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3302 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3303 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3304 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3305 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3306 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3307 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3308 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3309 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3310 }; 3311 3312 void 3313 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3314 { 3315 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3316 3317 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3318 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3319 trace_e1000e_wrn_regs_write_trivial(index << 2); 3320 } 3321 trace_e1000e_core_write(index << 2, size, val); 3322 e1000e_macreg_writeops[index](core, index, val); 3323 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3324 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3325 } else { 3326 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3327 } 3328 } 3329 3330 uint64_t 3331 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3332 { 3333 uint64_t val; 3334 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3335 3336 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3337 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3338 trace_e1000e_wrn_regs_read_trivial(index << 2); 3339 } 3340 val = e1000e_macreg_readops[index](core, index); 3341 trace_e1000e_core_read(index << 2, size, val); 3342 return val; 3343 } else { 3344 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3345 } 3346 return 0; 3347 } 3348 3349 static inline void 3350 e1000e_autoneg_pause(E1000ECore *core) 3351 { 3352 timer_del(core->autoneg_timer); 3353 } 3354 3355 static void 3356 e1000e_autoneg_resume(E1000ECore *core) 3357 { 3358 if (e1000e_have_autoneg(core) && 3359 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3360 qemu_get_queue(core->owner_nic)->link_down = false; 3361 timer_mod(core->autoneg_timer, 3362 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3363 } 3364 } 3365 3366 static void 3367 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3368 { 3369 E1000ECore *core = opaque; 3370 3371 if (running) { 3372 trace_e1000e_vm_state_running(); 3373 e1000e_intrmgr_resume(core); 3374 e1000e_autoneg_resume(core); 3375 } else { 3376 trace_e1000e_vm_state_stopped(); 3377 e1000e_autoneg_pause(core); 3378 e1000e_intrmgr_pause(core); 3379 } 3380 } 3381 3382 void 3383 e1000e_core_pci_realize(E1000ECore *core, 3384 const uint16_t *eeprom_templ, 3385 uint32_t eeprom_size, 3386 const uint8_t *macaddr) 3387 { 3388 int i; 3389 3390 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3391 e1000e_autoneg_timer, core); 3392 e1000e_intrmgr_pci_realize(core); 3393 3394 core->vmstate = 3395 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3396 3397 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3398 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner, 3399 E1000E_MAX_TX_FRAGS, core->has_vnet); 3400 } 3401 3402 net_rx_pkt_init(&core->rx_pkt, core->has_vnet); 3403 3404 e1000x_core_prepare_eeprom(core->eeprom, 3405 eeprom_templ, 3406 eeprom_size, 3407 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3408 macaddr); 3409 e1000e_update_rx_offloads(core); 3410 } 3411 3412 void 3413 e1000e_core_pci_uninit(E1000ECore *core) 3414 { 3415 int i; 3416 3417 timer_free(core->autoneg_timer); 3418 3419 e1000e_intrmgr_pci_unint(core); 3420 3421 qemu_del_vm_change_state_handler(core->vmstate); 3422 3423 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3424 net_tx_pkt_reset(core->tx[i].tx_pkt); 3425 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3426 } 3427 3428 net_rx_pkt_uninit(core->rx_pkt); 3429 } 3430 3431 static const uint16_t 3432 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3433 [0] = { 3434 [MII_BMCR] = MII_BMCR_SPEED1000 | 3435 MII_BMCR_FD | 3436 MII_BMCR_AUTOEN, 3437 3438 [MII_BMSR] = MII_BMSR_EXTCAP | 3439 MII_BMSR_LINK_ST | 3440 MII_BMSR_AUTONEG | 3441 MII_BMSR_MFPS | 3442 MII_BMSR_EXTSTAT | 3443 MII_BMSR_10T_HD | 3444 MII_BMSR_10T_FD | 3445 MII_BMSR_100TX_HD | 3446 MII_BMSR_100TX_FD, 3447 3448 [MII_PHYID1] = 0x141, 3449 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3450 [MII_ANAR] = 0xde1, 3451 [MII_ANLPAR] = 0x7e0, 3452 [MII_ANER] = BIT(2), 3453 [MII_ANNP] = BIT(0) | BIT(13), 3454 [MII_CTRL1000] = BIT(8) | BIT(9) | BIT(10) | BIT(11), 3455 [MII_STAT1000] = 0x3c00, 3456 [MII_EXTSTAT] = BIT(12) | BIT(13), 3457 3458 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3459 BIT(12) | BIT(13), 3460 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3461 }, 3462 [2] = { 3463 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3464 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3465 }, 3466 [3] = { 3467 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3468 } 3469 }; 3470 3471 static const uint32_t e1000e_mac_reg_init[] = { 3472 [PBA] = 0x00140014, 3473 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3474 [EXTCNF_CTRL] = BIT(3), 3475 [EEMNGCTL] = BIT(31), 3476 [FLASHT] = 0x2, 3477 [FLSWCTL] = BIT(30) | BIT(31), 3478 [FLOL] = BIT(0), 3479 [RXDCTL] = BIT(16), 3480 [RXDCTL1] = BIT(16), 3481 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3482 [RXCFGL] = 0x88F7, 3483 [RXUDP] = 0x319, 3484 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3485 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3486 E1000_CTRL_ADVD3WUC, 3487 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3488 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3489 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3490 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3491 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3492 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3493 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3494 [EERD] = E1000_EERW_DONE, 3495 [EEWR] = E1000_EERW_DONE, 3496 [GCR] = E1000_L0S_ADJUST | 3497 E1000_L1_ENTRY_LATENCY_MSB | 3498 E1000_L1_ENTRY_LATENCY_LSB, 3499 [TDFH] = 0x600, 3500 [TDFT] = 0x600, 3501 [TDFHS] = 0x600, 3502 [TDFTS] = 0x600, 3503 [POEMB] = 0x30D, 3504 [PBS] = 0x028, 3505 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3506 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3507 [SWSM] = 1, 3508 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3509 [ITR] = E1000E_MIN_XITR, 3510 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3511 }; 3512 3513 void 3514 e1000e_core_reset(E1000ECore *core) 3515 { 3516 int i; 3517 3518 timer_del(core->autoneg_timer); 3519 3520 e1000e_intrmgr_reset(core); 3521 3522 memset(core->phy, 0, sizeof core->phy); 3523 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3524 memset(core->mac, 0, sizeof core->mac); 3525 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init); 3526 3527 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3528 3529 if (qemu_get_queue(core->owner_nic)->link_down) { 3530 e1000e_link_down(core); 3531 } 3532 3533 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3534 3535 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3536 net_tx_pkt_reset(core->tx[i].tx_pkt); 3537 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3538 core->tx[i].skip_cp = false; 3539 } 3540 } 3541 3542 void e1000e_core_pre_save(E1000ECore *core) 3543 { 3544 int i; 3545 NetClientState *nc = qemu_get_queue(core->owner_nic); 3546 3547 /* 3548 * If link is down and auto-negotiation is supported and ongoing, 3549 * complete auto-negotiation immediately. This allows us to look 3550 * at MII_BMSR_AN_COMP to infer link status on load. 3551 */ 3552 if (nc->link_down && e1000e_have_autoneg(core)) { 3553 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3554 e1000e_update_flowctl_status(core); 3555 } 3556 3557 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3558 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3559 core->tx[i].skip_cp = true; 3560 } 3561 } 3562 } 3563 3564 int 3565 e1000e_core_post_load(E1000ECore *core) 3566 { 3567 NetClientState *nc = qemu_get_queue(core->owner_nic); 3568 3569 /* 3570 * nc.link_down can't be migrated, so infer link_down according 3571 * to link status bit in core.mac[STATUS]. 3572 */ 3573 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3574 3575 return 0; 3576 } 3577