1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000_common.h" 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 55 #define E1000E_MIN_XITR (500) 56 57 #define E1000E_MAX_TX_FRAGS (64) 58 59 union e1000_rx_desc_union { 60 struct e1000_rx_desc legacy; 61 union e1000_rx_desc_extended extended; 62 union e1000_rx_desc_packet_split packet_split; 63 }; 64 65 static ssize_t 66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 67 bool has_vnet); 68 69 static inline void 70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 71 72 static void e1000e_reset(E1000ECore *core, bool sw); 73 74 static inline void 75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 76 { 77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 78 trace_e1000e_wrn_no_ts_support(); 79 } 80 } 81 82 static inline void 83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 84 { 85 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 86 trace_e1000e_wrn_no_snap_support(); 87 } 88 } 89 90 static inline void 91 e1000e_raise_legacy_irq(E1000ECore *core) 92 { 93 trace_e1000e_irq_legacy_notify(true); 94 e1000x_inc_reg_if_not_full(core->mac, IAC); 95 pci_set_irq(core->owner, 1); 96 } 97 98 static inline void 99 e1000e_lower_legacy_irq(E1000ECore *core) 100 { 101 trace_e1000e_irq_legacy_notify(false); 102 pci_set_irq(core->owner, 0); 103 } 104 105 static inline void 106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 107 { 108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 109 timer->delay_resolution_ns; 110 111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 112 113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 114 115 timer->running = true; 116 } 117 118 static void 119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 e1000e_intrmgr_rearm_timer(timer); 123 } 124 } 125 126 static void 127 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 128 { 129 if (timer->running) { 130 timer_del(timer->timer); 131 } 132 } 133 134 static inline void 135 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 136 { 137 if (timer->running) { 138 timer_del(timer->timer); 139 timer->running = false; 140 } 141 } 142 143 static inline void 144 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 145 { 146 trace_e1000e_irq_fire_delayed_interrupts(); 147 e1000e_set_interrupt_cause(core, 0); 148 } 149 150 static void 151 e1000e_intrmgr_on_timer(void *opaque) 152 { 153 E1000IntrDelayTimer *timer = opaque; 154 155 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 156 157 timer->running = false; 158 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 159 } 160 161 static void 162 e1000e_intrmgr_on_throttling_timer(void *opaque) 163 { 164 E1000IntrDelayTimer *timer = opaque; 165 166 timer->running = false; 167 168 if (timer->core->mac[IMS] & timer->core->mac[ICR]) { 169 if (msi_enabled(timer->core->owner)) { 170 trace_e1000e_irq_msi_notify_postponed(); 171 msi_notify(timer->core->owner, 0); 172 } else { 173 trace_e1000e_irq_legacy_notify_postponed(); 174 e1000e_raise_legacy_irq(timer->core); 175 } 176 } 177 } 178 179 static void 180 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 181 { 182 E1000IntrDelayTimer *timer = opaque; 183 int idx = timer - &timer->core->eitr[0]; 184 185 timer->running = false; 186 187 trace_e1000e_irq_msix_notify_postponed_vec(idx); 188 msix_notify(timer->core->owner, idx); 189 } 190 191 static void 192 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 193 { 194 int i; 195 196 core->radv.delay_reg = RADV; 197 core->rdtr.delay_reg = RDTR; 198 core->raid.delay_reg = RAID; 199 core->tadv.delay_reg = TADV; 200 core->tidv.delay_reg = TIDV; 201 202 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 207 208 core->radv.core = core; 209 core->rdtr.core = core; 210 core->raid.core = core; 211 core->tadv.core = core; 212 core->tidv.core = core; 213 214 core->itr.core = core; 215 core->itr.delay_reg = ITR; 216 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 217 218 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 219 core->eitr[i].core = core; 220 core->eitr[i].delay_reg = EITR + i; 221 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 222 } 223 224 if (!create) { 225 return; 226 } 227 228 core->radv.timer = 229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 230 core->rdtr.timer = 231 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 232 core->raid.timer = 233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 234 235 core->tadv.timer = 236 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 237 core->tidv.timer = 238 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 239 240 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 241 e1000e_intrmgr_on_throttling_timer, 242 &core->itr); 243 244 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 245 core->eitr[i].timer = 246 timer_new_ns(QEMU_CLOCK_VIRTUAL, 247 e1000e_intrmgr_on_msix_throttling_timer, 248 &core->eitr[i]); 249 } 250 } 251 252 static inline void 253 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 254 { 255 e1000e_intrmgr_stop_timer(&core->radv); 256 e1000e_intrmgr_stop_timer(&core->rdtr); 257 e1000e_intrmgr_stop_timer(&core->raid); 258 e1000e_intrmgr_stop_timer(&core->tidv); 259 e1000e_intrmgr_stop_timer(&core->tadv); 260 } 261 262 static bool 263 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 264 { 265 uint32_t delayable_causes; 266 uint32_t rdtr = core->mac[RDTR]; 267 uint32_t radv = core->mac[RADV]; 268 uint32_t raid = core->mac[RAID]; 269 270 if (msix_enabled(core->owner)) { 271 return false; 272 } 273 274 delayable_causes = E1000_ICR_RXQ0 | 275 E1000_ICR_RXQ1 | 276 E1000_ICR_RXT0; 277 278 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 279 delayable_causes |= E1000_ICR_ACK; 280 } 281 282 /* Clean up all causes that may be delayed */ 283 core->delayed_causes |= *causes & delayable_causes; 284 *causes &= ~delayable_causes; 285 286 /* 287 * Check if delayed RX interrupts disabled by client 288 * or if there are causes that cannot be delayed 289 */ 290 if ((rdtr == 0) || (*causes != 0)) { 291 return false; 292 } 293 294 /* 295 * Check if delayed RX ACK interrupts disabled by client 296 * and there is an ACK packet received 297 */ 298 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 299 return false; 300 } 301 302 /* All causes delayed */ 303 e1000e_intrmgr_rearm_timer(&core->rdtr); 304 305 if (!core->radv.running && (radv != 0)) { 306 e1000e_intrmgr_rearm_timer(&core->radv); 307 } 308 309 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 310 e1000e_intrmgr_rearm_timer(&core->raid); 311 } 312 313 return true; 314 } 315 316 static bool 317 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 318 { 319 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 320 E1000_ICR_TXQ1 | 321 E1000_ICR_TXQE | 322 E1000_ICR_TXDW; 323 324 if (msix_enabled(core->owner)) { 325 return false; 326 } 327 328 /* Clean up all causes that may be delayed */ 329 core->delayed_causes |= *causes & delayable_causes; 330 *causes &= ~delayable_causes; 331 332 /* If there are causes that cannot be delayed */ 333 if (*causes != 0) { 334 return false; 335 } 336 337 /* All causes delayed */ 338 e1000e_intrmgr_rearm_timer(&core->tidv); 339 340 if (!core->tadv.running && (core->mac[TADV] != 0)) { 341 e1000e_intrmgr_rearm_timer(&core->tadv); 342 } 343 344 return true; 345 } 346 347 static uint32_t 348 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 349 { 350 uint32_t res; 351 352 if (msix_enabled(core->owner)) { 353 assert(core->delayed_causes == 0); 354 return 0; 355 } 356 357 res = core->delayed_causes; 358 core->delayed_causes = 0; 359 360 e1000e_intrmgr_stop_delay_timers(core); 361 362 return res; 363 } 364 365 static void 366 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 367 { 368 int i; 369 370 if (core->itr.running) { 371 timer_del(core->itr.timer); 372 e1000e_intrmgr_on_throttling_timer(&core->itr); 373 } 374 375 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 376 if (core->eitr[i].running) { 377 timer_del(core->eitr[i].timer); 378 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 379 } 380 } 381 } 382 383 static void 384 e1000e_intrmgr_resume(E1000ECore *core) 385 { 386 int i; 387 388 e1000e_intmgr_timer_resume(&core->radv); 389 e1000e_intmgr_timer_resume(&core->rdtr); 390 e1000e_intmgr_timer_resume(&core->raid); 391 e1000e_intmgr_timer_resume(&core->tidv); 392 e1000e_intmgr_timer_resume(&core->tadv); 393 394 e1000e_intmgr_timer_resume(&core->itr); 395 396 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 397 e1000e_intmgr_timer_resume(&core->eitr[i]); 398 } 399 } 400 401 static void 402 e1000e_intrmgr_pause(E1000ECore *core) 403 { 404 int i; 405 406 e1000e_intmgr_timer_pause(&core->radv); 407 e1000e_intmgr_timer_pause(&core->rdtr); 408 e1000e_intmgr_timer_pause(&core->raid); 409 e1000e_intmgr_timer_pause(&core->tidv); 410 e1000e_intmgr_timer_pause(&core->tadv); 411 412 e1000e_intmgr_timer_pause(&core->itr); 413 414 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 415 e1000e_intmgr_timer_pause(&core->eitr[i]); 416 } 417 } 418 419 static void 420 e1000e_intrmgr_reset(E1000ECore *core) 421 { 422 int i; 423 424 core->delayed_causes = 0; 425 426 e1000e_intrmgr_stop_delay_timers(core); 427 428 e1000e_intrmgr_stop_timer(&core->itr); 429 430 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 431 e1000e_intrmgr_stop_timer(&core->eitr[i]); 432 } 433 } 434 435 static void 436 e1000e_intrmgr_pci_unint(E1000ECore *core) 437 { 438 int i; 439 440 timer_free(core->radv.timer); 441 timer_free(core->rdtr.timer); 442 timer_free(core->raid.timer); 443 444 timer_free(core->tadv.timer); 445 timer_free(core->tidv.timer); 446 447 timer_free(core->itr.timer); 448 449 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 450 timer_free(core->eitr[i].timer); 451 } 452 } 453 454 static void 455 e1000e_intrmgr_pci_realize(E1000ECore *core) 456 { 457 e1000e_intrmgr_initialize_all_timers(core, true); 458 } 459 460 static inline bool 461 e1000e_rx_csum_enabled(E1000ECore *core) 462 { 463 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 464 } 465 466 static inline bool 467 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 468 { 469 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 470 } 471 472 static inline bool 473 e1000e_rx_use_ps_descriptor(E1000ECore *core) 474 { 475 return !e1000e_rx_use_legacy_descriptor(core) && 476 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 477 } 478 479 static inline bool 480 e1000e_rss_enabled(E1000ECore *core) 481 { 482 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 483 !e1000e_rx_csum_enabled(core) && 484 !e1000e_rx_use_legacy_descriptor(core); 485 } 486 487 typedef struct E1000E_RSSInfo_st { 488 bool enabled; 489 uint32_t hash; 490 uint32_t queue; 491 uint32_t type; 492 } E1000E_RSSInfo; 493 494 static uint32_t 495 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 496 { 497 bool hasip4, hasip6; 498 EthL4HdrProto l4hdr_proto; 499 500 assert(e1000e_rss_enabled(core)); 501 502 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 503 504 if (hasip4) { 505 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 506 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 507 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 508 509 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 511 return E1000_MRQ_RSS_TYPE_IPV4TCP; 512 } 513 514 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 515 return E1000_MRQ_RSS_TYPE_IPV4; 516 } 517 } else if (hasip6) { 518 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 519 520 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 521 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 522 523 /* 524 * Following two traces must not be combined because resulting 525 * event will have 11 arguments totally and some trace backends 526 * (at least "ust") have limitation of maximum 10 arguments per 527 * event. Events with more arguments fail to compile for 528 * backends like these. 529 */ 530 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 531 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 532 ip6info->has_ext_hdrs, 533 ip6info->rss_ex_dst_valid, 534 ip6info->rss_ex_src_valid, 535 core->mac[MRQC], 536 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), 537 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 538 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 539 540 if ((!ex_dis || !ip6info->has_ext_hdrs) && 541 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 542 ip6info->rss_ex_src_valid))) { 543 544 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 545 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { 546 return E1000_MRQ_RSS_TYPE_IPV6TCPEX; 547 } 548 549 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 550 return E1000_MRQ_RSS_TYPE_IPV6EX; 551 } 552 553 } 554 555 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 556 return E1000_MRQ_RSS_TYPE_IPV6; 557 } 558 559 } 560 561 return E1000_MRQ_RSS_TYPE_NONE; 562 } 563 564 static uint32_t 565 e1000e_rss_calc_hash(E1000ECore *core, 566 struct NetRxPkt *pkt, 567 E1000E_RSSInfo *info) 568 { 569 NetRxPktRssType type; 570 571 assert(e1000e_rss_enabled(core)); 572 573 switch (info->type) { 574 case E1000_MRQ_RSS_TYPE_IPV4: 575 type = NetPktRssIpV4; 576 break; 577 case E1000_MRQ_RSS_TYPE_IPV4TCP: 578 type = NetPktRssIpV4Tcp; 579 break; 580 case E1000_MRQ_RSS_TYPE_IPV6TCPEX: 581 type = NetPktRssIpV6TcpEx; 582 break; 583 case E1000_MRQ_RSS_TYPE_IPV6: 584 type = NetPktRssIpV6; 585 break; 586 case E1000_MRQ_RSS_TYPE_IPV6EX: 587 type = NetPktRssIpV6Ex; 588 break; 589 default: 590 assert(false); 591 return 0; 592 } 593 594 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 595 } 596 597 static void 598 e1000e_rss_parse_packet(E1000ECore *core, 599 struct NetRxPkt *pkt, 600 E1000E_RSSInfo *info) 601 { 602 trace_e1000e_rx_rss_started(); 603 604 if (!e1000e_rss_enabled(core)) { 605 info->enabled = false; 606 info->hash = 0; 607 info->queue = 0; 608 info->type = 0; 609 trace_e1000e_rx_rss_disabled(); 610 return; 611 } 612 613 info->enabled = true; 614 615 info->type = e1000e_rss_get_hash_type(core, pkt); 616 617 trace_e1000e_rx_rss_type(info->type); 618 619 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 620 info->hash = 0; 621 info->queue = 0; 622 return; 623 } 624 625 info->hash = e1000e_rss_calc_hash(core, pkt, info); 626 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 627 } 628 629 static bool 630 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 631 { 632 if (tx->props.tse && tx->cptse) { 633 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 634 return false; 635 } 636 637 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 638 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 639 return true; 640 } 641 642 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 643 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 644 return false; 645 } 646 } 647 648 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 649 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 650 } 651 652 return true; 653 } 654 655 static void e1000e_tx_pkt_callback(void *core, 656 const struct iovec *iov, 657 int iovcnt, 658 const struct iovec *virt_iov, 659 int virt_iovcnt) 660 { 661 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 662 } 663 664 static bool 665 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 666 { 667 int target_queue = MIN(core->max_queue_num, queue_index); 668 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 669 670 if (!e1000e_setup_tx_offloads(core, tx)) { 671 return false; 672 } 673 674 net_tx_pkt_dump(tx->tx_pkt); 675 676 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 677 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 678 return net_tx_pkt_send_custom(tx->tx_pkt, false, 679 e1000e_tx_pkt_callback, core); 680 } else { 681 return net_tx_pkt_send(tx->tx_pkt, queue); 682 } 683 } 684 685 static void 686 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 687 { 688 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 689 PTC1023, PTC1522 }; 690 691 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 692 693 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 694 e1000x_inc_reg_if_not_full(core->mac, TPT); 695 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 696 697 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 698 case ETH_PKT_BCAST: 699 e1000x_inc_reg_if_not_full(core->mac, BPTC); 700 break; 701 case ETH_PKT_MCAST: 702 e1000x_inc_reg_if_not_full(core->mac, MPTC); 703 break; 704 case ETH_PKT_UCAST: 705 break; 706 default: 707 g_assert_not_reached(); 708 } 709 710 e1000x_inc_reg_if_not_full(core->mac, GPTC); 711 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 712 } 713 714 static void 715 e1000e_process_tx_desc(E1000ECore *core, 716 struct e1000e_tx *tx, 717 struct e1000_tx_desc *dp, 718 int queue_index) 719 { 720 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 721 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 722 unsigned int split_size = txd_lower & 0xffff; 723 uint64_t addr; 724 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 725 bool eop = txd_lower & E1000_TXD_CMD_EOP; 726 727 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 728 e1000x_read_tx_ctx_descr(xp, &tx->props); 729 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 730 return; 731 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 732 /* data descriptor */ 733 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 734 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 735 e1000e_process_ts_option(core, dp); 736 } else { 737 /* legacy descriptor */ 738 e1000e_process_ts_option(core, dp); 739 tx->cptse = 0; 740 } 741 742 addr = le64_to_cpu(dp->buffer_addr); 743 744 if (!tx->skip_cp) { 745 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, 746 addr, split_size)) { 747 tx->skip_cp = true; 748 } 749 } 750 751 if (eop) { 752 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 753 if (e1000x_vlan_enabled(core->mac) && 754 e1000x_is_vlan_txd(txd_lower)) { 755 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 756 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 757 } 758 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 759 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 760 } 761 } 762 763 tx->skip_cp = false; 764 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 765 766 tx->sum_needed = 0; 767 tx->cptse = 0; 768 } 769 } 770 771 static inline uint32_t 772 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 773 { 774 if (!msix_enabled(core->owner)) { 775 return E1000_ICR_TXDW; 776 } 777 778 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 779 } 780 781 static inline uint32_t 782 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 783 bool min_threshold_hit) 784 { 785 if (!msix_enabled(core->owner)) { 786 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 787 } 788 789 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 790 } 791 792 static uint32_t 793 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 794 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 795 { 796 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 797 798 if (!(txd_lower & E1000_TXD_CMD_RS) && 799 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 800 return 0; 801 } 802 803 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 804 805 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 806 807 dp->upper.data = cpu_to_le32(txd_upper); 808 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 809 &dp->upper, sizeof(dp->upper)); 810 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 811 } 812 813 typedef struct E1000ERingInfo { 814 int dbah; 815 int dbal; 816 int dlen; 817 int dh; 818 int dt; 819 int idx; 820 } E1000ERingInfo; 821 822 static inline bool 823 e1000e_ring_empty(E1000ECore *core, const E1000ERingInfo *r) 824 { 825 return core->mac[r->dh] == core->mac[r->dt] || 826 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 827 } 828 829 static inline uint64_t 830 e1000e_ring_base(E1000ECore *core, const E1000ERingInfo *r) 831 { 832 uint64_t bah = core->mac[r->dbah]; 833 uint64_t bal = core->mac[r->dbal]; 834 835 return (bah << 32) + bal; 836 } 837 838 static inline uint64_t 839 e1000e_ring_head_descr(E1000ECore *core, const E1000ERingInfo *r) 840 { 841 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 842 } 843 844 static inline void 845 e1000e_ring_advance(E1000ECore *core, const E1000ERingInfo *r, uint32_t count) 846 { 847 core->mac[r->dh] += count; 848 849 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 850 core->mac[r->dh] = 0; 851 } 852 } 853 854 static inline uint32_t 855 e1000e_ring_free_descr_num(E1000ECore *core, const E1000ERingInfo *r) 856 { 857 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 858 core->mac[r->dh], core->mac[r->dt]); 859 860 if (core->mac[r->dh] <= core->mac[r->dt]) { 861 return core->mac[r->dt] - core->mac[r->dh]; 862 } 863 864 if (core->mac[r->dh] > core->mac[r->dt]) { 865 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 866 core->mac[r->dt] - core->mac[r->dh]; 867 } 868 869 g_assert_not_reached(); 870 return 0; 871 } 872 873 static inline bool 874 e1000e_ring_enabled(E1000ECore *core, const E1000ERingInfo *r) 875 { 876 return core->mac[r->dlen] > 0; 877 } 878 879 static inline uint32_t 880 e1000e_ring_len(E1000ECore *core, const E1000ERingInfo *r) 881 { 882 return core->mac[r->dlen]; 883 } 884 885 typedef struct E1000E_TxRing_st { 886 const E1000ERingInfo *i; 887 struct e1000e_tx *tx; 888 } E1000E_TxRing; 889 890 static inline int 891 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 892 { 893 return (reg_idx - base_reg_idx) / (0x100 >> 2); 894 } 895 896 static inline void 897 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 898 { 899 static const E1000ERingInfo i[E1000E_NUM_QUEUES] = { 900 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 901 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 902 }; 903 904 assert(idx < ARRAY_SIZE(i)); 905 906 txr->i = &i[idx]; 907 txr->tx = &core->tx[idx]; 908 } 909 910 typedef struct E1000E_RxRing_st { 911 const E1000ERingInfo *i; 912 } E1000E_RxRing; 913 914 static inline void 915 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 916 { 917 static const E1000ERingInfo i[E1000E_NUM_QUEUES] = { 918 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 919 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 920 }; 921 922 assert(idx < ARRAY_SIZE(i)); 923 924 rxr->i = &i[idx]; 925 } 926 927 static void 928 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 929 { 930 dma_addr_t base; 931 struct e1000_tx_desc desc; 932 bool ide = false; 933 const E1000ERingInfo *txi = txr->i; 934 uint32_t cause = E1000_ICS_TXQE; 935 936 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 937 trace_e1000e_tx_disabled(); 938 return; 939 } 940 941 while (!e1000e_ring_empty(core, txi)) { 942 base = e1000e_ring_head_descr(core, txi); 943 944 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 945 946 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 947 desc.lower.data, desc.upper.data); 948 949 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 950 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 951 952 e1000e_ring_advance(core, txi, 1); 953 } 954 955 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 956 e1000e_set_interrupt_cause(core, cause); 957 } 958 959 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 960 } 961 962 static bool 963 e1000e_has_rxbufs(E1000ECore *core, const E1000ERingInfo *r, 964 size_t total_size) 965 { 966 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 967 968 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 969 core->rx_desc_buf_size); 970 971 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 972 core->rx_desc_buf_size; 973 } 974 975 void 976 e1000e_start_recv(E1000ECore *core) 977 { 978 int i; 979 980 trace_e1000e_rx_start_recv(); 981 982 for (i = 0; i <= core->max_queue_num; i++) { 983 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 984 } 985 } 986 987 bool 988 e1000e_can_receive(E1000ECore *core) 989 { 990 int i; 991 992 if (!e1000x_rx_ready(core->owner, core->mac)) { 993 return false; 994 } 995 996 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 997 E1000E_RxRing rxr; 998 999 e1000e_rx_ring_init(core, &rxr, i); 1000 if (e1000e_ring_enabled(core, rxr.i) && 1001 e1000e_has_rxbufs(core, rxr.i, 1)) { 1002 trace_e1000e_rx_can_recv(); 1003 return true; 1004 } 1005 } 1006 1007 trace_e1000e_rx_can_recv_rings_full(); 1008 return false; 1009 } 1010 1011 ssize_t 1012 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 1013 { 1014 const struct iovec iov = { 1015 .iov_base = (uint8_t *)buf, 1016 .iov_len = size 1017 }; 1018 1019 return e1000e_receive_iov(core, &iov, 1); 1020 } 1021 1022 static inline bool 1023 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1024 { 1025 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1026 } 1027 1028 static inline bool 1029 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1030 { 1031 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1032 } 1033 1034 static bool 1035 e1000e_receive_filter(E1000ECore *core, const void *buf) 1036 { 1037 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || 1038 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && 1039 e1000x_rx_group_filter(core->mac, buf); 1040 } 1041 1042 static inline void 1043 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1044 hwaddr *buff_addr) 1045 { 1046 *buff_addr = le64_to_cpu(desc->buffer_addr); 1047 } 1048 1049 static inline void 1050 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1051 hwaddr *buff_addr) 1052 { 1053 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1054 } 1055 1056 static inline void 1057 e1000e_read_ps_rx_descr(E1000ECore *core, 1058 union e1000_rx_desc_packet_split *desc, 1059 hwaddr buff_addr[MAX_PS_BUFFERS]) 1060 { 1061 int i; 1062 1063 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1064 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1065 } 1066 1067 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1068 buff_addr[2], buff_addr[3]); 1069 } 1070 1071 static inline void 1072 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1073 hwaddr buff_addr[MAX_PS_BUFFERS]) 1074 { 1075 if (e1000e_rx_use_legacy_descriptor(core)) { 1076 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1077 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1078 } else { 1079 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1080 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1081 } else { 1082 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1083 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1084 } 1085 } 1086 } 1087 1088 static void 1089 e1000e_verify_csum_in_sw(E1000ECore *core, 1090 struct NetRxPkt *pkt, 1091 uint32_t *status_flags, 1092 EthL4HdrProto l4hdr_proto) 1093 { 1094 bool csum_valid; 1095 uint32_t csum_error; 1096 1097 if (e1000e_rx_l3_cso_enabled(core)) { 1098 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1099 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1100 } else { 1101 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1102 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1103 } 1104 } else { 1105 trace_e1000e_rx_metadata_l3_cso_disabled(); 1106 } 1107 1108 if (!e1000e_rx_l4_cso_enabled(core)) { 1109 trace_e1000e_rx_metadata_l4_cso_disabled(); 1110 return; 1111 } 1112 1113 if (l4hdr_proto != ETH_L4_HDR_PROTO_TCP && 1114 l4hdr_proto != ETH_L4_HDR_PROTO_UDP) { 1115 return; 1116 } 1117 1118 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1119 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1120 return; 1121 } 1122 1123 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1124 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1125 1126 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1127 *status_flags |= E1000_RXD_STAT_UDPCS; 1128 } 1129 } 1130 1131 static inline bool 1132 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1133 { 1134 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1135 return false; 1136 } 1137 1138 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1139 return !net_rx_pkt_has_tcp_data(rx_pkt); 1140 } 1141 1142 return true; 1143 } 1144 1145 static void 1146 e1000e_build_rx_metadata(E1000ECore *core, 1147 struct NetRxPkt *pkt, 1148 bool is_eop, 1149 const E1000E_RSSInfo *rss_info, 1150 uint32_t *rss, uint32_t *mrq, 1151 uint32_t *status_flags, 1152 uint16_t *ip_id, 1153 uint16_t *vlan_tag) 1154 { 1155 struct virtio_net_hdr *vhdr; 1156 bool hasip4, hasip6; 1157 EthL4HdrProto l4hdr_proto; 1158 uint32_t pkt_type; 1159 1160 *status_flags = E1000_RXD_STAT_DD; 1161 1162 /* No additional metadata needed for non-EOP descriptors */ 1163 if (!is_eop) { 1164 goto func_exit; 1165 } 1166 1167 *status_flags |= E1000_RXD_STAT_EOP; 1168 1169 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1170 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1171 1172 /* VLAN state */ 1173 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1174 *status_flags |= E1000_RXD_STAT_VP; 1175 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1176 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1177 } 1178 1179 /* Packet parsing results */ 1180 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1181 if (rss_info->enabled) { 1182 *rss = cpu_to_le32(rss_info->hash); 1183 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1184 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1185 } 1186 } else if (hasip4) { 1187 *status_flags |= E1000_RXD_STAT_IPIDV; 1188 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1189 trace_e1000e_rx_metadata_ip_id(*ip_id); 1190 } 1191 1192 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { 1193 *status_flags |= E1000_RXD_STAT_ACK; 1194 trace_e1000e_rx_metadata_ack(); 1195 } 1196 1197 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1198 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1199 pkt_type = E1000_RXD_PKT_MAC; 1200 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1201 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1202 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1203 } else if (hasip4 || hasip6) { 1204 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1205 } else { 1206 pkt_type = E1000_RXD_PKT_MAC; 1207 } 1208 1209 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1210 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1211 1212 /* RX CSO information */ 1213 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1214 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1215 goto func_exit; 1216 } 1217 1218 vhdr = net_rx_pkt_get_vhdr(pkt); 1219 1220 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1221 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1222 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1223 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1224 goto func_exit; 1225 } 1226 1227 if (e1000e_rx_l3_cso_enabled(core)) { 1228 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1229 } else { 1230 trace_e1000e_rx_metadata_l3_cso_disabled(); 1231 } 1232 1233 if (e1000e_rx_l4_cso_enabled(core)) { 1234 switch (l4hdr_proto) { 1235 case ETH_L4_HDR_PROTO_TCP: 1236 *status_flags |= E1000_RXD_STAT_TCPCS; 1237 break; 1238 1239 case ETH_L4_HDR_PROTO_UDP: 1240 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1241 break; 1242 1243 default: 1244 break; 1245 } 1246 } else { 1247 trace_e1000e_rx_metadata_l4_cso_disabled(); 1248 } 1249 1250 func_exit: 1251 trace_e1000e_rx_metadata_status_flags(*status_flags); 1252 *status_flags = cpu_to_le32(*status_flags); 1253 } 1254 1255 static inline void 1256 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1257 struct NetRxPkt *pkt, 1258 const E1000E_RSSInfo *rss_info, 1259 uint16_t length) 1260 { 1261 uint32_t status_flags, rss, mrq; 1262 uint16_t ip_id; 1263 1264 assert(!rss_info->enabled); 1265 1266 desc->length = cpu_to_le16(length); 1267 desc->csum = 0; 1268 1269 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1270 rss_info, 1271 &rss, &mrq, 1272 &status_flags, &ip_id, 1273 &desc->special); 1274 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1275 desc->status = (uint8_t) le32_to_cpu(status_flags); 1276 } 1277 1278 static inline void 1279 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1280 struct NetRxPkt *pkt, 1281 const E1000E_RSSInfo *rss_info, 1282 uint16_t length) 1283 { 1284 memset(&desc->wb, 0, sizeof(desc->wb)); 1285 1286 desc->wb.upper.length = cpu_to_le16(length); 1287 1288 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1289 rss_info, 1290 &desc->wb.lower.hi_dword.rss, 1291 &desc->wb.lower.mrq, 1292 &desc->wb.upper.status_error, 1293 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1294 &desc->wb.upper.vlan); 1295 } 1296 1297 static inline void 1298 e1000e_write_ps_rx_descr(E1000ECore *core, 1299 union e1000_rx_desc_packet_split *desc, 1300 struct NetRxPkt *pkt, 1301 const E1000E_RSSInfo *rss_info, 1302 size_t ps_hdr_len, 1303 uint16_t(*written)[MAX_PS_BUFFERS]) 1304 { 1305 int i; 1306 1307 memset(&desc->wb, 0, sizeof(desc->wb)); 1308 1309 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1310 1311 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1312 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1313 } 1314 1315 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1316 rss_info, 1317 &desc->wb.lower.hi_dword.rss, 1318 &desc->wb.lower.mrq, 1319 &desc->wb.middle.status_error, 1320 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1321 &desc->wb.middle.vlan); 1322 1323 desc->wb.upper.header_status = 1324 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1325 1326 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1327 (*written)[2], (*written)[3]); 1328 } 1329 1330 static inline void 1331 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1332 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1333 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1334 { 1335 if (e1000e_rx_use_legacy_descriptor(core)) { 1336 assert(ps_hdr_len == 0); 1337 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1338 (*written)[0]); 1339 } else { 1340 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1341 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1342 ps_hdr_len, written); 1343 } else { 1344 assert(ps_hdr_len == 0); 1345 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1346 (*written)[0]); 1347 } 1348 } 1349 } 1350 1351 static inline void 1352 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1353 union e1000_rx_desc_union *desc, dma_addr_t len) 1354 { 1355 PCIDevice *dev = core->owner; 1356 1357 if (e1000e_rx_use_legacy_descriptor(core)) { 1358 struct e1000_rx_desc *d = &desc->legacy; 1359 size_t offset = offsetof(struct e1000_rx_desc, status); 1360 uint8_t status = d->status; 1361 1362 d->status &= ~E1000_RXD_STAT_DD; 1363 pci_dma_write(dev, addr, desc, len); 1364 1365 if (status & E1000_RXD_STAT_DD) { 1366 d->status = status; 1367 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1368 } 1369 } else { 1370 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1371 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1372 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1373 wb.middle.status_error); 1374 uint32_t status = d->wb.middle.status_error; 1375 1376 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1377 pci_dma_write(dev, addr, desc, len); 1378 1379 if (status & E1000_RXD_STAT_DD) { 1380 d->wb.middle.status_error = status; 1381 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1382 } 1383 } else { 1384 union e1000_rx_desc_extended *d = &desc->extended; 1385 size_t offset = offsetof(union e1000_rx_desc_extended, 1386 wb.upper.status_error); 1387 uint32_t status = d->wb.upper.status_error; 1388 1389 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1390 pci_dma_write(dev, addr, desc, len); 1391 1392 if (status & E1000_RXD_STAT_DD) { 1393 d->wb.upper.status_error = status; 1394 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1395 } 1396 } 1397 } 1398 } 1399 1400 typedef struct E1000EBAState { 1401 uint16_t written[MAX_PS_BUFFERS]; 1402 uint8_t cur_idx; 1403 } E1000EBAState; 1404 1405 static inline void 1406 e1000e_write_hdr_frag_to_rx_buffers(E1000ECore *core, 1407 hwaddr ba[MAX_PS_BUFFERS], 1408 E1000EBAState *bastate, 1409 const char *data, 1410 dma_addr_t data_len) 1411 { 1412 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1413 1414 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1415 bastate->written[0] += data_len; 1416 1417 bastate->cur_idx = 1; 1418 } 1419 1420 static void 1421 e1000e_write_payload_frag_to_rx_buffers(E1000ECore *core, 1422 hwaddr ba[MAX_PS_BUFFERS], 1423 E1000EBAState *bastate, 1424 const char *data, 1425 dma_addr_t data_len) 1426 { 1427 while (data_len > 0) { 1428 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1429 uint32_t cur_buf_bytes_left = cur_buf_len - 1430 bastate->written[bastate->cur_idx]; 1431 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1432 1433 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1434 ba[bastate->cur_idx], 1435 bastate->written[bastate->cur_idx], 1436 data, 1437 bytes_to_write); 1438 1439 pci_dma_write(core->owner, 1440 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1441 data, bytes_to_write); 1442 1443 bastate->written[bastate->cur_idx] += bytes_to_write; 1444 data += bytes_to_write; 1445 data_len -= bytes_to_write; 1446 1447 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1448 bastate->cur_idx++; 1449 } 1450 1451 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1452 } 1453 } 1454 1455 static void 1456 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) 1457 { 1458 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1459 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1460 } 1461 1462 static inline bool 1463 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000ERingInfo *rxi) 1464 { 1465 return e1000e_ring_free_descr_num(core, rxi) == 1466 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1467 } 1468 1469 static bool 1470 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1471 { 1472 bool hasip4, hasip6; 1473 EthL4HdrProto l4hdr_proto; 1474 bool fragment; 1475 1476 if (!e1000e_rx_use_ps_descriptor(core)) { 1477 return false; 1478 } 1479 1480 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1481 1482 if (hasip4) { 1483 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1484 } else if (hasip6) { 1485 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1486 } else { 1487 return false; 1488 } 1489 1490 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1491 return false; 1492 } 1493 1494 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1495 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1496 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1497 } else { 1498 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1499 } 1500 1501 if ((*hdr_len > core->rxbuf_sizes[0]) || 1502 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1503 return false; 1504 } 1505 1506 return true; 1507 } 1508 1509 static void 1510 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1511 const E1000E_RxRing *rxr, 1512 const E1000E_RSSInfo *rss_info) 1513 { 1514 PCIDevice *d = core->owner; 1515 dma_addr_t base; 1516 union e1000_rx_desc_union desc; 1517 size_t desc_size; 1518 size_t desc_offset = 0; 1519 size_t iov_ofs = 0; 1520 1521 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1522 size_t size = net_rx_pkt_get_total_len(pkt); 1523 size_t total_size = size + e1000x_fcs_len(core->mac); 1524 const E1000ERingInfo *rxi; 1525 size_t ps_hdr_len = 0; 1526 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1527 bool is_first = true; 1528 1529 rxi = rxr->i; 1530 1531 do { 1532 hwaddr ba[MAX_PS_BUFFERS]; 1533 E1000EBAState bastate = { { 0 } }; 1534 bool is_last = false; 1535 1536 desc_size = total_size - desc_offset; 1537 1538 if (desc_size > core->rx_desc_buf_size) { 1539 desc_size = core->rx_desc_buf_size; 1540 } 1541 1542 if (e1000e_ring_empty(core, rxi)) { 1543 return; 1544 } 1545 1546 base = e1000e_ring_head_descr(core, rxi); 1547 1548 pci_dma_read(d, base, &desc, core->rx_desc_len); 1549 1550 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1551 1552 e1000e_read_rx_descr(core, &desc, ba); 1553 1554 if (ba[0]) { 1555 if (desc_offset < size) { 1556 static const uint32_t fcs_pad; 1557 size_t iov_copy; 1558 size_t copy_size = size - desc_offset; 1559 if (copy_size > core->rx_desc_buf_size) { 1560 copy_size = core->rx_desc_buf_size; 1561 } 1562 1563 /* For PS mode copy the packet header first */ 1564 if (do_ps) { 1565 if (is_first) { 1566 size_t ps_hdr_copied = 0; 1567 do { 1568 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1569 iov->iov_len - iov_ofs); 1570 1571 e1000e_write_hdr_frag_to_rx_buffers(core, ba, 1572 &bastate, 1573 iov->iov_base, 1574 iov_copy); 1575 1576 copy_size -= iov_copy; 1577 ps_hdr_copied += iov_copy; 1578 1579 iov_ofs += iov_copy; 1580 if (iov_ofs == iov->iov_len) { 1581 iov++; 1582 iov_ofs = 0; 1583 } 1584 } while (ps_hdr_copied < ps_hdr_len); 1585 1586 is_first = false; 1587 } else { 1588 /* Leave buffer 0 of each descriptor except first */ 1589 /* empty as per spec 7.1.5.1 */ 1590 e1000e_write_hdr_frag_to_rx_buffers(core, ba, &bastate, 1591 NULL, 0); 1592 } 1593 } 1594 1595 /* Copy packet payload */ 1596 while (copy_size) { 1597 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1598 1599 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, 1600 iov->iov_base + 1601 iov_ofs, 1602 iov_copy); 1603 1604 copy_size -= iov_copy; 1605 iov_ofs += iov_copy; 1606 if (iov_ofs == iov->iov_len) { 1607 iov++; 1608 iov_ofs = 0; 1609 } 1610 } 1611 1612 if (desc_offset + desc_size >= total_size) { 1613 /* Simulate FCS checksum presence in the last descriptor */ 1614 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, 1615 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1616 } 1617 } 1618 } else { /* as per intel docs; skip descriptors with null buf addr */ 1619 trace_e1000e_rx_null_descriptor(); 1620 } 1621 desc_offset += desc_size; 1622 if (desc_offset >= total_size) { 1623 is_last = true; 1624 } 1625 1626 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1627 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1628 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1629 1630 e1000e_ring_advance(core, rxi, 1631 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1632 1633 } while (desc_offset < total_size); 1634 1635 e1000e_update_rx_stats(core, size, total_size); 1636 } 1637 1638 static inline void 1639 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1640 { 1641 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1642 1643 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1644 net_rx_pkt_fix_l4_csum(pkt); 1645 } 1646 } 1647 1648 ssize_t 1649 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1650 { 1651 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1652 } 1653 1654 static ssize_t 1655 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1656 bool has_vnet) 1657 { 1658 uint32_t causes = 0; 1659 uint8_t buf[ETH_ZLEN]; 1660 struct iovec min_iov; 1661 size_t size, orig_size; 1662 size_t iov_ofs = 0; 1663 E1000E_RxRing rxr; 1664 E1000E_RSSInfo rss_info; 1665 size_t total_size; 1666 ssize_t retval; 1667 bool rdmts_hit; 1668 1669 trace_e1000e_rx_receive_iov(iovcnt); 1670 1671 if (!e1000x_hw_rx_enabled(core->mac)) { 1672 return -1; 1673 } 1674 1675 /* Pull virtio header in */ 1676 if (has_vnet) { 1677 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1678 iov_ofs = sizeof(struct virtio_net_hdr); 1679 } else { 1680 net_rx_pkt_unset_vhdr(core->rx_pkt); 1681 } 1682 1683 orig_size = iov_size(iov, iovcnt); 1684 size = orig_size - iov_ofs; 1685 1686 /* Pad to minimum Ethernet frame length */ 1687 if (size < sizeof(buf)) { 1688 iov_to_buf(iov, iovcnt, iov_ofs, buf, size); 1689 memset(&buf[size], 0, sizeof(buf) - size); 1690 e1000x_inc_reg_if_not_full(core->mac, RUC); 1691 min_iov.iov_base = buf; 1692 min_iov.iov_len = size = sizeof(buf); 1693 iovcnt = 1; 1694 iov = &min_iov; 1695 iov_ofs = 0; 1696 } else { 1697 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4); 1698 } 1699 1700 /* Discard oversized packets if !LPE and !SBP. */ 1701 if (e1000x_is_oversized(core->mac, size)) { 1702 return orig_size; 1703 } 1704 1705 net_rx_pkt_set_packet_type(core->rx_pkt, 1706 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1707 1708 if (!e1000e_receive_filter(core, buf)) { 1709 trace_e1000e_rx_flt_dropped(); 1710 return orig_size; 1711 } 1712 1713 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1714 e1000x_vlan_enabled(core->mac) ? 0 : -1, 1715 core->mac[VET], 0); 1716 1717 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1718 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1719 1720 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1721 e1000x_fcs_len(core->mac); 1722 1723 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1724 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1725 1726 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1727 1728 retval = orig_size; 1729 1730 /* Perform small receive detection (RSRPD) */ 1731 if (total_size < core->mac[RSRPD]) { 1732 causes |= E1000_ICS_SRPD; 1733 } 1734 1735 /* Perform ACK receive detection */ 1736 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1737 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1738 causes |= E1000_ICS_ACK; 1739 } 1740 1741 /* Check if receive descriptor minimum threshold hit */ 1742 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1743 causes |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1744 1745 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1746 } else { 1747 causes |= E1000_ICS_RXO; 1748 retval = 0; 1749 1750 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1751 } 1752 1753 if (!e1000e_intrmgr_delay_rx_causes(core, &causes)) { 1754 trace_e1000e_rx_interrupt_set(causes); 1755 e1000e_set_interrupt_cause(core, causes); 1756 } else { 1757 trace_e1000e_rx_interrupt_delayed(causes); 1758 } 1759 1760 return retval; 1761 } 1762 1763 static inline bool 1764 e1000e_have_autoneg(E1000ECore *core) 1765 { 1766 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1767 } 1768 1769 static void e1000e_update_flowctl_status(E1000ECore *core) 1770 { 1771 if (e1000e_have_autoneg(core) && 1772 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1773 trace_e1000e_link_autoneg_flowctl(true); 1774 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1775 } else { 1776 trace_e1000e_link_autoneg_flowctl(false); 1777 } 1778 } 1779 1780 static inline void 1781 e1000e_link_down(E1000ECore *core) 1782 { 1783 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1784 e1000e_update_flowctl_status(core); 1785 } 1786 1787 static inline void 1788 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1789 { 1790 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1791 core->phy[0][MII_BMCR] = val & ~(0x3f | 1792 MII_BMCR_RESET | 1793 MII_BMCR_ANRESTART); 1794 1795 if ((val & MII_BMCR_ANRESTART) && 1796 e1000e_have_autoneg(core)) { 1797 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1798 } 1799 } 1800 1801 static void 1802 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1803 { 1804 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1805 1806 if (val & BIT(10)) { 1807 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1808 } 1809 } 1810 1811 static void 1812 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1813 { 1814 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1815 } 1816 1817 void 1818 e1000e_core_set_link_status(E1000ECore *core) 1819 { 1820 NetClientState *nc = qemu_get_queue(core->owner_nic); 1821 uint32_t old_status = core->mac[STATUS]; 1822 1823 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1824 1825 if (nc->link_down) { 1826 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1827 } else { 1828 if (e1000e_have_autoneg(core) && 1829 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1830 e1000x_restart_autoneg(core->mac, core->phy[0], 1831 core->autoneg_timer); 1832 } else { 1833 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1834 e1000e_start_recv(core); 1835 } 1836 } 1837 1838 if (core->mac[STATUS] != old_status) { 1839 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1840 } 1841 } 1842 1843 static void 1844 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1845 { 1846 trace_e1000e_core_ctrl_write(index, val); 1847 1848 /* RST is self clearing */ 1849 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1850 core->mac[CTRL_DUP] = core->mac[CTRL]; 1851 1852 trace_e1000e_link_set_params( 1853 !!(val & E1000_CTRL_ASDE), 1854 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1855 !!(val & E1000_CTRL_FRCSPD), 1856 !!(val & E1000_CTRL_FRCDPX), 1857 !!(val & E1000_CTRL_RFCE), 1858 !!(val & E1000_CTRL_TFCE)); 1859 1860 if (val & E1000_CTRL_RST) { 1861 trace_e1000e_core_ctrl_sw_reset(); 1862 e1000e_reset(core, true); 1863 } 1864 1865 if (val & E1000_CTRL_PHY_RST) { 1866 trace_e1000e_core_ctrl_phy_reset(); 1867 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1868 } 1869 } 1870 1871 static void 1872 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1873 { 1874 trace_e1000e_rx_set_rfctl(val); 1875 1876 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1877 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1878 } 1879 1880 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1881 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1882 } 1883 1884 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1885 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1886 } 1887 1888 core->mac[RFCTL] = val; 1889 } 1890 1891 static void 1892 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1893 { 1894 int i; 1895 core->rx_desc_buf_size = 0; 1896 1897 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1898 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1899 } 1900 } 1901 1902 static void 1903 e1000e_parse_rxbufsize(E1000ECore *core) 1904 { 1905 uint32_t rctl = core->mac[RCTL]; 1906 1907 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1908 1909 if (rctl & E1000_RCTL_DTYP_MASK) { 1910 uint32_t bsize; 1911 1912 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1913 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1914 1915 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1916 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1917 1918 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1919 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1920 1921 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1922 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1923 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1924 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1925 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1926 } else { 1927 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1928 } 1929 1930 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1931 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1932 1933 e1000e_calc_per_desc_buf_size(core); 1934 } 1935 1936 static void 1937 e1000e_calc_rxdesclen(E1000ECore *core) 1938 { 1939 if (e1000e_rx_use_legacy_descriptor(core)) { 1940 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1941 } else { 1942 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1943 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1944 } else { 1945 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1946 } 1947 } 1948 trace_e1000e_rx_desc_len(core->rx_desc_len); 1949 } 1950 1951 static void 1952 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1953 { 1954 core->mac[RCTL] = val; 1955 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1956 1957 if (val & E1000_RCTL_EN) { 1958 e1000e_parse_rxbufsize(core); 1959 e1000e_calc_rxdesclen(core); 1960 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1961 E1000_RING_DESC_LEN_SHIFT; 1962 1963 e1000e_start_recv(core); 1964 } 1965 } 1966 1967 static 1968 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1969 (E1000ECore *, int, uint16_t) = { 1970 [0] = { 1971 [MII_BMCR] = e1000e_set_phy_ctrl, 1972 [PHY_PAGE] = e1000e_set_phy_page, 1973 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1974 } 1975 }; 1976 1977 static inline bool 1978 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 1979 { 1980 if (timer->running) { 1981 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1982 1983 return true; 1984 } 1985 1986 if (timer->core->mac[timer->delay_reg] != 0) { 1987 e1000e_intrmgr_rearm_timer(timer); 1988 } 1989 1990 return false; 1991 } 1992 1993 static inline bool 1994 e1000e_itr_should_postpone(E1000ECore *core) 1995 { 1996 return e1000e_postpone_interrupt(&core->itr); 1997 } 1998 1999 static inline bool 2000 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 2001 { 2002 return e1000e_postpone_interrupt(&core->eitr[idx]); 2003 } 2004 2005 static void 2006 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2007 { 2008 uint32_t effective_eiac; 2009 2010 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2011 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2012 if (vec < E1000E_MSIX_VEC_NUM) { 2013 if (!e1000e_eitr_should_postpone(core, vec)) { 2014 trace_e1000e_irq_msix_notify_vec(vec); 2015 msix_notify(core->owner, vec); 2016 } 2017 } else { 2018 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2019 } 2020 } else { 2021 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2022 } 2023 2024 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2025 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2026 core->mac[IAM] &= ~cause; 2027 } 2028 2029 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2030 2031 effective_eiac = core->mac[EIAC] & cause; 2032 2033 core->mac[ICR] &= ~effective_eiac; 2034 2035 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2036 core->mac[IMS] &= ~effective_eiac; 2037 } 2038 } 2039 2040 static void 2041 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2042 { 2043 if (causes & E1000_ICR_RXQ0) { 2044 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2045 E1000_IVAR_RXQ0(core->mac[IVAR])); 2046 } 2047 2048 if (causes & E1000_ICR_RXQ1) { 2049 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2050 E1000_IVAR_RXQ1(core->mac[IVAR])); 2051 } 2052 2053 if (causes & E1000_ICR_TXQ0) { 2054 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2055 E1000_IVAR_TXQ0(core->mac[IVAR])); 2056 } 2057 2058 if (causes & E1000_ICR_TXQ1) { 2059 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2060 E1000_IVAR_TXQ1(core->mac[IVAR])); 2061 } 2062 2063 if (causes & E1000_ICR_OTHER) { 2064 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2065 E1000_IVAR_OTHER(core->mac[IVAR])); 2066 } 2067 } 2068 2069 static void 2070 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2071 { 2072 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2073 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2074 if (vec < E1000E_MSIX_VEC_NUM) { 2075 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2076 msix_clr_pending(core->owner, vec); 2077 } else { 2078 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2079 } 2080 } else { 2081 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2082 } 2083 } 2084 2085 static void 2086 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2087 { 2088 if (causes & E1000_ICR_RXQ0) { 2089 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2090 E1000_IVAR_RXQ0(core->mac[IVAR])); 2091 } 2092 2093 if (causes & E1000_ICR_RXQ1) { 2094 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2095 E1000_IVAR_RXQ1(core->mac[IVAR])); 2096 } 2097 2098 if (causes & E1000_ICR_TXQ0) { 2099 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2100 E1000_IVAR_TXQ0(core->mac[IVAR])); 2101 } 2102 2103 if (causes & E1000_ICR_TXQ1) { 2104 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2105 E1000_IVAR_TXQ1(core->mac[IVAR])); 2106 } 2107 2108 if (causes & E1000_ICR_OTHER) { 2109 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2110 E1000_IVAR_OTHER(core->mac[IVAR])); 2111 } 2112 } 2113 2114 static inline void 2115 e1000e_fix_icr_asserted(E1000ECore *core) 2116 { 2117 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2118 if (core->mac[ICR]) { 2119 core->mac[ICR] |= E1000_ICR_ASSERTED; 2120 } 2121 2122 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2123 } 2124 2125 static void e1000e_raise_interrupts(E1000ECore *core, 2126 size_t index, uint32_t causes) 2127 { 2128 bool is_msix = msix_enabled(core->owner); 2129 uint32_t old_causes = core->mac[IMS] & core->mac[ICR]; 2130 uint32_t raised_causes; 2131 2132 trace_e1000e_irq_set(index << 2, 2133 core->mac[index], core->mac[index] | causes); 2134 2135 core->mac[index] |= causes; 2136 2137 /* Set ICR[OTHER] for MSI-X */ 2138 if (is_msix) { 2139 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2140 core->mac[ICR] |= E1000_ICR_OTHER; 2141 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2142 } 2143 } 2144 2145 e1000e_fix_icr_asserted(core); 2146 2147 /* 2148 * Make sure ICR and ICS registers have the same value. 2149 * The spec says that the ICS register is write-only. However in practice, 2150 * on real hardware ICS is readable, and for reads it has the same value as 2151 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2152 * 2153 * The VxWorks PRO/1000 driver uses this behaviour. 2154 */ 2155 core->mac[ICS] = core->mac[ICR]; 2156 2157 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2158 core->mac[ICR], core->mac[IMS]); 2159 2160 raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes; 2161 if (!raised_causes) { 2162 return; 2163 } 2164 2165 if (is_msix) { 2166 e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED); 2167 } else if (!e1000e_itr_should_postpone(core)) { 2168 if (msi_enabled(core->owner)) { 2169 trace_e1000e_irq_msi_notify(raised_causes); 2170 msi_notify(core->owner, 0); 2171 } else { 2172 e1000e_raise_legacy_irq(core); 2173 } 2174 } 2175 } 2176 2177 static void e1000e_lower_interrupts(E1000ECore *core, 2178 size_t index, uint32_t causes) 2179 { 2180 trace_e1000e_irq_clear(index << 2, 2181 core->mac[index], core->mac[index] & ~causes); 2182 2183 core->mac[index] &= ~causes; 2184 2185 /* 2186 * Make sure ICR and ICS registers have the same value. 2187 * The spec says that the ICS register is write-only. However in practice, 2188 * on real hardware ICS is readable, and for reads it has the same value as 2189 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2190 * 2191 * The VxWorks PRO/1000 driver uses this behaviour. 2192 */ 2193 core->mac[ICS] = core->mac[ICR]; 2194 2195 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2196 core->mac[ICR], core->mac[IMS]); 2197 2198 if (!(core->mac[IMS] & core->mac[ICR]) && 2199 !msix_enabled(core->owner) && !msi_enabled(core->owner)) { 2200 e1000e_lower_legacy_irq(core); 2201 } 2202 } 2203 2204 static void 2205 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2206 { 2207 val |= e1000e_intmgr_collect_delayed_causes(core); 2208 e1000e_raise_interrupts(core, ICR, val); 2209 } 2210 2211 static inline void 2212 e1000e_autoneg_timer(void *opaque) 2213 { 2214 E1000ECore *core = opaque; 2215 if (!qemu_get_queue(core->owner_nic)->link_down) { 2216 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2217 e1000e_start_recv(core); 2218 2219 e1000e_update_flowctl_status(core); 2220 /* signal link status change to the guest */ 2221 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2222 } 2223 } 2224 2225 static inline uint16_t 2226 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2227 { 2228 uint16_t index = (addr & 0x1ffff) >> 2; 2229 return index + (mac_reg_access[index] & 0xfffe); 2230 } 2231 2232 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2233 [0] = { 2234 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2235 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2236 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2237 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2238 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2239 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2240 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2241 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2242 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2243 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2244 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2245 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2246 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2247 2248 [PHY_COPPER_CTRL1] = PHY_RW, 2249 [PHY_COPPER_STAT1] = PHY_R, 2250 [PHY_COPPER_CTRL3] = PHY_RW, 2251 [PHY_RX_ERR_CNTR] = PHY_R, 2252 [PHY_OEM_BITS] = PHY_RW, 2253 [PHY_BIAS_1] = PHY_RW, 2254 [PHY_BIAS_2] = PHY_RW, 2255 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2256 [PHY_COPPER_STAT2] = PHY_R, 2257 [PHY_COPPER_CTRL2] = PHY_RW 2258 }, 2259 [2] = { 2260 [PHY_MAC_CTRL1] = PHY_RW, 2261 [PHY_MAC_INT_ENABLE] = PHY_RW, 2262 [PHY_MAC_STAT] = PHY_R, 2263 [PHY_MAC_CTRL2] = PHY_RW 2264 }, 2265 [3] = { 2266 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2267 [PHY_LED_03_POL_CTRL] = PHY_RW, 2268 [PHY_LED_TIMER_CTRL] = PHY_RW, 2269 [PHY_LED_45_CTRL] = PHY_RW 2270 }, 2271 [5] = { 2272 [PHY_1000T_SKEW] = PHY_R, 2273 [PHY_1000T_SWAP] = PHY_R 2274 }, 2275 [6] = { 2276 [PHY_CRC_COUNTERS] = PHY_R 2277 } 2278 }; 2279 2280 static bool 2281 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2282 char cap, uint8_t *page) 2283 { 2284 *page = 2285 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2286 : core->phy[0][PHY_PAGE]; 2287 2288 if (*page >= E1000E_PHY_PAGES) { 2289 return false; 2290 } 2291 2292 return e1000e_phy_regcap[*page][addr] & cap; 2293 } 2294 2295 static void 2296 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2297 uint32_t addr, uint16_t data) 2298 { 2299 assert(page < E1000E_PHY_PAGES); 2300 assert(addr < E1000E_PHY_PAGE_SIZE); 2301 2302 if (e1000e_phyreg_writeops[page][addr]) { 2303 e1000e_phyreg_writeops[page][addr](core, addr, data); 2304 } else { 2305 core->phy[page][addr] = data; 2306 } 2307 } 2308 2309 static void 2310 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2311 { 2312 uint32_t data = val & E1000_MDIC_DATA_MASK; 2313 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2314 uint8_t page; 2315 2316 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2317 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2318 } else if (val & E1000_MDIC_OP_READ) { 2319 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2320 trace_e1000e_core_mdic_read_unhandled(page, addr); 2321 val |= E1000_MDIC_ERROR; 2322 } else { 2323 val = (val ^ data) | core->phy[page][addr]; 2324 trace_e1000e_core_mdic_read(page, addr, val); 2325 } 2326 } else if (val & E1000_MDIC_OP_WRITE) { 2327 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2328 trace_e1000e_core_mdic_write_unhandled(page, addr); 2329 val |= E1000_MDIC_ERROR; 2330 } else { 2331 trace_e1000e_core_mdic_write(page, addr, data); 2332 e1000e_phy_reg_write(core, page, addr, data); 2333 } 2334 } 2335 core->mac[MDIC] = val | E1000_MDIC_READY; 2336 2337 if (val & E1000_MDIC_INT_EN) { 2338 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2339 } 2340 } 2341 2342 static void 2343 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2344 { 2345 core->mac[index] = val & 0xffff; 2346 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2347 e1000e_start_recv(core); 2348 } 2349 2350 static void 2351 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2352 { 2353 if ((val & E1000_STATUS_PHYRA) == 0) { 2354 core->mac[index] &= ~E1000_STATUS_PHYRA; 2355 } 2356 } 2357 2358 static void 2359 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2360 { 2361 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2362 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2363 2364 /* Zero self-clearing bits */ 2365 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2366 core->mac[CTRL_EXT] = val; 2367 } 2368 2369 static void 2370 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2371 { 2372 int i; 2373 2374 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2375 2376 if (!msix_enabled(core->owner)) { 2377 return; 2378 } 2379 2380 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2381 if (core->mac[PBACLR] & BIT(i)) { 2382 msix_clr_pending(core->owner, i); 2383 } 2384 } 2385 } 2386 2387 static void 2388 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2389 { 2390 core->mac[FCRTH] = val & 0xFFF8; 2391 } 2392 2393 static void 2394 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2395 { 2396 core->mac[FCRTL] = val & 0x8000FFF8; 2397 } 2398 2399 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2400 static void \ 2401 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2402 { \ 2403 core->mac[index] = val & (BIT(num) - 1); \ 2404 } 2405 2406 E1000E_LOW_BITS_SET_FUNC(4) 2407 E1000E_LOW_BITS_SET_FUNC(6) 2408 E1000E_LOW_BITS_SET_FUNC(11) 2409 E1000E_LOW_BITS_SET_FUNC(12) 2410 E1000E_LOW_BITS_SET_FUNC(13) 2411 E1000E_LOW_BITS_SET_FUNC(16) 2412 2413 static void 2414 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2415 { 2416 core->mac[VET] = val & 0xffff; 2417 trace_e1000e_vlan_vet(core->mac[VET]); 2418 } 2419 2420 static void 2421 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2422 { 2423 core->mac[index] = val & E1000_XDLEN_MASK; 2424 } 2425 2426 static void 2427 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2428 { 2429 core->mac[index] = val & E1000_XDBAL_MASK; 2430 } 2431 2432 static void 2433 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2434 { 2435 E1000E_TxRing txr; 2436 core->mac[index] = val; 2437 2438 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2439 e1000e_tx_ring_init(core, &txr, 0); 2440 e1000e_start_xmit(core, &txr); 2441 } 2442 2443 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2444 e1000e_tx_ring_init(core, &txr, 1); 2445 e1000e_start_xmit(core, &txr); 2446 } 2447 } 2448 2449 static void 2450 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2451 { 2452 E1000E_TxRing txr; 2453 int qidx = e1000e_mq_queue_idx(TDT, index); 2454 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2455 2456 core->mac[index] = val & 0xffff; 2457 2458 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2459 e1000e_tx_ring_init(core, &txr, qidx); 2460 e1000e_start_xmit(core, &txr); 2461 } 2462 } 2463 2464 static void 2465 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2466 { 2467 trace_e1000e_irq_write_ics(val); 2468 e1000e_set_interrupt_cause(core, val); 2469 } 2470 2471 static void 2472 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2473 { 2474 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2475 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2476 trace_e1000e_irq_icr_process_iame(); 2477 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2478 } 2479 2480 /* 2481 * Windows driver expects that the "receive overrun" bit and other 2482 * ones to be cleared when the "Other" bit (#24) is cleared. 2483 */ 2484 if (val & E1000_ICR_OTHER) { 2485 val |= E1000_ICR_OTHER_CAUSES; 2486 } 2487 e1000e_lower_interrupts(core, ICR, val); 2488 } 2489 2490 static void 2491 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2492 { 2493 trace_e1000e_irq_ims_clear_set_imc(val); 2494 e1000e_lower_interrupts(core, IMS, val); 2495 } 2496 2497 static void 2498 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2499 { 2500 static const uint32_t ims_ext_mask = 2501 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2502 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2503 E1000_IMS_OTHER; 2504 2505 static const uint32_t ims_valid_mask = 2506 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2507 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2508 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2509 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2510 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2511 E1000_IMS_OTHER; 2512 2513 uint32_t valid_val = val & ims_valid_mask; 2514 2515 if ((valid_val & ims_ext_mask) && 2516 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2517 msix_enabled(core->owner)) { 2518 e1000e_msix_clear(core, valid_val); 2519 } 2520 2521 if ((valid_val == ims_valid_mask) && 2522 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2523 trace_e1000e_irq_fire_all_timers(val); 2524 e1000e_intrmgr_fire_all_timers(core); 2525 } 2526 2527 e1000e_raise_interrupts(core, IMS, valid_val); 2528 } 2529 2530 static void 2531 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2532 { 2533 e1000e_set_16bit(core, index, val); 2534 2535 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2536 trace_e1000e_irq_rdtr_fpd_running(); 2537 e1000e_intrmgr_fire_delayed_interrupts(core); 2538 } else { 2539 trace_e1000e_irq_rdtr_fpd_not_running(); 2540 } 2541 } 2542 2543 static void 2544 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2545 { 2546 e1000e_set_16bit(core, index, val); 2547 2548 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2549 trace_e1000e_irq_tidv_fpd_running(); 2550 e1000e_intrmgr_fire_delayed_interrupts(core); 2551 } else { 2552 trace_e1000e_irq_tidv_fpd_not_running(); 2553 } 2554 } 2555 2556 static uint32_t 2557 e1000e_mac_readreg(E1000ECore *core, int index) 2558 { 2559 return core->mac[index]; 2560 } 2561 2562 static uint32_t 2563 e1000e_mac_ics_read(E1000ECore *core, int index) 2564 { 2565 trace_e1000e_irq_read_ics(core->mac[ICS]); 2566 return core->mac[ICS]; 2567 } 2568 2569 static uint32_t 2570 e1000e_mac_ims_read(E1000ECore *core, int index) 2571 { 2572 trace_e1000e_irq_read_ims(core->mac[IMS]); 2573 return core->mac[IMS]; 2574 } 2575 2576 static uint32_t 2577 e1000e_mac_swsm_read(E1000ECore *core, int index) 2578 { 2579 uint32_t val = core->mac[SWSM]; 2580 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2581 return val; 2582 } 2583 2584 static uint32_t 2585 e1000e_mac_itr_read(E1000ECore *core, int index) 2586 { 2587 return core->itr_guest_value; 2588 } 2589 2590 static uint32_t 2591 e1000e_mac_eitr_read(E1000ECore *core, int index) 2592 { 2593 return core->eitr_guest_value[index - EITR]; 2594 } 2595 2596 static uint32_t 2597 e1000e_mac_icr_read(E1000ECore *core, int index) 2598 { 2599 uint32_t ret = core->mac[ICR]; 2600 2601 if (core->mac[IMS] == 0) { 2602 trace_e1000e_irq_icr_clear_zero_ims(); 2603 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2604 } 2605 2606 if (!msix_enabled(core->owner)) { 2607 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2608 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2609 } 2610 2611 if (core->mac[ICR] & E1000_ICR_ASSERTED) { 2612 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) { 2613 trace_e1000e_irq_icr_clear_iame(); 2614 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2615 trace_e1000e_irq_icr_process_iame(); 2616 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2617 } 2618 2619 /* 2620 * The datasheet does not say what happens when interrupt was asserted 2621 * (ICR.INT_ASSERT=1) and auto mask is *not* active. 2622 * However, section of 13.3.27 the PCIe* GbE Controllers Open Source 2623 * Software Developer’s Manual, which were written for older devices, 2624 * namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI & 2625 * 82573E/82573V/82573L, does say: 2626 * > If IMS = 0b, then the ICR register is always clear-on-read. If IMS 2627 * > is not 0b, but some ICR bit is set where the corresponding IMS bit 2628 * > is not set, then a read does not clear the ICR register. For 2629 * > example, if IMS = 10101010b and ICR = 01010101b, then a read to the 2630 * > ICR register does not clear it. If IMS = 10101010b and 2631 * > ICR = 0101011b, then a read to the ICR register clears it entirely 2632 * > (ICR.INT_ASSERTED = 1b). 2633 * 2634 * Linux does no longer activate auto mask since commit 2635 * 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware 2636 * clears ICR even in such a case so we also should do so. 2637 */ 2638 if (core->mac[ICR] & core->mac[IMS]) { 2639 trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR], 2640 core->mac[IMS]); 2641 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2642 } 2643 } 2644 2645 return ret; 2646 } 2647 2648 static uint32_t 2649 e1000e_mac_read_clr4(E1000ECore *core, int index) 2650 { 2651 uint32_t ret = core->mac[index]; 2652 2653 core->mac[index] = 0; 2654 return ret; 2655 } 2656 2657 static uint32_t 2658 e1000e_mac_read_clr8(E1000ECore *core, int index) 2659 { 2660 uint32_t ret = core->mac[index]; 2661 2662 core->mac[index] = 0; 2663 core->mac[index - 1] = 0; 2664 return ret; 2665 } 2666 2667 static uint32_t 2668 e1000e_get_ctrl(E1000ECore *core, int index) 2669 { 2670 uint32_t val = core->mac[CTRL]; 2671 2672 trace_e1000e_link_read_params( 2673 !!(val & E1000_CTRL_ASDE), 2674 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2675 !!(val & E1000_CTRL_FRCSPD), 2676 !!(val & E1000_CTRL_FRCDPX), 2677 !!(val & E1000_CTRL_RFCE), 2678 !!(val & E1000_CTRL_TFCE)); 2679 2680 return val; 2681 } 2682 2683 static uint32_t 2684 e1000e_get_status(E1000ECore *core, int index) 2685 { 2686 uint32_t res = core->mac[STATUS]; 2687 2688 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2689 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2690 } 2691 2692 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2693 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2694 } else { 2695 res |= E1000_STATUS_FD; 2696 } 2697 2698 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2699 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2700 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2701 case E1000_CTRL_SPD_10: 2702 res |= E1000_STATUS_SPEED_10; 2703 break; 2704 case E1000_CTRL_SPD_100: 2705 res |= E1000_STATUS_SPEED_100; 2706 break; 2707 case E1000_CTRL_SPD_1000: 2708 default: 2709 res |= E1000_STATUS_SPEED_1000; 2710 break; 2711 } 2712 } else { 2713 res |= E1000_STATUS_SPEED_1000; 2714 } 2715 2716 trace_e1000e_link_status( 2717 !!(res & E1000_STATUS_LU), 2718 !!(res & E1000_STATUS_FD), 2719 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2720 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2721 2722 return res; 2723 } 2724 2725 static uint32_t 2726 e1000e_get_tarc(E1000ECore *core, int index) 2727 { 2728 return core->mac[index] & ((BIT(11) - 1) | 2729 BIT(27) | 2730 BIT(28) | 2731 BIT(29) | 2732 BIT(30)); 2733 } 2734 2735 static void 2736 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2737 { 2738 core->mac[index] = val; 2739 } 2740 2741 static void 2742 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2743 { 2744 uint32_t macaddr[2]; 2745 2746 core->mac[index] = val; 2747 2748 macaddr[0] = cpu_to_le32(core->mac[RA]); 2749 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2750 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2751 (uint8_t *) macaddr); 2752 2753 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2754 } 2755 2756 static void 2757 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2758 { 2759 static const uint32_t ro_bits = E1000_EECD_PRES | 2760 E1000_EECD_AUTO_RD | 2761 E1000_EECD_SIZE_EX_MASK; 2762 2763 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2764 } 2765 2766 static void 2767 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2768 { 2769 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2770 uint32_t flags = 0; 2771 uint32_t data = 0; 2772 2773 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2774 data = core->eeprom[addr]; 2775 flags = E1000_EERW_DONE; 2776 } 2777 2778 core->mac[EERD] = flags | 2779 (addr << E1000_EERW_ADDR_SHIFT) | 2780 (data << E1000_EERW_DATA_SHIFT); 2781 } 2782 2783 static void 2784 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2785 { 2786 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2787 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2788 uint32_t flags = 0; 2789 2790 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2791 core->eeprom[addr] = data; 2792 flags = E1000_EERW_DONE; 2793 } 2794 2795 core->mac[EERD] = flags | 2796 (addr << E1000_EERW_ADDR_SHIFT) | 2797 (data << E1000_EERW_DATA_SHIFT); 2798 } 2799 2800 static void 2801 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2802 { 2803 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2804 } 2805 2806 static void 2807 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2808 { 2809 uint32_t interval = val & 0xffff; 2810 2811 trace_e1000e_irq_itr_set(val); 2812 2813 core->itr_guest_value = interval; 2814 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2815 } 2816 2817 static void 2818 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2819 { 2820 uint32_t interval = val & 0xffff; 2821 uint32_t eitr_num = index - EITR; 2822 2823 trace_e1000e_irq_eitr_set(eitr_num, val); 2824 2825 core->eitr_guest_value[eitr_num] = interval; 2826 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2827 } 2828 2829 static void 2830 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2831 { 2832 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2833 2834 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2835 qemu_log_mask(LOG_GUEST_ERROR, 2836 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2837 return; 2838 } 2839 2840 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2841 qemu_log_mask(LOG_GUEST_ERROR, 2842 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2843 return; 2844 } 2845 } 2846 2847 core->mac[PSRCTL] = val; 2848 } 2849 2850 static void 2851 e1000e_update_rx_offloads(E1000ECore *core) 2852 { 2853 int cso_state = e1000e_rx_l4_cso_enabled(core); 2854 2855 trace_e1000e_rx_set_cso(cso_state); 2856 2857 if (core->has_vnet) { 2858 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2859 cso_state, 0, 0, 0, 0, 0, 0); 2860 } 2861 } 2862 2863 static void 2864 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2865 { 2866 core->mac[RXCSUM] = val; 2867 e1000e_update_rx_offloads(core); 2868 } 2869 2870 static void 2871 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2872 { 2873 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2874 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2875 } 2876 2877 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) 2878 { 2879 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2880 return core->mac[SYSTIML]; 2881 } 2882 2883 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) 2884 { 2885 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2886 return core->mac[RXSATRH]; 2887 } 2888 2889 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) 2890 { 2891 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2892 return core->mac[TXSTMPH]; 2893 } 2894 2895 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) 2896 { 2897 e1000x_set_timinca(core->mac, &core->timadj, val); 2898 } 2899 2900 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) 2901 { 2902 core->mac[TIMADJH] = val; 2903 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2904 } 2905 2906 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2907 typedef uint32_t (*readops)(E1000ECore *, int); 2908 static const readops e1000e_macreg_readops[] = { 2909 e1000e_getreg(PBA), 2910 e1000e_getreg(WUFC), 2911 e1000e_getreg(MANC), 2912 e1000e_getreg(TOTL), 2913 e1000e_getreg(RDT0), 2914 e1000e_getreg(RDBAH0), 2915 e1000e_getreg(TDBAL1), 2916 e1000e_getreg(RDLEN0), 2917 e1000e_getreg(RDH1), 2918 e1000e_getreg(LATECOL), 2919 e1000e_getreg(SEQEC), 2920 e1000e_getreg(XONTXC), 2921 e1000e_getreg(AIT), 2922 e1000e_getreg(TDFH), 2923 e1000e_getreg(TDFT), 2924 e1000e_getreg(TDFHS), 2925 e1000e_getreg(TDFTS), 2926 e1000e_getreg(TDFPC), 2927 e1000e_getreg(WUS), 2928 e1000e_getreg(PBS), 2929 e1000e_getreg(RDFH), 2930 e1000e_getreg(RDFT), 2931 e1000e_getreg(RDFHS), 2932 e1000e_getreg(RDFTS), 2933 e1000e_getreg(RDFPC), 2934 e1000e_getreg(GORCL), 2935 e1000e_getreg(MGTPRC), 2936 e1000e_getreg(EERD), 2937 e1000e_getreg(EIAC), 2938 e1000e_getreg(PSRCTL), 2939 e1000e_getreg(MANC2H), 2940 e1000e_getreg(RXCSUM), 2941 e1000e_getreg(GSCL_3), 2942 e1000e_getreg(GSCN_2), 2943 e1000e_getreg(RSRPD), 2944 e1000e_getreg(RDBAL1), 2945 e1000e_getreg(FCAH), 2946 e1000e_getreg(FCRTH), 2947 e1000e_getreg(FLOP), 2948 e1000e_getreg(FLASHT), 2949 e1000e_getreg(RXSTMPH), 2950 e1000e_getreg(TXSTMPL), 2951 e1000e_getreg(TIMADJL), 2952 e1000e_getreg(TXDCTL), 2953 e1000e_getreg(RDH0), 2954 e1000e_getreg(TDT1), 2955 e1000e_getreg(TNCRS), 2956 e1000e_getreg(RJC), 2957 e1000e_getreg(IAM), 2958 e1000e_getreg(GSCL_2), 2959 e1000e_getreg(RDBAH1), 2960 e1000e_getreg(FLSWDATA), 2961 e1000e_getreg(TIPG), 2962 e1000e_getreg(FLMNGCTL), 2963 e1000e_getreg(FLMNGCNT), 2964 e1000e_getreg(TSYNCTXCTL), 2965 e1000e_getreg(EXTCNF_SIZE), 2966 e1000e_getreg(EXTCNF_CTRL), 2967 e1000e_getreg(EEMNGDATA), 2968 e1000e_getreg(CTRL_EXT), 2969 e1000e_getreg(SYSTIMH), 2970 e1000e_getreg(EEMNGCTL), 2971 e1000e_getreg(FLMNGDATA), 2972 e1000e_getreg(TSYNCRXCTL), 2973 e1000e_getreg(TDH), 2974 e1000e_getreg(LEDCTL), 2975 e1000e_getreg(TCTL), 2976 e1000e_getreg(TDBAL), 2977 e1000e_getreg(TDLEN), 2978 e1000e_getreg(TDH1), 2979 e1000e_getreg(RADV), 2980 e1000e_getreg(ECOL), 2981 e1000e_getreg(DC), 2982 e1000e_getreg(RLEC), 2983 e1000e_getreg(XOFFTXC), 2984 e1000e_getreg(RFC), 2985 e1000e_getreg(RNBC), 2986 e1000e_getreg(MGTPTC), 2987 e1000e_getreg(TIMINCA), 2988 e1000e_getreg(RXCFGL), 2989 e1000e_getreg(MFUTP01), 2990 e1000e_getreg(FACTPS), 2991 e1000e_getreg(GSCL_1), 2992 e1000e_getreg(GSCN_0), 2993 e1000e_getreg(GCR2), 2994 e1000e_getreg(RDT1), 2995 e1000e_getreg(PBACLR), 2996 e1000e_getreg(FCTTV), 2997 e1000e_getreg(EEWR), 2998 e1000e_getreg(FLSWCTL), 2999 e1000e_getreg(RXDCTL1), 3000 e1000e_getreg(RXSATRL), 3001 e1000e_getreg(RXUDP), 3002 e1000e_getreg(TORL), 3003 e1000e_getreg(TDLEN1), 3004 e1000e_getreg(MCC), 3005 e1000e_getreg(WUC), 3006 e1000e_getreg(EECD), 3007 e1000e_getreg(MFUTP23), 3008 e1000e_getreg(RAID), 3009 e1000e_getreg(FCRTV), 3010 e1000e_getreg(TXDCTL1), 3011 e1000e_getreg(RCTL), 3012 e1000e_getreg(TDT), 3013 e1000e_getreg(MDIC), 3014 e1000e_getreg(FCRUC), 3015 e1000e_getreg(VET), 3016 e1000e_getreg(RDBAL0), 3017 e1000e_getreg(TDBAH1), 3018 e1000e_getreg(RDTR), 3019 e1000e_getreg(SCC), 3020 e1000e_getreg(COLC), 3021 e1000e_getreg(CEXTERR), 3022 e1000e_getreg(XOFFRXC), 3023 e1000e_getreg(IPAV), 3024 e1000e_getreg(GOTCL), 3025 e1000e_getreg(MGTPDC), 3026 e1000e_getreg(GCR), 3027 e1000e_getreg(IVAR), 3028 e1000e_getreg(POEMB), 3029 e1000e_getreg(MFVAL), 3030 e1000e_getreg(FUNCTAG), 3031 e1000e_getreg(GSCL_4), 3032 e1000e_getreg(GSCN_3), 3033 e1000e_getreg(MRQC), 3034 e1000e_getreg(RDLEN1), 3035 e1000e_getreg(FCT), 3036 e1000e_getreg(FLA), 3037 e1000e_getreg(FLOL), 3038 e1000e_getreg(RXDCTL), 3039 e1000e_getreg(RXSTMPL), 3040 e1000e_getreg(TIMADJH), 3041 e1000e_getreg(FCRTL), 3042 e1000e_getreg(TDBAH), 3043 e1000e_getreg(TADV), 3044 e1000e_getreg(XONRXC), 3045 e1000e_getreg(TSCTFC), 3046 e1000e_getreg(RFCTL), 3047 e1000e_getreg(GSCN_1), 3048 e1000e_getreg(FCAL), 3049 e1000e_getreg(FLSWCNT), 3050 3051 [TOTH] = e1000e_mac_read_clr8, 3052 [GOTCH] = e1000e_mac_read_clr8, 3053 [PRC64] = e1000e_mac_read_clr4, 3054 [PRC255] = e1000e_mac_read_clr4, 3055 [PRC1023] = e1000e_mac_read_clr4, 3056 [PTC64] = e1000e_mac_read_clr4, 3057 [PTC255] = e1000e_mac_read_clr4, 3058 [PTC1023] = e1000e_mac_read_clr4, 3059 [GPRC] = e1000e_mac_read_clr4, 3060 [TPT] = e1000e_mac_read_clr4, 3061 [RUC] = e1000e_mac_read_clr4, 3062 [BPRC] = e1000e_mac_read_clr4, 3063 [MPTC] = e1000e_mac_read_clr4, 3064 [IAC] = e1000e_mac_read_clr4, 3065 [ICR] = e1000e_mac_icr_read, 3066 [STATUS] = e1000e_get_status, 3067 [TARC0] = e1000e_get_tarc, 3068 [ICS] = e1000e_mac_ics_read, 3069 [TORH] = e1000e_mac_read_clr8, 3070 [GORCH] = e1000e_mac_read_clr8, 3071 [PRC127] = e1000e_mac_read_clr4, 3072 [PRC511] = e1000e_mac_read_clr4, 3073 [PRC1522] = e1000e_mac_read_clr4, 3074 [PTC127] = e1000e_mac_read_clr4, 3075 [PTC511] = e1000e_mac_read_clr4, 3076 [PTC1522] = e1000e_mac_read_clr4, 3077 [GPTC] = e1000e_mac_read_clr4, 3078 [TPR] = e1000e_mac_read_clr4, 3079 [ROC] = e1000e_mac_read_clr4, 3080 [MPRC] = e1000e_mac_read_clr4, 3081 [BPTC] = e1000e_mac_read_clr4, 3082 [TSCTC] = e1000e_mac_read_clr4, 3083 [ITR] = e1000e_mac_itr_read, 3084 [CTRL] = e1000e_get_ctrl, 3085 [TARC1] = e1000e_get_tarc, 3086 [SWSM] = e1000e_mac_swsm_read, 3087 [IMS] = e1000e_mac_ims_read, 3088 [SYSTIML] = e1000e_get_systiml, 3089 [RXSATRH] = e1000e_get_rxsatrh, 3090 [TXSTMPH] = e1000e_get_txstmph, 3091 3092 [CRCERRS ... MPC] = e1000e_mac_readreg, 3093 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3094 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3095 [RA ... RA + 31] = e1000e_mac_readreg, 3096 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3097 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3098 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3099 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3100 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3101 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3102 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3103 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3104 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3105 [RETA ... RETA + 31] = e1000e_mac_readreg, 3106 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3107 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3108 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3109 }; 3110 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3111 3112 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3113 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3114 static const writeops e1000e_macreg_writeops[] = { 3115 e1000e_putreg(PBA), 3116 e1000e_putreg(SWSM), 3117 e1000e_putreg(WUFC), 3118 e1000e_putreg(RDBAH1), 3119 e1000e_putreg(TDBAH), 3120 e1000e_putreg(TXDCTL), 3121 e1000e_putreg(RDBAH0), 3122 e1000e_putreg(LEDCTL), 3123 e1000e_putreg(FCAL), 3124 e1000e_putreg(FCRUC), 3125 e1000e_putreg(WUC), 3126 e1000e_putreg(WUS), 3127 e1000e_putreg(IPAV), 3128 e1000e_putreg(TDBAH1), 3129 e1000e_putreg(IAM), 3130 e1000e_putreg(EIAC), 3131 e1000e_putreg(IVAR), 3132 e1000e_putreg(TARC0), 3133 e1000e_putreg(TARC1), 3134 e1000e_putreg(FLSWDATA), 3135 e1000e_putreg(POEMB), 3136 e1000e_putreg(MFUTP01), 3137 e1000e_putreg(MFUTP23), 3138 e1000e_putreg(MANC), 3139 e1000e_putreg(MANC2H), 3140 e1000e_putreg(MFVAL), 3141 e1000e_putreg(EXTCNF_CTRL), 3142 e1000e_putreg(FACTPS), 3143 e1000e_putreg(FUNCTAG), 3144 e1000e_putreg(GSCL_1), 3145 e1000e_putreg(GSCL_2), 3146 e1000e_putreg(GSCL_3), 3147 e1000e_putreg(GSCL_4), 3148 e1000e_putreg(GSCN_0), 3149 e1000e_putreg(GSCN_1), 3150 e1000e_putreg(GSCN_2), 3151 e1000e_putreg(GSCN_3), 3152 e1000e_putreg(GCR2), 3153 e1000e_putreg(MRQC), 3154 e1000e_putreg(FLOP), 3155 e1000e_putreg(FLOL), 3156 e1000e_putreg(FLSWCTL), 3157 e1000e_putreg(FLSWCNT), 3158 e1000e_putreg(FLA), 3159 e1000e_putreg(RXDCTL1), 3160 e1000e_putreg(TXDCTL1), 3161 e1000e_putreg(TIPG), 3162 e1000e_putreg(RXSTMPH), 3163 e1000e_putreg(RXSTMPL), 3164 e1000e_putreg(RXSATRL), 3165 e1000e_putreg(RXSATRH), 3166 e1000e_putreg(TXSTMPL), 3167 e1000e_putreg(TXSTMPH), 3168 e1000e_putreg(SYSTIML), 3169 e1000e_putreg(SYSTIMH), 3170 e1000e_putreg(TIMADJL), 3171 e1000e_putreg(RXUDP), 3172 e1000e_putreg(RXCFGL), 3173 e1000e_putreg(TSYNCRXCTL), 3174 e1000e_putreg(TSYNCTXCTL), 3175 e1000e_putreg(EXTCNF_SIZE), 3176 e1000e_putreg(EEMNGCTL), 3177 e1000e_putreg(RA), 3178 3179 [TDH1] = e1000e_set_16bit, 3180 [TDT1] = e1000e_set_tdt, 3181 [TCTL] = e1000e_set_tctl, 3182 [TDT] = e1000e_set_tdt, 3183 [MDIC] = e1000e_set_mdic, 3184 [ICS] = e1000e_set_ics, 3185 [TDH] = e1000e_set_16bit, 3186 [RDH0] = e1000e_set_16bit, 3187 [RDT0] = e1000e_set_rdt, 3188 [IMC] = e1000e_set_imc, 3189 [IMS] = e1000e_set_ims, 3190 [ICR] = e1000e_set_icr, 3191 [EECD] = e1000e_set_eecd, 3192 [RCTL] = e1000e_set_rx_control, 3193 [CTRL] = e1000e_set_ctrl, 3194 [RDTR] = e1000e_set_rdtr, 3195 [RADV] = e1000e_set_16bit, 3196 [TADV] = e1000e_set_16bit, 3197 [ITR] = e1000e_set_itr, 3198 [EERD] = e1000e_set_eerd, 3199 [AIT] = e1000e_set_16bit, 3200 [TDFH] = e1000e_set_13bit, 3201 [TDFT] = e1000e_set_13bit, 3202 [TDFHS] = e1000e_set_13bit, 3203 [TDFTS] = e1000e_set_13bit, 3204 [TDFPC] = e1000e_set_13bit, 3205 [RDFH] = e1000e_set_13bit, 3206 [RDFHS] = e1000e_set_13bit, 3207 [RDFT] = e1000e_set_13bit, 3208 [RDFTS] = e1000e_set_13bit, 3209 [RDFPC] = e1000e_set_13bit, 3210 [PBS] = e1000e_set_6bit, 3211 [GCR] = e1000e_set_gcr, 3212 [PSRCTL] = e1000e_set_psrctl, 3213 [RXCSUM] = e1000e_set_rxcsum, 3214 [RAID] = e1000e_set_16bit, 3215 [RSRPD] = e1000e_set_12bit, 3216 [TIDV] = e1000e_set_tidv, 3217 [TDLEN1] = e1000e_set_dlen, 3218 [TDLEN] = e1000e_set_dlen, 3219 [RDLEN0] = e1000e_set_dlen, 3220 [RDLEN1] = e1000e_set_dlen, 3221 [TDBAL] = e1000e_set_dbal, 3222 [TDBAL1] = e1000e_set_dbal, 3223 [RDBAL0] = e1000e_set_dbal, 3224 [RDBAL1] = e1000e_set_dbal, 3225 [RDH1] = e1000e_set_16bit, 3226 [RDT1] = e1000e_set_rdt, 3227 [STATUS] = e1000e_set_status, 3228 [PBACLR] = e1000e_set_pbaclr, 3229 [CTRL_EXT] = e1000e_set_ctrlext, 3230 [FCAH] = e1000e_set_16bit, 3231 [FCT] = e1000e_set_16bit, 3232 [FCTTV] = e1000e_set_16bit, 3233 [FCRTV] = e1000e_set_16bit, 3234 [FCRTH] = e1000e_set_fcrth, 3235 [FCRTL] = e1000e_set_fcrtl, 3236 [VET] = e1000e_set_vet, 3237 [RXDCTL] = e1000e_set_rxdctl, 3238 [FLASHT] = e1000e_set_16bit, 3239 [EEWR] = e1000e_set_eewr, 3240 [CTRL_DUP] = e1000e_set_ctrl, 3241 [RFCTL] = e1000e_set_rfctl, 3242 [RA + 1] = e1000e_mac_setmacaddr, 3243 [TIMINCA] = e1000e_set_timinca, 3244 [TIMADJH] = e1000e_set_timadjh, 3245 3246 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3247 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3248 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3249 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3250 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3251 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3252 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3253 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3254 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3255 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3256 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3257 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3258 [RETA ... RETA + 31] = e1000e_mac_writereg, 3259 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3260 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3261 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3262 }; 3263 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3264 3265 enum { MAC_ACCESS_PARTIAL = 1 }; 3266 3267 /* 3268 * The array below combines alias offsets of the index values for the 3269 * MAC registers that have aliases, with the indication of not fully 3270 * implemented registers (lowest bit). This combination is possible 3271 * because all of the offsets are even. 3272 */ 3273 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3274 /* Alias index offsets */ 3275 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3276 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3277 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3278 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3279 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3280 [RA_A ... RA_A + 31] = 0x14f0, 3281 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3282 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3283 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3284 /* Access options */ 3285 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3286 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3287 [RDFPC] = MAC_ACCESS_PARTIAL, 3288 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3289 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3290 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3291 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3292 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3293 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3294 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3295 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3296 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3297 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3298 }; 3299 3300 void 3301 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3302 { 3303 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3304 3305 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3306 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3307 trace_e1000e_wrn_regs_write_trivial(index << 2); 3308 } 3309 trace_e1000e_core_write(index << 2, size, val); 3310 e1000e_macreg_writeops[index](core, index, val); 3311 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3312 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3313 } else { 3314 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3315 } 3316 } 3317 3318 uint64_t 3319 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3320 { 3321 uint64_t val; 3322 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3323 3324 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3325 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3326 trace_e1000e_wrn_regs_read_trivial(index << 2); 3327 } 3328 val = e1000e_macreg_readops[index](core, index); 3329 trace_e1000e_core_read(index << 2, size, val); 3330 return val; 3331 } else { 3332 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3333 } 3334 return 0; 3335 } 3336 3337 static inline void 3338 e1000e_autoneg_pause(E1000ECore *core) 3339 { 3340 timer_del(core->autoneg_timer); 3341 } 3342 3343 static void 3344 e1000e_autoneg_resume(E1000ECore *core) 3345 { 3346 if (e1000e_have_autoneg(core) && 3347 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3348 qemu_get_queue(core->owner_nic)->link_down = false; 3349 timer_mod(core->autoneg_timer, 3350 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3351 } 3352 } 3353 3354 static void 3355 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3356 { 3357 E1000ECore *core = opaque; 3358 3359 if (running) { 3360 trace_e1000e_vm_state_running(); 3361 e1000e_intrmgr_resume(core); 3362 e1000e_autoneg_resume(core); 3363 } else { 3364 trace_e1000e_vm_state_stopped(); 3365 e1000e_autoneg_pause(core); 3366 e1000e_intrmgr_pause(core); 3367 } 3368 } 3369 3370 void 3371 e1000e_core_pci_realize(E1000ECore *core, 3372 const uint16_t *eeprom_templ, 3373 uint32_t eeprom_size, 3374 const uint8_t *macaddr) 3375 { 3376 int i; 3377 3378 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3379 e1000e_autoneg_timer, core); 3380 e1000e_intrmgr_pci_realize(core); 3381 3382 core->vmstate = 3383 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3384 3385 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3386 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3387 } 3388 3389 net_rx_pkt_init(&core->rx_pkt); 3390 3391 e1000x_core_prepare_eeprom(core->eeprom, 3392 eeprom_templ, 3393 eeprom_size, 3394 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3395 macaddr); 3396 e1000e_update_rx_offloads(core); 3397 } 3398 3399 void 3400 e1000e_core_pci_uninit(E1000ECore *core) 3401 { 3402 int i; 3403 3404 timer_free(core->autoneg_timer); 3405 3406 e1000e_intrmgr_pci_unint(core); 3407 3408 qemu_del_vm_change_state_handler(core->vmstate); 3409 3410 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3411 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3412 } 3413 3414 net_rx_pkt_uninit(core->rx_pkt); 3415 } 3416 3417 static const uint16_t 3418 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3419 [0] = { 3420 [MII_BMCR] = MII_BMCR_SPEED1000 | 3421 MII_BMCR_FD | 3422 MII_BMCR_AUTOEN, 3423 3424 [MII_BMSR] = MII_BMSR_EXTCAP | 3425 MII_BMSR_LINK_ST | 3426 MII_BMSR_AUTONEG | 3427 MII_BMSR_MFPS | 3428 MII_BMSR_EXTSTAT | 3429 MII_BMSR_10T_HD | 3430 MII_BMSR_10T_FD | 3431 MII_BMSR_100TX_HD | 3432 MII_BMSR_100TX_FD, 3433 3434 [MII_PHYID1] = 0x141, 3435 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3436 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3437 MII_ANAR_10FD | MII_ANAR_TX | 3438 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3439 MII_ANAR_PAUSE_ASYM, 3440 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3441 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3442 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3443 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3444 [MII_ANNP] = 1 | MII_ANNP_MP, 3445 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3446 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3447 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3448 MII_STAT1000_ROK | MII_STAT1000_LOK, 3449 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3450 3451 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3452 BIT(12) | BIT(13), 3453 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3454 }, 3455 [2] = { 3456 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3457 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3458 }, 3459 [3] = { 3460 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3461 } 3462 }; 3463 3464 static const uint32_t e1000e_mac_reg_init[] = { 3465 [PBA] = 0x00140014, 3466 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3467 [EXTCNF_CTRL] = BIT(3), 3468 [EEMNGCTL] = BIT(31), 3469 [FLASHT] = 0x2, 3470 [FLSWCTL] = BIT(30) | BIT(31), 3471 [FLOL] = BIT(0), 3472 [RXDCTL] = BIT(16), 3473 [RXDCTL1] = BIT(16), 3474 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3475 [RXCFGL] = 0x88F7, 3476 [RXUDP] = 0x319, 3477 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3478 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3479 E1000_CTRL_ADVD3WUC, 3480 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3481 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3482 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3483 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3484 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3485 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3486 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3487 [EERD] = E1000_EERW_DONE, 3488 [EEWR] = E1000_EERW_DONE, 3489 [GCR] = E1000_L0S_ADJUST | 3490 E1000_L1_ENTRY_LATENCY_MSB | 3491 E1000_L1_ENTRY_LATENCY_LSB, 3492 [TDFH] = 0x600, 3493 [TDFT] = 0x600, 3494 [TDFHS] = 0x600, 3495 [TDFTS] = 0x600, 3496 [POEMB] = 0x30D, 3497 [PBS] = 0x028, 3498 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3499 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3500 [SWSM] = 1, 3501 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3502 [ITR] = E1000E_MIN_XITR, 3503 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3504 }; 3505 3506 static void e1000e_reset(E1000ECore *core, bool sw) 3507 { 3508 int i; 3509 3510 timer_del(core->autoneg_timer); 3511 3512 e1000e_intrmgr_reset(core); 3513 3514 memset(core->phy, 0, sizeof core->phy); 3515 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3516 3517 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3518 if (sw && (i == PBA || i == PBS || i == FLA)) { 3519 continue; 3520 } 3521 3522 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3523 e1000e_mac_reg_init[i] : 0; 3524 } 3525 3526 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3527 3528 if (qemu_get_queue(core->owner_nic)->link_down) { 3529 e1000e_link_down(core); 3530 } 3531 3532 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3533 3534 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3535 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3536 core->tx[i].skip_cp = false; 3537 } 3538 } 3539 3540 void 3541 e1000e_core_reset(E1000ECore *core) 3542 { 3543 e1000e_reset(core, false); 3544 } 3545 3546 void e1000e_core_pre_save(E1000ECore *core) 3547 { 3548 int i; 3549 NetClientState *nc = qemu_get_queue(core->owner_nic); 3550 3551 /* 3552 * If link is down and auto-negotiation is supported and ongoing, 3553 * complete auto-negotiation immediately. This allows us to look 3554 * at MII_BMSR_AN_COMP to infer link status on load. 3555 */ 3556 if (nc->link_down && e1000e_have_autoneg(core)) { 3557 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3558 e1000e_update_flowctl_status(core); 3559 } 3560 3561 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3562 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3563 core->tx[i].skip_cp = true; 3564 } 3565 } 3566 } 3567 3568 int 3569 e1000e_core_post_load(E1000ECore *core) 3570 { 3571 NetClientState *nc = qemu_get_queue(core->owner_nic); 3572 3573 /* 3574 * nc.link_down can't be migrated, so infer link_down according 3575 * to link status bit in core.mac[STATUS]. 3576 */ 3577 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3578 3579 return 0; 3580 } 3581