1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000_common.h" 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 55 #define E1000E_MIN_XITR (500) 56 57 #define E1000E_MAX_TX_FRAGS (64) 58 59 union e1000_rx_desc_union { 60 struct e1000_rx_desc legacy; 61 union e1000_rx_desc_extended extended; 62 union e1000_rx_desc_packet_split packet_split; 63 }; 64 65 static ssize_t 66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 67 bool has_vnet); 68 69 static inline void 70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 71 72 static void e1000e_reset(E1000ECore *core, bool sw); 73 74 static inline void 75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 76 { 77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 78 trace_e1000e_wrn_no_ts_support(); 79 } 80 } 81 82 static inline void 83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 84 { 85 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 86 trace_e1000e_wrn_no_snap_support(); 87 } 88 } 89 90 static inline void 91 e1000e_raise_legacy_irq(E1000ECore *core) 92 { 93 trace_e1000e_irq_legacy_notify(true); 94 e1000x_inc_reg_if_not_full(core->mac, IAC); 95 pci_set_irq(core->owner, 1); 96 } 97 98 static inline void 99 e1000e_lower_legacy_irq(E1000ECore *core) 100 { 101 trace_e1000e_irq_legacy_notify(false); 102 pci_set_irq(core->owner, 0); 103 } 104 105 static inline void 106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 107 { 108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 109 timer->delay_resolution_ns; 110 111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 112 113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 114 115 timer->running = true; 116 } 117 118 static void 119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 e1000e_intrmgr_rearm_timer(timer); 123 } 124 } 125 126 static void 127 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 128 { 129 if (timer->running) { 130 timer_del(timer->timer); 131 } 132 } 133 134 static inline void 135 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 136 { 137 if (timer->running) { 138 timer_del(timer->timer); 139 timer->running = false; 140 } 141 } 142 143 static inline void 144 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 145 { 146 trace_e1000e_irq_fire_delayed_interrupts(); 147 e1000e_set_interrupt_cause(core, 0); 148 } 149 150 static void 151 e1000e_intrmgr_on_timer(void *opaque) 152 { 153 E1000IntrDelayTimer *timer = opaque; 154 155 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 156 157 timer->running = false; 158 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 159 } 160 161 static void 162 e1000e_intrmgr_on_throttling_timer(void *opaque) 163 { 164 E1000IntrDelayTimer *timer = opaque; 165 166 timer->running = false; 167 168 if (msi_enabled(timer->core->owner)) { 169 trace_e1000e_irq_msi_notify_postponed(); 170 /* Clear msi_causes_pending to fire MSI eventually */ 171 timer->core->msi_causes_pending = 0; 172 e1000e_set_interrupt_cause(timer->core, 0); 173 } else { 174 trace_e1000e_irq_legacy_notify_postponed(); 175 e1000e_set_interrupt_cause(timer->core, 0); 176 } 177 } 178 179 static void 180 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 181 { 182 E1000IntrDelayTimer *timer = opaque; 183 int idx = timer - &timer->core->eitr[0]; 184 185 timer->running = false; 186 187 trace_e1000e_irq_msix_notify_postponed_vec(idx); 188 msix_notify(timer->core->owner, idx); 189 } 190 191 static void 192 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 193 { 194 int i; 195 196 core->radv.delay_reg = RADV; 197 core->rdtr.delay_reg = RDTR; 198 core->raid.delay_reg = RAID; 199 core->tadv.delay_reg = TADV; 200 core->tidv.delay_reg = TIDV; 201 202 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 207 208 core->radv.core = core; 209 core->rdtr.core = core; 210 core->raid.core = core; 211 core->tadv.core = core; 212 core->tidv.core = core; 213 214 core->itr.core = core; 215 core->itr.delay_reg = ITR; 216 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 217 218 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 219 core->eitr[i].core = core; 220 core->eitr[i].delay_reg = EITR + i; 221 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 222 } 223 224 if (!create) { 225 return; 226 } 227 228 core->radv.timer = 229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 230 core->rdtr.timer = 231 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 232 core->raid.timer = 233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 234 235 core->tadv.timer = 236 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 237 core->tidv.timer = 238 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 239 240 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 241 e1000e_intrmgr_on_throttling_timer, 242 &core->itr); 243 244 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 245 core->eitr[i].timer = 246 timer_new_ns(QEMU_CLOCK_VIRTUAL, 247 e1000e_intrmgr_on_msix_throttling_timer, 248 &core->eitr[i]); 249 } 250 } 251 252 static inline void 253 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 254 { 255 e1000e_intrmgr_stop_timer(&core->radv); 256 e1000e_intrmgr_stop_timer(&core->rdtr); 257 e1000e_intrmgr_stop_timer(&core->raid); 258 e1000e_intrmgr_stop_timer(&core->tidv); 259 e1000e_intrmgr_stop_timer(&core->tadv); 260 } 261 262 static bool 263 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 264 { 265 uint32_t delayable_causes; 266 uint32_t rdtr = core->mac[RDTR]; 267 uint32_t radv = core->mac[RADV]; 268 uint32_t raid = core->mac[RAID]; 269 270 if (msix_enabled(core->owner)) { 271 return false; 272 } 273 274 delayable_causes = E1000_ICR_RXQ0 | 275 E1000_ICR_RXQ1 | 276 E1000_ICR_RXT0; 277 278 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 279 delayable_causes |= E1000_ICR_ACK; 280 } 281 282 /* Clean up all causes that may be delayed */ 283 core->delayed_causes |= *causes & delayable_causes; 284 *causes &= ~delayable_causes; 285 286 /* 287 * Check if delayed RX interrupts disabled by client 288 * or if there are causes that cannot be delayed 289 */ 290 if ((rdtr == 0) || (*causes != 0)) { 291 return false; 292 } 293 294 /* 295 * Check if delayed RX ACK interrupts disabled by client 296 * and there is an ACK packet received 297 */ 298 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 299 return false; 300 } 301 302 /* All causes delayed */ 303 e1000e_intrmgr_rearm_timer(&core->rdtr); 304 305 if (!core->radv.running && (radv != 0)) { 306 e1000e_intrmgr_rearm_timer(&core->radv); 307 } 308 309 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 310 e1000e_intrmgr_rearm_timer(&core->raid); 311 } 312 313 return true; 314 } 315 316 static bool 317 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 318 { 319 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 320 E1000_ICR_TXQ1 | 321 E1000_ICR_TXQE | 322 E1000_ICR_TXDW; 323 324 if (msix_enabled(core->owner)) { 325 return false; 326 } 327 328 /* Clean up all causes that may be delayed */ 329 core->delayed_causes |= *causes & delayable_causes; 330 *causes &= ~delayable_causes; 331 332 /* If there are causes that cannot be delayed */ 333 if (*causes != 0) { 334 return false; 335 } 336 337 /* All causes delayed */ 338 e1000e_intrmgr_rearm_timer(&core->tidv); 339 340 if (!core->tadv.running && (core->mac[TADV] != 0)) { 341 e1000e_intrmgr_rearm_timer(&core->tadv); 342 } 343 344 return true; 345 } 346 347 static uint32_t 348 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 349 { 350 uint32_t res; 351 352 if (msix_enabled(core->owner)) { 353 assert(core->delayed_causes == 0); 354 return 0; 355 } 356 357 res = core->delayed_causes; 358 core->delayed_causes = 0; 359 360 e1000e_intrmgr_stop_delay_timers(core); 361 362 return res; 363 } 364 365 static void 366 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 367 { 368 int i; 369 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 370 371 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 372 core->mac[ICR] |= val; 373 374 if (core->itr.running) { 375 timer_del(core->itr.timer); 376 e1000e_intrmgr_on_throttling_timer(&core->itr); 377 } 378 379 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 380 if (core->eitr[i].running) { 381 timer_del(core->eitr[i].timer); 382 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 383 } 384 } 385 } 386 387 static void 388 e1000e_intrmgr_resume(E1000ECore *core) 389 { 390 int i; 391 392 e1000e_intmgr_timer_resume(&core->radv); 393 e1000e_intmgr_timer_resume(&core->rdtr); 394 e1000e_intmgr_timer_resume(&core->raid); 395 e1000e_intmgr_timer_resume(&core->tidv); 396 e1000e_intmgr_timer_resume(&core->tadv); 397 398 e1000e_intmgr_timer_resume(&core->itr); 399 400 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 401 e1000e_intmgr_timer_resume(&core->eitr[i]); 402 } 403 } 404 405 static void 406 e1000e_intrmgr_pause(E1000ECore *core) 407 { 408 int i; 409 410 e1000e_intmgr_timer_pause(&core->radv); 411 e1000e_intmgr_timer_pause(&core->rdtr); 412 e1000e_intmgr_timer_pause(&core->raid); 413 e1000e_intmgr_timer_pause(&core->tidv); 414 e1000e_intmgr_timer_pause(&core->tadv); 415 416 e1000e_intmgr_timer_pause(&core->itr); 417 418 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 419 e1000e_intmgr_timer_pause(&core->eitr[i]); 420 } 421 } 422 423 static void 424 e1000e_intrmgr_reset(E1000ECore *core) 425 { 426 int i; 427 428 core->delayed_causes = 0; 429 430 e1000e_intrmgr_stop_delay_timers(core); 431 432 e1000e_intrmgr_stop_timer(&core->itr); 433 434 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 435 e1000e_intrmgr_stop_timer(&core->eitr[i]); 436 } 437 } 438 439 static void 440 e1000e_intrmgr_pci_unint(E1000ECore *core) 441 { 442 int i; 443 444 timer_free(core->radv.timer); 445 timer_free(core->rdtr.timer); 446 timer_free(core->raid.timer); 447 448 timer_free(core->tadv.timer); 449 timer_free(core->tidv.timer); 450 451 timer_free(core->itr.timer); 452 453 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 454 timer_free(core->eitr[i].timer); 455 } 456 } 457 458 static void 459 e1000e_intrmgr_pci_realize(E1000ECore *core) 460 { 461 e1000e_intrmgr_initialize_all_timers(core, true); 462 } 463 464 static inline bool 465 e1000e_rx_csum_enabled(E1000ECore *core) 466 { 467 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 468 } 469 470 static inline bool 471 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 472 { 473 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 474 } 475 476 static inline bool 477 e1000e_rx_use_ps_descriptor(E1000ECore *core) 478 { 479 return !e1000e_rx_use_legacy_descriptor(core) && 480 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 481 } 482 483 static inline bool 484 e1000e_rss_enabled(E1000ECore *core) 485 { 486 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 487 !e1000e_rx_csum_enabled(core) && 488 !e1000e_rx_use_legacy_descriptor(core); 489 } 490 491 typedef struct E1000E_RSSInfo_st { 492 bool enabled; 493 uint32_t hash; 494 uint32_t queue; 495 uint32_t type; 496 } E1000E_RSSInfo; 497 498 static uint32_t 499 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 500 { 501 bool hasip4, hasip6; 502 EthL4HdrProto l4hdr_proto; 503 504 assert(e1000e_rss_enabled(core)); 505 506 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 507 508 if (hasip4) { 509 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 511 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 512 513 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 514 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 515 return E1000_MRQ_RSS_TYPE_IPV4TCP; 516 } 517 518 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 519 return E1000_MRQ_RSS_TYPE_IPV4; 520 } 521 } else if (hasip6) { 522 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 523 524 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 525 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 526 527 /* 528 * Following two traces must not be combined because resulting 529 * event will have 11 arguments totally and some trace backends 530 * (at least "ust") have limitation of maximum 10 arguments per 531 * event. Events with more arguments fail to compile for 532 * backends like these. 533 */ 534 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 535 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 536 ip6info->has_ext_hdrs, 537 ip6info->rss_ex_dst_valid, 538 ip6info->rss_ex_src_valid, 539 core->mac[MRQC], 540 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), 541 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 542 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 543 544 if ((!ex_dis || !ip6info->has_ext_hdrs) && 545 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 546 ip6info->rss_ex_src_valid))) { 547 548 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 549 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { 550 return E1000_MRQ_RSS_TYPE_IPV6TCPEX; 551 } 552 553 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 554 return E1000_MRQ_RSS_TYPE_IPV6EX; 555 } 556 557 } 558 559 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 560 return E1000_MRQ_RSS_TYPE_IPV6; 561 } 562 563 } 564 565 return E1000_MRQ_RSS_TYPE_NONE; 566 } 567 568 static uint32_t 569 e1000e_rss_calc_hash(E1000ECore *core, 570 struct NetRxPkt *pkt, 571 E1000E_RSSInfo *info) 572 { 573 NetRxPktRssType type; 574 575 assert(e1000e_rss_enabled(core)); 576 577 switch (info->type) { 578 case E1000_MRQ_RSS_TYPE_IPV4: 579 type = NetPktRssIpV4; 580 break; 581 case E1000_MRQ_RSS_TYPE_IPV4TCP: 582 type = NetPktRssIpV4Tcp; 583 break; 584 case E1000_MRQ_RSS_TYPE_IPV6TCPEX: 585 type = NetPktRssIpV6TcpEx; 586 break; 587 case E1000_MRQ_RSS_TYPE_IPV6: 588 type = NetPktRssIpV6; 589 break; 590 case E1000_MRQ_RSS_TYPE_IPV6EX: 591 type = NetPktRssIpV6Ex; 592 break; 593 default: 594 assert(false); 595 return 0; 596 } 597 598 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 599 } 600 601 static void 602 e1000e_rss_parse_packet(E1000ECore *core, 603 struct NetRxPkt *pkt, 604 E1000E_RSSInfo *info) 605 { 606 trace_e1000e_rx_rss_started(); 607 608 if (!e1000e_rss_enabled(core)) { 609 info->enabled = false; 610 info->hash = 0; 611 info->queue = 0; 612 info->type = 0; 613 trace_e1000e_rx_rss_disabled(); 614 return; 615 } 616 617 info->enabled = true; 618 619 info->type = e1000e_rss_get_hash_type(core, pkt); 620 621 trace_e1000e_rx_rss_type(info->type); 622 623 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 624 info->hash = 0; 625 info->queue = 0; 626 return; 627 } 628 629 info->hash = e1000e_rss_calc_hash(core, pkt, info); 630 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 631 } 632 633 static bool 634 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 635 { 636 if (tx->props.tse && tx->cptse) { 637 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 638 return false; 639 } 640 641 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 642 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 643 return true; 644 } 645 646 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 647 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 648 return false; 649 } 650 } 651 652 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 653 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 654 } 655 656 return true; 657 } 658 659 static void e1000e_tx_pkt_callback(void *core, 660 const struct iovec *iov, 661 int iovcnt, 662 const struct iovec *virt_iov, 663 int virt_iovcnt) 664 { 665 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 666 } 667 668 static bool 669 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 670 { 671 int target_queue = MIN(core->max_queue_num, queue_index); 672 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 673 674 if (!e1000e_setup_tx_offloads(core, tx)) { 675 return false; 676 } 677 678 net_tx_pkt_dump(tx->tx_pkt); 679 680 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 681 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 682 return net_tx_pkt_send_custom(tx->tx_pkt, false, 683 e1000e_tx_pkt_callback, core); 684 } else { 685 return net_tx_pkt_send(tx->tx_pkt, queue); 686 } 687 } 688 689 static void 690 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 691 { 692 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 693 PTC1023, PTC1522 }; 694 695 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 696 697 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 698 e1000x_inc_reg_if_not_full(core->mac, TPT); 699 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 700 701 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 702 case ETH_PKT_BCAST: 703 e1000x_inc_reg_if_not_full(core->mac, BPTC); 704 break; 705 case ETH_PKT_MCAST: 706 e1000x_inc_reg_if_not_full(core->mac, MPTC); 707 break; 708 case ETH_PKT_UCAST: 709 break; 710 default: 711 g_assert_not_reached(); 712 } 713 714 e1000x_inc_reg_if_not_full(core->mac, GPTC); 715 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 716 } 717 718 static void 719 e1000e_process_tx_desc(E1000ECore *core, 720 struct e1000e_tx *tx, 721 struct e1000_tx_desc *dp, 722 int queue_index) 723 { 724 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 725 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 726 unsigned int split_size = txd_lower & 0xffff; 727 uint64_t addr; 728 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 729 bool eop = txd_lower & E1000_TXD_CMD_EOP; 730 731 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 732 e1000x_read_tx_ctx_descr(xp, &tx->props); 733 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 734 return; 735 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 736 /* data descriptor */ 737 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 738 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 739 e1000e_process_ts_option(core, dp); 740 } else { 741 /* legacy descriptor */ 742 e1000e_process_ts_option(core, dp); 743 tx->cptse = 0; 744 } 745 746 addr = le64_to_cpu(dp->buffer_addr); 747 748 if (!tx->skip_cp) { 749 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, 750 addr, split_size)) { 751 tx->skip_cp = true; 752 } 753 } 754 755 if (eop) { 756 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 757 if (e1000x_vlan_enabled(core->mac) && 758 e1000x_is_vlan_txd(txd_lower)) { 759 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 760 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 761 } 762 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 763 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 764 } 765 } 766 767 tx->skip_cp = false; 768 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 769 770 tx->sum_needed = 0; 771 tx->cptse = 0; 772 } 773 } 774 775 static inline uint32_t 776 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 777 { 778 if (!msix_enabled(core->owner)) { 779 return E1000_ICR_TXDW; 780 } 781 782 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 783 } 784 785 static inline uint32_t 786 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 787 bool min_threshold_hit) 788 { 789 if (!msix_enabled(core->owner)) { 790 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 791 } 792 793 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 794 } 795 796 static uint32_t 797 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 798 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 799 { 800 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 801 802 if (!(txd_lower & E1000_TXD_CMD_RS) && 803 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 804 return 0; 805 } 806 807 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 808 809 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 810 811 dp->upper.data = cpu_to_le32(txd_upper); 812 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 813 &dp->upper, sizeof(dp->upper)); 814 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 815 } 816 817 typedef struct E1000E_RingInfo_st { 818 int dbah; 819 int dbal; 820 int dlen; 821 int dh; 822 int dt; 823 int idx; 824 } E1000E_RingInfo; 825 826 static inline bool 827 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 828 { 829 return core->mac[r->dh] == core->mac[r->dt] || 830 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 831 } 832 833 static inline uint64_t 834 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 835 { 836 uint64_t bah = core->mac[r->dbah]; 837 uint64_t bal = core->mac[r->dbal]; 838 839 return (bah << 32) + bal; 840 } 841 842 static inline uint64_t 843 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 844 { 845 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 846 } 847 848 static inline void 849 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 850 { 851 core->mac[r->dh] += count; 852 853 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 854 core->mac[r->dh] = 0; 855 } 856 } 857 858 static inline uint32_t 859 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 860 { 861 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 862 core->mac[r->dh], core->mac[r->dt]); 863 864 if (core->mac[r->dh] <= core->mac[r->dt]) { 865 return core->mac[r->dt] - core->mac[r->dh]; 866 } 867 868 if (core->mac[r->dh] > core->mac[r->dt]) { 869 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 870 core->mac[r->dt] - core->mac[r->dh]; 871 } 872 873 g_assert_not_reached(); 874 return 0; 875 } 876 877 static inline bool 878 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 879 { 880 return core->mac[r->dlen] > 0; 881 } 882 883 static inline uint32_t 884 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 885 { 886 return core->mac[r->dlen]; 887 } 888 889 typedef struct E1000E_TxRing_st { 890 const E1000E_RingInfo *i; 891 struct e1000e_tx *tx; 892 } E1000E_TxRing; 893 894 static inline int 895 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 896 { 897 return (reg_idx - base_reg_idx) / (0x100 >> 2); 898 } 899 900 static inline void 901 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 902 { 903 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 904 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 905 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 906 }; 907 908 assert(idx < ARRAY_SIZE(i)); 909 910 txr->i = &i[idx]; 911 txr->tx = &core->tx[idx]; 912 } 913 914 typedef struct E1000E_RxRing_st { 915 const E1000E_RingInfo *i; 916 } E1000E_RxRing; 917 918 static inline void 919 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 920 { 921 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 922 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 923 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 924 }; 925 926 assert(idx < ARRAY_SIZE(i)); 927 928 rxr->i = &i[idx]; 929 } 930 931 static void 932 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 933 { 934 dma_addr_t base; 935 struct e1000_tx_desc desc; 936 bool ide = false; 937 const E1000E_RingInfo *txi = txr->i; 938 uint32_t cause = E1000_ICS_TXQE; 939 940 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 941 trace_e1000e_tx_disabled(); 942 return; 943 } 944 945 while (!e1000e_ring_empty(core, txi)) { 946 base = e1000e_ring_head_descr(core, txi); 947 948 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 949 950 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 951 desc.lower.data, desc.upper.data); 952 953 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 954 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 955 956 e1000e_ring_advance(core, txi, 1); 957 } 958 959 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 960 e1000e_set_interrupt_cause(core, cause); 961 } 962 } 963 964 static bool 965 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 966 size_t total_size) 967 { 968 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 969 970 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 971 core->rx_desc_buf_size); 972 973 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 974 core->rx_desc_buf_size; 975 } 976 977 void 978 e1000e_start_recv(E1000ECore *core) 979 { 980 int i; 981 982 trace_e1000e_rx_start_recv(); 983 984 for (i = 0; i <= core->max_queue_num; i++) { 985 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 986 } 987 } 988 989 bool 990 e1000e_can_receive(E1000ECore *core) 991 { 992 int i; 993 994 if (!e1000x_rx_ready(core->owner, core->mac)) { 995 return false; 996 } 997 998 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 999 E1000E_RxRing rxr; 1000 1001 e1000e_rx_ring_init(core, &rxr, i); 1002 if (e1000e_ring_enabled(core, rxr.i) && 1003 e1000e_has_rxbufs(core, rxr.i, 1)) { 1004 trace_e1000e_rx_can_recv(); 1005 return true; 1006 } 1007 } 1008 1009 trace_e1000e_rx_can_recv_rings_full(); 1010 return false; 1011 } 1012 1013 ssize_t 1014 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 1015 { 1016 const struct iovec iov = { 1017 .iov_base = (uint8_t *)buf, 1018 .iov_len = size 1019 }; 1020 1021 return e1000e_receive_iov(core, &iov, 1); 1022 } 1023 1024 static inline bool 1025 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1026 { 1027 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1028 } 1029 1030 static inline bool 1031 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1032 { 1033 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1034 } 1035 1036 static bool 1037 e1000e_receive_filter(E1000ECore *core, const void *buf) 1038 { 1039 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || 1040 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && 1041 e1000x_rx_group_filter(core->mac, buf); 1042 } 1043 1044 static inline void 1045 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1046 hwaddr *buff_addr) 1047 { 1048 *buff_addr = le64_to_cpu(desc->buffer_addr); 1049 } 1050 1051 static inline void 1052 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1053 hwaddr *buff_addr) 1054 { 1055 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1056 } 1057 1058 static inline void 1059 e1000e_read_ps_rx_descr(E1000ECore *core, 1060 union e1000_rx_desc_packet_split *desc, 1061 hwaddr buff_addr[MAX_PS_BUFFERS]) 1062 { 1063 int i; 1064 1065 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1066 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1067 } 1068 1069 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1070 buff_addr[2], buff_addr[3]); 1071 } 1072 1073 static inline void 1074 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1075 hwaddr buff_addr[MAX_PS_BUFFERS]) 1076 { 1077 if (e1000e_rx_use_legacy_descriptor(core)) { 1078 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1079 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1080 } else { 1081 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1082 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1083 } else { 1084 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1085 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1086 } 1087 } 1088 } 1089 1090 static void 1091 e1000e_verify_csum_in_sw(E1000ECore *core, 1092 struct NetRxPkt *pkt, 1093 uint32_t *status_flags, 1094 EthL4HdrProto l4hdr_proto) 1095 { 1096 bool csum_valid; 1097 uint32_t csum_error; 1098 1099 if (e1000e_rx_l3_cso_enabled(core)) { 1100 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1101 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1102 } else { 1103 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1104 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1105 } 1106 } else { 1107 trace_e1000e_rx_metadata_l3_cso_disabled(); 1108 } 1109 1110 if (!e1000e_rx_l4_cso_enabled(core)) { 1111 trace_e1000e_rx_metadata_l4_cso_disabled(); 1112 return; 1113 } 1114 1115 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1116 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1117 return; 1118 } 1119 1120 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1121 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1122 1123 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1124 *status_flags |= E1000_RXD_STAT_UDPCS; 1125 } 1126 } 1127 1128 static inline bool 1129 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1130 { 1131 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1132 return false; 1133 } 1134 1135 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1136 return !net_rx_pkt_has_tcp_data(rx_pkt); 1137 } 1138 1139 return true; 1140 } 1141 1142 static void 1143 e1000e_build_rx_metadata(E1000ECore *core, 1144 struct NetRxPkt *pkt, 1145 bool is_eop, 1146 const E1000E_RSSInfo *rss_info, 1147 uint32_t *rss, uint32_t *mrq, 1148 uint32_t *status_flags, 1149 uint16_t *ip_id, 1150 uint16_t *vlan_tag) 1151 { 1152 struct virtio_net_hdr *vhdr; 1153 bool hasip4, hasip6; 1154 EthL4HdrProto l4hdr_proto; 1155 uint32_t pkt_type; 1156 1157 *status_flags = E1000_RXD_STAT_DD; 1158 1159 /* No additional metadata needed for non-EOP descriptors */ 1160 if (!is_eop) { 1161 goto func_exit; 1162 } 1163 1164 *status_flags |= E1000_RXD_STAT_EOP; 1165 1166 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1167 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1168 1169 /* VLAN state */ 1170 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1171 *status_flags |= E1000_RXD_STAT_VP; 1172 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1173 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1174 } 1175 1176 /* Packet parsing results */ 1177 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1178 if (rss_info->enabled) { 1179 *rss = cpu_to_le32(rss_info->hash); 1180 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1181 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1182 } 1183 } else if (hasip4) { 1184 *status_flags |= E1000_RXD_STAT_IPIDV; 1185 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1186 trace_e1000e_rx_metadata_ip_id(*ip_id); 1187 } 1188 1189 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { 1190 *status_flags |= E1000_RXD_STAT_ACK; 1191 trace_e1000e_rx_metadata_ack(); 1192 } 1193 1194 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1195 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1196 pkt_type = E1000_RXD_PKT_MAC; 1197 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1198 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1199 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1200 } else if (hasip4 || hasip6) { 1201 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1202 } else { 1203 pkt_type = E1000_RXD_PKT_MAC; 1204 } 1205 1206 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1207 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1208 1209 /* RX CSO information */ 1210 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1211 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1212 goto func_exit; 1213 } 1214 1215 vhdr = net_rx_pkt_get_vhdr(pkt); 1216 1217 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1218 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1219 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1220 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1221 goto func_exit; 1222 } 1223 1224 if (e1000e_rx_l3_cso_enabled(core)) { 1225 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1226 } else { 1227 trace_e1000e_rx_metadata_l3_cso_disabled(); 1228 } 1229 1230 if (e1000e_rx_l4_cso_enabled(core)) { 1231 switch (l4hdr_proto) { 1232 case ETH_L4_HDR_PROTO_TCP: 1233 *status_flags |= E1000_RXD_STAT_TCPCS; 1234 break; 1235 1236 case ETH_L4_HDR_PROTO_UDP: 1237 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1238 break; 1239 1240 default: 1241 break; 1242 } 1243 } else { 1244 trace_e1000e_rx_metadata_l4_cso_disabled(); 1245 } 1246 1247 func_exit: 1248 trace_e1000e_rx_metadata_status_flags(*status_flags); 1249 *status_flags = cpu_to_le32(*status_flags); 1250 } 1251 1252 static inline void 1253 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1254 struct NetRxPkt *pkt, 1255 const E1000E_RSSInfo *rss_info, 1256 uint16_t length) 1257 { 1258 uint32_t status_flags, rss, mrq; 1259 uint16_t ip_id; 1260 1261 assert(!rss_info->enabled); 1262 1263 desc->length = cpu_to_le16(length); 1264 desc->csum = 0; 1265 1266 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1267 rss_info, 1268 &rss, &mrq, 1269 &status_flags, &ip_id, 1270 &desc->special); 1271 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1272 desc->status = (uint8_t) le32_to_cpu(status_flags); 1273 } 1274 1275 static inline void 1276 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1277 struct NetRxPkt *pkt, 1278 const E1000E_RSSInfo *rss_info, 1279 uint16_t length) 1280 { 1281 memset(&desc->wb, 0, sizeof(desc->wb)); 1282 1283 desc->wb.upper.length = cpu_to_le16(length); 1284 1285 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1286 rss_info, 1287 &desc->wb.lower.hi_dword.rss, 1288 &desc->wb.lower.mrq, 1289 &desc->wb.upper.status_error, 1290 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1291 &desc->wb.upper.vlan); 1292 } 1293 1294 static inline void 1295 e1000e_write_ps_rx_descr(E1000ECore *core, 1296 union e1000_rx_desc_packet_split *desc, 1297 struct NetRxPkt *pkt, 1298 const E1000E_RSSInfo *rss_info, 1299 size_t ps_hdr_len, 1300 uint16_t(*written)[MAX_PS_BUFFERS]) 1301 { 1302 int i; 1303 1304 memset(&desc->wb, 0, sizeof(desc->wb)); 1305 1306 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1307 1308 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1309 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1310 } 1311 1312 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1313 rss_info, 1314 &desc->wb.lower.hi_dword.rss, 1315 &desc->wb.lower.mrq, 1316 &desc->wb.middle.status_error, 1317 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1318 &desc->wb.middle.vlan); 1319 1320 desc->wb.upper.header_status = 1321 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1322 1323 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1324 (*written)[2], (*written)[3]); 1325 } 1326 1327 static inline void 1328 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1329 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1330 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1331 { 1332 if (e1000e_rx_use_legacy_descriptor(core)) { 1333 assert(ps_hdr_len == 0); 1334 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1335 (*written)[0]); 1336 } else { 1337 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1338 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1339 ps_hdr_len, written); 1340 } else { 1341 assert(ps_hdr_len == 0); 1342 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1343 (*written)[0]); 1344 } 1345 } 1346 } 1347 1348 static inline void 1349 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1350 union e1000_rx_desc_union *desc, dma_addr_t len) 1351 { 1352 PCIDevice *dev = core->owner; 1353 1354 if (e1000e_rx_use_legacy_descriptor(core)) { 1355 struct e1000_rx_desc *d = &desc->legacy; 1356 size_t offset = offsetof(struct e1000_rx_desc, status); 1357 uint8_t status = d->status; 1358 1359 d->status &= ~E1000_RXD_STAT_DD; 1360 pci_dma_write(dev, addr, desc, len); 1361 1362 if (status & E1000_RXD_STAT_DD) { 1363 d->status = status; 1364 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1365 } 1366 } else { 1367 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1368 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1369 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1370 wb.middle.status_error); 1371 uint32_t status = d->wb.middle.status_error; 1372 1373 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1374 pci_dma_write(dev, addr, desc, len); 1375 1376 if (status & E1000_RXD_STAT_DD) { 1377 d->wb.middle.status_error = status; 1378 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1379 } 1380 } else { 1381 union e1000_rx_desc_extended *d = &desc->extended; 1382 size_t offset = offsetof(union e1000_rx_desc_extended, 1383 wb.upper.status_error); 1384 uint32_t status = d->wb.upper.status_error; 1385 1386 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1387 pci_dma_write(dev, addr, desc, len); 1388 1389 if (status & E1000_RXD_STAT_DD) { 1390 d->wb.upper.status_error = status; 1391 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1392 } 1393 } 1394 } 1395 } 1396 1397 typedef struct e1000e_ba_state_st { 1398 uint16_t written[MAX_PS_BUFFERS]; 1399 uint8_t cur_idx; 1400 } e1000e_ba_state; 1401 1402 static inline void 1403 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1404 hwaddr ba[MAX_PS_BUFFERS], 1405 e1000e_ba_state *bastate, 1406 const char *data, 1407 dma_addr_t data_len) 1408 { 1409 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1410 1411 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1412 bastate->written[0] += data_len; 1413 1414 bastate->cur_idx = 1; 1415 } 1416 1417 static void 1418 e1000e_write_to_rx_buffers(E1000ECore *core, 1419 hwaddr ba[MAX_PS_BUFFERS], 1420 e1000e_ba_state *bastate, 1421 const char *data, 1422 dma_addr_t data_len) 1423 { 1424 while (data_len > 0) { 1425 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1426 uint32_t cur_buf_bytes_left = cur_buf_len - 1427 bastate->written[bastate->cur_idx]; 1428 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1429 1430 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1431 ba[bastate->cur_idx], 1432 bastate->written[bastate->cur_idx], 1433 data, 1434 bytes_to_write); 1435 1436 pci_dma_write(core->owner, 1437 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1438 data, bytes_to_write); 1439 1440 bastate->written[bastate->cur_idx] += bytes_to_write; 1441 data += bytes_to_write; 1442 data_len -= bytes_to_write; 1443 1444 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1445 bastate->cur_idx++; 1446 } 1447 1448 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1449 } 1450 } 1451 1452 static void 1453 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) 1454 { 1455 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1456 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1457 } 1458 1459 static inline bool 1460 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1461 { 1462 return e1000e_ring_free_descr_num(core, rxi) == 1463 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1464 } 1465 1466 static bool 1467 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1468 { 1469 bool hasip4, hasip6; 1470 EthL4HdrProto l4hdr_proto; 1471 bool fragment; 1472 1473 if (!e1000e_rx_use_ps_descriptor(core)) { 1474 return false; 1475 } 1476 1477 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1478 1479 if (hasip4) { 1480 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1481 } else if (hasip6) { 1482 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1483 } else { 1484 return false; 1485 } 1486 1487 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1488 return false; 1489 } 1490 1491 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1492 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1493 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1494 } else { 1495 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1496 } 1497 1498 if ((*hdr_len > core->rxbuf_sizes[0]) || 1499 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1500 return false; 1501 } 1502 1503 return true; 1504 } 1505 1506 static void 1507 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1508 const E1000E_RxRing *rxr, 1509 const E1000E_RSSInfo *rss_info) 1510 { 1511 PCIDevice *d = core->owner; 1512 dma_addr_t base; 1513 union e1000_rx_desc_union desc; 1514 size_t desc_size; 1515 size_t desc_offset = 0; 1516 size_t iov_ofs = 0; 1517 1518 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1519 size_t size = net_rx_pkt_get_total_len(pkt); 1520 size_t total_size = size + e1000x_fcs_len(core->mac); 1521 const E1000E_RingInfo *rxi; 1522 size_t ps_hdr_len = 0; 1523 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1524 bool is_first = true; 1525 1526 rxi = rxr->i; 1527 1528 do { 1529 hwaddr ba[MAX_PS_BUFFERS]; 1530 e1000e_ba_state bastate = { { 0 } }; 1531 bool is_last = false; 1532 1533 desc_size = total_size - desc_offset; 1534 1535 if (desc_size > core->rx_desc_buf_size) { 1536 desc_size = core->rx_desc_buf_size; 1537 } 1538 1539 if (e1000e_ring_empty(core, rxi)) { 1540 return; 1541 } 1542 1543 base = e1000e_ring_head_descr(core, rxi); 1544 1545 pci_dma_read(d, base, &desc, core->rx_desc_len); 1546 1547 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1548 1549 e1000e_read_rx_descr(core, &desc, ba); 1550 1551 if (ba[0]) { 1552 if (desc_offset < size) { 1553 static const uint32_t fcs_pad; 1554 size_t iov_copy; 1555 size_t copy_size = size - desc_offset; 1556 if (copy_size > core->rx_desc_buf_size) { 1557 copy_size = core->rx_desc_buf_size; 1558 } 1559 1560 /* For PS mode copy the packet header first */ 1561 if (do_ps) { 1562 if (is_first) { 1563 size_t ps_hdr_copied = 0; 1564 do { 1565 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1566 iov->iov_len - iov_ofs); 1567 1568 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1569 iov->iov_base, iov_copy); 1570 1571 copy_size -= iov_copy; 1572 ps_hdr_copied += iov_copy; 1573 1574 iov_ofs += iov_copy; 1575 if (iov_ofs == iov->iov_len) { 1576 iov++; 1577 iov_ofs = 0; 1578 } 1579 } while (ps_hdr_copied < ps_hdr_len); 1580 1581 is_first = false; 1582 } else { 1583 /* Leave buffer 0 of each descriptor except first */ 1584 /* empty as per spec 7.1.5.1 */ 1585 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1586 NULL, 0); 1587 } 1588 } 1589 1590 /* Copy packet payload */ 1591 while (copy_size) { 1592 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1593 1594 e1000e_write_to_rx_buffers(core, ba, &bastate, 1595 iov->iov_base + iov_ofs, iov_copy); 1596 1597 copy_size -= iov_copy; 1598 iov_ofs += iov_copy; 1599 if (iov_ofs == iov->iov_len) { 1600 iov++; 1601 iov_ofs = 0; 1602 } 1603 } 1604 1605 if (desc_offset + desc_size >= total_size) { 1606 /* Simulate FCS checksum presence in the last descriptor */ 1607 e1000e_write_to_rx_buffers(core, ba, &bastate, 1608 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1609 } 1610 } 1611 } else { /* as per intel docs; skip descriptors with null buf addr */ 1612 trace_e1000e_rx_null_descriptor(); 1613 } 1614 desc_offset += desc_size; 1615 if (desc_offset >= total_size) { 1616 is_last = true; 1617 } 1618 1619 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1620 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1621 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1622 1623 e1000e_ring_advance(core, rxi, 1624 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1625 1626 } while (desc_offset < total_size); 1627 1628 e1000e_update_rx_stats(core, size, total_size); 1629 } 1630 1631 static inline void 1632 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1633 { 1634 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1635 1636 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1637 net_rx_pkt_fix_l4_csum(pkt); 1638 } 1639 } 1640 1641 ssize_t 1642 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1643 { 1644 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1645 } 1646 1647 static ssize_t 1648 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1649 bool has_vnet) 1650 { 1651 uint32_t n = 0; 1652 uint8_t buf[ETH_ZLEN]; 1653 struct iovec min_iov; 1654 size_t size, orig_size; 1655 size_t iov_ofs = 0; 1656 E1000E_RxRing rxr; 1657 E1000E_RSSInfo rss_info; 1658 size_t total_size; 1659 ssize_t retval; 1660 bool rdmts_hit; 1661 1662 trace_e1000e_rx_receive_iov(iovcnt); 1663 1664 if (!e1000x_hw_rx_enabled(core->mac)) { 1665 return -1; 1666 } 1667 1668 /* Pull virtio header in */ 1669 if (has_vnet) { 1670 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1671 iov_ofs = sizeof(struct virtio_net_hdr); 1672 } else { 1673 net_rx_pkt_unset_vhdr(core->rx_pkt); 1674 } 1675 1676 orig_size = iov_size(iov, iovcnt); 1677 size = orig_size - iov_ofs; 1678 1679 /* Pad to minimum Ethernet frame length */ 1680 if (size < sizeof(buf)) { 1681 iov_to_buf(iov, iovcnt, iov_ofs, buf, size); 1682 memset(&buf[size], 0, sizeof(buf) - size); 1683 e1000x_inc_reg_if_not_full(core->mac, RUC); 1684 min_iov.iov_base = buf; 1685 min_iov.iov_len = size = sizeof(buf); 1686 iovcnt = 1; 1687 iov = &min_iov; 1688 iov_ofs = 0; 1689 } else { 1690 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4); 1691 } 1692 1693 /* Discard oversized packets if !LPE and !SBP. */ 1694 if (e1000x_is_oversized(core->mac, size)) { 1695 return orig_size; 1696 } 1697 1698 net_rx_pkt_set_packet_type(core->rx_pkt, 1699 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1700 1701 if (!e1000e_receive_filter(core, buf)) { 1702 trace_e1000e_rx_flt_dropped(); 1703 return orig_size; 1704 } 1705 1706 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1707 e1000x_vlan_enabled(core->mac), core->mac[VET]); 1708 1709 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1710 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1711 1712 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1713 e1000x_fcs_len(core->mac); 1714 1715 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1716 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1717 1718 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1719 1720 retval = orig_size; 1721 1722 /* Perform small receive detection (RSRPD) */ 1723 if (total_size < core->mac[RSRPD]) { 1724 n |= E1000_ICS_SRPD; 1725 } 1726 1727 /* Perform ACK receive detection */ 1728 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1729 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1730 n |= E1000_ICS_ACK; 1731 } 1732 1733 /* Check if receive descriptor minimum threshold hit */ 1734 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1735 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1736 1737 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1738 } else { 1739 n |= E1000_ICS_RXO; 1740 retval = 0; 1741 1742 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1743 } 1744 1745 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1746 trace_e1000e_rx_interrupt_set(n); 1747 e1000e_set_interrupt_cause(core, n); 1748 } else { 1749 trace_e1000e_rx_interrupt_delayed(n); 1750 } 1751 1752 return retval; 1753 } 1754 1755 static inline bool 1756 e1000e_have_autoneg(E1000ECore *core) 1757 { 1758 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1759 } 1760 1761 static void e1000e_update_flowctl_status(E1000ECore *core) 1762 { 1763 if (e1000e_have_autoneg(core) && 1764 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1765 trace_e1000e_link_autoneg_flowctl(true); 1766 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1767 } else { 1768 trace_e1000e_link_autoneg_flowctl(false); 1769 } 1770 } 1771 1772 static inline void 1773 e1000e_link_down(E1000ECore *core) 1774 { 1775 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1776 e1000e_update_flowctl_status(core); 1777 } 1778 1779 static inline void 1780 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1781 { 1782 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1783 core->phy[0][MII_BMCR] = val & ~(0x3f | 1784 MII_BMCR_RESET | 1785 MII_BMCR_ANRESTART); 1786 1787 if ((val & MII_BMCR_ANRESTART) && 1788 e1000e_have_autoneg(core)) { 1789 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1790 } 1791 } 1792 1793 static void 1794 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1795 { 1796 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1797 1798 if (val & BIT(10)) { 1799 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1800 } 1801 } 1802 1803 static void 1804 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1805 { 1806 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1807 } 1808 1809 void 1810 e1000e_core_set_link_status(E1000ECore *core) 1811 { 1812 NetClientState *nc = qemu_get_queue(core->owner_nic); 1813 uint32_t old_status = core->mac[STATUS]; 1814 1815 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1816 1817 if (nc->link_down) { 1818 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1819 } else { 1820 if (e1000e_have_autoneg(core) && 1821 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1822 e1000x_restart_autoneg(core->mac, core->phy[0], 1823 core->autoneg_timer); 1824 } else { 1825 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1826 e1000e_start_recv(core); 1827 } 1828 } 1829 1830 if (core->mac[STATUS] != old_status) { 1831 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1832 } 1833 } 1834 1835 static void 1836 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1837 { 1838 trace_e1000e_core_ctrl_write(index, val); 1839 1840 /* RST is self clearing */ 1841 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1842 core->mac[CTRL_DUP] = core->mac[CTRL]; 1843 1844 trace_e1000e_link_set_params( 1845 !!(val & E1000_CTRL_ASDE), 1846 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1847 !!(val & E1000_CTRL_FRCSPD), 1848 !!(val & E1000_CTRL_FRCDPX), 1849 !!(val & E1000_CTRL_RFCE), 1850 !!(val & E1000_CTRL_TFCE)); 1851 1852 if (val & E1000_CTRL_RST) { 1853 trace_e1000e_core_ctrl_sw_reset(); 1854 e1000e_reset(core, true); 1855 } 1856 1857 if (val & E1000_CTRL_PHY_RST) { 1858 trace_e1000e_core_ctrl_phy_reset(); 1859 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1860 } 1861 } 1862 1863 static void 1864 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1865 { 1866 trace_e1000e_rx_set_rfctl(val); 1867 1868 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1869 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1870 } 1871 1872 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1873 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1874 } 1875 1876 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1877 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1878 } 1879 1880 core->mac[RFCTL] = val; 1881 } 1882 1883 static void 1884 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1885 { 1886 int i; 1887 core->rx_desc_buf_size = 0; 1888 1889 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1890 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1891 } 1892 } 1893 1894 static void 1895 e1000e_parse_rxbufsize(E1000ECore *core) 1896 { 1897 uint32_t rctl = core->mac[RCTL]; 1898 1899 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1900 1901 if (rctl & E1000_RCTL_DTYP_MASK) { 1902 uint32_t bsize; 1903 1904 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1905 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1906 1907 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1908 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1909 1910 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1911 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1912 1913 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1914 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1915 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1916 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1917 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1918 } else { 1919 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1920 } 1921 1922 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1923 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1924 1925 e1000e_calc_per_desc_buf_size(core); 1926 } 1927 1928 static void 1929 e1000e_calc_rxdesclen(E1000ECore *core) 1930 { 1931 if (e1000e_rx_use_legacy_descriptor(core)) { 1932 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1933 } else { 1934 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1935 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1936 } else { 1937 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1938 } 1939 } 1940 trace_e1000e_rx_desc_len(core->rx_desc_len); 1941 } 1942 1943 static void 1944 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1945 { 1946 core->mac[RCTL] = val; 1947 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1948 1949 if (val & E1000_RCTL_EN) { 1950 e1000e_parse_rxbufsize(core); 1951 e1000e_calc_rxdesclen(core); 1952 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1953 E1000_RING_DESC_LEN_SHIFT; 1954 1955 e1000e_start_recv(core); 1956 } 1957 } 1958 1959 static 1960 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1961 (E1000ECore *, int, uint16_t) = { 1962 [0] = { 1963 [MII_BMCR] = e1000e_set_phy_ctrl, 1964 [PHY_PAGE] = e1000e_set_phy_page, 1965 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1966 } 1967 }; 1968 1969 static inline void 1970 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 1971 { 1972 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1973 core->mac[IMS] &= ~bits; 1974 } 1975 1976 static inline bool 1977 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 1978 { 1979 if (timer->running) { 1980 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1981 1982 return true; 1983 } 1984 1985 if (timer->core->mac[timer->delay_reg] != 0) { 1986 e1000e_intrmgr_rearm_timer(timer); 1987 } 1988 1989 return false; 1990 } 1991 1992 static inline bool 1993 e1000e_itr_should_postpone(E1000ECore *core) 1994 { 1995 return e1000e_postpone_interrupt(&core->itr); 1996 } 1997 1998 static inline bool 1999 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 2000 { 2001 return e1000e_postpone_interrupt(&core->eitr[idx]); 2002 } 2003 2004 static void 2005 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2006 { 2007 uint32_t effective_eiac; 2008 2009 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2010 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2011 if (vec < E1000E_MSIX_VEC_NUM) { 2012 if (!e1000e_eitr_should_postpone(core, vec)) { 2013 trace_e1000e_irq_msix_notify_vec(vec); 2014 msix_notify(core->owner, vec); 2015 } 2016 } else { 2017 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2018 } 2019 } else { 2020 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2021 } 2022 2023 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2024 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2025 core->mac[IAM] &= ~cause; 2026 } 2027 2028 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2029 2030 effective_eiac = core->mac[EIAC] & cause; 2031 2032 core->mac[ICR] &= ~effective_eiac; 2033 core->msi_causes_pending &= ~effective_eiac; 2034 2035 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2036 core->mac[IMS] &= ~effective_eiac; 2037 } 2038 } 2039 2040 static void 2041 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2042 { 2043 if (causes & E1000_ICR_RXQ0) { 2044 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2045 E1000_IVAR_RXQ0(core->mac[IVAR])); 2046 } 2047 2048 if (causes & E1000_ICR_RXQ1) { 2049 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2050 E1000_IVAR_RXQ1(core->mac[IVAR])); 2051 } 2052 2053 if (causes & E1000_ICR_TXQ0) { 2054 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2055 E1000_IVAR_TXQ0(core->mac[IVAR])); 2056 } 2057 2058 if (causes & E1000_ICR_TXQ1) { 2059 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2060 E1000_IVAR_TXQ1(core->mac[IVAR])); 2061 } 2062 2063 if (causes & E1000_ICR_OTHER) { 2064 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2065 E1000_IVAR_OTHER(core->mac[IVAR])); 2066 } 2067 } 2068 2069 static void 2070 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2071 { 2072 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2073 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2074 if (vec < E1000E_MSIX_VEC_NUM) { 2075 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2076 msix_clr_pending(core->owner, vec); 2077 } else { 2078 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2079 } 2080 } else { 2081 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2082 } 2083 } 2084 2085 static void 2086 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2087 { 2088 if (causes & E1000_ICR_RXQ0) { 2089 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2090 E1000_IVAR_RXQ0(core->mac[IVAR])); 2091 } 2092 2093 if (causes & E1000_ICR_RXQ1) { 2094 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2095 E1000_IVAR_RXQ1(core->mac[IVAR])); 2096 } 2097 2098 if (causes & E1000_ICR_TXQ0) { 2099 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2100 E1000_IVAR_TXQ0(core->mac[IVAR])); 2101 } 2102 2103 if (causes & E1000_ICR_TXQ1) { 2104 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2105 E1000_IVAR_TXQ1(core->mac[IVAR])); 2106 } 2107 2108 if (causes & E1000_ICR_OTHER) { 2109 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2110 E1000_IVAR_OTHER(core->mac[IVAR])); 2111 } 2112 } 2113 2114 static inline void 2115 e1000e_fix_icr_asserted(E1000ECore *core) 2116 { 2117 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2118 if (core->mac[ICR]) { 2119 core->mac[ICR] |= E1000_ICR_ASSERTED; 2120 } 2121 2122 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2123 } 2124 2125 static void 2126 e1000e_send_msi(E1000ECore *core, bool msix) 2127 { 2128 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2129 2130 core->msi_causes_pending &= causes; 2131 causes ^= core->msi_causes_pending; 2132 if (causes == 0) { 2133 return; 2134 } 2135 core->msi_causes_pending |= causes; 2136 2137 if (msix) { 2138 e1000e_msix_notify(core, causes); 2139 } else { 2140 if (!e1000e_itr_should_postpone(core)) { 2141 trace_e1000e_irq_msi_notify(causes); 2142 msi_notify(core->owner, 0); 2143 } 2144 } 2145 } 2146 2147 static void 2148 e1000e_update_interrupt_state(E1000ECore *core) 2149 { 2150 bool interrupts_pending; 2151 bool is_msix = msix_enabled(core->owner); 2152 2153 /* Set ICR[OTHER] for MSI-X */ 2154 if (is_msix) { 2155 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2156 core->mac[ICR] |= E1000_ICR_OTHER; 2157 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2158 } 2159 } 2160 2161 e1000e_fix_icr_asserted(core); 2162 2163 /* 2164 * Make sure ICR and ICS registers have the same value. 2165 * The spec says that the ICS register is write-only. However in practice, 2166 * on real hardware ICS is readable, and for reads it has the same value as 2167 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2168 * 2169 * The VxWorks PRO/1000 driver uses this behaviour. 2170 */ 2171 core->mac[ICS] = core->mac[ICR]; 2172 2173 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2174 if (!interrupts_pending) { 2175 core->msi_causes_pending = 0; 2176 } 2177 2178 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2179 core->mac[ICR], core->mac[IMS]); 2180 2181 if (is_msix || msi_enabled(core->owner)) { 2182 if (interrupts_pending) { 2183 e1000e_send_msi(core, is_msix); 2184 } 2185 } else { 2186 if (interrupts_pending) { 2187 if (!e1000e_itr_should_postpone(core)) { 2188 e1000e_raise_legacy_irq(core); 2189 } 2190 } else { 2191 e1000e_lower_legacy_irq(core); 2192 } 2193 } 2194 } 2195 2196 static void 2197 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2198 { 2199 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2200 2201 val |= e1000e_intmgr_collect_delayed_causes(core); 2202 core->mac[ICR] |= val; 2203 2204 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2205 2206 e1000e_update_interrupt_state(core); 2207 } 2208 2209 static inline void 2210 e1000e_autoneg_timer(void *opaque) 2211 { 2212 E1000ECore *core = opaque; 2213 if (!qemu_get_queue(core->owner_nic)->link_down) { 2214 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2215 e1000e_start_recv(core); 2216 2217 e1000e_update_flowctl_status(core); 2218 /* signal link status change to the guest */ 2219 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2220 } 2221 } 2222 2223 static inline uint16_t 2224 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2225 { 2226 uint16_t index = (addr & 0x1ffff) >> 2; 2227 return index + (mac_reg_access[index] & 0xfffe); 2228 } 2229 2230 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2231 [0] = { 2232 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2233 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2234 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2235 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2236 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2237 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2238 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2239 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2240 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2241 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2242 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2243 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2244 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2245 2246 [PHY_COPPER_CTRL1] = PHY_RW, 2247 [PHY_COPPER_STAT1] = PHY_R, 2248 [PHY_COPPER_CTRL3] = PHY_RW, 2249 [PHY_RX_ERR_CNTR] = PHY_R, 2250 [PHY_OEM_BITS] = PHY_RW, 2251 [PHY_BIAS_1] = PHY_RW, 2252 [PHY_BIAS_2] = PHY_RW, 2253 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2254 [PHY_COPPER_STAT2] = PHY_R, 2255 [PHY_COPPER_CTRL2] = PHY_RW 2256 }, 2257 [2] = { 2258 [PHY_MAC_CTRL1] = PHY_RW, 2259 [PHY_MAC_INT_ENABLE] = PHY_RW, 2260 [PHY_MAC_STAT] = PHY_R, 2261 [PHY_MAC_CTRL2] = PHY_RW 2262 }, 2263 [3] = { 2264 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2265 [PHY_LED_03_POL_CTRL] = PHY_RW, 2266 [PHY_LED_TIMER_CTRL] = PHY_RW, 2267 [PHY_LED_45_CTRL] = PHY_RW 2268 }, 2269 [5] = { 2270 [PHY_1000T_SKEW] = PHY_R, 2271 [PHY_1000T_SWAP] = PHY_R 2272 }, 2273 [6] = { 2274 [PHY_CRC_COUNTERS] = PHY_R 2275 } 2276 }; 2277 2278 static bool 2279 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2280 char cap, uint8_t *page) 2281 { 2282 *page = 2283 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2284 : core->phy[0][PHY_PAGE]; 2285 2286 if (*page >= E1000E_PHY_PAGES) { 2287 return false; 2288 } 2289 2290 return e1000e_phy_regcap[*page][addr] & cap; 2291 } 2292 2293 static void 2294 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2295 uint32_t addr, uint16_t data) 2296 { 2297 assert(page < E1000E_PHY_PAGES); 2298 assert(addr < E1000E_PHY_PAGE_SIZE); 2299 2300 if (e1000e_phyreg_writeops[page][addr]) { 2301 e1000e_phyreg_writeops[page][addr](core, addr, data); 2302 } else { 2303 core->phy[page][addr] = data; 2304 } 2305 } 2306 2307 static void 2308 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2309 { 2310 uint32_t data = val & E1000_MDIC_DATA_MASK; 2311 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2312 uint8_t page; 2313 2314 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2315 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2316 } else if (val & E1000_MDIC_OP_READ) { 2317 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2318 trace_e1000e_core_mdic_read_unhandled(page, addr); 2319 val |= E1000_MDIC_ERROR; 2320 } else { 2321 val = (val ^ data) | core->phy[page][addr]; 2322 trace_e1000e_core_mdic_read(page, addr, val); 2323 } 2324 } else if (val & E1000_MDIC_OP_WRITE) { 2325 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2326 trace_e1000e_core_mdic_write_unhandled(page, addr); 2327 val |= E1000_MDIC_ERROR; 2328 } else { 2329 trace_e1000e_core_mdic_write(page, addr, data); 2330 e1000e_phy_reg_write(core, page, addr, data); 2331 } 2332 } 2333 core->mac[MDIC] = val | E1000_MDIC_READY; 2334 2335 if (val & E1000_MDIC_INT_EN) { 2336 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2337 } 2338 } 2339 2340 static void 2341 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2342 { 2343 core->mac[index] = val & 0xffff; 2344 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2345 e1000e_start_recv(core); 2346 } 2347 2348 static void 2349 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2350 { 2351 if ((val & E1000_STATUS_PHYRA) == 0) { 2352 core->mac[index] &= ~E1000_STATUS_PHYRA; 2353 } 2354 } 2355 2356 static void 2357 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2358 { 2359 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2360 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2361 2362 /* Zero self-clearing bits */ 2363 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2364 core->mac[CTRL_EXT] = val; 2365 } 2366 2367 static void 2368 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2369 { 2370 int i; 2371 2372 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2373 2374 if (!msix_enabled(core->owner)) { 2375 return; 2376 } 2377 2378 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2379 if (core->mac[PBACLR] & BIT(i)) { 2380 msix_clr_pending(core->owner, i); 2381 } 2382 } 2383 } 2384 2385 static void 2386 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2387 { 2388 core->mac[FCRTH] = val & 0xFFF8; 2389 } 2390 2391 static void 2392 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2393 { 2394 core->mac[FCRTL] = val & 0x8000FFF8; 2395 } 2396 2397 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2398 static void \ 2399 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2400 { \ 2401 core->mac[index] = val & (BIT(num) - 1); \ 2402 } 2403 2404 E1000E_LOW_BITS_SET_FUNC(4) 2405 E1000E_LOW_BITS_SET_FUNC(6) 2406 E1000E_LOW_BITS_SET_FUNC(11) 2407 E1000E_LOW_BITS_SET_FUNC(12) 2408 E1000E_LOW_BITS_SET_FUNC(13) 2409 E1000E_LOW_BITS_SET_FUNC(16) 2410 2411 static void 2412 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2413 { 2414 core->mac[VET] = val & 0xffff; 2415 trace_e1000e_vlan_vet(core->mac[VET]); 2416 } 2417 2418 static void 2419 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2420 { 2421 core->mac[index] = val & E1000_XDLEN_MASK; 2422 } 2423 2424 static void 2425 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2426 { 2427 core->mac[index] = val & E1000_XDBAL_MASK; 2428 } 2429 2430 static void 2431 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2432 { 2433 E1000E_TxRing txr; 2434 core->mac[index] = val; 2435 2436 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2437 e1000e_tx_ring_init(core, &txr, 0); 2438 e1000e_start_xmit(core, &txr); 2439 } 2440 2441 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2442 e1000e_tx_ring_init(core, &txr, 1); 2443 e1000e_start_xmit(core, &txr); 2444 } 2445 } 2446 2447 static void 2448 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2449 { 2450 E1000E_TxRing txr; 2451 int qidx = e1000e_mq_queue_idx(TDT, index); 2452 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2453 2454 core->mac[index] = val & 0xffff; 2455 2456 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2457 e1000e_tx_ring_init(core, &txr, qidx); 2458 e1000e_start_xmit(core, &txr); 2459 } 2460 } 2461 2462 static void 2463 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2464 { 2465 trace_e1000e_irq_write_ics(val); 2466 e1000e_set_interrupt_cause(core, val); 2467 } 2468 2469 static void 2470 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2471 { 2472 uint32_t icr = 0; 2473 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2474 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2475 trace_e1000e_irq_icr_process_iame(); 2476 e1000e_clear_ims_bits(core, core->mac[IAM]); 2477 } 2478 2479 icr = core->mac[ICR] & ~val; 2480 /* 2481 * Windows driver expects that the "receive overrun" bit and other 2482 * ones to be cleared when the "Other" bit (#24) is cleared. 2483 */ 2484 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr; 2485 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); 2486 core->mac[ICR] = icr; 2487 e1000e_update_interrupt_state(core); 2488 } 2489 2490 static void 2491 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2492 { 2493 trace_e1000e_irq_ims_clear_set_imc(val); 2494 e1000e_clear_ims_bits(core, val); 2495 e1000e_update_interrupt_state(core); 2496 } 2497 2498 static void 2499 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2500 { 2501 static const uint32_t ims_ext_mask = 2502 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2503 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2504 E1000_IMS_OTHER; 2505 2506 static const uint32_t ims_valid_mask = 2507 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2508 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2509 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2510 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2511 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2512 E1000_IMS_OTHER; 2513 2514 uint32_t valid_val = val & ims_valid_mask; 2515 2516 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2517 core->mac[IMS] |= valid_val; 2518 2519 if ((valid_val & ims_ext_mask) && 2520 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2521 msix_enabled(core->owner)) { 2522 e1000e_msix_clear(core, valid_val); 2523 } 2524 2525 if ((valid_val == ims_valid_mask) && 2526 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2527 trace_e1000e_irq_fire_all_timers(val); 2528 e1000e_intrmgr_fire_all_timers(core); 2529 } 2530 2531 e1000e_update_interrupt_state(core); 2532 } 2533 2534 static void 2535 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2536 { 2537 e1000e_set_16bit(core, index, val); 2538 2539 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2540 trace_e1000e_irq_rdtr_fpd_running(); 2541 e1000e_intrmgr_fire_delayed_interrupts(core); 2542 } else { 2543 trace_e1000e_irq_rdtr_fpd_not_running(); 2544 } 2545 } 2546 2547 static void 2548 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2549 { 2550 e1000e_set_16bit(core, index, val); 2551 2552 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2553 trace_e1000e_irq_tidv_fpd_running(); 2554 e1000e_intrmgr_fire_delayed_interrupts(core); 2555 } else { 2556 trace_e1000e_irq_tidv_fpd_not_running(); 2557 } 2558 } 2559 2560 static uint32_t 2561 e1000e_mac_readreg(E1000ECore *core, int index) 2562 { 2563 return core->mac[index]; 2564 } 2565 2566 static uint32_t 2567 e1000e_mac_ics_read(E1000ECore *core, int index) 2568 { 2569 trace_e1000e_irq_read_ics(core->mac[ICS]); 2570 return core->mac[ICS]; 2571 } 2572 2573 static uint32_t 2574 e1000e_mac_ims_read(E1000ECore *core, int index) 2575 { 2576 trace_e1000e_irq_read_ims(core->mac[IMS]); 2577 return core->mac[IMS]; 2578 } 2579 2580 static uint32_t 2581 e1000e_mac_swsm_read(E1000ECore *core, int index) 2582 { 2583 uint32_t val = core->mac[SWSM]; 2584 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2585 return val; 2586 } 2587 2588 static uint32_t 2589 e1000e_mac_itr_read(E1000ECore *core, int index) 2590 { 2591 return core->itr_guest_value; 2592 } 2593 2594 static uint32_t 2595 e1000e_mac_eitr_read(E1000ECore *core, int index) 2596 { 2597 return core->eitr_guest_value[index - EITR]; 2598 } 2599 2600 static uint32_t 2601 e1000e_mac_icr_read(E1000ECore *core, int index) 2602 { 2603 uint32_t ret = core->mac[ICR]; 2604 trace_e1000e_irq_icr_read_entry(ret); 2605 2606 if (core->mac[IMS] == 0) { 2607 trace_e1000e_irq_icr_clear_zero_ims(); 2608 core->mac[ICR] = 0; 2609 } 2610 2611 if (!msix_enabled(core->owner)) { 2612 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2613 core->mac[ICR] = 0; 2614 } 2615 2616 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2617 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2618 trace_e1000e_irq_icr_clear_iame(); 2619 core->mac[ICR] = 0; 2620 trace_e1000e_irq_icr_process_iame(); 2621 e1000e_clear_ims_bits(core, core->mac[IAM]); 2622 } 2623 2624 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2625 e1000e_update_interrupt_state(core); 2626 return ret; 2627 } 2628 2629 static uint32_t 2630 e1000e_mac_read_clr4(E1000ECore *core, int index) 2631 { 2632 uint32_t ret = core->mac[index]; 2633 2634 core->mac[index] = 0; 2635 return ret; 2636 } 2637 2638 static uint32_t 2639 e1000e_mac_read_clr8(E1000ECore *core, int index) 2640 { 2641 uint32_t ret = core->mac[index]; 2642 2643 core->mac[index] = 0; 2644 core->mac[index - 1] = 0; 2645 return ret; 2646 } 2647 2648 static uint32_t 2649 e1000e_get_ctrl(E1000ECore *core, int index) 2650 { 2651 uint32_t val = core->mac[CTRL]; 2652 2653 trace_e1000e_link_read_params( 2654 !!(val & E1000_CTRL_ASDE), 2655 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2656 !!(val & E1000_CTRL_FRCSPD), 2657 !!(val & E1000_CTRL_FRCDPX), 2658 !!(val & E1000_CTRL_RFCE), 2659 !!(val & E1000_CTRL_TFCE)); 2660 2661 return val; 2662 } 2663 2664 static uint32_t 2665 e1000e_get_status(E1000ECore *core, int index) 2666 { 2667 uint32_t res = core->mac[STATUS]; 2668 2669 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2670 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2671 } 2672 2673 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2674 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2675 } else { 2676 res |= E1000_STATUS_FD; 2677 } 2678 2679 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2680 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2681 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2682 case E1000_CTRL_SPD_10: 2683 res |= E1000_STATUS_SPEED_10; 2684 break; 2685 case E1000_CTRL_SPD_100: 2686 res |= E1000_STATUS_SPEED_100; 2687 break; 2688 case E1000_CTRL_SPD_1000: 2689 default: 2690 res |= E1000_STATUS_SPEED_1000; 2691 break; 2692 } 2693 } else { 2694 res |= E1000_STATUS_SPEED_1000; 2695 } 2696 2697 trace_e1000e_link_status( 2698 !!(res & E1000_STATUS_LU), 2699 !!(res & E1000_STATUS_FD), 2700 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2701 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2702 2703 return res; 2704 } 2705 2706 static uint32_t 2707 e1000e_get_tarc(E1000ECore *core, int index) 2708 { 2709 return core->mac[index] & ((BIT(11) - 1) | 2710 BIT(27) | 2711 BIT(28) | 2712 BIT(29) | 2713 BIT(30)); 2714 } 2715 2716 static void 2717 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2718 { 2719 core->mac[index] = val; 2720 } 2721 2722 static void 2723 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2724 { 2725 uint32_t macaddr[2]; 2726 2727 core->mac[index] = val; 2728 2729 macaddr[0] = cpu_to_le32(core->mac[RA]); 2730 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2731 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2732 (uint8_t *) macaddr); 2733 2734 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2735 } 2736 2737 static void 2738 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2739 { 2740 static const uint32_t ro_bits = E1000_EECD_PRES | 2741 E1000_EECD_AUTO_RD | 2742 E1000_EECD_SIZE_EX_MASK; 2743 2744 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2745 } 2746 2747 static void 2748 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2749 { 2750 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2751 uint32_t flags = 0; 2752 uint32_t data = 0; 2753 2754 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2755 data = core->eeprom[addr]; 2756 flags = E1000_EERW_DONE; 2757 } 2758 2759 core->mac[EERD] = flags | 2760 (addr << E1000_EERW_ADDR_SHIFT) | 2761 (data << E1000_EERW_DATA_SHIFT); 2762 } 2763 2764 static void 2765 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2766 { 2767 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2768 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2769 uint32_t flags = 0; 2770 2771 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2772 core->eeprom[addr] = data; 2773 flags = E1000_EERW_DONE; 2774 } 2775 2776 core->mac[EERD] = flags | 2777 (addr << E1000_EERW_ADDR_SHIFT) | 2778 (data << E1000_EERW_DATA_SHIFT); 2779 } 2780 2781 static void 2782 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2783 { 2784 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2785 } 2786 2787 static void 2788 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2789 { 2790 uint32_t interval = val & 0xffff; 2791 2792 trace_e1000e_irq_itr_set(val); 2793 2794 core->itr_guest_value = interval; 2795 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2796 } 2797 2798 static void 2799 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2800 { 2801 uint32_t interval = val & 0xffff; 2802 uint32_t eitr_num = index - EITR; 2803 2804 trace_e1000e_irq_eitr_set(eitr_num, val); 2805 2806 core->eitr_guest_value[eitr_num] = interval; 2807 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2808 } 2809 2810 static void 2811 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2812 { 2813 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2814 2815 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2816 qemu_log_mask(LOG_GUEST_ERROR, 2817 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2818 return; 2819 } 2820 2821 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2822 qemu_log_mask(LOG_GUEST_ERROR, 2823 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2824 return; 2825 } 2826 } 2827 2828 core->mac[PSRCTL] = val; 2829 } 2830 2831 static void 2832 e1000e_update_rx_offloads(E1000ECore *core) 2833 { 2834 int cso_state = e1000e_rx_l4_cso_enabled(core); 2835 2836 trace_e1000e_rx_set_cso(cso_state); 2837 2838 if (core->has_vnet) { 2839 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2840 cso_state, 0, 0, 0, 0); 2841 } 2842 } 2843 2844 static void 2845 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2846 { 2847 core->mac[RXCSUM] = val; 2848 e1000e_update_rx_offloads(core); 2849 } 2850 2851 static void 2852 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2853 { 2854 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2855 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2856 } 2857 2858 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) 2859 { 2860 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2861 return core->mac[SYSTIML]; 2862 } 2863 2864 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) 2865 { 2866 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2867 return core->mac[RXSATRH]; 2868 } 2869 2870 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) 2871 { 2872 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2873 return core->mac[TXSTMPH]; 2874 } 2875 2876 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) 2877 { 2878 e1000x_set_timinca(core->mac, &core->timadj, val); 2879 } 2880 2881 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) 2882 { 2883 core->mac[TIMADJH] = val; 2884 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2885 } 2886 2887 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2888 typedef uint32_t (*readops)(E1000ECore *, int); 2889 static const readops e1000e_macreg_readops[] = { 2890 e1000e_getreg(PBA), 2891 e1000e_getreg(WUFC), 2892 e1000e_getreg(MANC), 2893 e1000e_getreg(TOTL), 2894 e1000e_getreg(RDT0), 2895 e1000e_getreg(RDBAH0), 2896 e1000e_getreg(TDBAL1), 2897 e1000e_getreg(RDLEN0), 2898 e1000e_getreg(RDH1), 2899 e1000e_getreg(LATECOL), 2900 e1000e_getreg(SEQEC), 2901 e1000e_getreg(XONTXC), 2902 e1000e_getreg(AIT), 2903 e1000e_getreg(TDFH), 2904 e1000e_getreg(TDFT), 2905 e1000e_getreg(TDFHS), 2906 e1000e_getreg(TDFTS), 2907 e1000e_getreg(TDFPC), 2908 e1000e_getreg(WUS), 2909 e1000e_getreg(PBS), 2910 e1000e_getreg(RDFH), 2911 e1000e_getreg(RDFT), 2912 e1000e_getreg(RDFHS), 2913 e1000e_getreg(RDFTS), 2914 e1000e_getreg(RDFPC), 2915 e1000e_getreg(GORCL), 2916 e1000e_getreg(MGTPRC), 2917 e1000e_getreg(EERD), 2918 e1000e_getreg(EIAC), 2919 e1000e_getreg(PSRCTL), 2920 e1000e_getreg(MANC2H), 2921 e1000e_getreg(RXCSUM), 2922 e1000e_getreg(GSCL_3), 2923 e1000e_getreg(GSCN_2), 2924 e1000e_getreg(RSRPD), 2925 e1000e_getreg(RDBAL1), 2926 e1000e_getreg(FCAH), 2927 e1000e_getreg(FCRTH), 2928 e1000e_getreg(FLOP), 2929 e1000e_getreg(FLASHT), 2930 e1000e_getreg(RXSTMPH), 2931 e1000e_getreg(TXSTMPL), 2932 e1000e_getreg(TIMADJL), 2933 e1000e_getreg(TXDCTL), 2934 e1000e_getreg(RDH0), 2935 e1000e_getreg(TDT1), 2936 e1000e_getreg(TNCRS), 2937 e1000e_getreg(RJC), 2938 e1000e_getreg(IAM), 2939 e1000e_getreg(GSCL_2), 2940 e1000e_getreg(RDBAH1), 2941 e1000e_getreg(FLSWDATA), 2942 e1000e_getreg(TIPG), 2943 e1000e_getreg(FLMNGCTL), 2944 e1000e_getreg(FLMNGCNT), 2945 e1000e_getreg(TSYNCTXCTL), 2946 e1000e_getreg(EXTCNF_SIZE), 2947 e1000e_getreg(EXTCNF_CTRL), 2948 e1000e_getreg(EEMNGDATA), 2949 e1000e_getreg(CTRL_EXT), 2950 e1000e_getreg(SYSTIMH), 2951 e1000e_getreg(EEMNGCTL), 2952 e1000e_getreg(FLMNGDATA), 2953 e1000e_getreg(TSYNCRXCTL), 2954 e1000e_getreg(TDH), 2955 e1000e_getreg(LEDCTL), 2956 e1000e_getreg(TCTL), 2957 e1000e_getreg(TDBAL), 2958 e1000e_getreg(TDLEN), 2959 e1000e_getreg(TDH1), 2960 e1000e_getreg(RADV), 2961 e1000e_getreg(ECOL), 2962 e1000e_getreg(DC), 2963 e1000e_getreg(RLEC), 2964 e1000e_getreg(XOFFTXC), 2965 e1000e_getreg(RFC), 2966 e1000e_getreg(RNBC), 2967 e1000e_getreg(MGTPTC), 2968 e1000e_getreg(TIMINCA), 2969 e1000e_getreg(RXCFGL), 2970 e1000e_getreg(MFUTP01), 2971 e1000e_getreg(FACTPS), 2972 e1000e_getreg(GSCL_1), 2973 e1000e_getreg(GSCN_0), 2974 e1000e_getreg(GCR2), 2975 e1000e_getreg(RDT1), 2976 e1000e_getreg(PBACLR), 2977 e1000e_getreg(FCTTV), 2978 e1000e_getreg(EEWR), 2979 e1000e_getreg(FLSWCTL), 2980 e1000e_getreg(RXDCTL1), 2981 e1000e_getreg(RXSATRL), 2982 e1000e_getreg(RXUDP), 2983 e1000e_getreg(TORL), 2984 e1000e_getreg(TDLEN1), 2985 e1000e_getreg(MCC), 2986 e1000e_getreg(WUC), 2987 e1000e_getreg(EECD), 2988 e1000e_getreg(MFUTP23), 2989 e1000e_getreg(RAID), 2990 e1000e_getreg(FCRTV), 2991 e1000e_getreg(TXDCTL1), 2992 e1000e_getreg(RCTL), 2993 e1000e_getreg(TDT), 2994 e1000e_getreg(MDIC), 2995 e1000e_getreg(FCRUC), 2996 e1000e_getreg(VET), 2997 e1000e_getreg(RDBAL0), 2998 e1000e_getreg(TDBAH1), 2999 e1000e_getreg(RDTR), 3000 e1000e_getreg(SCC), 3001 e1000e_getreg(COLC), 3002 e1000e_getreg(CEXTERR), 3003 e1000e_getreg(XOFFRXC), 3004 e1000e_getreg(IPAV), 3005 e1000e_getreg(GOTCL), 3006 e1000e_getreg(MGTPDC), 3007 e1000e_getreg(GCR), 3008 e1000e_getreg(IVAR), 3009 e1000e_getreg(POEMB), 3010 e1000e_getreg(MFVAL), 3011 e1000e_getreg(FUNCTAG), 3012 e1000e_getreg(GSCL_4), 3013 e1000e_getreg(GSCN_3), 3014 e1000e_getreg(MRQC), 3015 e1000e_getreg(RDLEN1), 3016 e1000e_getreg(FCT), 3017 e1000e_getreg(FLA), 3018 e1000e_getreg(FLOL), 3019 e1000e_getreg(RXDCTL), 3020 e1000e_getreg(RXSTMPL), 3021 e1000e_getreg(TIMADJH), 3022 e1000e_getreg(FCRTL), 3023 e1000e_getreg(TDBAH), 3024 e1000e_getreg(TADV), 3025 e1000e_getreg(XONRXC), 3026 e1000e_getreg(TSCTFC), 3027 e1000e_getreg(RFCTL), 3028 e1000e_getreg(GSCN_1), 3029 e1000e_getreg(FCAL), 3030 e1000e_getreg(FLSWCNT), 3031 3032 [TOTH] = e1000e_mac_read_clr8, 3033 [GOTCH] = e1000e_mac_read_clr8, 3034 [PRC64] = e1000e_mac_read_clr4, 3035 [PRC255] = e1000e_mac_read_clr4, 3036 [PRC1023] = e1000e_mac_read_clr4, 3037 [PTC64] = e1000e_mac_read_clr4, 3038 [PTC255] = e1000e_mac_read_clr4, 3039 [PTC1023] = e1000e_mac_read_clr4, 3040 [GPRC] = e1000e_mac_read_clr4, 3041 [TPT] = e1000e_mac_read_clr4, 3042 [RUC] = e1000e_mac_read_clr4, 3043 [BPRC] = e1000e_mac_read_clr4, 3044 [MPTC] = e1000e_mac_read_clr4, 3045 [IAC] = e1000e_mac_read_clr4, 3046 [ICR] = e1000e_mac_icr_read, 3047 [STATUS] = e1000e_get_status, 3048 [TARC0] = e1000e_get_tarc, 3049 [ICS] = e1000e_mac_ics_read, 3050 [TORH] = e1000e_mac_read_clr8, 3051 [GORCH] = e1000e_mac_read_clr8, 3052 [PRC127] = e1000e_mac_read_clr4, 3053 [PRC511] = e1000e_mac_read_clr4, 3054 [PRC1522] = e1000e_mac_read_clr4, 3055 [PTC127] = e1000e_mac_read_clr4, 3056 [PTC511] = e1000e_mac_read_clr4, 3057 [PTC1522] = e1000e_mac_read_clr4, 3058 [GPTC] = e1000e_mac_read_clr4, 3059 [TPR] = e1000e_mac_read_clr4, 3060 [ROC] = e1000e_mac_read_clr4, 3061 [MPRC] = e1000e_mac_read_clr4, 3062 [BPTC] = e1000e_mac_read_clr4, 3063 [TSCTC] = e1000e_mac_read_clr4, 3064 [ITR] = e1000e_mac_itr_read, 3065 [CTRL] = e1000e_get_ctrl, 3066 [TARC1] = e1000e_get_tarc, 3067 [SWSM] = e1000e_mac_swsm_read, 3068 [IMS] = e1000e_mac_ims_read, 3069 [SYSTIML] = e1000e_get_systiml, 3070 [RXSATRH] = e1000e_get_rxsatrh, 3071 [TXSTMPH] = e1000e_get_txstmph, 3072 3073 [CRCERRS ... MPC] = e1000e_mac_readreg, 3074 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3075 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3076 [RA ... RA + 31] = e1000e_mac_readreg, 3077 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3078 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3079 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3080 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3081 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3082 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3083 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3084 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3085 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3086 [RETA ... RETA + 31] = e1000e_mac_readreg, 3087 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3088 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3089 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3090 }; 3091 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3092 3093 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3094 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3095 static const writeops e1000e_macreg_writeops[] = { 3096 e1000e_putreg(PBA), 3097 e1000e_putreg(SWSM), 3098 e1000e_putreg(WUFC), 3099 e1000e_putreg(RDBAH1), 3100 e1000e_putreg(TDBAH), 3101 e1000e_putreg(TXDCTL), 3102 e1000e_putreg(RDBAH0), 3103 e1000e_putreg(LEDCTL), 3104 e1000e_putreg(FCAL), 3105 e1000e_putreg(FCRUC), 3106 e1000e_putreg(WUC), 3107 e1000e_putreg(WUS), 3108 e1000e_putreg(IPAV), 3109 e1000e_putreg(TDBAH1), 3110 e1000e_putreg(IAM), 3111 e1000e_putreg(EIAC), 3112 e1000e_putreg(IVAR), 3113 e1000e_putreg(TARC0), 3114 e1000e_putreg(TARC1), 3115 e1000e_putreg(FLSWDATA), 3116 e1000e_putreg(POEMB), 3117 e1000e_putreg(MFUTP01), 3118 e1000e_putreg(MFUTP23), 3119 e1000e_putreg(MANC), 3120 e1000e_putreg(MANC2H), 3121 e1000e_putreg(MFVAL), 3122 e1000e_putreg(EXTCNF_CTRL), 3123 e1000e_putreg(FACTPS), 3124 e1000e_putreg(FUNCTAG), 3125 e1000e_putreg(GSCL_1), 3126 e1000e_putreg(GSCL_2), 3127 e1000e_putreg(GSCL_3), 3128 e1000e_putreg(GSCL_4), 3129 e1000e_putreg(GSCN_0), 3130 e1000e_putreg(GSCN_1), 3131 e1000e_putreg(GSCN_2), 3132 e1000e_putreg(GSCN_3), 3133 e1000e_putreg(GCR2), 3134 e1000e_putreg(MRQC), 3135 e1000e_putreg(FLOP), 3136 e1000e_putreg(FLOL), 3137 e1000e_putreg(FLSWCTL), 3138 e1000e_putreg(FLSWCNT), 3139 e1000e_putreg(FLA), 3140 e1000e_putreg(RXDCTL1), 3141 e1000e_putreg(TXDCTL1), 3142 e1000e_putreg(TIPG), 3143 e1000e_putreg(RXSTMPH), 3144 e1000e_putreg(RXSTMPL), 3145 e1000e_putreg(RXSATRL), 3146 e1000e_putreg(RXSATRH), 3147 e1000e_putreg(TXSTMPL), 3148 e1000e_putreg(TXSTMPH), 3149 e1000e_putreg(SYSTIML), 3150 e1000e_putreg(SYSTIMH), 3151 e1000e_putreg(TIMADJL), 3152 e1000e_putreg(RXUDP), 3153 e1000e_putreg(RXCFGL), 3154 e1000e_putreg(TSYNCRXCTL), 3155 e1000e_putreg(TSYNCTXCTL), 3156 e1000e_putreg(EXTCNF_SIZE), 3157 e1000e_putreg(EEMNGCTL), 3158 e1000e_putreg(RA), 3159 3160 [TDH1] = e1000e_set_16bit, 3161 [TDT1] = e1000e_set_tdt, 3162 [TCTL] = e1000e_set_tctl, 3163 [TDT] = e1000e_set_tdt, 3164 [MDIC] = e1000e_set_mdic, 3165 [ICS] = e1000e_set_ics, 3166 [TDH] = e1000e_set_16bit, 3167 [RDH0] = e1000e_set_16bit, 3168 [RDT0] = e1000e_set_rdt, 3169 [IMC] = e1000e_set_imc, 3170 [IMS] = e1000e_set_ims, 3171 [ICR] = e1000e_set_icr, 3172 [EECD] = e1000e_set_eecd, 3173 [RCTL] = e1000e_set_rx_control, 3174 [CTRL] = e1000e_set_ctrl, 3175 [RDTR] = e1000e_set_rdtr, 3176 [RADV] = e1000e_set_16bit, 3177 [TADV] = e1000e_set_16bit, 3178 [ITR] = e1000e_set_itr, 3179 [EERD] = e1000e_set_eerd, 3180 [AIT] = e1000e_set_16bit, 3181 [TDFH] = e1000e_set_13bit, 3182 [TDFT] = e1000e_set_13bit, 3183 [TDFHS] = e1000e_set_13bit, 3184 [TDFTS] = e1000e_set_13bit, 3185 [TDFPC] = e1000e_set_13bit, 3186 [RDFH] = e1000e_set_13bit, 3187 [RDFHS] = e1000e_set_13bit, 3188 [RDFT] = e1000e_set_13bit, 3189 [RDFTS] = e1000e_set_13bit, 3190 [RDFPC] = e1000e_set_13bit, 3191 [PBS] = e1000e_set_6bit, 3192 [GCR] = e1000e_set_gcr, 3193 [PSRCTL] = e1000e_set_psrctl, 3194 [RXCSUM] = e1000e_set_rxcsum, 3195 [RAID] = e1000e_set_16bit, 3196 [RSRPD] = e1000e_set_12bit, 3197 [TIDV] = e1000e_set_tidv, 3198 [TDLEN1] = e1000e_set_dlen, 3199 [TDLEN] = e1000e_set_dlen, 3200 [RDLEN0] = e1000e_set_dlen, 3201 [RDLEN1] = e1000e_set_dlen, 3202 [TDBAL] = e1000e_set_dbal, 3203 [TDBAL1] = e1000e_set_dbal, 3204 [RDBAL0] = e1000e_set_dbal, 3205 [RDBAL1] = e1000e_set_dbal, 3206 [RDH1] = e1000e_set_16bit, 3207 [RDT1] = e1000e_set_rdt, 3208 [STATUS] = e1000e_set_status, 3209 [PBACLR] = e1000e_set_pbaclr, 3210 [CTRL_EXT] = e1000e_set_ctrlext, 3211 [FCAH] = e1000e_set_16bit, 3212 [FCT] = e1000e_set_16bit, 3213 [FCTTV] = e1000e_set_16bit, 3214 [FCRTV] = e1000e_set_16bit, 3215 [FCRTH] = e1000e_set_fcrth, 3216 [FCRTL] = e1000e_set_fcrtl, 3217 [VET] = e1000e_set_vet, 3218 [RXDCTL] = e1000e_set_rxdctl, 3219 [FLASHT] = e1000e_set_16bit, 3220 [EEWR] = e1000e_set_eewr, 3221 [CTRL_DUP] = e1000e_set_ctrl, 3222 [RFCTL] = e1000e_set_rfctl, 3223 [RA + 1] = e1000e_mac_setmacaddr, 3224 [TIMINCA] = e1000e_set_timinca, 3225 [TIMADJH] = e1000e_set_timadjh, 3226 3227 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3228 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3229 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3230 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3231 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3232 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3233 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3234 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3235 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3236 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3237 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3238 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3239 [RETA ... RETA + 31] = e1000e_mac_writereg, 3240 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3241 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3242 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3243 }; 3244 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3245 3246 enum { MAC_ACCESS_PARTIAL = 1 }; 3247 3248 /* 3249 * The array below combines alias offsets of the index values for the 3250 * MAC registers that have aliases, with the indication of not fully 3251 * implemented registers (lowest bit). This combination is possible 3252 * because all of the offsets are even. 3253 */ 3254 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3255 /* Alias index offsets */ 3256 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3257 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3258 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3259 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3260 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3261 [RA_A ... RA_A + 31] = 0x14f0, 3262 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3263 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3264 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3265 /* Access options */ 3266 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3267 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3268 [RDFPC] = MAC_ACCESS_PARTIAL, 3269 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3270 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3271 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3272 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3273 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3274 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3275 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3276 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3277 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3278 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3279 }; 3280 3281 void 3282 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3283 { 3284 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3285 3286 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3287 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3288 trace_e1000e_wrn_regs_write_trivial(index << 2); 3289 } 3290 trace_e1000e_core_write(index << 2, size, val); 3291 e1000e_macreg_writeops[index](core, index, val); 3292 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3293 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3294 } else { 3295 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3296 } 3297 } 3298 3299 uint64_t 3300 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3301 { 3302 uint64_t val; 3303 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3304 3305 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3306 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3307 trace_e1000e_wrn_regs_read_trivial(index << 2); 3308 } 3309 val = e1000e_macreg_readops[index](core, index); 3310 trace_e1000e_core_read(index << 2, size, val); 3311 return val; 3312 } else { 3313 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3314 } 3315 return 0; 3316 } 3317 3318 static inline void 3319 e1000e_autoneg_pause(E1000ECore *core) 3320 { 3321 timer_del(core->autoneg_timer); 3322 } 3323 3324 static void 3325 e1000e_autoneg_resume(E1000ECore *core) 3326 { 3327 if (e1000e_have_autoneg(core) && 3328 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3329 qemu_get_queue(core->owner_nic)->link_down = false; 3330 timer_mod(core->autoneg_timer, 3331 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3332 } 3333 } 3334 3335 static void 3336 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3337 { 3338 E1000ECore *core = opaque; 3339 3340 if (running) { 3341 trace_e1000e_vm_state_running(); 3342 e1000e_intrmgr_resume(core); 3343 e1000e_autoneg_resume(core); 3344 } else { 3345 trace_e1000e_vm_state_stopped(); 3346 e1000e_autoneg_pause(core); 3347 e1000e_intrmgr_pause(core); 3348 } 3349 } 3350 3351 void 3352 e1000e_core_pci_realize(E1000ECore *core, 3353 const uint16_t *eeprom_templ, 3354 uint32_t eeprom_size, 3355 const uint8_t *macaddr) 3356 { 3357 int i; 3358 3359 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3360 e1000e_autoneg_timer, core); 3361 e1000e_intrmgr_pci_realize(core); 3362 3363 core->vmstate = 3364 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3365 3366 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3367 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3368 } 3369 3370 net_rx_pkt_init(&core->rx_pkt); 3371 3372 e1000x_core_prepare_eeprom(core->eeprom, 3373 eeprom_templ, 3374 eeprom_size, 3375 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3376 macaddr); 3377 e1000e_update_rx_offloads(core); 3378 } 3379 3380 void 3381 e1000e_core_pci_uninit(E1000ECore *core) 3382 { 3383 int i; 3384 3385 timer_free(core->autoneg_timer); 3386 3387 e1000e_intrmgr_pci_unint(core); 3388 3389 qemu_del_vm_change_state_handler(core->vmstate); 3390 3391 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3392 net_tx_pkt_reset(core->tx[i].tx_pkt, 3393 net_tx_pkt_unmap_frag_pci, core->owner); 3394 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3395 } 3396 3397 net_rx_pkt_uninit(core->rx_pkt); 3398 } 3399 3400 static const uint16_t 3401 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3402 [0] = { 3403 [MII_BMCR] = MII_BMCR_SPEED1000 | 3404 MII_BMCR_FD | 3405 MII_BMCR_AUTOEN, 3406 3407 [MII_BMSR] = MII_BMSR_EXTCAP | 3408 MII_BMSR_LINK_ST | 3409 MII_BMSR_AUTONEG | 3410 MII_BMSR_MFPS | 3411 MII_BMSR_EXTSTAT | 3412 MII_BMSR_10T_HD | 3413 MII_BMSR_10T_FD | 3414 MII_BMSR_100TX_HD | 3415 MII_BMSR_100TX_FD, 3416 3417 [MII_PHYID1] = 0x141, 3418 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3419 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3420 MII_ANAR_10FD | MII_ANAR_TX | 3421 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3422 MII_ANAR_PAUSE_ASYM, 3423 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3424 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3425 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3426 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3427 [MII_ANNP] = 1 | MII_ANNP_MP, 3428 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3429 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3430 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3431 MII_STAT1000_ROK | MII_STAT1000_LOK, 3432 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3433 3434 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3435 BIT(12) | BIT(13), 3436 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3437 }, 3438 [2] = { 3439 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3440 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3441 }, 3442 [3] = { 3443 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3444 } 3445 }; 3446 3447 static const uint32_t e1000e_mac_reg_init[] = { 3448 [PBA] = 0x00140014, 3449 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3450 [EXTCNF_CTRL] = BIT(3), 3451 [EEMNGCTL] = BIT(31), 3452 [FLASHT] = 0x2, 3453 [FLSWCTL] = BIT(30) | BIT(31), 3454 [FLOL] = BIT(0), 3455 [RXDCTL] = BIT(16), 3456 [RXDCTL1] = BIT(16), 3457 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3458 [RXCFGL] = 0x88F7, 3459 [RXUDP] = 0x319, 3460 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3461 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3462 E1000_CTRL_ADVD3WUC, 3463 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3464 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3465 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3466 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3467 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3468 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3469 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3470 [EERD] = E1000_EERW_DONE, 3471 [EEWR] = E1000_EERW_DONE, 3472 [GCR] = E1000_L0S_ADJUST | 3473 E1000_L1_ENTRY_LATENCY_MSB | 3474 E1000_L1_ENTRY_LATENCY_LSB, 3475 [TDFH] = 0x600, 3476 [TDFT] = 0x600, 3477 [TDFHS] = 0x600, 3478 [TDFTS] = 0x600, 3479 [POEMB] = 0x30D, 3480 [PBS] = 0x028, 3481 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3482 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3483 [SWSM] = 1, 3484 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3485 [ITR] = E1000E_MIN_XITR, 3486 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3487 }; 3488 3489 static void e1000e_reset(E1000ECore *core, bool sw) 3490 { 3491 int i; 3492 3493 timer_del(core->autoneg_timer); 3494 3495 e1000e_intrmgr_reset(core); 3496 3497 memset(core->phy, 0, sizeof core->phy); 3498 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3499 3500 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3501 if (sw && (i == PBA || i == PBS || i == FLA)) { 3502 continue; 3503 } 3504 3505 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3506 e1000e_mac_reg_init[i] : 0; 3507 } 3508 3509 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3510 3511 if (qemu_get_queue(core->owner_nic)->link_down) { 3512 e1000e_link_down(core); 3513 } 3514 3515 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3516 3517 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3518 net_tx_pkt_reset(core->tx[i].tx_pkt, 3519 net_tx_pkt_unmap_frag_pci, core->owner); 3520 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3521 core->tx[i].skip_cp = false; 3522 } 3523 } 3524 3525 void 3526 e1000e_core_reset(E1000ECore *core) 3527 { 3528 e1000e_reset(core, false); 3529 } 3530 3531 void e1000e_core_pre_save(E1000ECore *core) 3532 { 3533 int i; 3534 NetClientState *nc = qemu_get_queue(core->owner_nic); 3535 3536 /* 3537 * If link is down and auto-negotiation is supported and ongoing, 3538 * complete auto-negotiation immediately. This allows us to look 3539 * at MII_BMSR_AN_COMP to infer link status on load. 3540 */ 3541 if (nc->link_down && e1000e_have_autoneg(core)) { 3542 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3543 e1000e_update_flowctl_status(core); 3544 } 3545 3546 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3547 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3548 core->tx[i].skip_cp = true; 3549 } 3550 } 3551 } 3552 3553 int 3554 e1000e_core_post_load(E1000ECore *core) 3555 { 3556 NetClientState *nc = qemu_get_queue(core->owner_nic); 3557 3558 /* 3559 * nc.link_down can't be migrated, so infer link_down according 3560 * to link status bit in core.mac[STATUS]. 3561 */ 3562 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3563 3564 return 0; 3565 } 3566