1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000_common.h" 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 55 #define E1000E_MIN_XITR (500) 56 57 #define E1000E_MAX_TX_FRAGS (64) 58 59 union e1000_rx_desc_union { 60 struct e1000_rx_desc legacy; 61 union e1000_rx_desc_extended extended; 62 union e1000_rx_desc_packet_split packet_split; 63 }; 64 65 static ssize_t 66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 67 bool has_vnet); 68 69 static inline void 70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 71 72 static void e1000e_reset(E1000ECore *core, bool sw); 73 74 static inline void 75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 76 { 77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 78 trace_e1000e_wrn_no_ts_support(); 79 } 80 } 81 82 static inline void 83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 84 { 85 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 86 trace_e1000e_wrn_no_snap_support(); 87 } 88 } 89 90 static inline void 91 e1000e_raise_legacy_irq(E1000ECore *core) 92 { 93 trace_e1000e_irq_legacy_notify(true); 94 e1000x_inc_reg_if_not_full(core->mac, IAC); 95 pci_set_irq(core->owner, 1); 96 } 97 98 static inline void 99 e1000e_lower_legacy_irq(E1000ECore *core) 100 { 101 trace_e1000e_irq_legacy_notify(false); 102 pci_set_irq(core->owner, 0); 103 } 104 105 static inline void 106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 107 { 108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 109 timer->delay_resolution_ns; 110 111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 112 113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 114 115 timer->running = true; 116 } 117 118 static void 119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 e1000e_intrmgr_rearm_timer(timer); 123 } 124 } 125 126 static inline void 127 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 128 { 129 if (timer->running) { 130 timer_del(timer->timer); 131 timer->running = false; 132 } 133 } 134 135 static inline void 136 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 137 { 138 trace_e1000e_irq_fire_delayed_interrupts(); 139 e1000e_set_interrupt_cause(core, 0); 140 } 141 142 static void 143 e1000e_intrmgr_on_timer(void *opaque) 144 { 145 E1000IntrDelayTimer *timer = opaque; 146 147 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 148 149 timer->running = false; 150 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 151 } 152 153 static void 154 e1000e_intrmgr_on_throttling_timer(void *opaque) 155 { 156 E1000IntrDelayTimer *timer = opaque; 157 158 timer->running = false; 159 160 if (timer->core->mac[IMS] & timer->core->mac[ICR]) { 161 if (msi_enabled(timer->core->owner)) { 162 trace_e1000e_irq_msi_notify_postponed(); 163 msi_notify(timer->core->owner, 0); 164 } else { 165 trace_e1000e_irq_legacy_notify_postponed(); 166 e1000e_raise_legacy_irq(timer->core); 167 } 168 } 169 } 170 171 static void 172 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 173 { 174 E1000IntrDelayTimer *timer = opaque; 175 int idx = timer - &timer->core->eitr[0]; 176 177 timer->running = false; 178 179 trace_e1000e_irq_msix_notify_postponed_vec(idx); 180 msix_notify(timer->core->owner, idx); 181 } 182 183 static void 184 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 185 { 186 int i; 187 188 core->radv.delay_reg = RADV; 189 core->rdtr.delay_reg = RDTR; 190 core->raid.delay_reg = RAID; 191 core->tadv.delay_reg = TADV; 192 core->tidv.delay_reg = TIDV; 193 194 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 195 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 196 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 197 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 198 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 199 200 core->radv.core = core; 201 core->rdtr.core = core; 202 core->raid.core = core; 203 core->tadv.core = core; 204 core->tidv.core = core; 205 206 core->itr.core = core; 207 core->itr.delay_reg = ITR; 208 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 209 210 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 211 core->eitr[i].core = core; 212 core->eitr[i].delay_reg = EITR + i; 213 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 214 } 215 216 if (!create) { 217 return; 218 } 219 220 core->radv.timer = 221 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 222 core->rdtr.timer = 223 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 224 core->raid.timer = 225 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 226 227 core->tadv.timer = 228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 229 core->tidv.timer = 230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 231 232 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 233 e1000e_intrmgr_on_throttling_timer, 234 &core->itr); 235 236 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 237 core->eitr[i].timer = 238 timer_new_ns(QEMU_CLOCK_VIRTUAL, 239 e1000e_intrmgr_on_msix_throttling_timer, 240 &core->eitr[i]); 241 } 242 } 243 244 static inline void 245 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 246 { 247 e1000e_intrmgr_stop_timer(&core->radv); 248 e1000e_intrmgr_stop_timer(&core->rdtr); 249 e1000e_intrmgr_stop_timer(&core->raid); 250 e1000e_intrmgr_stop_timer(&core->tidv); 251 e1000e_intrmgr_stop_timer(&core->tadv); 252 } 253 254 static bool 255 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 256 { 257 uint32_t delayable_causes; 258 uint32_t rdtr = core->mac[RDTR]; 259 uint32_t radv = core->mac[RADV]; 260 uint32_t raid = core->mac[RAID]; 261 262 if (msix_enabled(core->owner)) { 263 return false; 264 } 265 266 delayable_causes = E1000_ICR_RXQ0 | 267 E1000_ICR_RXQ1 | 268 E1000_ICR_RXT0; 269 270 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 271 delayable_causes |= E1000_ICR_ACK; 272 } 273 274 /* Clean up all causes that may be delayed */ 275 core->delayed_causes |= *causes & delayable_causes; 276 *causes &= ~delayable_causes; 277 278 /* 279 * Check if delayed RX interrupts disabled by client 280 * or if there are causes that cannot be delayed 281 */ 282 if ((rdtr == 0) || (*causes != 0)) { 283 return false; 284 } 285 286 /* 287 * Check if delayed RX ACK interrupts disabled by client 288 * and there is an ACK packet received 289 */ 290 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 291 return false; 292 } 293 294 /* All causes delayed */ 295 e1000e_intrmgr_rearm_timer(&core->rdtr); 296 297 if (!core->radv.running && (radv != 0)) { 298 e1000e_intrmgr_rearm_timer(&core->radv); 299 } 300 301 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 302 e1000e_intrmgr_rearm_timer(&core->raid); 303 } 304 305 return true; 306 } 307 308 static bool 309 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 310 { 311 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 312 E1000_ICR_TXQ1 | 313 E1000_ICR_TXQE | 314 E1000_ICR_TXDW; 315 316 if (msix_enabled(core->owner)) { 317 return false; 318 } 319 320 /* Clean up all causes that may be delayed */ 321 core->delayed_causes |= *causes & delayable_causes; 322 *causes &= ~delayable_causes; 323 324 /* If there are causes that cannot be delayed */ 325 if (*causes != 0) { 326 return false; 327 } 328 329 /* All causes delayed */ 330 e1000e_intrmgr_rearm_timer(&core->tidv); 331 332 if (!core->tadv.running && (core->mac[TADV] != 0)) { 333 e1000e_intrmgr_rearm_timer(&core->tadv); 334 } 335 336 return true; 337 } 338 339 static uint32_t 340 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 341 { 342 uint32_t res; 343 344 if (msix_enabled(core->owner)) { 345 assert(core->delayed_causes == 0); 346 return 0; 347 } 348 349 res = core->delayed_causes; 350 core->delayed_causes = 0; 351 352 e1000e_intrmgr_stop_delay_timers(core); 353 354 return res; 355 } 356 357 static void 358 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 359 { 360 int i; 361 362 if (core->itr.running) { 363 timer_del(core->itr.timer); 364 e1000e_intrmgr_on_throttling_timer(&core->itr); 365 } 366 367 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 368 if (core->eitr[i].running) { 369 timer_del(core->eitr[i].timer); 370 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 371 } 372 } 373 } 374 375 static void 376 e1000e_intrmgr_resume(E1000ECore *core) 377 { 378 int i; 379 380 e1000e_intmgr_timer_resume(&core->radv); 381 e1000e_intmgr_timer_resume(&core->rdtr); 382 e1000e_intmgr_timer_resume(&core->raid); 383 e1000e_intmgr_timer_resume(&core->tidv); 384 e1000e_intmgr_timer_resume(&core->tadv); 385 386 e1000e_intmgr_timer_resume(&core->itr); 387 388 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 389 e1000e_intmgr_timer_resume(&core->eitr[i]); 390 } 391 } 392 393 static void 394 e1000e_intrmgr_reset(E1000ECore *core) 395 { 396 int i; 397 398 core->delayed_causes = 0; 399 400 e1000e_intrmgr_stop_delay_timers(core); 401 402 e1000e_intrmgr_stop_timer(&core->itr); 403 404 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 405 e1000e_intrmgr_stop_timer(&core->eitr[i]); 406 } 407 } 408 409 static void 410 e1000e_intrmgr_pci_unint(E1000ECore *core) 411 { 412 int i; 413 414 timer_free(core->radv.timer); 415 timer_free(core->rdtr.timer); 416 timer_free(core->raid.timer); 417 418 timer_free(core->tadv.timer); 419 timer_free(core->tidv.timer); 420 421 timer_free(core->itr.timer); 422 423 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 424 timer_free(core->eitr[i].timer); 425 } 426 } 427 428 static void 429 e1000e_intrmgr_pci_realize(E1000ECore *core) 430 { 431 e1000e_intrmgr_initialize_all_timers(core, true); 432 } 433 434 static inline bool 435 e1000e_rx_csum_enabled(E1000ECore *core) 436 { 437 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 438 } 439 440 static inline bool 441 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 442 { 443 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 444 } 445 446 static inline bool 447 e1000e_rx_use_ps_descriptor(E1000ECore *core) 448 { 449 return !e1000e_rx_use_legacy_descriptor(core) && 450 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 451 } 452 453 static inline bool 454 e1000e_rss_enabled(E1000ECore *core) 455 { 456 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 457 !e1000e_rx_csum_enabled(core) && 458 !e1000e_rx_use_legacy_descriptor(core); 459 } 460 461 typedef struct E1000E_RSSInfo_st { 462 bool enabled; 463 uint32_t hash; 464 uint32_t queue; 465 uint32_t type; 466 } E1000E_RSSInfo; 467 468 static uint32_t 469 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 470 { 471 bool hasip4, hasip6; 472 EthL4HdrProto l4hdr_proto; 473 474 assert(e1000e_rss_enabled(core)); 475 476 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 477 478 if (hasip4) { 479 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 480 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 481 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 482 483 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 484 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 485 return E1000_MRQ_RSS_TYPE_IPV4TCP; 486 } 487 488 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 489 return E1000_MRQ_RSS_TYPE_IPV4; 490 } 491 } else if (hasip6) { 492 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 493 494 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 495 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 496 497 /* 498 * Following two traces must not be combined because resulting 499 * event will have 11 arguments totally and some trace backends 500 * (at least "ust") have limitation of maximum 10 arguments per 501 * event. Events with more arguments fail to compile for 502 * backends like these. 503 */ 504 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 505 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 506 ip6info->has_ext_hdrs, 507 ip6info->rss_ex_dst_valid, 508 ip6info->rss_ex_src_valid, 509 core->mac[MRQC], 510 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]), 511 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 512 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 513 514 if ((!ex_dis || !ip6info->has_ext_hdrs) && 515 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 516 ip6info->rss_ex_src_valid))) { 517 518 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 519 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) { 520 return E1000_MRQ_RSS_TYPE_IPV6TCPEX; 521 } 522 523 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 524 return E1000_MRQ_RSS_TYPE_IPV6EX; 525 } 526 527 } 528 529 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 530 return E1000_MRQ_RSS_TYPE_IPV6; 531 } 532 533 } 534 535 return E1000_MRQ_RSS_TYPE_NONE; 536 } 537 538 static uint32_t 539 e1000e_rss_calc_hash(E1000ECore *core, 540 struct NetRxPkt *pkt, 541 E1000E_RSSInfo *info) 542 { 543 NetRxPktRssType type; 544 545 assert(e1000e_rss_enabled(core)); 546 547 switch (info->type) { 548 case E1000_MRQ_RSS_TYPE_IPV4: 549 type = NetPktRssIpV4; 550 break; 551 case E1000_MRQ_RSS_TYPE_IPV4TCP: 552 type = NetPktRssIpV4Tcp; 553 break; 554 case E1000_MRQ_RSS_TYPE_IPV6TCPEX: 555 type = NetPktRssIpV6TcpEx; 556 break; 557 case E1000_MRQ_RSS_TYPE_IPV6: 558 type = NetPktRssIpV6; 559 break; 560 case E1000_MRQ_RSS_TYPE_IPV6EX: 561 type = NetPktRssIpV6Ex; 562 break; 563 default: 564 g_assert_not_reached(); 565 } 566 567 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 568 } 569 570 static void 571 e1000e_rss_parse_packet(E1000ECore *core, 572 struct NetRxPkt *pkt, 573 E1000E_RSSInfo *info) 574 { 575 trace_e1000e_rx_rss_started(); 576 577 if (!e1000e_rss_enabled(core)) { 578 info->enabled = false; 579 info->hash = 0; 580 info->queue = 0; 581 info->type = 0; 582 trace_e1000e_rx_rss_disabled(); 583 return; 584 } 585 586 info->enabled = true; 587 588 info->type = e1000e_rss_get_hash_type(core, pkt); 589 590 trace_e1000e_rx_rss_type(info->type); 591 592 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 593 info->hash = 0; 594 info->queue = 0; 595 return; 596 } 597 598 info->hash = e1000e_rss_calc_hash(core, pkt, info); 599 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 600 } 601 602 static bool 603 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 604 { 605 if (tx->props.tse && tx->cptse) { 606 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 607 return false; 608 } 609 610 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 611 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 612 return true; 613 } 614 615 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 616 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 617 return false; 618 } 619 } 620 621 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 622 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 623 } 624 625 return true; 626 } 627 628 static void e1000e_tx_pkt_callback(void *core, 629 const struct iovec *iov, 630 int iovcnt, 631 const struct iovec *virt_iov, 632 int virt_iovcnt) 633 { 634 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 635 } 636 637 static bool 638 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 639 { 640 int target_queue = MIN(core->max_queue_num, queue_index); 641 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 642 643 if (!e1000e_setup_tx_offloads(core, tx)) { 644 return false; 645 } 646 647 net_tx_pkt_dump(tx->tx_pkt); 648 649 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 650 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 651 return net_tx_pkt_send_custom(tx->tx_pkt, false, 652 e1000e_tx_pkt_callback, core); 653 } else { 654 return net_tx_pkt_send(tx->tx_pkt, queue); 655 } 656 } 657 658 static void 659 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 660 { 661 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 662 PTC1023, PTC1522 }; 663 664 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 665 666 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 667 e1000x_inc_reg_if_not_full(core->mac, TPT); 668 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 669 670 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 671 case ETH_PKT_BCAST: 672 e1000x_inc_reg_if_not_full(core->mac, BPTC); 673 break; 674 case ETH_PKT_MCAST: 675 e1000x_inc_reg_if_not_full(core->mac, MPTC); 676 break; 677 case ETH_PKT_UCAST: 678 break; 679 default: 680 g_assert_not_reached(); 681 } 682 683 e1000x_inc_reg_if_not_full(core->mac, GPTC); 684 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 685 } 686 687 static void 688 e1000e_process_tx_desc(E1000ECore *core, 689 struct e1000e_tx *tx, 690 struct e1000_tx_desc *dp, 691 int queue_index) 692 { 693 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 694 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 695 unsigned int split_size = txd_lower & 0xffff; 696 uint64_t addr; 697 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 698 bool eop = txd_lower & E1000_TXD_CMD_EOP; 699 700 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 701 e1000x_read_tx_ctx_descr(xp, &tx->props); 702 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 703 return; 704 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 705 /* data descriptor */ 706 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 707 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 708 e1000e_process_ts_option(core, dp); 709 } else { 710 /* legacy descriptor */ 711 e1000e_process_ts_option(core, dp); 712 tx->cptse = 0; 713 } 714 715 addr = le64_to_cpu(dp->buffer_addr); 716 717 if (!tx->skip_cp) { 718 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, 719 addr, split_size)) { 720 tx->skip_cp = true; 721 } 722 } 723 724 if (eop) { 725 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 726 if (e1000x_vlan_enabled(core->mac) && 727 e1000x_is_vlan_txd(txd_lower)) { 728 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 729 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 730 } 731 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 732 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 733 } 734 } 735 736 tx->skip_cp = false; 737 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 738 739 tx->sum_needed = 0; 740 tx->cptse = 0; 741 } 742 } 743 744 static inline uint32_t 745 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 746 { 747 if (!msix_enabled(core->owner)) { 748 return E1000_ICR_TXDW; 749 } 750 751 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 752 } 753 754 static inline uint32_t 755 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 756 bool min_threshold_hit) 757 { 758 if (!msix_enabled(core->owner)) { 759 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 760 } 761 762 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 763 } 764 765 static uint32_t 766 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 767 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 768 { 769 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 770 771 if (!(txd_lower & E1000_TXD_CMD_RS) && 772 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 773 return 0; 774 } 775 776 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 777 778 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 779 780 dp->upper.data = cpu_to_le32(txd_upper); 781 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 782 &dp->upper, sizeof(dp->upper)); 783 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 784 } 785 786 typedef struct E1000ERingInfo { 787 int dbah; 788 int dbal; 789 int dlen; 790 int dh; 791 int dt; 792 int idx; 793 } E1000ERingInfo; 794 795 static inline bool 796 e1000e_ring_empty(E1000ECore *core, const E1000ERingInfo *r) 797 { 798 return core->mac[r->dh] == core->mac[r->dt] || 799 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 800 } 801 802 static inline uint64_t 803 e1000e_ring_base(E1000ECore *core, const E1000ERingInfo *r) 804 { 805 uint64_t bah = core->mac[r->dbah]; 806 uint64_t bal = core->mac[r->dbal]; 807 808 return (bah << 32) + bal; 809 } 810 811 static inline uint64_t 812 e1000e_ring_head_descr(E1000ECore *core, const E1000ERingInfo *r) 813 { 814 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 815 } 816 817 static inline void 818 e1000e_ring_advance(E1000ECore *core, const E1000ERingInfo *r, uint32_t count) 819 { 820 core->mac[r->dh] += count; 821 822 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 823 core->mac[r->dh] = 0; 824 } 825 } 826 827 static inline uint32_t 828 e1000e_ring_free_descr_num(E1000ECore *core, const E1000ERingInfo *r) 829 { 830 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 831 core->mac[r->dh], core->mac[r->dt]); 832 833 if (core->mac[r->dh] <= core->mac[r->dt]) { 834 return core->mac[r->dt] - core->mac[r->dh]; 835 } 836 837 if (core->mac[r->dh] > core->mac[r->dt]) { 838 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 839 core->mac[r->dt] - core->mac[r->dh]; 840 } 841 842 g_assert_not_reached(); 843 } 844 845 static inline bool 846 e1000e_ring_enabled(E1000ECore *core, const E1000ERingInfo *r) 847 { 848 return core->mac[r->dlen] > 0; 849 } 850 851 static inline uint32_t 852 e1000e_ring_len(E1000ECore *core, const E1000ERingInfo *r) 853 { 854 return core->mac[r->dlen]; 855 } 856 857 typedef struct E1000E_TxRing_st { 858 const E1000ERingInfo *i; 859 struct e1000e_tx *tx; 860 } E1000E_TxRing; 861 862 static inline int 863 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 864 { 865 return (reg_idx - base_reg_idx) / (0x100 >> 2); 866 } 867 868 static inline void 869 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 870 { 871 static const E1000ERingInfo i[E1000E_NUM_QUEUES] = { 872 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 873 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 874 }; 875 876 assert(idx < ARRAY_SIZE(i)); 877 878 txr->i = &i[idx]; 879 txr->tx = &core->tx[idx]; 880 } 881 882 typedef struct E1000E_RxRing_st { 883 const E1000ERingInfo *i; 884 } E1000E_RxRing; 885 886 static inline void 887 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 888 { 889 static const E1000ERingInfo i[E1000E_NUM_QUEUES] = { 890 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 891 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 892 }; 893 894 assert(idx < ARRAY_SIZE(i)); 895 896 rxr->i = &i[idx]; 897 } 898 899 static void 900 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 901 { 902 dma_addr_t base; 903 struct e1000_tx_desc desc; 904 bool ide = false; 905 const E1000ERingInfo *txi = txr->i; 906 uint32_t cause = E1000_ICS_TXQE; 907 908 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 909 trace_e1000e_tx_disabled(); 910 return; 911 } 912 913 while (!e1000e_ring_empty(core, txi)) { 914 base = e1000e_ring_head_descr(core, txi); 915 916 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 917 918 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 919 desc.lower.data, desc.upper.data); 920 921 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 922 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 923 924 e1000e_ring_advance(core, txi, 1); 925 } 926 927 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 928 e1000e_set_interrupt_cause(core, cause); 929 } 930 931 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 932 } 933 934 static bool 935 e1000e_has_rxbufs(E1000ECore *core, const E1000ERingInfo *r, 936 size_t total_size) 937 { 938 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 939 940 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 941 core->rx_desc_buf_size); 942 943 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 944 core->rx_desc_buf_size; 945 } 946 947 void 948 e1000e_start_recv(E1000ECore *core) 949 { 950 int i; 951 952 trace_e1000e_rx_start_recv(); 953 954 for (i = 0; i <= core->max_queue_num; i++) { 955 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 956 } 957 } 958 959 bool 960 e1000e_can_receive(E1000ECore *core) 961 { 962 int i; 963 964 if (!e1000x_rx_ready(core->owner, core->mac)) { 965 return false; 966 } 967 968 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 969 E1000E_RxRing rxr; 970 971 e1000e_rx_ring_init(core, &rxr, i); 972 if (e1000e_ring_enabled(core, rxr.i) && 973 e1000e_has_rxbufs(core, rxr.i, 1)) { 974 trace_e1000e_rx_can_recv(); 975 return true; 976 } 977 } 978 979 trace_e1000e_rx_can_recv_rings_full(); 980 return false; 981 } 982 983 ssize_t 984 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 985 { 986 const struct iovec iov = { 987 .iov_base = (uint8_t *)buf, 988 .iov_len = size 989 }; 990 991 return e1000e_receive_iov(core, &iov, 1); 992 } 993 994 static inline bool 995 e1000e_rx_l3_cso_enabled(E1000ECore *core) 996 { 997 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 998 } 999 1000 static inline bool 1001 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1002 { 1003 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1004 } 1005 1006 static bool 1007 e1000e_receive_filter(E1000ECore *core, const void *buf) 1008 { 1009 return (!e1000x_is_vlan_packet(buf, core->mac[VET]) || 1010 e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(buf))) && 1011 e1000x_rx_group_filter(core->mac, buf); 1012 } 1013 1014 static inline void 1015 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1016 hwaddr *buff_addr) 1017 { 1018 *buff_addr = le64_to_cpu(desc->buffer_addr); 1019 } 1020 1021 static inline void 1022 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1023 hwaddr *buff_addr) 1024 { 1025 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1026 } 1027 1028 static inline void 1029 e1000e_read_ps_rx_descr(E1000ECore *core, 1030 union e1000_rx_desc_packet_split *desc, 1031 hwaddr buff_addr[MAX_PS_BUFFERS]) 1032 { 1033 int i; 1034 1035 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1036 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1037 } 1038 1039 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1040 buff_addr[2], buff_addr[3]); 1041 } 1042 1043 static inline void 1044 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1045 hwaddr buff_addr[MAX_PS_BUFFERS]) 1046 { 1047 if (e1000e_rx_use_legacy_descriptor(core)) { 1048 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1049 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1050 } else { 1051 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1052 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1053 } else { 1054 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1055 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1056 } 1057 } 1058 } 1059 1060 static void 1061 e1000e_verify_csum_in_sw(E1000ECore *core, 1062 struct NetRxPkt *pkt, 1063 uint32_t *status_flags, 1064 EthL4HdrProto l4hdr_proto) 1065 { 1066 bool csum_valid; 1067 uint32_t csum_error; 1068 1069 if (e1000e_rx_l3_cso_enabled(core)) { 1070 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1071 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1072 } else { 1073 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1074 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1075 } 1076 } else { 1077 trace_e1000e_rx_metadata_l3_cso_disabled(); 1078 } 1079 1080 if (!e1000e_rx_l4_cso_enabled(core)) { 1081 trace_e1000e_rx_metadata_l4_cso_disabled(); 1082 return; 1083 } 1084 1085 if (l4hdr_proto != ETH_L4_HDR_PROTO_TCP && 1086 l4hdr_proto != ETH_L4_HDR_PROTO_UDP) { 1087 return; 1088 } 1089 1090 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1091 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1092 return; 1093 } 1094 1095 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1096 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1097 1098 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1099 *status_flags |= E1000_RXD_STAT_UDPCS; 1100 } 1101 } 1102 1103 static inline bool 1104 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1105 { 1106 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1107 return false; 1108 } 1109 1110 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1111 return !net_rx_pkt_has_tcp_data(rx_pkt); 1112 } 1113 1114 return true; 1115 } 1116 1117 static void 1118 e1000e_build_rx_metadata(E1000ECore *core, 1119 struct NetRxPkt *pkt, 1120 bool is_eop, 1121 const E1000E_RSSInfo *rss_info, 1122 uint32_t *rss, uint32_t *mrq, 1123 uint32_t *status_flags, 1124 uint16_t *ip_id, 1125 uint16_t *vlan_tag) 1126 { 1127 struct virtio_net_hdr *vhdr; 1128 bool hasip4, hasip6; 1129 EthL4HdrProto l4hdr_proto; 1130 uint32_t pkt_type; 1131 1132 *status_flags = E1000_RXD_STAT_DD; 1133 1134 /* No additional metadata needed for non-EOP descriptors */ 1135 if (!is_eop) { 1136 goto func_exit; 1137 } 1138 1139 *status_flags |= E1000_RXD_STAT_EOP; 1140 1141 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1142 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1143 1144 /* VLAN state */ 1145 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1146 *status_flags |= E1000_RXD_STAT_VP; 1147 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1148 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1149 } 1150 1151 /* Packet parsing results */ 1152 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1153 if (rss_info->enabled) { 1154 *rss = cpu_to_le32(rss_info->hash); 1155 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1156 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1157 } 1158 } else if (hasip4) { 1159 *status_flags |= E1000_RXD_STAT_IPIDV; 1160 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1161 trace_e1000e_rx_metadata_ip_id(*ip_id); 1162 } 1163 1164 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { 1165 *status_flags |= E1000_RXD_STAT_ACK; 1166 trace_e1000e_rx_metadata_ack(); 1167 } 1168 1169 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1170 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1171 pkt_type = E1000_RXD_PKT_MAC; 1172 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1173 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1174 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1175 } else if (hasip4 || hasip6) { 1176 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1177 } else { 1178 pkt_type = E1000_RXD_PKT_MAC; 1179 } 1180 1181 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1182 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1183 1184 /* RX CSO information */ 1185 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1186 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1187 goto func_exit; 1188 } 1189 1190 vhdr = net_rx_pkt_get_vhdr(pkt); 1191 1192 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1193 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1194 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1195 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1196 goto func_exit; 1197 } 1198 1199 if (e1000e_rx_l3_cso_enabled(core)) { 1200 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1201 } else { 1202 trace_e1000e_rx_metadata_l3_cso_disabled(); 1203 } 1204 1205 if (e1000e_rx_l4_cso_enabled(core)) { 1206 switch (l4hdr_proto) { 1207 case ETH_L4_HDR_PROTO_TCP: 1208 *status_flags |= E1000_RXD_STAT_TCPCS; 1209 break; 1210 1211 case ETH_L4_HDR_PROTO_UDP: 1212 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1213 break; 1214 1215 default: 1216 break; 1217 } 1218 } else { 1219 trace_e1000e_rx_metadata_l4_cso_disabled(); 1220 } 1221 1222 func_exit: 1223 trace_e1000e_rx_metadata_status_flags(*status_flags); 1224 *status_flags = cpu_to_le32(*status_flags); 1225 } 1226 1227 static inline void 1228 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1229 struct NetRxPkt *pkt, 1230 const E1000E_RSSInfo *rss_info, 1231 uint16_t length) 1232 { 1233 uint32_t status_flags, rss, mrq; 1234 uint16_t ip_id; 1235 1236 assert(!rss_info->enabled); 1237 1238 desc->length = cpu_to_le16(length); 1239 desc->csum = 0; 1240 1241 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1242 rss_info, 1243 &rss, &mrq, 1244 &status_flags, &ip_id, 1245 &desc->special); 1246 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1247 desc->status = (uint8_t) le32_to_cpu(status_flags); 1248 } 1249 1250 static inline void 1251 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1252 struct NetRxPkt *pkt, 1253 const E1000E_RSSInfo *rss_info, 1254 uint16_t length) 1255 { 1256 memset(&desc->wb, 0, sizeof(desc->wb)); 1257 1258 desc->wb.upper.length = cpu_to_le16(length); 1259 1260 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1261 rss_info, 1262 &desc->wb.lower.hi_dword.rss, 1263 &desc->wb.lower.mrq, 1264 &desc->wb.upper.status_error, 1265 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1266 &desc->wb.upper.vlan); 1267 } 1268 1269 static inline void 1270 e1000e_write_ps_rx_descr(E1000ECore *core, 1271 union e1000_rx_desc_packet_split *desc, 1272 struct NetRxPkt *pkt, 1273 const E1000E_RSSInfo *rss_info, 1274 size_t ps_hdr_len, 1275 uint16_t(*written)[MAX_PS_BUFFERS]) 1276 { 1277 int i; 1278 1279 memset(&desc->wb, 0, sizeof(desc->wb)); 1280 1281 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1282 1283 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1284 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1285 } 1286 1287 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1288 rss_info, 1289 &desc->wb.lower.hi_dword.rss, 1290 &desc->wb.lower.mrq, 1291 &desc->wb.middle.status_error, 1292 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1293 &desc->wb.middle.vlan); 1294 1295 desc->wb.upper.header_status = 1296 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1297 1298 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1299 (*written)[2], (*written)[3]); 1300 } 1301 1302 static inline void 1303 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1304 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1305 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1306 { 1307 if (e1000e_rx_use_legacy_descriptor(core)) { 1308 assert(ps_hdr_len == 0); 1309 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1310 (*written)[0]); 1311 } else { 1312 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1313 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1314 ps_hdr_len, written); 1315 } else { 1316 assert(ps_hdr_len == 0); 1317 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1318 (*written)[0]); 1319 } 1320 } 1321 } 1322 1323 static inline void 1324 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1325 union e1000_rx_desc_union *desc, dma_addr_t len) 1326 { 1327 PCIDevice *dev = core->owner; 1328 1329 if (e1000e_rx_use_legacy_descriptor(core)) { 1330 struct e1000_rx_desc *d = &desc->legacy; 1331 size_t offset = offsetof(struct e1000_rx_desc, status); 1332 uint8_t status = d->status; 1333 1334 d->status &= ~E1000_RXD_STAT_DD; 1335 pci_dma_write(dev, addr, desc, len); 1336 1337 if (status & E1000_RXD_STAT_DD) { 1338 d->status = status; 1339 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1340 } 1341 } else { 1342 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1343 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1344 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1345 wb.middle.status_error); 1346 uint32_t status = d->wb.middle.status_error; 1347 1348 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1349 pci_dma_write(dev, addr, desc, len); 1350 1351 if (status & E1000_RXD_STAT_DD) { 1352 d->wb.middle.status_error = status; 1353 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1354 } 1355 } else { 1356 union e1000_rx_desc_extended *d = &desc->extended; 1357 size_t offset = offsetof(union e1000_rx_desc_extended, 1358 wb.upper.status_error); 1359 uint32_t status = d->wb.upper.status_error; 1360 1361 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1362 pci_dma_write(dev, addr, desc, len); 1363 1364 if (status & E1000_RXD_STAT_DD) { 1365 d->wb.upper.status_error = status; 1366 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1367 } 1368 } 1369 } 1370 } 1371 1372 typedef struct E1000EBAState { 1373 uint16_t written[MAX_PS_BUFFERS]; 1374 uint8_t cur_idx; 1375 } E1000EBAState; 1376 1377 static inline void 1378 e1000e_write_hdr_frag_to_rx_buffers(E1000ECore *core, 1379 hwaddr ba[MAX_PS_BUFFERS], 1380 E1000EBAState *bastate, 1381 const char *data, 1382 dma_addr_t data_len) 1383 { 1384 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1385 1386 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1387 bastate->written[0] += data_len; 1388 1389 bastate->cur_idx = 1; 1390 } 1391 1392 static void 1393 e1000e_write_payload_frag_to_rx_buffers(E1000ECore *core, 1394 hwaddr ba[MAX_PS_BUFFERS], 1395 E1000EBAState *bastate, 1396 const char *data, 1397 dma_addr_t data_len) 1398 { 1399 while (data_len > 0) { 1400 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1401 uint32_t cur_buf_bytes_left = cur_buf_len - 1402 bastate->written[bastate->cur_idx]; 1403 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1404 1405 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1406 ba[bastate->cur_idx], 1407 bastate->written[bastate->cur_idx], 1408 data, 1409 bytes_to_write); 1410 1411 pci_dma_write(core->owner, 1412 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1413 data, bytes_to_write); 1414 1415 bastate->written[bastate->cur_idx] += bytes_to_write; 1416 data += bytes_to_write; 1417 data_len -= bytes_to_write; 1418 1419 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1420 bastate->cur_idx++; 1421 } 1422 1423 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1424 } 1425 } 1426 1427 static void 1428 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) 1429 { 1430 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1431 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1432 } 1433 1434 static inline bool 1435 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000ERingInfo *rxi) 1436 { 1437 return e1000e_ring_free_descr_num(core, rxi) == 1438 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1439 } 1440 1441 static bool 1442 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1443 { 1444 bool hasip4, hasip6; 1445 EthL4HdrProto l4hdr_proto; 1446 bool fragment; 1447 1448 if (!e1000e_rx_use_ps_descriptor(core)) { 1449 return false; 1450 } 1451 1452 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1453 1454 if (hasip4) { 1455 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1456 } else if (hasip6) { 1457 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1458 } else { 1459 return false; 1460 } 1461 1462 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1463 return false; 1464 } 1465 1466 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1467 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1468 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1469 } else { 1470 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1471 } 1472 1473 if ((*hdr_len > core->rxbuf_sizes[0]) || 1474 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1475 return false; 1476 } 1477 1478 return true; 1479 } 1480 1481 static void 1482 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1483 const E1000E_RxRing *rxr, 1484 const E1000E_RSSInfo *rss_info) 1485 { 1486 PCIDevice *d = core->owner; 1487 dma_addr_t base; 1488 union e1000_rx_desc_union desc; 1489 size_t desc_size; 1490 size_t desc_offset = 0; 1491 size_t iov_ofs = 0; 1492 1493 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1494 size_t size = net_rx_pkt_get_total_len(pkt); 1495 size_t total_size = size + e1000x_fcs_len(core->mac); 1496 const E1000ERingInfo *rxi; 1497 size_t ps_hdr_len = 0; 1498 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1499 bool is_first = true; 1500 1501 rxi = rxr->i; 1502 1503 do { 1504 hwaddr ba[MAX_PS_BUFFERS]; 1505 E1000EBAState bastate = { { 0 } }; 1506 bool is_last = false; 1507 1508 desc_size = total_size - desc_offset; 1509 1510 if (desc_size > core->rx_desc_buf_size) { 1511 desc_size = core->rx_desc_buf_size; 1512 } 1513 1514 if (e1000e_ring_empty(core, rxi)) { 1515 return; 1516 } 1517 1518 base = e1000e_ring_head_descr(core, rxi); 1519 1520 pci_dma_read(d, base, &desc, core->rx_desc_len); 1521 1522 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1523 1524 e1000e_read_rx_descr(core, &desc, ba); 1525 1526 if (ba[0]) { 1527 if (desc_offset < size) { 1528 static const uint32_t fcs_pad; 1529 size_t iov_copy; 1530 size_t copy_size = size - desc_offset; 1531 if (copy_size > core->rx_desc_buf_size) { 1532 copy_size = core->rx_desc_buf_size; 1533 } 1534 1535 /* For PS mode copy the packet header first */ 1536 if (do_ps) { 1537 if (is_first) { 1538 size_t ps_hdr_copied = 0; 1539 do { 1540 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1541 iov->iov_len - iov_ofs); 1542 1543 e1000e_write_hdr_frag_to_rx_buffers(core, ba, 1544 &bastate, 1545 iov->iov_base, 1546 iov_copy); 1547 1548 copy_size -= iov_copy; 1549 ps_hdr_copied += iov_copy; 1550 1551 iov_ofs += iov_copy; 1552 if (iov_ofs == iov->iov_len) { 1553 iov++; 1554 iov_ofs = 0; 1555 } 1556 } while (ps_hdr_copied < ps_hdr_len); 1557 1558 is_first = false; 1559 } else { 1560 /* Leave buffer 0 of each descriptor except first */ 1561 /* empty as per spec 7.1.5.1 */ 1562 e1000e_write_hdr_frag_to_rx_buffers(core, ba, &bastate, 1563 NULL, 0); 1564 } 1565 } 1566 1567 /* Copy packet payload */ 1568 while (copy_size) { 1569 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1570 1571 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, 1572 iov->iov_base + 1573 iov_ofs, 1574 iov_copy); 1575 1576 copy_size -= iov_copy; 1577 iov_ofs += iov_copy; 1578 if (iov_ofs == iov->iov_len) { 1579 iov++; 1580 iov_ofs = 0; 1581 } 1582 } 1583 1584 if (desc_offset + desc_size >= total_size) { 1585 /* Simulate FCS checksum presence in the last descriptor */ 1586 e1000e_write_payload_frag_to_rx_buffers(core, ba, &bastate, 1587 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1588 } 1589 } 1590 } else { /* as per intel docs; skip descriptors with null buf addr */ 1591 trace_e1000e_rx_null_descriptor(); 1592 } 1593 desc_offset += desc_size; 1594 if (desc_offset >= total_size) { 1595 is_last = true; 1596 } 1597 1598 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1599 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1600 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1601 1602 e1000e_ring_advance(core, rxi, 1603 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1604 1605 } while (desc_offset < total_size); 1606 1607 e1000e_update_rx_stats(core, size, total_size); 1608 } 1609 1610 static inline void 1611 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1612 { 1613 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1614 1615 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1616 net_rx_pkt_fix_l4_csum(pkt); 1617 } 1618 } 1619 1620 ssize_t 1621 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1622 { 1623 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1624 } 1625 1626 static ssize_t 1627 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1628 bool has_vnet) 1629 { 1630 uint32_t causes = 0; 1631 uint8_t buf[ETH_ZLEN]; 1632 struct iovec min_iov; 1633 size_t size, orig_size; 1634 size_t iov_ofs = 0; 1635 E1000E_RxRing rxr; 1636 E1000E_RSSInfo rss_info; 1637 size_t total_size; 1638 ssize_t retval; 1639 bool rdmts_hit; 1640 1641 trace_e1000e_rx_receive_iov(iovcnt); 1642 1643 if (!e1000x_hw_rx_enabled(core->mac)) { 1644 return -1; 1645 } 1646 1647 /* Pull virtio header in */ 1648 if (has_vnet) { 1649 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1650 iov_ofs = sizeof(struct virtio_net_hdr); 1651 } else { 1652 net_rx_pkt_unset_vhdr(core->rx_pkt); 1653 } 1654 1655 orig_size = iov_size(iov, iovcnt); 1656 size = orig_size - iov_ofs; 1657 1658 /* Pad to minimum Ethernet frame length */ 1659 if (size < sizeof(buf)) { 1660 iov_to_buf(iov, iovcnt, iov_ofs, buf, size); 1661 memset(&buf[size], 0, sizeof(buf) - size); 1662 e1000x_inc_reg_if_not_full(core->mac, RUC); 1663 min_iov.iov_base = buf; 1664 min_iov.iov_len = size = sizeof(buf); 1665 iovcnt = 1; 1666 iov = &min_iov; 1667 iov_ofs = 0; 1668 } else { 1669 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4); 1670 } 1671 1672 /* Discard oversized packets if !LPE and !SBP. */ 1673 if (e1000x_is_oversized(core->mac, size)) { 1674 return orig_size; 1675 } 1676 1677 net_rx_pkt_set_packet_type(core->rx_pkt, 1678 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1679 1680 if (!e1000e_receive_filter(core, buf)) { 1681 trace_e1000e_rx_flt_dropped(); 1682 return orig_size; 1683 } 1684 1685 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1686 e1000x_vlan_enabled(core->mac) ? 0 : -1, 1687 core->mac[VET], 0); 1688 1689 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1690 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1691 1692 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1693 e1000x_fcs_len(core->mac); 1694 1695 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1696 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1697 1698 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1699 1700 retval = orig_size; 1701 1702 /* Perform small receive detection (RSRPD) */ 1703 if (total_size < core->mac[RSRPD]) { 1704 causes |= E1000_ICS_SRPD; 1705 } 1706 1707 /* Perform ACK receive detection */ 1708 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1709 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1710 causes |= E1000_ICS_ACK; 1711 } 1712 1713 /* Check if receive descriptor minimum threshold hit */ 1714 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1715 causes |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1716 1717 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1718 } else { 1719 causes |= E1000_ICS_RXO; 1720 retval = 0; 1721 1722 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1723 } 1724 1725 if (!e1000e_intrmgr_delay_rx_causes(core, &causes)) { 1726 trace_e1000e_rx_interrupt_set(causes); 1727 e1000e_set_interrupt_cause(core, causes); 1728 } else { 1729 trace_e1000e_rx_interrupt_delayed(causes); 1730 } 1731 1732 return retval; 1733 } 1734 1735 static inline bool 1736 e1000e_have_autoneg(E1000ECore *core) 1737 { 1738 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1739 } 1740 1741 static void e1000e_update_flowctl_status(E1000ECore *core) 1742 { 1743 if (e1000e_have_autoneg(core) && 1744 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1745 trace_e1000e_link_autoneg_flowctl(true); 1746 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1747 } else { 1748 trace_e1000e_link_autoneg_flowctl(false); 1749 } 1750 } 1751 1752 static inline void 1753 e1000e_link_down(E1000ECore *core) 1754 { 1755 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1756 e1000e_update_flowctl_status(core); 1757 } 1758 1759 static inline void 1760 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1761 { 1762 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1763 core->phy[0][MII_BMCR] = val & ~(0x3f | 1764 MII_BMCR_RESET | 1765 MII_BMCR_ANRESTART); 1766 1767 if ((val & MII_BMCR_ANRESTART) && 1768 e1000e_have_autoneg(core)) { 1769 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1770 } 1771 } 1772 1773 static void 1774 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1775 { 1776 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1777 1778 if (val & BIT(10)) { 1779 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1780 } 1781 } 1782 1783 static void 1784 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1785 { 1786 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1787 } 1788 1789 void 1790 e1000e_core_set_link_status(E1000ECore *core) 1791 { 1792 NetClientState *nc = qemu_get_queue(core->owner_nic); 1793 uint32_t old_status = core->mac[STATUS]; 1794 1795 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1796 1797 if (nc->link_down) { 1798 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1799 } else { 1800 if (e1000e_have_autoneg(core) && 1801 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1802 e1000x_restart_autoneg(core->mac, core->phy[0], 1803 core->autoneg_timer); 1804 } else { 1805 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1806 e1000e_start_recv(core); 1807 } 1808 } 1809 1810 if (core->mac[STATUS] != old_status) { 1811 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1812 } 1813 } 1814 1815 static void 1816 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1817 { 1818 trace_e1000e_core_ctrl_write(index, val); 1819 1820 /* RST is self clearing */ 1821 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1822 core->mac[CTRL_DUP] = core->mac[CTRL]; 1823 1824 trace_e1000e_link_set_params( 1825 !!(val & E1000_CTRL_ASDE), 1826 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1827 !!(val & E1000_CTRL_FRCSPD), 1828 !!(val & E1000_CTRL_FRCDPX), 1829 !!(val & E1000_CTRL_RFCE), 1830 !!(val & E1000_CTRL_TFCE)); 1831 1832 if (val & E1000_CTRL_RST) { 1833 trace_e1000e_core_ctrl_sw_reset(); 1834 e1000e_reset(core, true); 1835 } 1836 1837 if (val & E1000_CTRL_PHY_RST) { 1838 trace_e1000e_core_ctrl_phy_reset(); 1839 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1840 } 1841 } 1842 1843 static void 1844 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1845 { 1846 trace_e1000e_rx_set_rfctl(val); 1847 1848 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1849 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1850 } 1851 1852 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1853 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1854 } 1855 1856 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1857 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1858 } 1859 1860 core->mac[RFCTL] = val; 1861 } 1862 1863 static void 1864 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1865 { 1866 int i; 1867 core->rx_desc_buf_size = 0; 1868 1869 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1870 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1871 } 1872 } 1873 1874 static void 1875 e1000e_parse_rxbufsize(E1000ECore *core) 1876 { 1877 uint32_t rctl = core->mac[RCTL]; 1878 1879 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1880 1881 if (rctl & E1000_RCTL_DTYP_MASK) { 1882 uint32_t bsize; 1883 1884 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1885 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1886 1887 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1888 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1889 1890 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1891 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1892 1893 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1894 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1895 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1896 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1897 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1898 } else { 1899 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1900 } 1901 1902 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1903 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1904 1905 e1000e_calc_per_desc_buf_size(core); 1906 } 1907 1908 static void 1909 e1000e_calc_rxdesclen(E1000ECore *core) 1910 { 1911 if (e1000e_rx_use_legacy_descriptor(core)) { 1912 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1913 } else { 1914 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1915 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1916 } else { 1917 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1918 } 1919 } 1920 trace_e1000e_rx_desc_len(core->rx_desc_len); 1921 } 1922 1923 static void 1924 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1925 { 1926 core->mac[RCTL] = val; 1927 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1928 1929 if (val & E1000_RCTL_EN) { 1930 e1000e_parse_rxbufsize(core); 1931 e1000e_calc_rxdesclen(core); 1932 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1933 E1000_RING_DESC_LEN_SHIFT; 1934 1935 e1000e_start_recv(core); 1936 } 1937 } 1938 1939 static 1940 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1941 (E1000ECore *, int, uint16_t) = { 1942 [0] = { 1943 [MII_BMCR] = e1000e_set_phy_ctrl, 1944 [PHY_PAGE] = e1000e_set_phy_page, 1945 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1946 } 1947 }; 1948 1949 static inline bool 1950 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 1951 { 1952 if (timer->running) { 1953 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1954 1955 return true; 1956 } 1957 1958 if (timer->core->mac[timer->delay_reg] != 0) { 1959 e1000e_intrmgr_rearm_timer(timer); 1960 } 1961 1962 return false; 1963 } 1964 1965 static inline bool 1966 e1000e_itr_should_postpone(E1000ECore *core) 1967 { 1968 return e1000e_postpone_interrupt(&core->itr); 1969 } 1970 1971 static inline bool 1972 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 1973 { 1974 return e1000e_postpone_interrupt(&core->eitr[idx]); 1975 } 1976 1977 static void 1978 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 1979 { 1980 uint32_t effective_eiac; 1981 1982 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 1983 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 1984 if (vec < E1000E_MSIX_VEC_NUM) { 1985 if (!e1000e_eitr_should_postpone(core, vec)) { 1986 trace_e1000e_irq_msix_notify_vec(vec); 1987 msix_notify(core->owner, vec); 1988 } 1989 } else { 1990 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 1991 } 1992 } else { 1993 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 1994 } 1995 1996 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 1997 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 1998 core->mac[IAM] &= ~cause; 1999 } 2000 2001 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2002 2003 effective_eiac = core->mac[EIAC] & cause; 2004 2005 core->mac[ICR] &= ~effective_eiac; 2006 2007 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2008 core->mac[IMS] &= ~effective_eiac; 2009 } 2010 } 2011 2012 static void 2013 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2014 { 2015 if (causes & E1000_ICR_RXQ0) { 2016 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2017 E1000_IVAR_RXQ0(core->mac[IVAR])); 2018 } 2019 2020 if (causes & E1000_ICR_RXQ1) { 2021 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2022 E1000_IVAR_RXQ1(core->mac[IVAR])); 2023 } 2024 2025 if (causes & E1000_ICR_TXQ0) { 2026 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2027 E1000_IVAR_TXQ0(core->mac[IVAR])); 2028 } 2029 2030 if (causes & E1000_ICR_TXQ1) { 2031 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2032 E1000_IVAR_TXQ1(core->mac[IVAR])); 2033 } 2034 2035 if (causes & E1000_ICR_OTHER) { 2036 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2037 E1000_IVAR_OTHER(core->mac[IVAR])); 2038 } 2039 } 2040 2041 static void 2042 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2043 { 2044 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2045 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2046 if (vec < E1000E_MSIX_VEC_NUM) { 2047 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2048 msix_clr_pending(core->owner, vec); 2049 } else { 2050 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2051 } 2052 } else { 2053 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2054 } 2055 } 2056 2057 static void 2058 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2059 { 2060 if (causes & E1000_ICR_RXQ0) { 2061 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2062 E1000_IVAR_RXQ0(core->mac[IVAR])); 2063 } 2064 2065 if (causes & E1000_ICR_RXQ1) { 2066 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2067 E1000_IVAR_RXQ1(core->mac[IVAR])); 2068 } 2069 2070 if (causes & E1000_ICR_TXQ0) { 2071 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2072 E1000_IVAR_TXQ0(core->mac[IVAR])); 2073 } 2074 2075 if (causes & E1000_ICR_TXQ1) { 2076 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2077 E1000_IVAR_TXQ1(core->mac[IVAR])); 2078 } 2079 2080 if (causes & E1000_ICR_OTHER) { 2081 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2082 E1000_IVAR_OTHER(core->mac[IVAR])); 2083 } 2084 } 2085 2086 static inline void 2087 e1000e_fix_icr_asserted(E1000ECore *core) 2088 { 2089 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2090 if (core->mac[ICR]) { 2091 core->mac[ICR] |= E1000_ICR_ASSERTED; 2092 } 2093 2094 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2095 } 2096 2097 static void e1000e_raise_interrupts(E1000ECore *core, 2098 size_t index, uint32_t causes) 2099 { 2100 bool is_msix = msix_enabled(core->owner); 2101 uint32_t old_causes = core->mac[IMS] & core->mac[ICR]; 2102 uint32_t raised_causes; 2103 2104 trace_e1000e_irq_set(index << 2, 2105 core->mac[index], core->mac[index] | causes); 2106 2107 core->mac[index] |= causes; 2108 2109 /* Set ICR[OTHER] for MSI-X */ 2110 if (is_msix) { 2111 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2112 core->mac[ICR] |= E1000_ICR_OTHER; 2113 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2114 } 2115 } 2116 2117 e1000e_fix_icr_asserted(core); 2118 2119 /* 2120 * Make sure ICR and ICS registers have the same value. 2121 * The spec says that the ICS register is write-only. However in practice, 2122 * on real hardware ICS is readable, and for reads it has the same value as 2123 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2124 * 2125 * The VxWorks PRO/1000 driver uses this behaviour. 2126 */ 2127 core->mac[ICS] = core->mac[ICR]; 2128 2129 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2130 core->mac[ICR], core->mac[IMS]); 2131 2132 raised_causes = core->mac[IMS] & core->mac[ICR] & ~old_causes; 2133 if (!raised_causes) { 2134 return; 2135 } 2136 2137 if (is_msix) { 2138 e1000e_msix_notify(core, raised_causes & ~E1000_ICR_ASSERTED); 2139 } else if (!e1000e_itr_should_postpone(core)) { 2140 if (msi_enabled(core->owner)) { 2141 trace_e1000e_irq_msi_notify(raised_causes); 2142 msi_notify(core->owner, 0); 2143 } else { 2144 e1000e_raise_legacy_irq(core); 2145 } 2146 } 2147 } 2148 2149 static void e1000e_lower_interrupts(E1000ECore *core, 2150 size_t index, uint32_t causes) 2151 { 2152 trace_e1000e_irq_clear(index << 2, 2153 core->mac[index], core->mac[index] & ~causes); 2154 2155 core->mac[index] &= ~causes; 2156 2157 /* 2158 * Make sure ICR and ICS registers have the same value. 2159 * The spec says that the ICS register is write-only. However in practice, 2160 * on real hardware ICS is readable, and for reads it has the same value as 2161 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2162 * 2163 * The VxWorks PRO/1000 driver uses this behaviour. 2164 */ 2165 core->mac[ICS] = core->mac[ICR]; 2166 2167 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2168 core->mac[ICR], core->mac[IMS]); 2169 2170 if (!(core->mac[IMS] & core->mac[ICR]) && 2171 !msix_enabled(core->owner) && !msi_enabled(core->owner)) { 2172 e1000e_lower_legacy_irq(core); 2173 } 2174 } 2175 2176 static void 2177 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2178 { 2179 val |= e1000e_intmgr_collect_delayed_causes(core); 2180 e1000e_raise_interrupts(core, ICR, val); 2181 } 2182 2183 static inline void 2184 e1000e_autoneg_timer(void *opaque) 2185 { 2186 E1000ECore *core = opaque; 2187 if (!qemu_get_queue(core->owner_nic)->link_down) { 2188 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2189 e1000e_start_recv(core); 2190 2191 e1000e_update_flowctl_status(core); 2192 /* signal link status change to the guest */ 2193 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2194 } 2195 } 2196 2197 static inline uint16_t 2198 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2199 { 2200 uint16_t index = (addr & 0x1ffff) >> 2; 2201 return index + (mac_reg_access[index] & 0xfffe); 2202 } 2203 2204 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2205 [0] = { 2206 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2207 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2208 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2209 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2210 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2211 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2212 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2213 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2214 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2215 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2216 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2217 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2218 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2219 2220 [PHY_COPPER_CTRL1] = PHY_RW, 2221 [PHY_COPPER_STAT1] = PHY_R, 2222 [PHY_COPPER_CTRL3] = PHY_RW, 2223 [PHY_RX_ERR_CNTR] = PHY_R, 2224 [PHY_OEM_BITS] = PHY_RW, 2225 [PHY_BIAS_1] = PHY_RW, 2226 [PHY_BIAS_2] = PHY_RW, 2227 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2228 [PHY_COPPER_STAT2] = PHY_R, 2229 [PHY_COPPER_CTRL2] = PHY_RW 2230 }, 2231 [2] = { 2232 [PHY_MAC_CTRL1] = PHY_RW, 2233 [PHY_MAC_INT_ENABLE] = PHY_RW, 2234 [PHY_MAC_STAT] = PHY_R, 2235 [PHY_MAC_CTRL2] = PHY_RW 2236 }, 2237 [3] = { 2238 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2239 [PHY_LED_03_POL_CTRL] = PHY_RW, 2240 [PHY_LED_TIMER_CTRL] = PHY_RW, 2241 [PHY_LED_45_CTRL] = PHY_RW 2242 }, 2243 [5] = { 2244 [PHY_1000T_SKEW] = PHY_R, 2245 [PHY_1000T_SWAP] = PHY_R 2246 }, 2247 [6] = { 2248 [PHY_CRC_COUNTERS] = PHY_R 2249 } 2250 }; 2251 2252 static bool 2253 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2254 char cap, uint8_t *page) 2255 { 2256 *page = 2257 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2258 : core->phy[0][PHY_PAGE]; 2259 2260 if (*page >= E1000E_PHY_PAGES) { 2261 return false; 2262 } 2263 2264 return e1000e_phy_regcap[*page][addr] & cap; 2265 } 2266 2267 static void 2268 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2269 uint32_t addr, uint16_t data) 2270 { 2271 assert(page < E1000E_PHY_PAGES); 2272 assert(addr < E1000E_PHY_PAGE_SIZE); 2273 2274 if (e1000e_phyreg_writeops[page][addr]) { 2275 e1000e_phyreg_writeops[page][addr](core, addr, data); 2276 } else { 2277 core->phy[page][addr] = data; 2278 } 2279 } 2280 2281 static void 2282 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2283 { 2284 uint32_t data = val & E1000_MDIC_DATA_MASK; 2285 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2286 uint8_t page; 2287 2288 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2289 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2290 } else if (val & E1000_MDIC_OP_READ) { 2291 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2292 trace_e1000e_core_mdic_read_unhandled(page, addr); 2293 val |= E1000_MDIC_ERROR; 2294 } else { 2295 val = (val ^ data) | core->phy[page][addr]; 2296 trace_e1000e_core_mdic_read(page, addr, val); 2297 } 2298 } else if (val & E1000_MDIC_OP_WRITE) { 2299 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2300 trace_e1000e_core_mdic_write_unhandled(page, addr); 2301 val |= E1000_MDIC_ERROR; 2302 } else { 2303 trace_e1000e_core_mdic_write(page, addr, data); 2304 e1000e_phy_reg_write(core, page, addr, data); 2305 } 2306 } 2307 core->mac[MDIC] = val | E1000_MDIC_READY; 2308 2309 if (val & E1000_MDIC_INT_EN) { 2310 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2311 } 2312 } 2313 2314 static void 2315 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2316 { 2317 core->mac[index] = val & 0xffff; 2318 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2319 e1000e_start_recv(core); 2320 } 2321 2322 static void 2323 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2324 { 2325 if ((val & E1000_STATUS_PHYRA) == 0) { 2326 core->mac[index] &= ~E1000_STATUS_PHYRA; 2327 } 2328 } 2329 2330 static void 2331 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2332 { 2333 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2334 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2335 2336 /* Zero self-clearing bits */ 2337 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2338 core->mac[CTRL_EXT] = val; 2339 } 2340 2341 static void 2342 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2343 { 2344 int i; 2345 2346 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2347 2348 if (!msix_enabled(core->owner)) { 2349 return; 2350 } 2351 2352 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2353 if (core->mac[PBACLR] & BIT(i)) { 2354 msix_clr_pending(core->owner, i); 2355 } 2356 } 2357 } 2358 2359 static void 2360 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2361 { 2362 core->mac[FCRTH] = val & 0xFFF8; 2363 } 2364 2365 static void 2366 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2367 { 2368 core->mac[FCRTL] = val & 0x8000FFF8; 2369 } 2370 2371 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2372 static void \ 2373 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2374 { \ 2375 core->mac[index] = val & (BIT(num) - 1); \ 2376 } 2377 2378 E1000E_LOW_BITS_SET_FUNC(4) 2379 E1000E_LOW_BITS_SET_FUNC(6) 2380 E1000E_LOW_BITS_SET_FUNC(11) 2381 E1000E_LOW_BITS_SET_FUNC(12) 2382 E1000E_LOW_BITS_SET_FUNC(13) 2383 E1000E_LOW_BITS_SET_FUNC(16) 2384 2385 static void 2386 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2387 { 2388 core->mac[VET] = val & 0xffff; 2389 trace_e1000e_vlan_vet(core->mac[VET]); 2390 } 2391 2392 static void 2393 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2394 { 2395 core->mac[index] = val & E1000_XDLEN_MASK; 2396 } 2397 2398 static void 2399 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2400 { 2401 core->mac[index] = val & E1000_XDBAL_MASK; 2402 } 2403 2404 static void 2405 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2406 { 2407 E1000E_TxRing txr; 2408 core->mac[index] = val; 2409 2410 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2411 e1000e_tx_ring_init(core, &txr, 0); 2412 e1000e_start_xmit(core, &txr); 2413 } 2414 2415 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2416 e1000e_tx_ring_init(core, &txr, 1); 2417 e1000e_start_xmit(core, &txr); 2418 } 2419 } 2420 2421 static void 2422 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2423 { 2424 E1000E_TxRing txr; 2425 int qidx = e1000e_mq_queue_idx(TDT, index); 2426 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2427 2428 core->mac[index] = val & 0xffff; 2429 2430 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2431 e1000e_tx_ring_init(core, &txr, qidx); 2432 e1000e_start_xmit(core, &txr); 2433 } 2434 } 2435 2436 static void 2437 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2438 { 2439 trace_e1000e_irq_write_ics(val); 2440 e1000e_set_interrupt_cause(core, val); 2441 } 2442 2443 static void 2444 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2445 { 2446 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2447 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2448 trace_e1000e_irq_icr_process_iame(); 2449 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2450 } 2451 2452 /* 2453 * Windows driver expects that the "receive overrun" bit and other 2454 * ones to be cleared when the "Other" bit (#24) is cleared. 2455 */ 2456 if (val & E1000_ICR_OTHER) { 2457 val |= E1000_ICR_OTHER_CAUSES; 2458 } 2459 e1000e_lower_interrupts(core, ICR, val); 2460 } 2461 2462 static void 2463 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2464 { 2465 trace_e1000e_irq_ims_clear_set_imc(val); 2466 e1000e_lower_interrupts(core, IMS, val); 2467 } 2468 2469 static void 2470 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2471 { 2472 static const uint32_t ims_ext_mask = 2473 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2474 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2475 E1000_IMS_OTHER; 2476 2477 static const uint32_t ims_valid_mask = 2478 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2479 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2480 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2481 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2482 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2483 E1000_IMS_OTHER; 2484 2485 uint32_t valid_val = val & ims_valid_mask; 2486 2487 if ((valid_val & ims_ext_mask) && 2488 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2489 msix_enabled(core->owner)) { 2490 e1000e_msix_clear(core, valid_val); 2491 } 2492 2493 if ((valid_val == ims_valid_mask) && 2494 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2495 trace_e1000e_irq_fire_all_timers(val); 2496 e1000e_intrmgr_fire_all_timers(core); 2497 } 2498 2499 e1000e_raise_interrupts(core, IMS, valid_val); 2500 } 2501 2502 static void 2503 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2504 { 2505 e1000e_set_16bit(core, index, val); 2506 2507 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2508 trace_e1000e_irq_rdtr_fpd_running(); 2509 e1000e_intrmgr_fire_delayed_interrupts(core); 2510 } else { 2511 trace_e1000e_irq_rdtr_fpd_not_running(); 2512 } 2513 } 2514 2515 static void 2516 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2517 { 2518 e1000e_set_16bit(core, index, val); 2519 2520 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2521 trace_e1000e_irq_tidv_fpd_running(); 2522 e1000e_intrmgr_fire_delayed_interrupts(core); 2523 } else { 2524 trace_e1000e_irq_tidv_fpd_not_running(); 2525 } 2526 } 2527 2528 static uint32_t 2529 e1000e_mac_readreg(E1000ECore *core, int index) 2530 { 2531 return core->mac[index]; 2532 } 2533 2534 static uint32_t 2535 e1000e_mac_ics_read(E1000ECore *core, int index) 2536 { 2537 trace_e1000e_irq_read_ics(core->mac[ICS]); 2538 return core->mac[ICS]; 2539 } 2540 2541 static uint32_t 2542 e1000e_mac_ims_read(E1000ECore *core, int index) 2543 { 2544 trace_e1000e_irq_read_ims(core->mac[IMS]); 2545 return core->mac[IMS]; 2546 } 2547 2548 static uint32_t 2549 e1000e_mac_swsm_read(E1000ECore *core, int index) 2550 { 2551 uint32_t val = core->mac[SWSM]; 2552 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2553 return val; 2554 } 2555 2556 static uint32_t 2557 e1000e_mac_itr_read(E1000ECore *core, int index) 2558 { 2559 return core->itr_guest_value; 2560 } 2561 2562 static uint32_t 2563 e1000e_mac_eitr_read(E1000ECore *core, int index) 2564 { 2565 return core->eitr_guest_value[index - EITR]; 2566 } 2567 2568 static uint32_t 2569 e1000e_mac_icr_read(E1000ECore *core, int index) 2570 { 2571 uint32_t ret = core->mac[ICR]; 2572 2573 if (core->mac[IMS] == 0) { 2574 trace_e1000e_irq_icr_clear_zero_ims(); 2575 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2576 } 2577 2578 if (!msix_enabled(core->owner)) { 2579 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2580 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2581 } 2582 2583 if (core->mac[ICR] & E1000_ICR_ASSERTED) { 2584 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) { 2585 trace_e1000e_irq_icr_clear_iame(); 2586 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2587 trace_e1000e_irq_icr_process_iame(); 2588 e1000e_lower_interrupts(core, IMS, core->mac[IAM]); 2589 } 2590 2591 /* 2592 * The datasheet does not say what happens when interrupt was asserted 2593 * (ICR.INT_ASSERT=1) and auto mask is *not* active. 2594 * However, section of 13.3.27 the PCIe* GbE Controllers Open Source 2595 * Software Developer’s Manual, which were written for older devices, 2596 * namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI & 2597 * 82573E/82573V/82573L, does say: 2598 * > If IMS = 0b, then the ICR register is always clear-on-read. If IMS 2599 * > is not 0b, but some ICR bit is set where the corresponding IMS bit 2600 * > is not set, then a read does not clear the ICR register. For 2601 * > example, if IMS = 10101010b and ICR = 01010101b, then a read to the 2602 * > ICR register does not clear it. If IMS = 10101010b and 2603 * > ICR = 0101011b, then a read to the ICR register clears it entirely 2604 * > (ICR.INT_ASSERTED = 1b). 2605 * 2606 * Linux does no longer activate auto mask since commit 2607 * 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware 2608 * clears ICR even in such a case so we also should do so. 2609 */ 2610 if (core->mac[ICR] & core->mac[IMS]) { 2611 trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR], 2612 core->mac[IMS]); 2613 e1000e_lower_interrupts(core, ICR, 0xffffffff); 2614 } 2615 } 2616 2617 return ret; 2618 } 2619 2620 static uint32_t 2621 e1000e_mac_read_clr4(E1000ECore *core, int index) 2622 { 2623 uint32_t ret = core->mac[index]; 2624 2625 core->mac[index] = 0; 2626 return ret; 2627 } 2628 2629 static uint32_t 2630 e1000e_mac_read_clr8(E1000ECore *core, int index) 2631 { 2632 uint32_t ret = core->mac[index]; 2633 2634 core->mac[index] = 0; 2635 core->mac[index - 1] = 0; 2636 return ret; 2637 } 2638 2639 static uint32_t 2640 e1000e_get_ctrl(E1000ECore *core, int index) 2641 { 2642 uint32_t val = core->mac[CTRL]; 2643 2644 trace_e1000e_link_read_params( 2645 !!(val & E1000_CTRL_ASDE), 2646 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2647 !!(val & E1000_CTRL_FRCSPD), 2648 !!(val & E1000_CTRL_FRCDPX), 2649 !!(val & E1000_CTRL_RFCE), 2650 !!(val & E1000_CTRL_TFCE)); 2651 2652 return val; 2653 } 2654 2655 static uint32_t 2656 e1000e_get_status(E1000ECore *core, int index) 2657 { 2658 uint32_t res = core->mac[STATUS]; 2659 2660 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2661 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2662 } 2663 2664 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2665 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2666 } else { 2667 res |= E1000_STATUS_FD; 2668 } 2669 2670 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2671 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2672 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2673 case E1000_CTRL_SPD_10: 2674 res |= E1000_STATUS_SPEED_10; 2675 break; 2676 case E1000_CTRL_SPD_100: 2677 res |= E1000_STATUS_SPEED_100; 2678 break; 2679 case E1000_CTRL_SPD_1000: 2680 default: 2681 res |= E1000_STATUS_SPEED_1000; 2682 break; 2683 } 2684 } else { 2685 res |= E1000_STATUS_SPEED_1000; 2686 } 2687 2688 trace_e1000e_link_status( 2689 !!(res & E1000_STATUS_LU), 2690 !!(res & E1000_STATUS_FD), 2691 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2692 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2693 2694 return res; 2695 } 2696 2697 static uint32_t 2698 e1000e_get_tarc(E1000ECore *core, int index) 2699 { 2700 return core->mac[index] & ((BIT(11) - 1) | 2701 BIT(27) | 2702 BIT(28) | 2703 BIT(29) | 2704 BIT(30)); 2705 } 2706 2707 static void 2708 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2709 { 2710 core->mac[index] = val; 2711 } 2712 2713 static void 2714 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2715 { 2716 uint32_t macaddr[2]; 2717 2718 core->mac[index] = val; 2719 2720 macaddr[0] = cpu_to_le32(core->mac[RA]); 2721 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2722 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2723 (uint8_t *) macaddr); 2724 2725 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2726 } 2727 2728 static void 2729 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2730 { 2731 static const uint32_t ro_bits = E1000_EECD_PRES | 2732 E1000_EECD_AUTO_RD | 2733 E1000_EECD_SIZE_EX_MASK; 2734 2735 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2736 } 2737 2738 static void 2739 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2740 { 2741 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2742 uint32_t flags = 0; 2743 uint32_t data = 0; 2744 2745 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2746 data = core->eeprom[addr]; 2747 flags = E1000_EERW_DONE; 2748 } 2749 2750 core->mac[EERD] = flags | 2751 (addr << E1000_EERW_ADDR_SHIFT) | 2752 (data << E1000_EERW_DATA_SHIFT); 2753 } 2754 2755 static void 2756 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2757 { 2758 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2759 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2760 uint32_t flags = 0; 2761 2762 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2763 core->eeprom[addr] = data; 2764 flags = E1000_EERW_DONE; 2765 } 2766 2767 core->mac[EERD] = flags | 2768 (addr << E1000_EERW_ADDR_SHIFT) | 2769 (data << E1000_EERW_DATA_SHIFT); 2770 } 2771 2772 static void 2773 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2774 { 2775 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2776 } 2777 2778 static void 2779 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2780 { 2781 uint32_t interval = val & 0xffff; 2782 2783 trace_e1000e_irq_itr_set(val); 2784 2785 core->itr_guest_value = interval; 2786 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2787 } 2788 2789 static void 2790 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2791 { 2792 uint32_t interval = val & 0xffff; 2793 uint32_t eitr_num = index - EITR; 2794 2795 trace_e1000e_irq_eitr_set(eitr_num, val); 2796 2797 core->eitr_guest_value[eitr_num] = interval; 2798 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2799 } 2800 2801 static void 2802 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2803 { 2804 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2805 2806 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2807 qemu_log_mask(LOG_GUEST_ERROR, 2808 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2809 return; 2810 } 2811 2812 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2813 qemu_log_mask(LOG_GUEST_ERROR, 2814 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2815 return; 2816 } 2817 } 2818 2819 core->mac[PSRCTL] = val; 2820 } 2821 2822 static void 2823 e1000e_update_rx_offloads(E1000ECore *core) 2824 { 2825 int cso_state = e1000e_rx_l4_cso_enabled(core); 2826 2827 trace_e1000e_rx_set_cso(cso_state); 2828 2829 if (core->has_vnet) { 2830 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2831 cso_state, 0, 0, 0, 0, 0, 0); 2832 } 2833 } 2834 2835 static void 2836 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2837 { 2838 core->mac[RXCSUM] = val; 2839 e1000e_update_rx_offloads(core); 2840 } 2841 2842 static void 2843 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2844 { 2845 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2846 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2847 } 2848 2849 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) 2850 { 2851 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2852 return core->mac[SYSTIML]; 2853 } 2854 2855 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) 2856 { 2857 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2858 return core->mac[RXSATRH]; 2859 } 2860 2861 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) 2862 { 2863 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2864 return core->mac[TXSTMPH]; 2865 } 2866 2867 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) 2868 { 2869 e1000x_set_timinca(core->mac, &core->timadj, val); 2870 } 2871 2872 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) 2873 { 2874 core->mac[TIMADJH] = val; 2875 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2876 } 2877 2878 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2879 typedef uint32_t (*readops)(E1000ECore *, int); 2880 static const readops e1000e_macreg_readops[] = { 2881 e1000e_getreg(PBA), 2882 e1000e_getreg(WUFC), 2883 e1000e_getreg(MANC), 2884 e1000e_getreg(TOTL), 2885 e1000e_getreg(RDT0), 2886 e1000e_getreg(RDBAH0), 2887 e1000e_getreg(TDBAL1), 2888 e1000e_getreg(RDLEN0), 2889 e1000e_getreg(RDH1), 2890 e1000e_getreg(LATECOL), 2891 e1000e_getreg(SEQEC), 2892 e1000e_getreg(XONTXC), 2893 e1000e_getreg(AIT), 2894 e1000e_getreg(TDFH), 2895 e1000e_getreg(TDFT), 2896 e1000e_getreg(TDFHS), 2897 e1000e_getreg(TDFTS), 2898 e1000e_getreg(TDFPC), 2899 e1000e_getreg(WUS), 2900 e1000e_getreg(PBS), 2901 e1000e_getreg(RDFH), 2902 e1000e_getreg(RDFT), 2903 e1000e_getreg(RDFHS), 2904 e1000e_getreg(RDFTS), 2905 e1000e_getreg(RDFPC), 2906 e1000e_getreg(GORCL), 2907 e1000e_getreg(MGTPRC), 2908 e1000e_getreg(EERD), 2909 e1000e_getreg(EIAC), 2910 e1000e_getreg(PSRCTL), 2911 e1000e_getreg(MANC2H), 2912 e1000e_getreg(RXCSUM), 2913 e1000e_getreg(GSCL_3), 2914 e1000e_getreg(GSCN_2), 2915 e1000e_getreg(RSRPD), 2916 e1000e_getreg(RDBAL1), 2917 e1000e_getreg(FCAH), 2918 e1000e_getreg(FCRTH), 2919 e1000e_getreg(FLOP), 2920 e1000e_getreg(FLASHT), 2921 e1000e_getreg(RXSTMPH), 2922 e1000e_getreg(TXSTMPL), 2923 e1000e_getreg(TIMADJL), 2924 e1000e_getreg(TXDCTL), 2925 e1000e_getreg(RDH0), 2926 e1000e_getreg(TDT1), 2927 e1000e_getreg(TNCRS), 2928 e1000e_getreg(RJC), 2929 e1000e_getreg(IAM), 2930 e1000e_getreg(GSCL_2), 2931 e1000e_getreg(RDBAH1), 2932 e1000e_getreg(FLSWDATA), 2933 e1000e_getreg(TIPG), 2934 e1000e_getreg(FLMNGCTL), 2935 e1000e_getreg(FLMNGCNT), 2936 e1000e_getreg(TSYNCTXCTL), 2937 e1000e_getreg(EXTCNF_SIZE), 2938 e1000e_getreg(EXTCNF_CTRL), 2939 e1000e_getreg(EEMNGDATA), 2940 e1000e_getreg(CTRL_EXT), 2941 e1000e_getreg(SYSTIMH), 2942 e1000e_getreg(EEMNGCTL), 2943 e1000e_getreg(FLMNGDATA), 2944 e1000e_getreg(TSYNCRXCTL), 2945 e1000e_getreg(TDH), 2946 e1000e_getreg(LEDCTL), 2947 e1000e_getreg(TCTL), 2948 e1000e_getreg(TDBAL), 2949 e1000e_getreg(TDLEN), 2950 e1000e_getreg(TDH1), 2951 e1000e_getreg(RADV), 2952 e1000e_getreg(ECOL), 2953 e1000e_getreg(DC), 2954 e1000e_getreg(RLEC), 2955 e1000e_getreg(XOFFTXC), 2956 e1000e_getreg(RFC), 2957 e1000e_getreg(RNBC), 2958 e1000e_getreg(MGTPTC), 2959 e1000e_getreg(TIMINCA), 2960 e1000e_getreg(RXCFGL), 2961 e1000e_getreg(MFUTP01), 2962 e1000e_getreg(FACTPS), 2963 e1000e_getreg(GSCL_1), 2964 e1000e_getreg(GSCN_0), 2965 e1000e_getreg(GCR2), 2966 e1000e_getreg(RDT1), 2967 e1000e_getreg(PBACLR), 2968 e1000e_getreg(FCTTV), 2969 e1000e_getreg(EEWR), 2970 e1000e_getreg(FLSWCTL), 2971 e1000e_getreg(RXDCTL1), 2972 e1000e_getreg(RXSATRL), 2973 e1000e_getreg(RXUDP), 2974 e1000e_getreg(TORL), 2975 e1000e_getreg(TDLEN1), 2976 e1000e_getreg(MCC), 2977 e1000e_getreg(WUC), 2978 e1000e_getreg(EECD), 2979 e1000e_getreg(MFUTP23), 2980 e1000e_getreg(RAID), 2981 e1000e_getreg(FCRTV), 2982 e1000e_getreg(TXDCTL1), 2983 e1000e_getreg(RCTL), 2984 e1000e_getreg(TDT), 2985 e1000e_getreg(MDIC), 2986 e1000e_getreg(FCRUC), 2987 e1000e_getreg(VET), 2988 e1000e_getreg(RDBAL0), 2989 e1000e_getreg(TDBAH1), 2990 e1000e_getreg(RDTR), 2991 e1000e_getreg(SCC), 2992 e1000e_getreg(COLC), 2993 e1000e_getreg(CEXTERR), 2994 e1000e_getreg(XOFFRXC), 2995 e1000e_getreg(IPAV), 2996 e1000e_getreg(GOTCL), 2997 e1000e_getreg(MGTPDC), 2998 e1000e_getreg(GCR), 2999 e1000e_getreg(IVAR), 3000 e1000e_getreg(POEMB), 3001 e1000e_getreg(MFVAL), 3002 e1000e_getreg(FUNCTAG), 3003 e1000e_getreg(GSCL_4), 3004 e1000e_getreg(GSCN_3), 3005 e1000e_getreg(MRQC), 3006 e1000e_getreg(RDLEN1), 3007 e1000e_getreg(FCT), 3008 e1000e_getreg(FLA), 3009 e1000e_getreg(FLOL), 3010 e1000e_getreg(RXDCTL), 3011 e1000e_getreg(RXSTMPL), 3012 e1000e_getreg(TIMADJH), 3013 e1000e_getreg(FCRTL), 3014 e1000e_getreg(TDBAH), 3015 e1000e_getreg(TADV), 3016 e1000e_getreg(XONRXC), 3017 e1000e_getreg(TSCTFC), 3018 e1000e_getreg(RFCTL), 3019 e1000e_getreg(GSCN_1), 3020 e1000e_getreg(FCAL), 3021 e1000e_getreg(FLSWCNT), 3022 3023 [TOTH] = e1000e_mac_read_clr8, 3024 [GOTCH] = e1000e_mac_read_clr8, 3025 [PRC64] = e1000e_mac_read_clr4, 3026 [PRC255] = e1000e_mac_read_clr4, 3027 [PRC1023] = e1000e_mac_read_clr4, 3028 [PTC64] = e1000e_mac_read_clr4, 3029 [PTC255] = e1000e_mac_read_clr4, 3030 [PTC1023] = e1000e_mac_read_clr4, 3031 [GPRC] = e1000e_mac_read_clr4, 3032 [TPT] = e1000e_mac_read_clr4, 3033 [RUC] = e1000e_mac_read_clr4, 3034 [BPRC] = e1000e_mac_read_clr4, 3035 [MPTC] = e1000e_mac_read_clr4, 3036 [IAC] = e1000e_mac_read_clr4, 3037 [ICR] = e1000e_mac_icr_read, 3038 [STATUS] = e1000e_get_status, 3039 [TARC0] = e1000e_get_tarc, 3040 [ICS] = e1000e_mac_ics_read, 3041 [TORH] = e1000e_mac_read_clr8, 3042 [GORCH] = e1000e_mac_read_clr8, 3043 [PRC127] = e1000e_mac_read_clr4, 3044 [PRC511] = e1000e_mac_read_clr4, 3045 [PRC1522] = e1000e_mac_read_clr4, 3046 [PTC127] = e1000e_mac_read_clr4, 3047 [PTC511] = e1000e_mac_read_clr4, 3048 [PTC1522] = e1000e_mac_read_clr4, 3049 [GPTC] = e1000e_mac_read_clr4, 3050 [TPR] = e1000e_mac_read_clr4, 3051 [ROC] = e1000e_mac_read_clr4, 3052 [MPRC] = e1000e_mac_read_clr4, 3053 [BPTC] = e1000e_mac_read_clr4, 3054 [TSCTC] = e1000e_mac_read_clr4, 3055 [ITR] = e1000e_mac_itr_read, 3056 [CTRL] = e1000e_get_ctrl, 3057 [TARC1] = e1000e_get_tarc, 3058 [SWSM] = e1000e_mac_swsm_read, 3059 [IMS] = e1000e_mac_ims_read, 3060 [SYSTIML] = e1000e_get_systiml, 3061 [RXSATRH] = e1000e_get_rxsatrh, 3062 [TXSTMPH] = e1000e_get_txstmph, 3063 3064 [CRCERRS ... MPC] = e1000e_mac_readreg, 3065 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3066 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3067 [RA ... RA + 31] = e1000e_mac_readreg, 3068 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3069 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3070 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3071 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3072 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3073 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3074 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3075 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3076 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3077 [RETA ... RETA + 31] = e1000e_mac_readreg, 3078 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3079 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3080 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3081 }; 3082 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3083 3084 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3085 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3086 static const writeops e1000e_macreg_writeops[] = { 3087 e1000e_putreg(PBA), 3088 e1000e_putreg(SWSM), 3089 e1000e_putreg(WUFC), 3090 e1000e_putreg(RDBAH1), 3091 e1000e_putreg(TDBAH), 3092 e1000e_putreg(TXDCTL), 3093 e1000e_putreg(RDBAH0), 3094 e1000e_putreg(LEDCTL), 3095 e1000e_putreg(FCAL), 3096 e1000e_putreg(FCRUC), 3097 e1000e_putreg(WUC), 3098 e1000e_putreg(WUS), 3099 e1000e_putreg(IPAV), 3100 e1000e_putreg(TDBAH1), 3101 e1000e_putreg(IAM), 3102 e1000e_putreg(EIAC), 3103 e1000e_putreg(IVAR), 3104 e1000e_putreg(TARC0), 3105 e1000e_putreg(TARC1), 3106 e1000e_putreg(FLSWDATA), 3107 e1000e_putreg(POEMB), 3108 e1000e_putreg(MFUTP01), 3109 e1000e_putreg(MFUTP23), 3110 e1000e_putreg(MANC), 3111 e1000e_putreg(MANC2H), 3112 e1000e_putreg(MFVAL), 3113 e1000e_putreg(EXTCNF_CTRL), 3114 e1000e_putreg(FACTPS), 3115 e1000e_putreg(FUNCTAG), 3116 e1000e_putreg(GSCL_1), 3117 e1000e_putreg(GSCL_2), 3118 e1000e_putreg(GSCL_3), 3119 e1000e_putreg(GSCL_4), 3120 e1000e_putreg(GSCN_0), 3121 e1000e_putreg(GSCN_1), 3122 e1000e_putreg(GSCN_2), 3123 e1000e_putreg(GSCN_3), 3124 e1000e_putreg(GCR2), 3125 e1000e_putreg(MRQC), 3126 e1000e_putreg(FLOP), 3127 e1000e_putreg(FLOL), 3128 e1000e_putreg(FLSWCTL), 3129 e1000e_putreg(FLSWCNT), 3130 e1000e_putreg(FLA), 3131 e1000e_putreg(RXDCTL1), 3132 e1000e_putreg(TXDCTL1), 3133 e1000e_putreg(TIPG), 3134 e1000e_putreg(RXSTMPH), 3135 e1000e_putreg(RXSTMPL), 3136 e1000e_putreg(RXSATRL), 3137 e1000e_putreg(RXSATRH), 3138 e1000e_putreg(TXSTMPL), 3139 e1000e_putreg(TXSTMPH), 3140 e1000e_putreg(SYSTIML), 3141 e1000e_putreg(SYSTIMH), 3142 e1000e_putreg(TIMADJL), 3143 e1000e_putreg(RXUDP), 3144 e1000e_putreg(RXCFGL), 3145 e1000e_putreg(TSYNCRXCTL), 3146 e1000e_putreg(TSYNCTXCTL), 3147 e1000e_putreg(EXTCNF_SIZE), 3148 e1000e_putreg(EEMNGCTL), 3149 e1000e_putreg(RA), 3150 3151 [TDH1] = e1000e_set_16bit, 3152 [TDT1] = e1000e_set_tdt, 3153 [TCTL] = e1000e_set_tctl, 3154 [TDT] = e1000e_set_tdt, 3155 [MDIC] = e1000e_set_mdic, 3156 [ICS] = e1000e_set_ics, 3157 [TDH] = e1000e_set_16bit, 3158 [RDH0] = e1000e_set_16bit, 3159 [RDT0] = e1000e_set_rdt, 3160 [IMC] = e1000e_set_imc, 3161 [IMS] = e1000e_set_ims, 3162 [ICR] = e1000e_set_icr, 3163 [EECD] = e1000e_set_eecd, 3164 [RCTL] = e1000e_set_rx_control, 3165 [CTRL] = e1000e_set_ctrl, 3166 [RDTR] = e1000e_set_rdtr, 3167 [RADV] = e1000e_set_16bit, 3168 [TADV] = e1000e_set_16bit, 3169 [ITR] = e1000e_set_itr, 3170 [EERD] = e1000e_set_eerd, 3171 [AIT] = e1000e_set_16bit, 3172 [TDFH] = e1000e_set_13bit, 3173 [TDFT] = e1000e_set_13bit, 3174 [TDFHS] = e1000e_set_13bit, 3175 [TDFTS] = e1000e_set_13bit, 3176 [TDFPC] = e1000e_set_13bit, 3177 [RDFH] = e1000e_set_13bit, 3178 [RDFHS] = e1000e_set_13bit, 3179 [RDFT] = e1000e_set_13bit, 3180 [RDFTS] = e1000e_set_13bit, 3181 [RDFPC] = e1000e_set_13bit, 3182 [PBS] = e1000e_set_6bit, 3183 [GCR] = e1000e_set_gcr, 3184 [PSRCTL] = e1000e_set_psrctl, 3185 [RXCSUM] = e1000e_set_rxcsum, 3186 [RAID] = e1000e_set_16bit, 3187 [RSRPD] = e1000e_set_12bit, 3188 [TIDV] = e1000e_set_tidv, 3189 [TDLEN1] = e1000e_set_dlen, 3190 [TDLEN] = e1000e_set_dlen, 3191 [RDLEN0] = e1000e_set_dlen, 3192 [RDLEN1] = e1000e_set_dlen, 3193 [TDBAL] = e1000e_set_dbal, 3194 [TDBAL1] = e1000e_set_dbal, 3195 [RDBAL0] = e1000e_set_dbal, 3196 [RDBAL1] = e1000e_set_dbal, 3197 [RDH1] = e1000e_set_16bit, 3198 [RDT1] = e1000e_set_rdt, 3199 [STATUS] = e1000e_set_status, 3200 [PBACLR] = e1000e_set_pbaclr, 3201 [CTRL_EXT] = e1000e_set_ctrlext, 3202 [FCAH] = e1000e_set_16bit, 3203 [FCT] = e1000e_set_16bit, 3204 [FCTTV] = e1000e_set_16bit, 3205 [FCRTV] = e1000e_set_16bit, 3206 [FCRTH] = e1000e_set_fcrth, 3207 [FCRTL] = e1000e_set_fcrtl, 3208 [VET] = e1000e_set_vet, 3209 [RXDCTL] = e1000e_set_rxdctl, 3210 [FLASHT] = e1000e_set_16bit, 3211 [EEWR] = e1000e_set_eewr, 3212 [CTRL_DUP] = e1000e_set_ctrl, 3213 [RFCTL] = e1000e_set_rfctl, 3214 [RA + 1] = e1000e_mac_setmacaddr, 3215 [TIMINCA] = e1000e_set_timinca, 3216 [TIMADJH] = e1000e_set_timadjh, 3217 3218 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3219 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3220 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3221 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3222 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3223 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3224 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3225 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3226 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3227 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3228 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3229 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3230 [RETA ... RETA + 31] = e1000e_mac_writereg, 3231 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3232 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3233 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3234 }; 3235 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3236 3237 enum { MAC_ACCESS_PARTIAL = 1 }; 3238 3239 /* 3240 * The array below combines alias offsets of the index values for the 3241 * MAC registers that have aliases, with the indication of not fully 3242 * implemented registers (lowest bit). This combination is possible 3243 * because all of the offsets are even. 3244 */ 3245 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3246 /* Alias index offsets */ 3247 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3248 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3249 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3250 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3251 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3252 [RA_A ... RA_A + 31] = 0x14f0, 3253 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3254 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3255 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3256 /* Access options */ 3257 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3258 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3259 [RDFPC] = MAC_ACCESS_PARTIAL, 3260 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3261 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3262 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3263 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3264 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3265 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3266 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3267 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3268 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3269 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3270 }; 3271 3272 void 3273 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3274 { 3275 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3276 3277 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3278 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3279 trace_e1000e_wrn_regs_write_trivial(index << 2); 3280 } 3281 trace_e1000e_core_write(index << 2, size, val); 3282 e1000e_macreg_writeops[index](core, index, val); 3283 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3284 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3285 } else { 3286 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3287 } 3288 } 3289 3290 uint64_t 3291 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3292 { 3293 uint64_t val; 3294 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3295 3296 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3297 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3298 trace_e1000e_wrn_regs_read_trivial(index << 2); 3299 } 3300 val = e1000e_macreg_readops[index](core, index); 3301 trace_e1000e_core_read(index << 2, size, val); 3302 return val; 3303 } else { 3304 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3305 } 3306 return 0; 3307 } 3308 3309 static void 3310 e1000e_autoneg_resume(E1000ECore *core) 3311 { 3312 if (e1000e_have_autoneg(core) && 3313 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3314 qemu_get_queue(core->owner_nic)->link_down = false; 3315 timer_mod(core->autoneg_timer, 3316 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3317 } 3318 } 3319 3320 void 3321 e1000e_core_pci_realize(E1000ECore *core, 3322 const uint16_t *eeprom_templ, 3323 uint32_t eeprom_size, 3324 const uint8_t *macaddr) 3325 { 3326 int i; 3327 3328 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3329 e1000e_autoneg_timer, core); 3330 e1000e_intrmgr_pci_realize(core); 3331 3332 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3333 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3334 } 3335 3336 net_rx_pkt_init(&core->rx_pkt); 3337 3338 e1000x_core_prepare_eeprom(core->eeprom, 3339 eeprom_templ, 3340 eeprom_size, 3341 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3342 macaddr); 3343 e1000e_update_rx_offloads(core); 3344 } 3345 3346 void 3347 e1000e_core_pci_uninit(E1000ECore *core) 3348 { 3349 int i; 3350 3351 timer_free(core->autoneg_timer); 3352 3353 e1000e_intrmgr_pci_unint(core); 3354 3355 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3356 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3357 } 3358 3359 net_rx_pkt_uninit(core->rx_pkt); 3360 } 3361 3362 static const uint16_t 3363 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3364 [0] = { 3365 [MII_BMCR] = MII_BMCR_SPEED1000 | 3366 MII_BMCR_FD | 3367 MII_BMCR_AUTOEN, 3368 3369 [MII_BMSR] = MII_BMSR_EXTCAP | 3370 MII_BMSR_LINK_ST | 3371 MII_BMSR_AUTONEG | 3372 MII_BMSR_MFPS | 3373 MII_BMSR_EXTSTAT | 3374 MII_BMSR_10T_HD | 3375 MII_BMSR_10T_FD | 3376 MII_BMSR_100TX_HD | 3377 MII_BMSR_100TX_FD, 3378 3379 [MII_PHYID1] = 0x141, 3380 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3381 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3382 MII_ANAR_10FD | MII_ANAR_TX | 3383 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3384 MII_ANAR_PAUSE_ASYM, 3385 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3386 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3387 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3388 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3389 [MII_ANNP] = 1 | MII_ANNP_MP, 3390 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3391 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3392 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3393 MII_STAT1000_ROK | MII_STAT1000_LOK, 3394 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3395 3396 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3397 BIT(12) | BIT(13), 3398 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3399 }, 3400 [2] = { 3401 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3402 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3403 }, 3404 [3] = { 3405 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3406 } 3407 }; 3408 3409 static const uint32_t e1000e_mac_reg_init[] = { 3410 [PBA] = 0x00140014, 3411 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3412 [EXTCNF_CTRL] = BIT(3), 3413 [EEMNGCTL] = BIT(31), 3414 [FLASHT] = 0x2, 3415 [FLSWCTL] = BIT(30) | BIT(31), 3416 [FLOL] = BIT(0), 3417 [RXDCTL] = BIT(16), 3418 [RXDCTL1] = BIT(16), 3419 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3420 [RXCFGL] = 0x88F7, 3421 [RXUDP] = 0x319, 3422 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3423 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3424 E1000_CTRL_ADVD3WUC, 3425 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3426 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3427 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3428 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3429 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3430 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3431 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3432 [EERD] = E1000_EERW_DONE, 3433 [EEWR] = E1000_EERW_DONE, 3434 [GCR] = E1000_L0S_ADJUST | 3435 E1000_L1_ENTRY_LATENCY_MSB | 3436 E1000_L1_ENTRY_LATENCY_LSB, 3437 [TDFH] = 0x600, 3438 [TDFT] = 0x600, 3439 [TDFHS] = 0x600, 3440 [TDFTS] = 0x600, 3441 [POEMB] = 0x30D, 3442 [PBS] = 0x028, 3443 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3444 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3445 [SWSM] = 1, 3446 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3447 [ITR] = E1000E_MIN_XITR, 3448 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3449 }; 3450 3451 static void e1000e_reset(E1000ECore *core, bool sw) 3452 { 3453 int i; 3454 3455 timer_del(core->autoneg_timer); 3456 3457 e1000e_intrmgr_reset(core); 3458 3459 memset(core->phy, 0, sizeof core->phy); 3460 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3461 3462 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3463 if (sw && (i == PBA || i == PBS || i == FLA)) { 3464 continue; 3465 } 3466 3467 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3468 e1000e_mac_reg_init[i] : 0; 3469 } 3470 3471 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3472 3473 if (qemu_get_queue(core->owner_nic)->link_down) { 3474 e1000e_link_down(core); 3475 } 3476 3477 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3478 3479 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3480 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3481 core->tx[i].skip_cp = false; 3482 } 3483 } 3484 3485 void 3486 e1000e_core_reset(E1000ECore *core) 3487 { 3488 e1000e_reset(core, false); 3489 } 3490 3491 void e1000e_core_pre_save(E1000ECore *core) 3492 { 3493 int i; 3494 NetClientState *nc = qemu_get_queue(core->owner_nic); 3495 3496 /* 3497 * If link is down and auto-negotiation is supported and ongoing, 3498 * complete auto-negotiation immediately. This allows us to look 3499 * at MII_BMSR_AN_COMP to infer link status on load. 3500 */ 3501 if (nc->link_down && e1000e_have_autoneg(core)) { 3502 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3503 e1000e_update_flowctl_status(core); 3504 } 3505 3506 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3507 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3508 core->tx[i].skip_cp = true; 3509 } 3510 } 3511 } 3512 3513 int 3514 e1000e_core_post_load(E1000ECore *core) 3515 { 3516 NetClientState *nc = qemu_get_queue(core->owner_nic); 3517 3518 /* 3519 * nc.link_down can't be migrated, so infer link_down according 3520 * to link status bit in core.mac[STATUS]. 3521 */ 3522 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3523 3524 /* 3525 * we need to restart intrmgr timers, as an older version of 3526 * QEMU can have stopped them before migration 3527 */ 3528 e1000e_intrmgr_resume(core); 3529 e1000e_autoneg_resume(core); 3530 3531 return 0; 3532 } 3533