1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/log.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/net/mii.h" 41 #include "hw/pci/msi.h" 42 #include "hw/pci/msix.h" 43 #include "sysemu/runstate.h" 44 45 #include "net_tx_pkt.h" 46 #include "net_rx_pkt.h" 47 48 #include "e1000_common.h" 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */ 55 #define E1000E_MIN_XITR (500) 56 57 #define E1000E_MAX_TX_FRAGS (64) 58 59 union e1000_rx_desc_union { 60 struct e1000_rx_desc legacy; 61 union e1000_rx_desc_extended extended; 62 union e1000_rx_desc_packet_split packet_split; 63 }; 64 65 static ssize_t 66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 67 bool has_vnet); 68 69 static inline void 70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 71 72 static void e1000e_reset(E1000ECore *core, bool sw); 73 74 static inline void 75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 76 { 77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 78 trace_e1000e_wrn_no_ts_support(); 79 } 80 } 81 82 static inline void 83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 84 { 85 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 86 trace_e1000e_wrn_no_snap_support(); 87 } 88 } 89 90 static inline void 91 e1000e_raise_legacy_irq(E1000ECore *core) 92 { 93 trace_e1000e_irq_legacy_notify(true); 94 e1000x_inc_reg_if_not_full(core->mac, IAC); 95 pci_set_irq(core->owner, 1); 96 } 97 98 static inline void 99 e1000e_lower_legacy_irq(E1000ECore *core) 100 { 101 trace_e1000e_irq_legacy_notify(false); 102 pci_set_irq(core->owner, 0); 103 } 104 105 static inline void 106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 107 { 108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 109 timer->delay_resolution_ns; 110 111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 112 113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 114 115 timer->running = true; 116 } 117 118 static void 119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 e1000e_intrmgr_rearm_timer(timer); 123 } 124 } 125 126 static void 127 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 128 { 129 if (timer->running) { 130 timer_del(timer->timer); 131 } 132 } 133 134 static inline void 135 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 136 { 137 if (timer->running) { 138 timer_del(timer->timer); 139 timer->running = false; 140 } 141 } 142 143 static inline void 144 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 145 { 146 trace_e1000e_irq_fire_delayed_interrupts(); 147 e1000e_set_interrupt_cause(core, 0); 148 } 149 150 static void 151 e1000e_intrmgr_on_timer(void *opaque) 152 { 153 E1000IntrDelayTimer *timer = opaque; 154 155 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 156 157 timer->running = false; 158 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 159 } 160 161 static void 162 e1000e_intrmgr_on_throttling_timer(void *opaque) 163 { 164 E1000IntrDelayTimer *timer = opaque; 165 166 timer->running = false; 167 168 if (msi_enabled(timer->core->owner)) { 169 trace_e1000e_irq_msi_notify_postponed(); 170 /* Clear msi_causes_pending to fire MSI eventually */ 171 timer->core->msi_causes_pending = 0; 172 e1000e_set_interrupt_cause(timer->core, 0); 173 } else { 174 trace_e1000e_irq_legacy_notify_postponed(); 175 e1000e_set_interrupt_cause(timer->core, 0); 176 } 177 } 178 179 static void 180 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 181 { 182 E1000IntrDelayTimer *timer = opaque; 183 int idx = timer - &timer->core->eitr[0]; 184 185 timer->running = false; 186 187 trace_e1000e_irq_msix_notify_postponed_vec(idx); 188 msix_notify(timer->core->owner, idx); 189 } 190 191 static void 192 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 193 { 194 int i; 195 196 core->radv.delay_reg = RADV; 197 core->rdtr.delay_reg = RDTR; 198 core->raid.delay_reg = RAID; 199 core->tadv.delay_reg = TADV; 200 core->tidv.delay_reg = TIDV; 201 202 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 204 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 205 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 206 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 207 208 core->radv.core = core; 209 core->rdtr.core = core; 210 core->raid.core = core; 211 core->tadv.core = core; 212 core->tidv.core = core; 213 214 core->itr.core = core; 215 core->itr.delay_reg = ITR; 216 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 217 218 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 219 core->eitr[i].core = core; 220 core->eitr[i].delay_reg = EITR + i; 221 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 222 } 223 224 if (!create) { 225 return; 226 } 227 228 core->radv.timer = 229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 230 core->rdtr.timer = 231 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 232 core->raid.timer = 233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 234 235 core->tadv.timer = 236 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 237 core->tidv.timer = 238 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 239 240 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 241 e1000e_intrmgr_on_throttling_timer, 242 &core->itr); 243 244 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 245 core->eitr[i].timer = 246 timer_new_ns(QEMU_CLOCK_VIRTUAL, 247 e1000e_intrmgr_on_msix_throttling_timer, 248 &core->eitr[i]); 249 } 250 } 251 252 static inline void 253 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 254 { 255 e1000e_intrmgr_stop_timer(&core->radv); 256 e1000e_intrmgr_stop_timer(&core->rdtr); 257 e1000e_intrmgr_stop_timer(&core->raid); 258 e1000e_intrmgr_stop_timer(&core->tidv); 259 e1000e_intrmgr_stop_timer(&core->tadv); 260 } 261 262 static bool 263 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 264 { 265 uint32_t delayable_causes; 266 uint32_t rdtr = core->mac[RDTR]; 267 uint32_t radv = core->mac[RADV]; 268 uint32_t raid = core->mac[RAID]; 269 270 if (msix_enabled(core->owner)) { 271 return false; 272 } 273 274 delayable_causes = E1000_ICR_RXQ0 | 275 E1000_ICR_RXQ1 | 276 E1000_ICR_RXT0; 277 278 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 279 delayable_causes |= E1000_ICR_ACK; 280 } 281 282 /* Clean up all causes that may be delayed */ 283 core->delayed_causes |= *causes & delayable_causes; 284 *causes &= ~delayable_causes; 285 286 /* 287 * Check if delayed RX interrupts disabled by client 288 * or if there are causes that cannot be delayed 289 */ 290 if ((rdtr == 0) || (*causes != 0)) { 291 return false; 292 } 293 294 /* 295 * Check if delayed RX ACK interrupts disabled by client 296 * and there is an ACK packet received 297 */ 298 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 299 return false; 300 } 301 302 /* All causes delayed */ 303 e1000e_intrmgr_rearm_timer(&core->rdtr); 304 305 if (!core->radv.running && (radv != 0)) { 306 e1000e_intrmgr_rearm_timer(&core->radv); 307 } 308 309 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 310 e1000e_intrmgr_rearm_timer(&core->raid); 311 } 312 313 return true; 314 } 315 316 static bool 317 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 318 { 319 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 320 E1000_ICR_TXQ1 | 321 E1000_ICR_TXQE | 322 E1000_ICR_TXDW; 323 324 if (msix_enabled(core->owner)) { 325 return false; 326 } 327 328 /* Clean up all causes that may be delayed */ 329 core->delayed_causes |= *causes & delayable_causes; 330 *causes &= ~delayable_causes; 331 332 /* If there are causes that cannot be delayed */ 333 if (*causes != 0) { 334 return false; 335 } 336 337 /* All causes delayed */ 338 e1000e_intrmgr_rearm_timer(&core->tidv); 339 340 if (!core->tadv.running && (core->mac[TADV] != 0)) { 341 e1000e_intrmgr_rearm_timer(&core->tadv); 342 } 343 344 return true; 345 } 346 347 static uint32_t 348 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 349 { 350 uint32_t res; 351 352 if (msix_enabled(core->owner)) { 353 assert(core->delayed_causes == 0); 354 return 0; 355 } 356 357 res = core->delayed_causes; 358 core->delayed_causes = 0; 359 360 e1000e_intrmgr_stop_delay_timers(core); 361 362 return res; 363 } 364 365 static void 366 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 367 { 368 int i; 369 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 370 371 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 372 core->mac[ICR] |= val; 373 374 if (core->itr.running) { 375 timer_del(core->itr.timer); 376 e1000e_intrmgr_on_throttling_timer(&core->itr); 377 } 378 379 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 380 if (core->eitr[i].running) { 381 timer_del(core->eitr[i].timer); 382 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 383 } 384 } 385 } 386 387 static void 388 e1000e_intrmgr_resume(E1000ECore *core) 389 { 390 int i; 391 392 e1000e_intmgr_timer_resume(&core->radv); 393 e1000e_intmgr_timer_resume(&core->rdtr); 394 e1000e_intmgr_timer_resume(&core->raid); 395 e1000e_intmgr_timer_resume(&core->tidv); 396 e1000e_intmgr_timer_resume(&core->tadv); 397 398 e1000e_intmgr_timer_resume(&core->itr); 399 400 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 401 e1000e_intmgr_timer_resume(&core->eitr[i]); 402 } 403 } 404 405 static void 406 e1000e_intrmgr_pause(E1000ECore *core) 407 { 408 int i; 409 410 e1000e_intmgr_timer_pause(&core->radv); 411 e1000e_intmgr_timer_pause(&core->rdtr); 412 e1000e_intmgr_timer_pause(&core->raid); 413 e1000e_intmgr_timer_pause(&core->tidv); 414 e1000e_intmgr_timer_pause(&core->tadv); 415 416 e1000e_intmgr_timer_pause(&core->itr); 417 418 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 419 e1000e_intmgr_timer_pause(&core->eitr[i]); 420 } 421 } 422 423 static void 424 e1000e_intrmgr_reset(E1000ECore *core) 425 { 426 int i; 427 428 core->delayed_causes = 0; 429 430 e1000e_intrmgr_stop_delay_timers(core); 431 432 e1000e_intrmgr_stop_timer(&core->itr); 433 434 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 435 e1000e_intrmgr_stop_timer(&core->eitr[i]); 436 } 437 } 438 439 static void 440 e1000e_intrmgr_pci_unint(E1000ECore *core) 441 { 442 int i; 443 444 timer_free(core->radv.timer); 445 timer_free(core->rdtr.timer); 446 timer_free(core->raid.timer); 447 448 timer_free(core->tadv.timer); 449 timer_free(core->tidv.timer); 450 451 timer_free(core->itr.timer); 452 453 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 454 timer_free(core->eitr[i].timer); 455 } 456 } 457 458 static void 459 e1000e_intrmgr_pci_realize(E1000ECore *core) 460 { 461 e1000e_intrmgr_initialize_all_timers(core, true); 462 } 463 464 static inline bool 465 e1000e_rx_csum_enabled(E1000ECore *core) 466 { 467 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 468 } 469 470 static inline bool 471 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 472 { 473 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 474 } 475 476 static inline bool 477 e1000e_rx_use_ps_descriptor(E1000ECore *core) 478 { 479 return !e1000e_rx_use_legacy_descriptor(core) && 480 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 481 } 482 483 static inline bool 484 e1000e_rss_enabled(E1000ECore *core) 485 { 486 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 487 !e1000e_rx_csum_enabled(core) && 488 !e1000e_rx_use_legacy_descriptor(core); 489 } 490 491 typedef struct E1000E_RSSInfo_st { 492 bool enabled; 493 uint32_t hash; 494 uint32_t queue; 495 uint32_t type; 496 } E1000E_RSSInfo; 497 498 static uint32_t 499 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 500 { 501 bool hasip4, hasip6; 502 EthL4HdrProto l4hdr_proto; 503 504 assert(e1000e_rss_enabled(core)); 505 506 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 507 508 if (hasip4) { 509 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC], 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 511 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 512 513 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 514 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 515 return E1000_MRQ_RSS_TYPE_IPV4TCP; 516 } 517 518 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 519 return E1000_MRQ_RSS_TYPE_IPV4; 520 } 521 } else if (hasip6) { 522 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 523 524 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 525 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 526 527 /* 528 * Following two traces must not be combined because resulting 529 * event will have 11 arguments totally and some trace backends 530 * (at least "ust") have limitation of maximum 10 arguments per 531 * event. Events with more arguments fail to compile for 532 * backends like these. 533 */ 534 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]); 535 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto, 536 ip6info->has_ext_hdrs, 537 ip6info->rss_ex_dst_valid, 538 ip6info->rss_ex_src_valid, 539 core->mac[MRQC], 540 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 541 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 542 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 543 544 if ((!ex_dis || !ip6info->has_ext_hdrs) && 545 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 546 ip6info->rss_ex_src_valid))) { 547 548 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && 549 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 550 return E1000_MRQ_RSS_TYPE_IPV6TCP; 551 } 552 553 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 554 return E1000_MRQ_RSS_TYPE_IPV6EX; 555 } 556 557 } 558 559 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 560 return E1000_MRQ_RSS_TYPE_IPV6; 561 } 562 563 } 564 565 return E1000_MRQ_RSS_TYPE_NONE; 566 } 567 568 static uint32_t 569 e1000e_rss_calc_hash(E1000ECore *core, 570 struct NetRxPkt *pkt, 571 E1000E_RSSInfo *info) 572 { 573 NetRxPktRssType type; 574 575 assert(e1000e_rss_enabled(core)); 576 577 switch (info->type) { 578 case E1000_MRQ_RSS_TYPE_IPV4: 579 type = NetPktRssIpV4; 580 break; 581 case E1000_MRQ_RSS_TYPE_IPV4TCP: 582 type = NetPktRssIpV4Tcp; 583 break; 584 case E1000_MRQ_RSS_TYPE_IPV6TCP: 585 type = NetPktRssIpV6TcpEx; 586 break; 587 case E1000_MRQ_RSS_TYPE_IPV6: 588 type = NetPktRssIpV6; 589 break; 590 case E1000_MRQ_RSS_TYPE_IPV6EX: 591 type = NetPktRssIpV6Ex; 592 break; 593 default: 594 assert(false); 595 return 0; 596 } 597 598 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 599 } 600 601 static void 602 e1000e_rss_parse_packet(E1000ECore *core, 603 struct NetRxPkt *pkt, 604 E1000E_RSSInfo *info) 605 { 606 trace_e1000e_rx_rss_started(); 607 608 if (!e1000e_rss_enabled(core)) { 609 info->enabled = false; 610 info->hash = 0; 611 info->queue = 0; 612 info->type = 0; 613 trace_e1000e_rx_rss_disabled(); 614 return; 615 } 616 617 info->enabled = true; 618 619 info->type = e1000e_rss_get_hash_type(core, pkt); 620 621 trace_e1000e_rx_rss_type(info->type); 622 623 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 624 info->hash = 0; 625 info->queue = 0; 626 return; 627 } 628 629 info->hash = e1000e_rss_calc_hash(core, pkt, info); 630 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 631 } 632 633 static bool 634 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 635 { 636 if (tx->props.tse && tx->cptse) { 637 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) { 638 return false; 639 } 640 641 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 642 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 643 return true; 644 } 645 646 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) { 647 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) { 648 return false; 649 } 650 } 651 652 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) { 653 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 654 } 655 656 return true; 657 } 658 659 static void e1000e_tx_pkt_callback(void *core, 660 const struct iovec *iov, 661 int iovcnt, 662 const struct iovec *virt_iov, 663 int virt_iovcnt) 664 { 665 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true); 666 } 667 668 static bool 669 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 670 { 671 int target_queue = MIN(core->max_queue_num, queue_index); 672 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 673 674 if (!e1000e_setup_tx_offloads(core, tx)) { 675 return false; 676 } 677 678 net_tx_pkt_dump(tx->tx_pkt); 679 680 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) || 681 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 682 return net_tx_pkt_send_custom(tx->tx_pkt, false, 683 e1000e_tx_pkt_callback, core); 684 } else { 685 return net_tx_pkt_send(tx->tx_pkt, queue); 686 } 687 } 688 689 static void 690 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 691 { 692 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 693 PTC1023, PTC1522 }; 694 695 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4; 696 697 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 698 e1000x_inc_reg_if_not_full(core->mac, TPT); 699 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 700 701 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 702 case ETH_PKT_BCAST: 703 e1000x_inc_reg_if_not_full(core->mac, BPTC); 704 break; 705 case ETH_PKT_MCAST: 706 e1000x_inc_reg_if_not_full(core->mac, MPTC); 707 break; 708 case ETH_PKT_UCAST: 709 break; 710 default: 711 g_assert_not_reached(); 712 } 713 714 e1000x_inc_reg_if_not_full(core->mac, GPTC); 715 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len); 716 } 717 718 static void 719 e1000e_process_tx_desc(E1000ECore *core, 720 struct e1000e_tx *tx, 721 struct e1000_tx_desc *dp, 722 int queue_index) 723 { 724 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 725 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 726 unsigned int split_size = txd_lower & 0xffff; 727 uint64_t addr; 728 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 729 bool eop = txd_lower & E1000_TXD_CMD_EOP; 730 731 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 732 e1000x_read_tx_ctx_descr(xp, &tx->props); 733 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 734 return; 735 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 736 /* data descriptor */ 737 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8; 738 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 739 e1000e_process_ts_option(core, dp); 740 } else { 741 /* legacy descriptor */ 742 e1000e_process_ts_option(core, dp); 743 tx->cptse = 0; 744 } 745 746 addr = le64_to_cpu(dp->buffer_addr); 747 748 if (!tx->skip_cp) { 749 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, core->owner, 750 addr, split_size)) { 751 tx->skip_cp = true; 752 } 753 } 754 755 if (eop) { 756 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 757 if (e1000x_vlan_enabled(core->mac) && 758 e1000x_is_vlan_txd(txd_lower)) { 759 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 760 le16_to_cpu(dp->upper.fields.special), core->mac[VET]); 761 } 762 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 763 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 764 } 765 } 766 767 tx->skip_cp = false; 768 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, core->owner); 769 770 tx->sum_needed = 0; 771 tx->cptse = 0; 772 } 773 } 774 775 static inline uint32_t 776 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 777 { 778 if (!msix_enabled(core->owner)) { 779 return E1000_ICR_TXDW; 780 } 781 782 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 783 } 784 785 static inline uint32_t 786 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 787 bool min_threshold_hit) 788 { 789 if (!msix_enabled(core->owner)) { 790 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 791 } 792 793 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 794 } 795 796 static uint32_t 797 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 798 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 799 { 800 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 801 802 if (!(txd_lower & E1000_TXD_CMD_RS) && 803 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 804 return 0; 805 } 806 807 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 808 809 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 810 811 dp->upper.data = cpu_to_le32(txd_upper); 812 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 813 &dp->upper, sizeof(dp->upper)); 814 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 815 } 816 817 typedef struct E1000E_RingInfo_st { 818 int dbah; 819 int dbal; 820 int dlen; 821 int dh; 822 int dt; 823 int idx; 824 } E1000E_RingInfo; 825 826 static inline bool 827 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 828 { 829 return core->mac[r->dh] == core->mac[r->dt] || 830 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN; 831 } 832 833 static inline uint64_t 834 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 835 { 836 uint64_t bah = core->mac[r->dbah]; 837 uint64_t bal = core->mac[r->dbal]; 838 839 return (bah << 32) + bal; 840 } 841 842 static inline uint64_t 843 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 844 { 845 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 846 } 847 848 static inline void 849 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 850 { 851 core->mac[r->dh] += count; 852 853 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 854 core->mac[r->dh] = 0; 855 } 856 } 857 858 static inline uint32_t 859 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 860 { 861 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 862 core->mac[r->dh], core->mac[r->dt]); 863 864 if (core->mac[r->dh] <= core->mac[r->dt]) { 865 return core->mac[r->dt] - core->mac[r->dh]; 866 } 867 868 if (core->mac[r->dh] > core->mac[r->dt]) { 869 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 870 core->mac[r->dt] - core->mac[r->dh]; 871 } 872 873 g_assert_not_reached(); 874 return 0; 875 } 876 877 static inline bool 878 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 879 { 880 return core->mac[r->dlen] > 0; 881 } 882 883 static inline uint32_t 884 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 885 { 886 return core->mac[r->dlen]; 887 } 888 889 typedef struct E1000E_TxRing_st { 890 const E1000E_RingInfo *i; 891 struct e1000e_tx *tx; 892 } E1000E_TxRing; 893 894 static inline int 895 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 896 { 897 return (reg_idx - base_reg_idx) / (0x100 >> 2); 898 } 899 900 static inline void 901 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 902 { 903 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 904 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 905 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 906 }; 907 908 assert(idx < ARRAY_SIZE(i)); 909 910 txr->i = &i[idx]; 911 txr->tx = &core->tx[idx]; 912 } 913 914 typedef struct E1000E_RxRing_st { 915 const E1000E_RingInfo *i; 916 } E1000E_RxRing; 917 918 static inline void 919 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 920 { 921 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 922 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 923 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 924 }; 925 926 assert(idx < ARRAY_SIZE(i)); 927 928 rxr->i = &i[idx]; 929 } 930 931 static void 932 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 933 { 934 dma_addr_t base; 935 struct e1000_tx_desc desc; 936 bool ide = false; 937 const E1000E_RingInfo *txi = txr->i; 938 uint32_t cause = E1000_ICS_TXQE; 939 940 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 941 trace_e1000e_tx_disabled(); 942 return; 943 } 944 945 while (!e1000e_ring_empty(core, txi)) { 946 base = e1000e_ring_head_descr(core, txi); 947 948 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 949 950 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 951 desc.lower.data, desc.upper.data); 952 953 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 954 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 955 956 e1000e_ring_advance(core, txi, 1); 957 } 958 959 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 960 e1000e_set_interrupt_cause(core, cause); 961 } 962 } 963 964 static bool 965 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 966 size_t total_size) 967 { 968 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 969 970 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 971 core->rx_desc_buf_size); 972 973 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 974 core->rx_desc_buf_size; 975 } 976 977 void 978 e1000e_start_recv(E1000ECore *core) 979 { 980 int i; 981 982 trace_e1000e_rx_start_recv(); 983 984 for (i = 0; i <= core->max_queue_num; i++) { 985 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 986 } 987 } 988 989 bool 990 e1000e_can_receive(E1000ECore *core) 991 { 992 int i; 993 994 if (!e1000x_rx_ready(core->owner, core->mac)) { 995 return false; 996 } 997 998 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 999 E1000E_RxRing rxr; 1000 1001 e1000e_rx_ring_init(core, &rxr, i); 1002 if (e1000e_ring_enabled(core, rxr.i) && 1003 e1000e_has_rxbufs(core, rxr.i, 1)) { 1004 trace_e1000e_rx_can_recv(); 1005 return true; 1006 } 1007 } 1008 1009 trace_e1000e_rx_can_recv_rings_full(); 1010 return false; 1011 } 1012 1013 ssize_t 1014 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 1015 { 1016 const struct iovec iov = { 1017 .iov_base = (uint8_t *)buf, 1018 .iov_len = size 1019 }; 1020 1021 return e1000e_receive_iov(core, &iov, 1); 1022 } 1023 1024 static inline bool 1025 e1000e_rx_l3_cso_enabled(E1000ECore *core) 1026 { 1027 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1028 } 1029 1030 static inline bool 1031 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1032 { 1033 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1034 } 1035 1036 static bool 1037 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size) 1038 { 1039 uint32_t rctl = core->mac[RCTL]; 1040 1041 if (e1000x_is_vlan_packet(buf, core->mac[VET]) && 1042 e1000x_vlan_rx_filter_enabled(core->mac)) { 1043 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(buf)->h_tci); 1044 uint32_t vfta = 1045 ldl_le_p((uint32_t *)(core->mac + VFTA) + 1046 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK)); 1047 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) { 1048 trace_e1000e_rx_flt_vlan_mismatch(vid); 1049 return false; 1050 } else { 1051 trace_e1000e_rx_flt_vlan_match(vid); 1052 } 1053 } 1054 1055 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1056 case ETH_PKT_UCAST: 1057 if (rctl & E1000_RCTL_UPE) { 1058 return true; /* promiscuous ucast */ 1059 } 1060 break; 1061 1062 case ETH_PKT_BCAST: 1063 if (rctl & E1000_RCTL_BAM) { 1064 return true; /* broadcast enabled */ 1065 } 1066 break; 1067 1068 case ETH_PKT_MCAST: 1069 if (rctl & E1000_RCTL_MPE) { 1070 return true; /* promiscuous mcast */ 1071 } 1072 break; 1073 1074 default: 1075 g_assert_not_reached(); 1076 } 1077 1078 return e1000x_rx_group_filter(core->mac, buf); 1079 } 1080 1081 static inline void 1082 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1083 hwaddr *buff_addr) 1084 { 1085 *buff_addr = le64_to_cpu(desc->buffer_addr); 1086 } 1087 1088 static inline void 1089 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1090 hwaddr *buff_addr) 1091 { 1092 *buff_addr = le64_to_cpu(desc->read.buffer_addr); 1093 } 1094 1095 static inline void 1096 e1000e_read_ps_rx_descr(E1000ECore *core, 1097 union e1000_rx_desc_packet_split *desc, 1098 hwaddr buff_addr[MAX_PS_BUFFERS]) 1099 { 1100 int i; 1101 1102 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1103 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]); 1104 } 1105 1106 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1], 1107 buff_addr[2], buff_addr[3]); 1108 } 1109 1110 static inline void 1111 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1112 hwaddr buff_addr[MAX_PS_BUFFERS]) 1113 { 1114 if (e1000e_rx_use_legacy_descriptor(core)) { 1115 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]); 1116 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1117 } else { 1118 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1119 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr); 1120 } else { 1121 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]); 1122 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0; 1123 } 1124 } 1125 } 1126 1127 static void 1128 e1000e_verify_csum_in_sw(E1000ECore *core, 1129 struct NetRxPkt *pkt, 1130 uint32_t *status_flags, 1131 EthL4HdrProto l4hdr_proto) 1132 { 1133 bool csum_valid; 1134 uint32_t csum_error; 1135 1136 if (e1000e_rx_l3_cso_enabled(core)) { 1137 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1138 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1139 } else { 1140 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1141 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1142 } 1143 } else { 1144 trace_e1000e_rx_metadata_l3_cso_disabled(); 1145 } 1146 1147 if (!e1000e_rx_l4_cso_enabled(core)) { 1148 trace_e1000e_rx_metadata_l4_cso_disabled(); 1149 return; 1150 } 1151 1152 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1153 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1154 return; 1155 } 1156 1157 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1158 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error; 1159 1160 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1161 *status_flags |= E1000_RXD_STAT_UDPCS; 1162 } 1163 } 1164 1165 static inline bool 1166 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1167 { 1168 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1169 return false; 1170 } 1171 1172 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1173 return !net_rx_pkt_has_tcp_data(rx_pkt); 1174 } 1175 1176 return true; 1177 } 1178 1179 static void 1180 e1000e_build_rx_metadata(E1000ECore *core, 1181 struct NetRxPkt *pkt, 1182 bool is_eop, 1183 const E1000E_RSSInfo *rss_info, 1184 uint32_t *rss, uint32_t *mrq, 1185 uint32_t *status_flags, 1186 uint16_t *ip_id, 1187 uint16_t *vlan_tag) 1188 { 1189 struct virtio_net_hdr *vhdr; 1190 bool hasip4, hasip6; 1191 EthL4HdrProto l4hdr_proto; 1192 uint32_t pkt_type; 1193 1194 *status_flags = E1000_RXD_STAT_DD; 1195 1196 /* No additional metadata needed for non-EOP descriptors */ 1197 if (!is_eop) { 1198 goto func_exit; 1199 } 1200 1201 *status_flags |= E1000_RXD_STAT_EOP; 1202 1203 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1204 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto); 1205 1206 /* VLAN state */ 1207 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1208 *status_flags |= E1000_RXD_STAT_VP; 1209 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1210 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1211 } 1212 1213 /* Packet parsing results */ 1214 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1215 if (rss_info->enabled) { 1216 *rss = cpu_to_le32(rss_info->hash); 1217 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1218 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1219 } 1220 } else if (hasip4) { 1221 *status_flags |= E1000_RXD_STAT_IPIDV; 1222 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1223 trace_e1000e_rx_metadata_ip_id(*ip_id); 1224 } 1225 1226 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) { 1227 *status_flags |= E1000_RXD_STAT_ACK; 1228 trace_e1000e_rx_metadata_ack(); 1229 } 1230 1231 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1232 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1233 pkt_type = E1000_RXD_PKT_MAC; 1234 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1235 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1236 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1237 } else if (hasip4 || hasip6) { 1238 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1239 } else { 1240 pkt_type = E1000_RXD_PKT_MAC; 1241 } 1242 1243 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1244 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1245 1246 /* RX CSO information */ 1247 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1248 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1249 goto func_exit; 1250 } 1251 1252 vhdr = net_rx_pkt_get_vhdr(pkt); 1253 1254 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1255 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1256 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1257 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto); 1258 goto func_exit; 1259 } 1260 1261 if (e1000e_rx_l3_cso_enabled(core)) { 1262 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0; 1263 } else { 1264 trace_e1000e_rx_metadata_l3_cso_disabled(); 1265 } 1266 1267 if (e1000e_rx_l4_cso_enabled(core)) { 1268 switch (l4hdr_proto) { 1269 case ETH_L4_HDR_PROTO_TCP: 1270 *status_flags |= E1000_RXD_STAT_TCPCS; 1271 break; 1272 1273 case ETH_L4_HDR_PROTO_UDP: 1274 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1275 break; 1276 1277 default: 1278 break; 1279 } 1280 } else { 1281 trace_e1000e_rx_metadata_l4_cso_disabled(); 1282 } 1283 1284 trace_e1000e_rx_metadata_status_flags(*status_flags); 1285 1286 func_exit: 1287 *status_flags = cpu_to_le32(*status_flags); 1288 } 1289 1290 static inline void 1291 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc, 1292 struct NetRxPkt *pkt, 1293 const E1000E_RSSInfo *rss_info, 1294 uint16_t length) 1295 { 1296 uint32_t status_flags, rss, mrq; 1297 uint16_t ip_id; 1298 1299 assert(!rss_info->enabled); 1300 1301 desc->length = cpu_to_le16(length); 1302 desc->csum = 0; 1303 1304 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1305 rss_info, 1306 &rss, &mrq, 1307 &status_flags, &ip_id, 1308 &desc->special); 1309 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1310 desc->status = (uint8_t) le32_to_cpu(status_flags); 1311 } 1312 1313 static inline void 1314 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc, 1315 struct NetRxPkt *pkt, 1316 const E1000E_RSSInfo *rss_info, 1317 uint16_t length) 1318 { 1319 memset(&desc->wb, 0, sizeof(desc->wb)); 1320 1321 desc->wb.upper.length = cpu_to_le16(length); 1322 1323 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1324 rss_info, 1325 &desc->wb.lower.hi_dword.rss, 1326 &desc->wb.lower.mrq, 1327 &desc->wb.upper.status_error, 1328 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1329 &desc->wb.upper.vlan); 1330 } 1331 1332 static inline void 1333 e1000e_write_ps_rx_descr(E1000ECore *core, 1334 union e1000_rx_desc_packet_split *desc, 1335 struct NetRxPkt *pkt, 1336 const E1000E_RSSInfo *rss_info, 1337 size_t ps_hdr_len, 1338 uint16_t(*written)[MAX_PS_BUFFERS]) 1339 { 1340 int i; 1341 1342 memset(&desc->wb, 0, sizeof(desc->wb)); 1343 1344 desc->wb.middle.length0 = cpu_to_le16((*written)[0]); 1345 1346 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1347 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1348 } 1349 1350 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1351 rss_info, 1352 &desc->wb.lower.hi_dword.rss, 1353 &desc->wb.lower.mrq, 1354 &desc->wb.middle.status_error, 1355 &desc->wb.lower.hi_dword.csum_ip.ip_id, 1356 &desc->wb.middle.vlan); 1357 1358 desc->wb.upper.header_status = 1359 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1360 1361 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1362 (*written)[2], (*written)[3]); 1363 } 1364 1365 static inline void 1366 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc, 1367 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1368 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1369 { 1370 if (e1000e_rx_use_legacy_descriptor(core)) { 1371 assert(ps_hdr_len == 0); 1372 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, 1373 (*written)[0]); 1374 } else { 1375 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1376 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info, 1377 ps_hdr_len, written); 1378 } else { 1379 assert(ps_hdr_len == 0); 1380 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info, 1381 (*written)[0]); 1382 } 1383 } 1384 } 1385 1386 static inline void 1387 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr, 1388 union e1000_rx_desc_union *desc, dma_addr_t len) 1389 { 1390 PCIDevice *dev = core->owner; 1391 1392 if (e1000e_rx_use_legacy_descriptor(core)) { 1393 struct e1000_rx_desc *d = &desc->legacy; 1394 size_t offset = offsetof(struct e1000_rx_desc, status); 1395 uint8_t status = d->status; 1396 1397 d->status &= ~E1000_RXD_STAT_DD; 1398 pci_dma_write(dev, addr, desc, len); 1399 1400 if (status & E1000_RXD_STAT_DD) { 1401 d->status = status; 1402 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1403 } 1404 } else { 1405 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1406 union e1000_rx_desc_packet_split *d = &desc->packet_split; 1407 size_t offset = offsetof(union e1000_rx_desc_packet_split, 1408 wb.middle.status_error); 1409 uint32_t status = d->wb.middle.status_error; 1410 1411 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD; 1412 pci_dma_write(dev, addr, desc, len); 1413 1414 if (status & E1000_RXD_STAT_DD) { 1415 d->wb.middle.status_error = status; 1416 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1417 } 1418 } else { 1419 union e1000_rx_desc_extended *d = &desc->extended; 1420 size_t offset = offsetof(union e1000_rx_desc_extended, 1421 wb.upper.status_error); 1422 uint32_t status = d->wb.upper.status_error; 1423 1424 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD; 1425 pci_dma_write(dev, addr, desc, len); 1426 1427 if (status & E1000_RXD_STAT_DD) { 1428 d->wb.upper.status_error = status; 1429 pci_dma_write(dev, addr + offset, &status, sizeof(status)); 1430 } 1431 } 1432 } 1433 } 1434 1435 typedef struct e1000e_ba_state_st { 1436 uint16_t written[MAX_PS_BUFFERS]; 1437 uint8_t cur_idx; 1438 } e1000e_ba_state; 1439 1440 static inline void 1441 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1442 hwaddr ba[MAX_PS_BUFFERS], 1443 e1000e_ba_state *bastate, 1444 const char *data, 1445 dma_addr_t data_len) 1446 { 1447 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1448 1449 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len); 1450 bastate->written[0] += data_len; 1451 1452 bastate->cur_idx = 1; 1453 } 1454 1455 static void 1456 e1000e_write_to_rx_buffers(E1000ECore *core, 1457 hwaddr ba[MAX_PS_BUFFERS], 1458 e1000e_ba_state *bastate, 1459 const char *data, 1460 dma_addr_t data_len) 1461 { 1462 while (data_len > 0) { 1463 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1464 uint32_t cur_buf_bytes_left = cur_buf_len - 1465 bastate->written[bastate->cur_idx]; 1466 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1467 1468 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1469 ba[bastate->cur_idx], 1470 bastate->written[bastate->cur_idx], 1471 data, 1472 bytes_to_write); 1473 1474 pci_dma_write(core->owner, 1475 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1476 data, bytes_to_write); 1477 1478 bastate->written[bastate->cur_idx] += bytes_to_write; 1479 data += bytes_to_write; 1480 data_len -= bytes_to_write; 1481 1482 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1483 bastate->cur_idx++; 1484 } 1485 1486 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1487 } 1488 } 1489 1490 static void 1491 e1000e_update_rx_stats(E1000ECore *core, size_t pkt_size, size_t pkt_fcs_size) 1492 { 1493 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt); 1494 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size); 1495 } 1496 1497 static inline bool 1498 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1499 { 1500 return e1000e_ring_free_descr_num(core, rxi) == 1501 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1502 } 1503 1504 static bool 1505 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1506 { 1507 bool hasip4, hasip6; 1508 EthL4HdrProto l4hdr_proto; 1509 bool fragment; 1510 1511 if (!e1000e_rx_use_ps_descriptor(core)) { 1512 return false; 1513 } 1514 1515 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); 1516 1517 if (hasip4) { 1518 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1519 } else if (hasip6) { 1520 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1521 } else { 1522 return false; 1523 } 1524 1525 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1526 return false; 1527 } 1528 1529 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP || 1530 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) { 1531 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1532 } else { 1533 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1534 } 1535 1536 if ((*hdr_len > core->rxbuf_sizes[0]) || 1537 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1538 return false; 1539 } 1540 1541 return true; 1542 } 1543 1544 static void 1545 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1546 const E1000E_RxRing *rxr, 1547 const E1000E_RSSInfo *rss_info) 1548 { 1549 PCIDevice *d = core->owner; 1550 dma_addr_t base; 1551 union e1000_rx_desc_union desc; 1552 size_t desc_size; 1553 size_t desc_offset = 0; 1554 size_t iov_ofs = 0; 1555 1556 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1557 size_t size = net_rx_pkt_get_total_len(pkt); 1558 size_t total_size = size + e1000x_fcs_len(core->mac); 1559 const E1000E_RingInfo *rxi; 1560 size_t ps_hdr_len = 0; 1561 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1562 bool is_first = true; 1563 1564 rxi = rxr->i; 1565 1566 do { 1567 hwaddr ba[MAX_PS_BUFFERS]; 1568 e1000e_ba_state bastate = { { 0 } }; 1569 bool is_last = false; 1570 1571 desc_size = total_size - desc_offset; 1572 1573 if (desc_size > core->rx_desc_buf_size) { 1574 desc_size = core->rx_desc_buf_size; 1575 } 1576 1577 if (e1000e_ring_empty(core, rxi)) { 1578 return; 1579 } 1580 1581 base = e1000e_ring_head_descr(core, rxi); 1582 1583 pci_dma_read(d, base, &desc, core->rx_desc_len); 1584 1585 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1586 1587 e1000e_read_rx_descr(core, &desc, ba); 1588 1589 if (ba[0]) { 1590 if (desc_offset < size) { 1591 static const uint32_t fcs_pad; 1592 size_t iov_copy; 1593 size_t copy_size = size - desc_offset; 1594 if (copy_size > core->rx_desc_buf_size) { 1595 copy_size = core->rx_desc_buf_size; 1596 } 1597 1598 /* For PS mode copy the packet header first */ 1599 if (do_ps) { 1600 if (is_first) { 1601 size_t ps_hdr_copied = 0; 1602 do { 1603 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1604 iov->iov_len - iov_ofs); 1605 1606 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1607 iov->iov_base, iov_copy); 1608 1609 copy_size -= iov_copy; 1610 ps_hdr_copied += iov_copy; 1611 1612 iov_ofs += iov_copy; 1613 if (iov_ofs == iov->iov_len) { 1614 iov++; 1615 iov_ofs = 0; 1616 } 1617 } while (ps_hdr_copied < ps_hdr_len); 1618 1619 is_first = false; 1620 } else { 1621 /* Leave buffer 0 of each descriptor except first */ 1622 /* empty as per spec 7.1.5.1 */ 1623 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate, 1624 NULL, 0); 1625 } 1626 } 1627 1628 /* Copy packet payload */ 1629 while (copy_size) { 1630 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1631 1632 e1000e_write_to_rx_buffers(core, ba, &bastate, 1633 iov->iov_base + iov_ofs, iov_copy); 1634 1635 copy_size -= iov_copy; 1636 iov_ofs += iov_copy; 1637 if (iov_ofs == iov->iov_len) { 1638 iov++; 1639 iov_ofs = 0; 1640 } 1641 } 1642 1643 if (desc_offset + desc_size >= total_size) { 1644 /* Simulate FCS checksum presence in the last descriptor */ 1645 e1000e_write_to_rx_buffers(core, ba, &bastate, 1646 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1647 } 1648 } 1649 } else { /* as per intel docs; skip descriptors with null buf addr */ 1650 trace_e1000e_rx_null_descriptor(); 1651 } 1652 desc_offset += desc_size; 1653 if (desc_offset >= total_size) { 1654 is_last = true; 1655 } 1656 1657 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, 1658 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1659 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len); 1660 1661 e1000e_ring_advance(core, rxi, 1662 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1663 1664 } while (desc_offset < total_size); 1665 1666 e1000e_update_rx_stats(core, size, total_size); 1667 } 1668 1669 static inline void 1670 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1671 { 1672 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1673 1674 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1675 net_rx_pkt_fix_l4_csum(pkt); 1676 } 1677 } 1678 1679 ssize_t 1680 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1681 { 1682 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet); 1683 } 1684 1685 static ssize_t 1686 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt, 1687 bool has_vnet) 1688 { 1689 uint32_t n = 0; 1690 uint8_t buf[ETH_ZLEN]; 1691 struct iovec min_iov; 1692 size_t size, orig_size; 1693 size_t iov_ofs = 0; 1694 E1000E_RxRing rxr; 1695 E1000E_RSSInfo rss_info; 1696 size_t total_size; 1697 ssize_t retval; 1698 bool rdmts_hit; 1699 1700 trace_e1000e_rx_receive_iov(iovcnt); 1701 1702 if (!e1000x_hw_rx_enabled(core->mac)) { 1703 return -1; 1704 } 1705 1706 /* Pull virtio header in */ 1707 if (has_vnet) { 1708 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1709 iov_ofs = sizeof(struct virtio_net_hdr); 1710 } else { 1711 net_rx_pkt_unset_vhdr(core->rx_pkt); 1712 } 1713 1714 orig_size = iov_size(iov, iovcnt); 1715 size = orig_size - iov_ofs; 1716 1717 /* Pad to minimum Ethernet frame length */ 1718 if (size < sizeof(buf)) { 1719 iov_to_buf(iov, iovcnt, iov_ofs, buf, size); 1720 memset(&buf[size], 0, sizeof(buf) - size); 1721 e1000x_inc_reg_if_not_full(core->mac, RUC); 1722 min_iov.iov_base = buf; 1723 min_iov.iov_len = size = sizeof(buf); 1724 iovcnt = 1; 1725 iov = &min_iov; 1726 iov_ofs = 0; 1727 } else { 1728 iov_to_buf(iov, iovcnt, iov_ofs, buf, ETH_HLEN + 4); 1729 } 1730 1731 /* Discard oversized packets if !LPE and !SBP. */ 1732 if (e1000x_is_oversized(core->mac, size)) { 1733 return orig_size; 1734 } 1735 1736 net_rx_pkt_set_packet_type(core->rx_pkt, 1737 get_eth_packet_type(PKT_GET_ETH_HDR(buf))); 1738 1739 if (!e1000e_receive_filter(core, buf, size)) { 1740 trace_e1000e_rx_flt_dropped(); 1741 return orig_size; 1742 } 1743 1744 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1745 e1000x_vlan_enabled(core->mac), core->mac[VET]); 1746 1747 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1748 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1749 1750 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1751 e1000x_fcs_len(core->mac); 1752 1753 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1754 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1755 1756 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1757 1758 retval = orig_size; 1759 1760 /* Perform small receive detection (RSRPD) */ 1761 if (total_size < core->mac[RSRPD]) { 1762 n |= E1000_ICS_SRPD; 1763 } 1764 1765 /* Perform ACK receive detection */ 1766 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) && 1767 (e1000e_is_tcp_ack(core, core->rx_pkt))) { 1768 n |= E1000_ICS_ACK; 1769 } 1770 1771 /* Check if receive descriptor minimum threshold hit */ 1772 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1773 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1774 1775 trace_e1000e_rx_written_to_guest(rxr.i->idx); 1776 } else { 1777 n |= E1000_ICS_RXO; 1778 retval = 0; 1779 1780 trace_e1000e_rx_not_written_to_guest(rxr.i->idx); 1781 } 1782 1783 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1784 trace_e1000e_rx_interrupt_set(n); 1785 e1000e_set_interrupt_cause(core, n); 1786 } else { 1787 trace_e1000e_rx_interrupt_delayed(n); 1788 } 1789 1790 return retval; 1791 } 1792 1793 static inline bool 1794 e1000e_have_autoneg(E1000ECore *core) 1795 { 1796 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN; 1797 } 1798 1799 static void e1000e_update_flowctl_status(E1000ECore *core) 1800 { 1801 if (e1000e_have_autoneg(core) && 1802 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) { 1803 trace_e1000e_link_autoneg_flowctl(true); 1804 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1805 } else { 1806 trace_e1000e_link_autoneg_flowctl(false); 1807 } 1808 } 1809 1810 static inline void 1811 e1000e_link_down(E1000ECore *core) 1812 { 1813 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1814 e1000e_update_flowctl_status(core); 1815 } 1816 1817 static inline void 1818 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1819 { 1820 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */ 1821 core->phy[0][MII_BMCR] = val & ~(0x3f | 1822 MII_BMCR_RESET | 1823 MII_BMCR_ANRESTART); 1824 1825 if ((val & MII_BMCR_ANRESTART) && 1826 e1000e_have_autoneg(core)) { 1827 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1828 } 1829 } 1830 1831 static void 1832 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1833 { 1834 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1835 1836 if (val & BIT(10)) { 1837 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1838 } 1839 } 1840 1841 static void 1842 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1843 { 1844 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1845 } 1846 1847 void 1848 e1000e_core_set_link_status(E1000ECore *core) 1849 { 1850 NetClientState *nc = qemu_get_queue(core->owner_nic); 1851 uint32_t old_status = core->mac[STATUS]; 1852 1853 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1854 1855 if (nc->link_down) { 1856 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1857 } else { 1858 if (e1000e_have_autoneg(core) && 1859 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 1860 e1000x_restart_autoneg(core->mac, core->phy[0], 1861 core->autoneg_timer); 1862 } else { 1863 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1864 e1000e_start_recv(core); 1865 } 1866 } 1867 1868 if (core->mac[STATUS] != old_status) { 1869 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1870 } 1871 } 1872 1873 static void 1874 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1875 { 1876 trace_e1000e_core_ctrl_write(index, val); 1877 1878 /* RST is self clearing */ 1879 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1880 core->mac[CTRL_DUP] = core->mac[CTRL]; 1881 1882 trace_e1000e_link_set_params( 1883 !!(val & E1000_CTRL_ASDE), 1884 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1885 !!(val & E1000_CTRL_FRCSPD), 1886 !!(val & E1000_CTRL_FRCDPX), 1887 !!(val & E1000_CTRL_RFCE), 1888 !!(val & E1000_CTRL_TFCE)); 1889 1890 if (val & E1000_CTRL_RST) { 1891 trace_e1000e_core_ctrl_sw_reset(); 1892 e1000e_reset(core, true); 1893 } 1894 1895 if (val & E1000_CTRL_PHY_RST) { 1896 trace_e1000e_core_ctrl_phy_reset(); 1897 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1898 } 1899 } 1900 1901 static void 1902 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1903 { 1904 trace_e1000e_rx_set_rfctl(val); 1905 1906 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1907 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1908 } 1909 1910 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1911 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1912 } 1913 1914 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1915 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1916 } 1917 1918 core->mac[RFCTL] = val; 1919 } 1920 1921 static void 1922 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1923 { 1924 int i; 1925 core->rx_desc_buf_size = 0; 1926 1927 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1928 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1929 } 1930 } 1931 1932 static void 1933 e1000e_parse_rxbufsize(E1000ECore *core) 1934 { 1935 uint32_t rctl = core->mac[RCTL]; 1936 1937 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1938 1939 if (rctl & E1000_RCTL_DTYP_MASK) { 1940 uint32_t bsize; 1941 1942 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1943 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1944 1945 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1946 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1947 1948 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1949 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1950 1951 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1952 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1953 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1954 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1955 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1956 } else { 1957 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1958 } 1959 1960 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1961 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1962 1963 e1000e_calc_per_desc_buf_size(core); 1964 } 1965 1966 static void 1967 e1000e_calc_rxdesclen(E1000ECore *core) 1968 { 1969 if (e1000e_rx_use_legacy_descriptor(core)) { 1970 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1971 } else { 1972 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1973 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1974 } else { 1975 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1976 } 1977 } 1978 trace_e1000e_rx_desc_len(core->rx_desc_len); 1979 } 1980 1981 static void 1982 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1983 { 1984 core->mac[RCTL] = val; 1985 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1986 1987 if (val & E1000_RCTL_EN) { 1988 e1000e_parse_rxbufsize(core); 1989 e1000e_calc_rxdesclen(core); 1990 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1991 E1000_RING_DESC_LEN_SHIFT; 1992 1993 e1000e_start_recv(core); 1994 } 1995 } 1996 1997 static 1998 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1999 (E1000ECore *, int, uint16_t) = { 2000 [0] = { 2001 [MII_BMCR] = e1000e_set_phy_ctrl, 2002 [PHY_PAGE] = e1000e_set_phy_page, 2003 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 2004 } 2005 }; 2006 2007 static inline void 2008 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 2009 { 2010 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 2011 core->mac[IMS] &= ~bits; 2012 } 2013 2014 static inline bool 2015 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer) 2016 { 2017 if (timer->running) { 2018 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 2019 2020 return true; 2021 } 2022 2023 if (timer->core->mac[timer->delay_reg] != 0) { 2024 e1000e_intrmgr_rearm_timer(timer); 2025 } 2026 2027 return false; 2028 } 2029 2030 static inline bool 2031 e1000e_itr_should_postpone(E1000ECore *core) 2032 { 2033 return e1000e_postpone_interrupt(&core->itr); 2034 } 2035 2036 static inline bool 2037 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 2038 { 2039 return e1000e_postpone_interrupt(&core->eitr[idx]); 2040 } 2041 2042 static void 2043 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2044 { 2045 uint32_t effective_eiac; 2046 2047 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2048 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2049 if (vec < E1000E_MSIX_VEC_NUM) { 2050 if (!e1000e_eitr_should_postpone(core, vec)) { 2051 trace_e1000e_irq_msix_notify_vec(vec); 2052 msix_notify(core->owner, vec); 2053 } 2054 } else { 2055 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2056 } 2057 } else { 2058 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2059 } 2060 2061 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2062 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); 2063 core->mac[IAM] &= ~cause; 2064 } 2065 2066 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2067 2068 effective_eiac = core->mac[EIAC] & cause; 2069 2070 core->mac[ICR] &= ~effective_eiac; 2071 core->msi_causes_pending &= ~effective_eiac; 2072 2073 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2074 core->mac[IMS] &= ~effective_eiac; 2075 } 2076 } 2077 2078 static void 2079 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2080 { 2081 if (causes & E1000_ICR_RXQ0) { 2082 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2083 E1000_IVAR_RXQ0(core->mac[IVAR])); 2084 } 2085 2086 if (causes & E1000_ICR_RXQ1) { 2087 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2088 E1000_IVAR_RXQ1(core->mac[IVAR])); 2089 } 2090 2091 if (causes & E1000_ICR_TXQ0) { 2092 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2093 E1000_IVAR_TXQ0(core->mac[IVAR])); 2094 } 2095 2096 if (causes & E1000_ICR_TXQ1) { 2097 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2098 E1000_IVAR_TXQ1(core->mac[IVAR])); 2099 } 2100 2101 if (causes & E1000_ICR_OTHER) { 2102 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2103 E1000_IVAR_OTHER(core->mac[IVAR])); 2104 } 2105 } 2106 2107 static void 2108 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2109 { 2110 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2111 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2112 if (vec < E1000E_MSIX_VEC_NUM) { 2113 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2114 msix_clr_pending(core->owner, vec); 2115 } else { 2116 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2117 } 2118 } else { 2119 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2120 } 2121 } 2122 2123 static void 2124 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2125 { 2126 if (causes & E1000_ICR_RXQ0) { 2127 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2128 E1000_IVAR_RXQ0(core->mac[IVAR])); 2129 } 2130 2131 if (causes & E1000_ICR_RXQ1) { 2132 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2133 E1000_IVAR_RXQ1(core->mac[IVAR])); 2134 } 2135 2136 if (causes & E1000_ICR_TXQ0) { 2137 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2138 E1000_IVAR_TXQ0(core->mac[IVAR])); 2139 } 2140 2141 if (causes & E1000_ICR_TXQ1) { 2142 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2143 E1000_IVAR_TXQ1(core->mac[IVAR])); 2144 } 2145 2146 if (causes & E1000_ICR_OTHER) { 2147 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2148 E1000_IVAR_OTHER(core->mac[IVAR])); 2149 } 2150 } 2151 2152 static inline void 2153 e1000e_fix_icr_asserted(E1000ECore *core) 2154 { 2155 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2156 if (core->mac[ICR]) { 2157 core->mac[ICR] |= E1000_ICR_ASSERTED; 2158 } 2159 2160 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2161 } 2162 2163 static void 2164 e1000e_send_msi(E1000ECore *core, bool msix) 2165 { 2166 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2167 2168 core->msi_causes_pending &= causes; 2169 causes ^= core->msi_causes_pending; 2170 if (causes == 0) { 2171 return; 2172 } 2173 core->msi_causes_pending |= causes; 2174 2175 if (msix) { 2176 e1000e_msix_notify(core, causes); 2177 } else { 2178 if (!e1000e_itr_should_postpone(core)) { 2179 trace_e1000e_irq_msi_notify(causes); 2180 msi_notify(core->owner, 0); 2181 } 2182 } 2183 } 2184 2185 static void 2186 e1000e_update_interrupt_state(E1000ECore *core) 2187 { 2188 bool interrupts_pending; 2189 bool is_msix = msix_enabled(core->owner); 2190 2191 /* Set ICR[OTHER] for MSI-X */ 2192 if (is_msix) { 2193 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { 2194 core->mac[ICR] |= E1000_ICR_OTHER; 2195 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2196 } 2197 } 2198 2199 e1000e_fix_icr_asserted(core); 2200 2201 /* 2202 * Make sure ICR and ICS registers have the same value. 2203 * The spec says that the ICS register is write-only. However in practice, 2204 * on real hardware ICS is readable, and for reads it has the same value as 2205 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2206 * 2207 * The VxWorks PRO/1000 driver uses this behaviour. 2208 */ 2209 core->mac[ICS] = core->mac[ICR]; 2210 2211 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2212 if (!interrupts_pending) { 2213 core->msi_causes_pending = 0; 2214 } 2215 2216 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2217 core->mac[ICR], core->mac[IMS]); 2218 2219 if (is_msix || msi_enabled(core->owner)) { 2220 if (interrupts_pending) { 2221 e1000e_send_msi(core, is_msix); 2222 } 2223 } else { 2224 if (interrupts_pending) { 2225 if (!e1000e_itr_should_postpone(core)) { 2226 e1000e_raise_legacy_irq(core); 2227 } 2228 } else { 2229 e1000e_lower_legacy_irq(core); 2230 } 2231 } 2232 } 2233 2234 static void 2235 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2236 { 2237 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2238 2239 val |= e1000e_intmgr_collect_delayed_causes(core); 2240 core->mac[ICR] |= val; 2241 2242 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2243 2244 e1000e_update_interrupt_state(core); 2245 } 2246 2247 static inline void 2248 e1000e_autoneg_timer(void *opaque) 2249 { 2250 E1000ECore *core = opaque; 2251 if (!qemu_get_queue(core->owner_nic)->link_down) { 2252 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2253 e1000e_start_recv(core); 2254 2255 e1000e_update_flowctl_status(core); 2256 /* signal link status change to the guest */ 2257 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2258 } 2259 } 2260 2261 static inline uint16_t 2262 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2263 { 2264 uint16_t index = (addr & 0x1ffff) >> 2; 2265 return index + (mac_reg_access[index] & 0xfffe); 2266 } 2267 2268 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2269 [0] = { 2270 [MII_BMCR] = PHY_ANYPAGE | PHY_RW, 2271 [MII_BMSR] = PHY_ANYPAGE | PHY_R, 2272 [MII_PHYID1] = PHY_ANYPAGE | PHY_R, 2273 [MII_PHYID2] = PHY_ANYPAGE | PHY_R, 2274 [MII_ANAR] = PHY_ANYPAGE | PHY_RW, 2275 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R, 2276 [MII_ANER] = PHY_ANYPAGE | PHY_R, 2277 [MII_ANNP] = PHY_ANYPAGE | PHY_RW, 2278 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R, 2279 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW, 2280 [MII_STAT1000] = PHY_ANYPAGE | PHY_R, 2281 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R, 2282 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2283 2284 [PHY_COPPER_CTRL1] = PHY_RW, 2285 [PHY_COPPER_STAT1] = PHY_R, 2286 [PHY_COPPER_CTRL3] = PHY_RW, 2287 [PHY_RX_ERR_CNTR] = PHY_R, 2288 [PHY_OEM_BITS] = PHY_RW, 2289 [PHY_BIAS_1] = PHY_RW, 2290 [PHY_BIAS_2] = PHY_RW, 2291 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2292 [PHY_COPPER_STAT2] = PHY_R, 2293 [PHY_COPPER_CTRL2] = PHY_RW 2294 }, 2295 [2] = { 2296 [PHY_MAC_CTRL1] = PHY_RW, 2297 [PHY_MAC_INT_ENABLE] = PHY_RW, 2298 [PHY_MAC_STAT] = PHY_R, 2299 [PHY_MAC_CTRL2] = PHY_RW 2300 }, 2301 [3] = { 2302 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2303 [PHY_LED_03_POL_CTRL] = PHY_RW, 2304 [PHY_LED_TIMER_CTRL] = PHY_RW, 2305 [PHY_LED_45_CTRL] = PHY_RW 2306 }, 2307 [5] = { 2308 [PHY_1000T_SKEW] = PHY_R, 2309 [PHY_1000T_SWAP] = PHY_R 2310 }, 2311 [6] = { 2312 [PHY_CRC_COUNTERS] = PHY_R 2313 } 2314 }; 2315 2316 static bool 2317 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2318 char cap, uint8_t *page) 2319 { 2320 *page = 2321 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2322 : core->phy[0][PHY_PAGE]; 2323 2324 if (*page >= E1000E_PHY_PAGES) { 2325 return false; 2326 } 2327 2328 return e1000e_phy_regcap[*page][addr] & cap; 2329 } 2330 2331 static void 2332 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2333 uint32_t addr, uint16_t data) 2334 { 2335 assert(page < E1000E_PHY_PAGES); 2336 assert(addr < E1000E_PHY_PAGE_SIZE); 2337 2338 if (e1000e_phyreg_writeops[page][addr]) { 2339 e1000e_phyreg_writeops[page][addr](core, addr, data); 2340 } else { 2341 core->phy[page][addr] = data; 2342 } 2343 } 2344 2345 static void 2346 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2347 { 2348 uint32_t data = val & E1000_MDIC_DATA_MASK; 2349 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2350 uint8_t page; 2351 2352 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2353 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2354 } else if (val & E1000_MDIC_OP_READ) { 2355 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2356 trace_e1000e_core_mdic_read_unhandled(page, addr); 2357 val |= E1000_MDIC_ERROR; 2358 } else { 2359 val = (val ^ data) | core->phy[page][addr]; 2360 trace_e1000e_core_mdic_read(page, addr, val); 2361 } 2362 } else if (val & E1000_MDIC_OP_WRITE) { 2363 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2364 trace_e1000e_core_mdic_write_unhandled(page, addr); 2365 val |= E1000_MDIC_ERROR; 2366 } else { 2367 trace_e1000e_core_mdic_write(page, addr, data); 2368 e1000e_phy_reg_write(core, page, addr, data); 2369 } 2370 } 2371 core->mac[MDIC] = val | E1000_MDIC_READY; 2372 2373 if (val & E1000_MDIC_INT_EN) { 2374 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2375 } 2376 } 2377 2378 static void 2379 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2380 { 2381 core->mac[index] = val & 0xffff; 2382 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2383 e1000e_start_recv(core); 2384 } 2385 2386 static void 2387 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2388 { 2389 if ((val & E1000_STATUS_PHYRA) == 0) { 2390 core->mac[index] &= ~E1000_STATUS_PHYRA; 2391 } 2392 } 2393 2394 static void 2395 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2396 { 2397 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2398 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2399 2400 /* Zero self-clearing bits */ 2401 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2402 core->mac[CTRL_EXT] = val; 2403 } 2404 2405 static void 2406 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2407 { 2408 int i; 2409 2410 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2411 2412 if (!msix_enabled(core->owner)) { 2413 return; 2414 } 2415 2416 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2417 if (core->mac[PBACLR] & BIT(i)) { 2418 msix_clr_pending(core->owner, i); 2419 } 2420 } 2421 } 2422 2423 static void 2424 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2425 { 2426 core->mac[FCRTH] = val & 0xFFF8; 2427 } 2428 2429 static void 2430 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2431 { 2432 core->mac[FCRTL] = val & 0x8000FFF8; 2433 } 2434 2435 #define E1000E_LOW_BITS_SET_FUNC(num) \ 2436 static void \ 2437 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \ 2438 { \ 2439 core->mac[index] = val & (BIT(num) - 1); \ 2440 } 2441 2442 E1000E_LOW_BITS_SET_FUNC(4) 2443 E1000E_LOW_BITS_SET_FUNC(6) 2444 E1000E_LOW_BITS_SET_FUNC(11) 2445 E1000E_LOW_BITS_SET_FUNC(12) 2446 E1000E_LOW_BITS_SET_FUNC(13) 2447 E1000E_LOW_BITS_SET_FUNC(16) 2448 2449 static void 2450 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2451 { 2452 core->mac[VET] = val & 0xffff; 2453 trace_e1000e_vlan_vet(core->mac[VET]); 2454 } 2455 2456 static void 2457 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2458 { 2459 core->mac[index] = val & E1000_XDLEN_MASK; 2460 } 2461 2462 static void 2463 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2464 { 2465 core->mac[index] = val & E1000_XDBAL_MASK; 2466 } 2467 2468 static void 2469 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2470 { 2471 E1000E_TxRing txr; 2472 core->mac[index] = val; 2473 2474 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2475 e1000e_tx_ring_init(core, &txr, 0); 2476 e1000e_start_xmit(core, &txr); 2477 } 2478 2479 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2480 e1000e_tx_ring_init(core, &txr, 1); 2481 e1000e_start_xmit(core, &txr); 2482 } 2483 } 2484 2485 static void 2486 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2487 { 2488 E1000E_TxRing txr; 2489 int qidx = e1000e_mq_queue_idx(TDT, index); 2490 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2491 2492 core->mac[index] = val & 0xffff; 2493 2494 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2495 e1000e_tx_ring_init(core, &txr, qidx); 2496 e1000e_start_xmit(core, &txr); 2497 } 2498 } 2499 2500 static void 2501 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2502 { 2503 trace_e1000e_irq_write_ics(val); 2504 e1000e_set_interrupt_cause(core, val); 2505 } 2506 2507 static void 2508 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2509 { 2510 uint32_t icr = 0; 2511 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2512 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2513 trace_e1000e_irq_icr_process_iame(); 2514 e1000e_clear_ims_bits(core, core->mac[IAM]); 2515 } 2516 2517 icr = core->mac[ICR] & ~val; 2518 /* 2519 * Windows driver expects that the "receive overrun" bit and other 2520 * ones to be cleared when the "Other" bit (#24) is cleared. 2521 */ 2522 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr; 2523 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr); 2524 core->mac[ICR] = icr; 2525 e1000e_update_interrupt_state(core); 2526 } 2527 2528 static void 2529 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2530 { 2531 trace_e1000e_irq_ims_clear_set_imc(val); 2532 e1000e_clear_ims_bits(core, val); 2533 e1000e_update_interrupt_state(core); 2534 } 2535 2536 static void 2537 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2538 { 2539 static const uint32_t ims_ext_mask = 2540 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2541 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2542 E1000_IMS_OTHER; 2543 2544 static const uint32_t ims_valid_mask = 2545 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2546 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2547 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2548 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2549 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2550 E1000_IMS_OTHER; 2551 2552 uint32_t valid_val = val & ims_valid_mask; 2553 2554 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2555 core->mac[IMS] |= valid_val; 2556 2557 if ((valid_val & ims_ext_mask) && 2558 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2559 msix_enabled(core->owner)) { 2560 e1000e_msix_clear(core, valid_val); 2561 } 2562 2563 if ((valid_val == ims_valid_mask) && 2564 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2565 trace_e1000e_irq_fire_all_timers(val); 2566 e1000e_intrmgr_fire_all_timers(core); 2567 } 2568 2569 e1000e_update_interrupt_state(core); 2570 } 2571 2572 static void 2573 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2574 { 2575 e1000e_set_16bit(core, index, val); 2576 2577 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2578 trace_e1000e_irq_rdtr_fpd_running(); 2579 e1000e_intrmgr_fire_delayed_interrupts(core); 2580 } else { 2581 trace_e1000e_irq_rdtr_fpd_not_running(); 2582 } 2583 } 2584 2585 static void 2586 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2587 { 2588 e1000e_set_16bit(core, index, val); 2589 2590 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2591 trace_e1000e_irq_tidv_fpd_running(); 2592 e1000e_intrmgr_fire_delayed_interrupts(core); 2593 } else { 2594 trace_e1000e_irq_tidv_fpd_not_running(); 2595 } 2596 } 2597 2598 static uint32_t 2599 e1000e_mac_readreg(E1000ECore *core, int index) 2600 { 2601 return core->mac[index]; 2602 } 2603 2604 static uint32_t 2605 e1000e_mac_ics_read(E1000ECore *core, int index) 2606 { 2607 trace_e1000e_irq_read_ics(core->mac[ICS]); 2608 return core->mac[ICS]; 2609 } 2610 2611 static uint32_t 2612 e1000e_mac_ims_read(E1000ECore *core, int index) 2613 { 2614 trace_e1000e_irq_read_ims(core->mac[IMS]); 2615 return core->mac[IMS]; 2616 } 2617 2618 static uint32_t 2619 e1000e_mac_swsm_read(E1000ECore *core, int index) 2620 { 2621 uint32_t val = core->mac[SWSM]; 2622 core->mac[SWSM] = val | E1000_SWSM_SMBI; 2623 return val; 2624 } 2625 2626 static uint32_t 2627 e1000e_mac_itr_read(E1000ECore *core, int index) 2628 { 2629 return core->itr_guest_value; 2630 } 2631 2632 static uint32_t 2633 e1000e_mac_eitr_read(E1000ECore *core, int index) 2634 { 2635 return core->eitr_guest_value[index - EITR]; 2636 } 2637 2638 static uint32_t 2639 e1000e_mac_icr_read(E1000ECore *core, int index) 2640 { 2641 uint32_t ret = core->mac[ICR]; 2642 trace_e1000e_irq_icr_read_entry(ret); 2643 2644 if (core->mac[IMS] == 0) { 2645 trace_e1000e_irq_icr_clear_zero_ims(); 2646 core->mac[ICR] = 0; 2647 } 2648 2649 if (!msix_enabled(core->owner)) { 2650 trace_e1000e_irq_icr_clear_nonmsix_icr_read(); 2651 core->mac[ICR] = 0; 2652 } 2653 2654 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2655 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2656 trace_e1000e_irq_icr_clear_iame(); 2657 core->mac[ICR] = 0; 2658 trace_e1000e_irq_icr_process_iame(); 2659 e1000e_clear_ims_bits(core, core->mac[IAM]); 2660 } 2661 2662 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2663 e1000e_update_interrupt_state(core); 2664 return ret; 2665 } 2666 2667 static uint32_t 2668 e1000e_mac_read_clr4(E1000ECore *core, int index) 2669 { 2670 uint32_t ret = core->mac[index]; 2671 2672 core->mac[index] = 0; 2673 return ret; 2674 } 2675 2676 static uint32_t 2677 e1000e_mac_read_clr8(E1000ECore *core, int index) 2678 { 2679 uint32_t ret = core->mac[index]; 2680 2681 core->mac[index] = 0; 2682 core->mac[index - 1] = 0; 2683 return ret; 2684 } 2685 2686 static uint32_t 2687 e1000e_get_ctrl(E1000ECore *core, int index) 2688 { 2689 uint32_t val = core->mac[CTRL]; 2690 2691 trace_e1000e_link_read_params( 2692 !!(val & E1000_CTRL_ASDE), 2693 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2694 !!(val & E1000_CTRL_FRCSPD), 2695 !!(val & E1000_CTRL_FRCDPX), 2696 !!(val & E1000_CTRL_RFCE), 2697 !!(val & E1000_CTRL_TFCE)); 2698 2699 return val; 2700 } 2701 2702 static uint32_t 2703 e1000e_get_status(E1000ECore *core, int index) 2704 { 2705 uint32_t res = core->mac[STATUS]; 2706 2707 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2708 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2709 } 2710 2711 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2712 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2713 } else { 2714 res |= E1000_STATUS_FD; 2715 } 2716 2717 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2718 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2719 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2720 case E1000_CTRL_SPD_10: 2721 res |= E1000_STATUS_SPEED_10; 2722 break; 2723 case E1000_CTRL_SPD_100: 2724 res |= E1000_STATUS_SPEED_100; 2725 break; 2726 case E1000_CTRL_SPD_1000: 2727 default: 2728 res |= E1000_STATUS_SPEED_1000; 2729 break; 2730 } 2731 } else { 2732 res |= E1000_STATUS_SPEED_1000; 2733 } 2734 2735 trace_e1000e_link_status( 2736 !!(res & E1000_STATUS_LU), 2737 !!(res & E1000_STATUS_FD), 2738 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2739 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2740 2741 return res; 2742 } 2743 2744 static uint32_t 2745 e1000e_get_tarc(E1000ECore *core, int index) 2746 { 2747 return core->mac[index] & ((BIT(11) - 1) | 2748 BIT(27) | 2749 BIT(28) | 2750 BIT(29) | 2751 BIT(30)); 2752 } 2753 2754 static void 2755 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2756 { 2757 core->mac[index] = val; 2758 } 2759 2760 static void 2761 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2762 { 2763 uint32_t macaddr[2]; 2764 2765 core->mac[index] = val; 2766 2767 macaddr[0] = cpu_to_le32(core->mac[RA]); 2768 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2769 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2770 (uint8_t *) macaddr); 2771 2772 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2773 } 2774 2775 static void 2776 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2777 { 2778 static const uint32_t ro_bits = E1000_EECD_PRES | 2779 E1000_EECD_AUTO_RD | 2780 E1000_EECD_SIZE_EX_MASK; 2781 2782 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2783 } 2784 2785 static void 2786 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2787 { 2788 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2789 uint32_t flags = 0; 2790 uint32_t data = 0; 2791 2792 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2793 data = core->eeprom[addr]; 2794 flags = E1000_EERW_DONE; 2795 } 2796 2797 core->mac[EERD] = flags | 2798 (addr << E1000_EERW_ADDR_SHIFT) | 2799 (data << E1000_EERW_DATA_SHIFT); 2800 } 2801 2802 static void 2803 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2804 { 2805 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2806 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2807 uint32_t flags = 0; 2808 2809 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2810 core->eeprom[addr] = data; 2811 flags = E1000_EERW_DONE; 2812 } 2813 2814 core->mac[EERD] = flags | 2815 (addr << E1000_EERW_ADDR_SHIFT) | 2816 (data << E1000_EERW_DATA_SHIFT); 2817 } 2818 2819 static void 2820 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2821 { 2822 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2823 } 2824 2825 static void 2826 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2827 { 2828 uint32_t interval = val & 0xffff; 2829 2830 trace_e1000e_irq_itr_set(val); 2831 2832 core->itr_guest_value = interval; 2833 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2834 } 2835 2836 static void 2837 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2838 { 2839 uint32_t interval = val & 0xffff; 2840 uint32_t eitr_num = index - EITR; 2841 2842 trace_e1000e_irq_eitr_set(eitr_num, val); 2843 2844 core->eitr_guest_value[eitr_num] = interval; 2845 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2846 } 2847 2848 static void 2849 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2850 { 2851 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) { 2852 2853 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2854 qemu_log_mask(LOG_GUEST_ERROR, 2855 "e1000e: PSRCTL.BSIZE0 cannot be zero"); 2856 return; 2857 } 2858 2859 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2860 qemu_log_mask(LOG_GUEST_ERROR, 2861 "e1000e: PSRCTL.BSIZE1 cannot be zero"); 2862 return; 2863 } 2864 } 2865 2866 core->mac[PSRCTL] = val; 2867 } 2868 2869 static void 2870 e1000e_update_rx_offloads(E1000ECore *core) 2871 { 2872 int cso_state = e1000e_rx_l4_cso_enabled(core); 2873 2874 trace_e1000e_rx_set_cso(cso_state); 2875 2876 if (core->has_vnet) { 2877 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2878 cso_state, 0, 0, 0, 0); 2879 } 2880 } 2881 2882 static void 2883 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2884 { 2885 core->mac[RXCSUM] = val; 2886 e1000e_update_rx_offloads(core); 2887 } 2888 2889 static void 2890 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2891 { 2892 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2893 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2894 } 2895 2896 static uint32_t e1000e_get_systiml(E1000ECore *core, int index) 2897 { 2898 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH); 2899 return core->mac[SYSTIML]; 2900 } 2901 2902 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index) 2903 { 2904 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID; 2905 return core->mac[RXSATRH]; 2906 } 2907 2908 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index) 2909 { 2910 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID; 2911 return core->mac[TXSTMPH]; 2912 } 2913 2914 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val) 2915 { 2916 e1000x_set_timinca(core->mac, &core->timadj, val); 2917 } 2918 2919 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val) 2920 { 2921 core->mac[TIMADJH] = val; 2922 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32); 2923 } 2924 2925 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2926 typedef uint32_t (*readops)(E1000ECore *, int); 2927 static const readops e1000e_macreg_readops[] = { 2928 e1000e_getreg(PBA), 2929 e1000e_getreg(WUFC), 2930 e1000e_getreg(MANC), 2931 e1000e_getreg(TOTL), 2932 e1000e_getreg(RDT0), 2933 e1000e_getreg(RDBAH0), 2934 e1000e_getreg(TDBAL1), 2935 e1000e_getreg(RDLEN0), 2936 e1000e_getreg(RDH1), 2937 e1000e_getreg(LATECOL), 2938 e1000e_getreg(SEQEC), 2939 e1000e_getreg(XONTXC), 2940 e1000e_getreg(AIT), 2941 e1000e_getreg(TDFH), 2942 e1000e_getreg(TDFT), 2943 e1000e_getreg(TDFHS), 2944 e1000e_getreg(TDFTS), 2945 e1000e_getreg(TDFPC), 2946 e1000e_getreg(WUS), 2947 e1000e_getreg(PBS), 2948 e1000e_getreg(RDFH), 2949 e1000e_getreg(RDFT), 2950 e1000e_getreg(RDFHS), 2951 e1000e_getreg(RDFTS), 2952 e1000e_getreg(RDFPC), 2953 e1000e_getreg(GORCL), 2954 e1000e_getreg(MGTPRC), 2955 e1000e_getreg(EERD), 2956 e1000e_getreg(EIAC), 2957 e1000e_getreg(PSRCTL), 2958 e1000e_getreg(MANC2H), 2959 e1000e_getreg(RXCSUM), 2960 e1000e_getreg(GSCL_3), 2961 e1000e_getreg(GSCN_2), 2962 e1000e_getreg(RSRPD), 2963 e1000e_getreg(RDBAL1), 2964 e1000e_getreg(FCAH), 2965 e1000e_getreg(FCRTH), 2966 e1000e_getreg(FLOP), 2967 e1000e_getreg(FLASHT), 2968 e1000e_getreg(RXSTMPH), 2969 e1000e_getreg(TXSTMPL), 2970 e1000e_getreg(TIMADJL), 2971 e1000e_getreg(TXDCTL), 2972 e1000e_getreg(RDH0), 2973 e1000e_getreg(TDT1), 2974 e1000e_getreg(TNCRS), 2975 e1000e_getreg(RJC), 2976 e1000e_getreg(IAM), 2977 e1000e_getreg(GSCL_2), 2978 e1000e_getreg(RDBAH1), 2979 e1000e_getreg(FLSWDATA), 2980 e1000e_getreg(TIPG), 2981 e1000e_getreg(FLMNGCTL), 2982 e1000e_getreg(FLMNGCNT), 2983 e1000e_getreg(TSYNCTXCTL), 2984 e1000e_getreg(EXTCNF_SIZE), 2985 e1000e_getreg(EXTCNF_CTRL), 2986 e1000e_getreg(EEMNGDATA), 2987 e1000e_getreg(CTRL_EXT), 2988 e1000e_getreg(SYSTIMH), 2989 e1000e_getreg(EEMNGCTL), 2990 e1000e_getreg(FLMNGDATA), 2991 e1000e_getreg(TSYNCRXCTL), 2992 e1000e_getreg(TDH), 2993 e1000e_getreg(LEDCTL), 2994 e1000e_getreg(TCTL), 2995 e1000e_getreg(TDBAL), 2996 e1000e_getreg(TDLEN), 2997 e1000e_getreg(TDH1), 2998 e1000e_getreg(RADV), 2999 e1000e_getreg(ECOL), 3000 e1000e_getreg(DC), 3001 e1000e_getreg(RLEC), 3002 e1000e_getreg(XOFFTXC), 3003 e1000e_getreg(RFC), 3004 e1000e_getreg(RNBC), 3005 e1000e_getreg(MGTPTC), 3006 e1000e_getreg(TIMINCA), 3007 e1000e_getreg(RXCFGL), 3008 e1000e_getreg(MFUTP01), 3009 e1000e_getreg(FACTPS), 3010 e1000e_getreg(GSCL_1), 3011 e1000e_getreg(GSCN_0), 3012 e1000e_getreg(GCR2), 3013 e1000e_getreg(RDT1), 3014 e1000e_getreg(PBACLR), 3015 e1000e_getreg(FCTTV), 3016 e1000e_getreg(EEWR), 3017 e1000e_getreg(FLSWCTL), 3018 e1000e_getreg(RXDCTL1), 3019 e1000e_getreg(RXSATRL), 3020 e1000e_getreg(RXUDP), 3021 e1000e_getreg(TORL), 3022 e1000e_getreg(TDLEN1), 3023 e1000e_getreg(MCC), 3024 e1000e_getreg(WUC), 3025 e1000e_getreg(EECD), 3026 e1000e_getreg(MFUTP23), 3027 e1000e_getreg(RAID), 3028 e1000e_getreg(FCRTV), 3029 e1000e_getreg(TXDCTL1), 3030 e1000e_getreg(RCTL), 3031 e1000e_getreg(TDT), 3032 e1000e_getreg(MDIC), 3033 e1000e_getreg(FCRUC), 3034 e1000e_getreg(VET), 3035 e1000e_getreg(RDBAL0), 3036 e1000e_getreg(TDBAH1), 3037 e1000e_getreg(RDTR), 3038 e1000e_getreg(SCC), 3039 e1000e_getreg(COLC), 3040 e1000e_getreg(CEXTERR), 3041 e1000e_getreg(XOFFRXC), 3042 e1000e_getreg(IPAV), 3043 e1000e_getreg(GOTCL), 3044 e1000e_getreg(MGTPDC), 3045 e1000e_getreg(GCR), 3046 e1000e_getreg(IVAR), 3047 e1000e_getreg(POEMB), 3048 e1000e_getreg(MFVAL), 3049 e1000e_getreg(FUNCTAG), 3050 e1000e_getreg(GSCL_4), 3051 e1000e_getreg(GSCN_3), 3052 e1000e_getreg(MRQC), 3053 e1000e_getreg(RDLEN1), 3054 e1000e_getreg(FCT), 3055 e1000e_getreg(FLA), 3056 e1000e_getreg(FLOL), 3057 e1000e_getreg(RXDCTL), 3058 e1000e_getreg(RXSTMPL), 3059 e1000e_getreg(TIMADJH), 3060 e1000e_getreg(FCRTL), 3061 e1000e_getreg(TDBAH), 3062 e1000e_getreg(TADV), 3063 e1000e_getreg(XONRXC), 3064 e1000e_getreg(TSCTFC), 3065 e1000e_getreg(RFCTL), 3066 e1000e_getreg(GSCN_1), 3067 e1000e_getreg(FCAL), 3068 e1000e_getreg(FLSWCNT), 3069 3070 [TOTH] = e1000e_mac_read_clr8, 3071 [GOTCH] = e1000e_mac_read_clr8, 3072 [PRC64] = e1000e_mac_read_clr4, 3073 [PRC255] = e1000e_mac_read_clr4, 3074 [PRC1023] = e1000e_mac_read_clr4, 3075 [PTC64] = e1000e_mac_read_clr4, 3076 [PTC255] = e1000e_mac_read_clr4, 3077 [PTC1023] = e1000e_mac_read_clr4, 3078 [GPRC] = e1000e_mac_read_clr4, 3079 [TPT] = e1000e_mac_read_clr4, 3080 [RUC] = e1000e_mac_read_clr4, 3081 [BPRC] = e1000e_mac_read_clr4, 3082 [MPTC] = e1000e_mac_read_clr4, 3083 [IAC] = e1000e_mac_read_clr4, 3084 [ICR] = e1000e_mac_icr_read, 3085 [STATUS] = e1000e_get_status, 3086 [TARC0] = e1000e_get_tarc, 3087 [ICS] = e1000e_mac_ics_read, 3088 [TORH] = e1000e_mac_read_clr8, 3089 [GORCH] = e1000e_mac_read_clr8, 3090 [PRC127] = e1000e_mac_read_clr4, 3091 [PRC511] = e1000e_mac_read_clr4, 3092 [PRC1522] = e1000e_mac_read_clr4, 3093 [PTC127] = e1000e_mac_read_clr4, 3094 [PTC511] = e1000e_mac_read_clr4, 3095 [PTC1522] = e1000e_mac_read_clr4, 3096 [GPTC] = e1000e_mac_read_clr4, 3097 [TPR] = e1000e_mac_read_clr4, 3098 [ROC] = e1000e_mac_read_clr4, 3099 [MPRC] = e1000e_mac_read_clr4, 3100 [BPTC] = e1000e_mac_read_clr4, 3101 [TSCTC] = e1000e_mac_read_clr4, 3102 [ITR] = e1000e_mac_itr_read, 3103 [CTRL] = e1000e_get_ctrl, 3104 [TARC1] = e1000e_get_tarc, 3105 [SWSM] = e1000e_mac_swsm_read, 3106 [IMS] = e1000e_mac_ims_read, 3107 [SYSTIML] = e1000e_get_systiml, 3108 [RXSATRH] = e1000e_get_rxsatrh, 3109 [TXSTMPH] = e1000e_get_txstmph, 3110 3111 [CRCERRS ... MPC] = e1000e_mac_readreg, 3112 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3113 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3114 [RA ... RA + 31] = e1000e_mac_readreg, 3115 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3116 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg, 3117 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg, 3118 [FFMT ... FFMT + 254] = e1000e_mac_readreg, 3119 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3120 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3121 [FFLT ... FFLT + 10] = e1000e_mac_readreg, 3122 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3123 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3124 [RETA ... RETA + 31] = e1000e_mac_readreg, 3125 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3126 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3127 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3128 }; 3129 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3130 3131 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3132 typedef void (*writeops)(E1000ECore *, int, uint32_t); 3133 static const writeops e1000e_macreg_writeops[] = { 3134 e1000e_putreg(PBA), 3135 e1000e_putreg(SWSM), 3136 e1000e_putreg(WUFC), 3137 e1000e_putreg(RDBAH1), 3138 e1000e_putreg(TDBAH), 3139 e1000e_putreg(TXDCTL), 3140 e1000e_putreg(RDBAH0), 3141 e1000e_putreg(LEDCTL), 3142 e1000e_putreg(FCAL), 3143 e1000e_putreg(FCRUC), 3144 e1000e_putreg(WUC), 3145 e1000e_putreg(WUS), 3146 e1000e_putreg(IPAV), 3147 e1000e_putreg(TDBAH1), 3148 e1000e_putreg(IAM), 3149 e1000e_putreg(EIAC), 3150 e1000e_putreg(IVAR), 3151 e1000e_putreg(TARC0), 3152 e1000e_putreg(TARC1), 3153 e1000e_putreg(FLSWDATA), 3154 e1000e_putreg(POEMB), 3155 e1000e_putreg(MFUTP01), 3156 e1000e_putreg(MFUTP23), 3157 e1000e_putreg(MANC), 3158 e1000e_putreg(MANC2H), 3159 e1000e_putreg(MFVAL), 3160 e1000e_putreg(EXTCNF_CTRL), 3161 e1000e_putreg(FACTPS), 3162 e1000e_putreg(FUNCTAG), 3163 e1000e_putreg(GSCL_1), 3164 e1000e_putreg(GSCL_2), 3165 e1000e_putreg(GSCL_3), 3166 e1000e_putreg(GSCL_4), 3167 e1000e_putreg(GSCN_0), 3168 e1000e_putreg(GSCN_1), 3169 e1000e_putreg(GSCN_2), 3170 e1000e_putreg(GSCN_3), 3171 e1000e_putreg(GCR2), 3172 e1000e_putreg(MRQC), 3173 e1000e_putreg(FLOP), 3174 e1000e_putreg(FLOL), 3175 e1000e_putreg(FLSWCTL), 3176 e1000e_putreg(FLSWCNT), 3177 e1000e_putreg(FLA), 3178 e1000e_putreg(RXDCTL1), 3179 e1000e_putreg(TXDCTL1), 3180 e1000e_putreg(TIPG), 3181 e1000e_putreg(RXSTMPH), 3182 e1000e_putreg(RXSTMPL), 3183 e1000e_putreg(RXSATRL), 3184 e1000e_putreg(RXSATRH), 3185 e1000e_putreg(TXSTMPL), 3186 e1000e_putreg(TXSTMPH), 3187 e1000e_putreg(SYSTIML), 3188 e1000e_putreg(SYSTIMH), 3189 e1000e_putreg(TIMADJL), 3190 e1000e_putreg(RXUDP), 3191 e1000e_putreg(RXCFGL), 3192 e1000e_putreg(TSYNCRXCTL), 3193 e1000e_putreg(TSYNCTXCTL), 3194 e1000e_putreg(EXTCNF_SIZE), 3195 e1000e_putreg(EEMNGCTL), 3196 e1000e_putreg(RA), 3197 3198 [TDH1] = e1000e_set_16bit, 3199 [TDT1] = e1000e_set_tdt, 3200 [TCTL] = e1000e_set_tctl, 3201 [TDT] = e1000e_set_tdt, 3202 [MDIC] = e1000e_set_mdic, 3203 [ICS] = e1000e_set_ics, 3204 [TDH] = e1000e_set_16bit, 3205 [RDH0] = e1000e_set_16bit, 3206 [RDT0] = e1000e_set_rdt, 3207 [IMC] = e1000e_set_imc, 3208 [IMS] = e1000e_set_ims, 3209 [ICR] = e1000e_set_icr, 3210 [EECD] = e1000e_set_eecd, 3211 [RCTL] = e1000e_set_rx_control, 3212 [CTRL] = e1000e_set_ctrl, 3213 [RDTR] = e1000e_set_rdtr, 3214 [RADV] = e1000e_set_16bit, 3215 [TADV] = e1000e_set_16bit, 3216 [ITR] = e1000e_set_itr, 3217 [EERD] = e1000e_set_eerd, 3218 [AIT] = e1000e_set_16bit, 3219 [TDFH] = e1000e_set_13bit, 3220 [TDFT] = e1000e_set_13bit, 3221 [TDFHS] = e1000e_set_13bit, 3222 [TDFTS] = e1000e_set_13bit, 3223 [TDFPC] = e1000e_set_13bit, 3224 [RDFH] = e1000e_set_13bit, 3225 [RDFHS] = e1000e_set_13bit, 3226 [RDFT] = e1000e_set_13bit, 3227 [RDFTS] = e1000e_set_13bit, 3228 [RDFPC] = e1000e_set_13bit, 3229 [PBS] = e1000e_set_6bit, 3230 [GCR] = e1000e_set_gcr, 3231 [PSRCTL] = e1000e_set_psrctl, 3232 [RXCSUM] = e1000e_set_rxcsum, 3233 [RAID] = e1000e_set_16bit, 3234 [RSRPD] = e1000e_set_12bit, 3235 [TIDV] = e1000e_set_tidv, 3236 [TDLEN1] = e1000e_set_dlen, 3237 [TDLEN] = e1000e_set_dlen, 3238 [RDLEN0] = e1000e_set_dlen, 3239 [RDLEN1] = e1000e_set_dlen, 3240 [TDBAL] = e1000e_set_dbal, 3241 [TDBAL1] = e1000e_set_dbal, 3242 [RDBAL0] = e1000e_set_dbal, 3243 [RDBAL1] = e1000e_set_dbal, 3244 [RDH1] = e1000e_set_16bit, 3245 [RDT1] = e1000e_set_rdt, 3246 [STATUS] = e1000e_set_status, 3247 [PBACLR] = e1000e_set_pbaclr, 3248 [CTRL_EXT] = e1000e_set_ctrlext, 3249 [FCAH] = e1000e_set_16bit, 3250 [FCT] = e1000e_set_16bit, 3251 [FCTTV] = e1000e_set_16bit, 3252 [FCRTV] = e1000e_set_16bit, 3253 [FCRTH] = e1000e_set_fcrth, 3254 [FCRTL] = e1000e_set_fcrtl, 3255 [VET] = e1000e_set_vet, 3256 [RXDCTL] = e1000e_set_rxdctl, 3257 [FLASHT] = e1000e_set_16bit, 3258 [EEWR] = e1000e_set_eewr, 3259 [CTRL_DUP] = e1000e_set_ctrl, 3260 [RFCTL] = e1000e_set_rfctl, 3261 [RA + 1] = e1000e_mac_setmacaddr, 3262 [TIMINCA] = e1000e_set_timinca, 3263 [TIMADJH] = e1000e_set_timadjh, 3264 3265 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3266 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3267 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3268 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3269 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg, 3270 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg, 3271 [FFMT ... FFMT + 254] = e1000e_set_4bit, 3272 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3273 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3274 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3275 [FFLT ... FFLT + 10] = e1000e_set_11bit, 3276 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3277 [RETA ... RETA + 31] = e1000e_mac_writereg, 3278 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3279 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3280 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3281 }; 3282 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3283 3284 enum { MAC_ACCESS_PARTIAL = 1 }; 3285 3286 /* 3287 * The array below combines alias offsets of the index values for the 3288 * MAC registers that have aliases, with the indication of not fully 3289 * implemented registers (lowest bit). This combination is possible 3290 * because all of the offsets are even. 3291 */ 3292 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3293 /* Alias index offsets */ 3294 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3295 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3296 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3297 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3298 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3299 [RA_A ... RA_A + 31] = 0x14f0, 3300 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400, 3301 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3302 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3303 /* Access options */ 3304 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3305 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3306 [RDFPC] = MAC_ACCESS_PARTIAL, 3307 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3308 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3309 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3310 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3311 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3312 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3313 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3314 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3315 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3316 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3317 }; 3318 3319 void 3320 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3321 { 3322 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3323 3324 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3325 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3326 trace_e1000e_wrn_regs_write_trivial(index << 2); 3327 } 3328 trace_e1000e_core_write(index << 2, size, val); 3329 e1000e_macreg_writeops[index](core, index, val); 3330 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3331 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3332 } else { 3333 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3334 } 3335 } 3336 3337 uint64_t 3338 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3339 { 3340 uint64_t val; 3341 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3342 3343 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3344 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3345 trace_e1000e_wrn_regs_read_trivial(index << 2); 3346 } 3347 val = e1000e_macreg_readops[index](core, index); 3348 trace_e1000e_core_read(index << 2, size, val); 3349 return val; 3350 } else { 3351 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3352 } 3353 return 0; 3354 } 3355 3356 static inline void 3357 e1000e_autoneg_pause(E1000ECore *core) 3358 { 3359 timer_del(core->autoneg_timer); 3360 } 3361 3362 static void 3363 e1000e_autoneg_resume(E1000ECore *core) 3364 { 3365 if (e1000e_have_autoneg(core) && 3366 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) { 3367 qemu_get_queue(core->owner_nic)->link_down = false; 3368 timer_mod(core->autoneg_timer, 3369 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3370 } 3371 } 3372 3373 static void 3374 e1000e_vm_state_change(void *opaque, bool running, RunState state) 3375 { 3376 E1000ECore *core = opaque; 3377 3378 if (running) { 3379 trace_e1000e_vm_state_running(); 3380 e1000e_intrmgr_resume(core); 3381 e1000e_autoneg_resume(core); 3382 } else { 3383 trace_e1000e_vm_state_stopped(); 3384 e1000e_autoneg_pause(core); 3385 e1000e_intrmgr_pause(core); 3386 } 3387 } 3388 3389 void 3390 e1000e_core_pci_realize(E1000ECore *core, 3391 const uint16_t *eeprom_templ, 3392 uint32_t eeprom_size, 3393 const uint8_t *macaddr) 3394 { 3395 int i; 3396 3397 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3398 e1000e_autoneg_timer, core); 3399 e1000e_intrmgr_pci_realize(core); 3400 3401 core->vmstate = 3402 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3403 3404 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3405 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS); 3406 } 3407 3408 net_rx_pkt_init(&core->rx_pkt); 3409 3410 e1000x_core_prepare_eeprom(core->eeprom, 3411 eeprom_templ, 3412 eeprom_size, 3413 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3414 macaddr); 3415 e1000e_update_rx_offloads(core); 3416 } 3417 3418 void 3419 e1000e_core_pci_uninit(E1000ECore *core) 3420 { 3421 int i; 3422 3423 timer_free(core->autoneg_timer); 3424 3425 e1000e_intrmgr_pci_unint(core); 3426 3427 qemu_del_vm_change_state_handler(core->vmstate); 3428 3429 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3430 net_tx_pkt_reset(core->tx[i].tx_pkt, 3431 net_tx_pkt_unmap_frag_pci, core->owner); 3432 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3433 } 3434 3435 net_rx_pkt_uninit(core->rx_pkt); 3436 } 3437 3438 static const uint16_t 3439 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3440 [0] = { 3441 [MII_BMCR] = MII_BMCR_SPEED1000 | 3442 MII_BMCR_FD | 3443 MII_BMCR_AUTOEN, 3444 3445 [MII_BMSR] = MII_BMSR_EXTCAP | 3446 MII_BMSR_LINK_ST | 3447 MII_BMSR_AUTONEG | 3448 MII_BMSR_MFPS | 3449 MII_BMSR_EXTSTAT | 3450 MII_BMSR_10T_HD | 3451 MII_BMSR_10T_FD | 3452 MII_BMSR_100TX_HD | 3453 MII_BMSR_100TX_FD, 3454 3455 [MII_PHYID1] = 0x141, 3456 [MII_PHYID2] = E1000_PHY_ID2_82574x, 3457 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 | 3458 MII_ANAR_10FD | MII_ANAR_TX | 3459 MII_ANAR_TXFD | MII_ANAR_PAUSE | 3460 MII_ANAR_PAUSE_ASYM, 3461 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD | 3462 MII_ANLPAR_TX | MII_ANLPAR_TXFD | 3463 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE, 3464 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY, 3465 [MII_ANNP] = 1 | MII_ANNP_MP, 3466 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL | 3467 MII_CTRL1000_PORT | MII_CTRL1000_MASTER, 3468 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL | 3469 MII_STAT1000_ROK | MII_STAT1000_LOK, 3470 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD, 3471 3472 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3473 BIT(12) | BIT(13), 3474 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3475 }, 3476 [2] = { 3477 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3478 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3479 }, 3480 [3] = { 3481 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3482 } 3483 }; 3484 3485 static const uint32_t e1000e_mac_reg_init[] = { 3486 [PBA] = 0x00140014, 3487 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3488 [EXTCNF_CTRL] = BIT(3), 3489 [EEMNGCTL] = BIT(31), 3490 [FLASHT] = 0x2, 3491 [FLSWCTL] = BIT(30) | BIT(31), 3492 [FLOL] = BIT(0), 3493 [RXDCTL] = BIT(16), 3494 [RXDCTL1] = BIT(16), 3495 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3496 [RXCFGL] = 0x88F7, 3497 [RXUDP] = 0x319, 3498 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3499 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3500 E1000_CTRL_ADVD3WUC, 3501 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3502 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3503 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3504 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3505 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3506 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3507 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3508 [EERD] = E1000_EERW_DONE, 3509 [EEWR] = E1000_EERW_DONE, 3510 [GCR] = E1000_L0S_ADJUST | 3511 E1000_L1_ENTRY_LATENCY_MSB | 3512 E1000_L1_ENTRY_LATENCY_LSB, 3513 [TDFH] = 0x600, 3514 [TDFT] = 0x600, 3515 [TDFHS] = 0x600, 3516 [TDFTS] = 0x600, 3517 [POEMB] = 0x30D, 3518 [PBS] = 0x028, 3519 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3520 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3521 [SWSM] = 1, 3522 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3523 [ITR] = E1000E_MIN_XITR, 3524 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3525 }; 3526 3527 static void e1000e_reset(E1000ECore *core, bool sw) 3528 { 3529 int i; 3530 3531 timer_del(core->autoneg_timer); 3532 3533 e1000e_intrmgr_reset(core); 3534 3535 memset(core->phy, 0, sizeof core->phy); 3536 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3537 3538 for (i = 0; i < E1000E_MAC_SIZE; i++) { 3539 if (sw && (i == PBA || i == PBS || i == FLA)) { 3540 continue; 3541 } 3542 3543 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ? 3544 e1000e_mac_reg_init[i] : 0; 3545 } 3546 3547 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3548 3549 if (qemu_get_queue(core->owner_nic)->link_down) { 3550 e1000e_link_down(core); 3551 } 3552 3553 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3554 3555 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3556 net_tx_pkt_reset(core->tx[i].tx_pkt, 3557 net_tx_pkt_unmap_frag_pci, core->owner); 3558 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3559 core->tx[i].skip_cp = false; 3560 } 3561 } 3562 3563 void 3564 e1000e_core_reset(E1000ECore *core) 3565 { 3566 e1000e_reset(core, false); 3567 } 3568 3569 void e1000e_core_pre_save(E1000ECore *core) 3570 { 3571 int i; 3572 NetClientState *nc = qemu_get_queue(core->owner_nic); 3573 3574 /* 3575 * If link is down and auto-negotiation is supported and ongoing, 3576 * complete auto-negotiation immediately. This allows us to look 3577 * at MII_BMSR_AN_COMP to infer link status on load. 3578 */ 3579 if (nc->link_down && e1000e_have_autoneg(core)) { 3580 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP; 3581 e1000e_update_flowctl_status(core); 3582 } 3583 3584 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3585 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3586 core->tx[i].skip_cp = true; 3587 } 3588 } 3589 } 3590 3591 int 3592 e1000e_core_post_load(E1000ECore *core) 3593 { 3594 NetClientState *nc = qemu_get_queue(core->owner_nic); 3595 3596 /* 3597 * nc.link_down can't be migrated, so infer link_down according 3598 * to link status bit in core.mac[STATUS]. 3599 */ 3600 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3601 3602 return 0; 3603 } 3604