1 /* 2 * Core code for QEMU e1000e emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "sysemu/sysemu.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "hw/pci/msi.h" 41 #include "hw/pci/msix.h" 42 43 #include "net_tx_pkt.h" 44 #include "net_rx_pkt.h" 45 46 #include "e1000x_common.h" 47 #include "e1000e_core.h" 48 49 #include "trace.h" 50 51 #define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per 52 second according to spec 10.2.4.2 */ 53 #define E1000E_MAX_TX_FRAGS (64) 54 55 static void 56 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val); 57 58 static inline void 59 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) 60 { 61 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) { 62 trace_e1000e_wrn_no_ts_support(); 63 } 64 } 65 66 static inline void 67 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) 68 { 69 if (cmd_and_length & E1000_TXD_CMD_SNAP) { 70 trace_e1000e_wrn_no_snap_support(); 71 } 72 } 73 74 static inline void 75 e1000e_raise_legacy_irq(E1000ECore *core) 76 { 77 trace_e1000e_irq_legacy_notify(true); 78 e1000x_inc_reg_if_not_full(core->mac, IAC); 79 pci_set_irq(core->owner, 1); 80 } 81 82 static inline void 83 e1000e_lower_legacy_irq(E1000ECore *core) 84 { 85 trace_e1000e_irq_legacy_notify(false); 86 pci_set_irq(core->owner, 0); 87 } 88 89 static inline void 90 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer) 91 { 92 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] * 93 timer->delay_resolution_ns; 94 95 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns); 96 97 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns); 98 99 timer->running = true; 100 } 101 102 static void 103 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer) 104 { 105 if (timer->running) { 106 e1000e_intrmgr_rearm_timer(timer); 107 } 108 } 109 110 static void 111 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer) 112 { 113 if (timer->running) { 114 timer_del(timer->timer); 115 } 116 } 117 118 static inline void 119 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer) 120 { 121 if (timer->running) { 122 timer_del(timer->timer); 123 timer->running = false; 124 } 125 } 126 127 static inline void 128 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core) 129 { 130 trace_e1000e_irq_fire_delayed_interrupts(); 131 e1000e_set_interrupt_cause(core, 0); 132 } 133 134 static void 135 e1000e_intrmgr_on_timer(void *opaque) 136 { 137 E1000IntrDelayTimer *timer = opaque; 138 139 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2); 140 141 timer->running = false; 142 e1000e_intrmgr_fire_delayed_interrupts(timer->core); 143 } 144 145 static void 146 e1000e_intrmgr_on_throttling_timer(void *opaque) 147 { 148 E1000IntrDelayTimer *timer = opaque; 149 150 assert(!msix_enabled(timer->core->owner)); 151 152 timer->running = false; 153 154 if (!timer->core->itr_intr_pending) { 155 trace_e1000e_irq_throttling_no_pending_interrupts(); 156 return; 157 } 158 159 if (msi_enabled(timer->core->owner)) { 160 trace_e1000e_irq_msi_notify_postponed(); 161 e1000e_set_interrupt_cause(timer->core, 0); 162 } else { 163 trace_e1000e_irq_legacy_notify_postponed(); 164 e1000e_set_interrupt_cause(timer->core, 0); 165 } 166 } 167 168 static void 169 e1000e_intrmgr_on_msix_throttling_timer(void *opaque) 170 { 171 E1000IntrDelayTimer *timer = opaque; 172 int idx = timer - &timer->core->eitr[0]; 173 174 assert(msix_enabled(timer->core->owner)); 175 176 timer->running = false; 177 178 if (!timer->core->eitr_intr_pending[idx]) { 179 trace_e1000e_irq_throttling_no_pending_vec(idx); 180 return; 181 } 182 183 trace_e1000e_irq_msix_notify_postponed_vec(idx); 184 msix_notify(timer->core->owner, idx); 185 } 186 187 static void 188 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create) 189 { 190 int i; 191 192 core->radv.delay_reg = RADV; 193 core->rdtr.delay_reg = RDTR; 194 core->raid.delay_reg = RAID; 195 core->tadv.delay_reg = TADV; 196 core->tidv.delay_reg = TIDV; 197 198 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 199 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 200 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 201 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 202 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES; 203 204 core->radv.core = core; 205 core->rdtr.core = core; 206 core->raid.core = core; 207 core->tadv.core = core; 208 core->tidv.core = core; 209 210 core->itr.core = core; 211 core->itr.delay_reg = ITR; 212 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 213 214 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 215 core->eitr[i].core = core; 216 core->eitr[i].delay_reg = EITR + i; 217 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES; 218 } 219 220 if (!create) { 221 return; 222 } 223 224 core->radv.timer = 225 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv); 226 core->rdtr.timer = 227 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr); 228 core->raid.timer = 229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid); 230 231 core->tadv.timer = 232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv); 233 core->tidv.timer = 234 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv); 235 236 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 237 e1000e_intrmgr_on_throttling_timer, 238 &core->itr); 239 240 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 241 core->eitr[i].timer = 242 timer_new_ns(QEMU_CLOCK_VIRTUAL, 243 e1000e_intrmgr_on_msix_throttling_timer, 244 &core->eitr[i]); 245 } 246 } 247 248 static inline void 249 e1000e_intrmgr_stop_delay_timers(E1000ECore *core) 250 { 251 e1000e_intrmgr_stop_timer(&core->radv); 252 e1000e_intrmgr_stop_timer(&core->rdtr); 253 e1000e_intrmgr_stop_timer(&core->raid); 254 e1000e_intrmgr_stop_timer(&core->tidv); 255 e1000e_intrmgr_stop_timer(&core->tadv); 256 } 257 258 static bool 259 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes) 260 { 261 uint32_t delayable_causes; 262 uint32_t rdtr = core->mac[RDTR]; 263 uint32_t radv = core->mac[RADV]; 264 uint32_t raid = core->mac[RAID]; 265 266 if (msix_enabled(core->owner)) { 267 return false; 268 } 269 270 delayable_causes = E1000_ICR_RXQ0 | 271 E1000_ICR_RXQ1 | 272 E1000_ICR_RXT0; 273 274 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) { 275 delayable_causes |= E1000_ICR_ACK; 276 } 277 278 /* Clean up all causes that may be delayed */ 279 core->delayed_causes |= *causes & delayable_causes; 280 *causes &= ~delayable_causes; 281 282 /* Check if delayed RX interrupts disabled by client 283 or if there are causes that cannot be delayed */ 284 if ((rdtr == 0) || (causes != 0)) { 285 return false; 286 } 287 288 /* Check if delayed RX ACK interrupts disabled by client 289 and there is an ACK packet received */ 290 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) { 291 return false; 292 } 293 294 /* All causes delayed */ 295 e1000e_intrmgr_rearm_timer(&core->rdtr); 296 297 if (!core->radv.running && (radv != 0)) { 298 e1000e_intrmgr_rearm_timer(&core->radv); 299 } 300 301 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) { 302 e1000e_intrmgr_rearm_timer(&core->raid); 303 } 304 305 return true; 306 } 307 308 static bool 309 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes) 310 { 311 static const uint32_t delayable_causes = E1000_ICR_TXQ0 | 312 E1000_ICR_TXQ1 | 313 E1000_ICR_TXQE | 314 E1000_ICR_TXDW; 315 316 if (msix_enabled(core->owner)) { 317 return false; 318 } 319 320 /* Clean up all causes that may be delayed */ 321 core->delayed_causes |= *causes & delayable_causes; 322 *causes &= ~delayable_causes; 323 324 /* If there are causes that cannot be delayed */ 325 if (causes != 0) { 326 return false; 327 } 328 329 /* All causes delayed */ 330 e1000e_intrmgr_rearm_timer(&core->tidv); 331 332 if (!core->tadv.running && (core->mac[TADV] != 0)) { 333 e1000e_intrmgr_rearm_timer(&core->tadv); 334 } 335 336 return true; 337 } 338 339 static uint32_t 340 e1000e_intmgr_collect_delayed_causes(E1000ECore *core) 341 { 342 uint32_t res; 343 344 if (msix_enabled(core->owner)) { 345 assert(core->delayed_causes == 0); 346 return 0; 347 } 348 349 res = core->delayed_causes; 350 core->delayed_causes = 0; 351 352 e1000e_intrmgr_stop_delay_timers(core); 353 354 return res; 355 } 356 357 static void 358 e1000e_intrmgr_fire_all_timers(E1000ECore *core) 359 { 360 int i; 361 uint32_t val = e1000e_intmgr_collect_delayed_causes(core); 362 363 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]); 364 core->mac[ICR] |= val; 365 366 if (core->itr.running) { 367 timer_del(core->itr.timer); 368 e1000e_intrmgr_on_throttling_timer(&core->itr); 369 } 370 371 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 372 if (core->eitr[i].running) { 373 timer_del(core->eitr[i].timer); 374 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]); 375 } 376 } 377 } 378 379 static void 380 e1000e_intrmgr_resume(E1000ECore *core) 381 { 382 int i; 383 384 e1000e_intmgr_timer_resume(&core->radv); 385 e1000e_intmgr_timer_resume(&core->rdtr); 386 e1000e_intmgr_timer_resume(&core->raid); 387 e1000e_intmgr_timer_resume(&core->tidv); 388 e1000e_intmgr_timer_resume(&core->tadv); 389 390 e1000e_intmgr_timer_resume(&core->itr); 391 392 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 393 e1000e_intmgr_timer_resume(&core->eitr[i]); 394 } 395 } 396 397 static void 398 e1000e_intrmgr_pause(E1000ECore *core) 399 { 400 int i; 401 402 e1000e_intmgr_timer_pause(&core->radv); 403 e1000e_intmgr_timer_pause(&core->rdtr); 404 e1000e_intmgr_timer_pause(&core->raid); 405 e1000e_intmgr_timer_pause(&core->tidv); 406 e1000e_intmgr_timer_pause(&core->tadv); 407 408 e1000e_intmgr_timer_pause(&core->itr); 409 410 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 411 e1000e_intmgr_timer_pause(&core->eitr[i]); 412 } 413 } 414 415 static void 416 e1000e_intrmgr_reset(E1000ECore *core) 417 { 418 int i; 419 420 core->delayed_causes = 0; 421 422 e1000e_intrmgr_stop_delay_timers(core); 423 424 e1000e_intrmgr_stop_timer(&core->itr); 425 426 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 427 e1000e_intrmgr_stop_timer(&core->eitr[i]); 428 } 429 } 430 431 static void 432 e1000e_intrmgr_pci_unint(E1000ECore *core) 433 { 434 int i; 435 436 timer_del(core->radv.timer); 437 timer_free(core->radv.timer); 438 timer_del(core->rdtr.timer); 439 timer_free(core->rdtr.timer); 440 timer_del(core->raid.timer); 441 timer_free(core->raid.timer); 442 443 timer_del(core->tadv.timer); 444 timer_free(core->tadv.timer); 445 timer_del(core->tidv.timer); 446 timer_free(core->tidv.timer); 447 448 timer_del(core->itr.timer); 449 timer_free(core->itr.timer); 450 451 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 452 timer_del(core->eitr[i].timer); 453 timer_free(core->eitr[i].timer); 454 } 455 } 456 457 static void 458 e1000e_intrmgr_pci_realize(E1000ECore *core) 459 { 460 e1000e_intrmgr_initialize_all_timers(core, true); 461 } 462 463 static inline bool 464 e1000e_rx_csum_enabled(E1000ECore *core) 465 { 466 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true; 467 } 468 469 static inline bool 470 e1000e_rx_use_legacy_descriptor(E1000ECore *core) 471 { 472 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true; 473 } 474 475 static inline bool 476 e1000e_rx_use_ps_descriptor(E1000ECore *core) 477 { 478 return !e1000e_rx_use_legacy_descriptor(core) && 479 (core->mac[RCTL] & E1000_RCTL_DTYP_PS); 480 } 481 482 static inline bool 483 e1000e_rss_enabled(E1000ECore *core) 484 { 485 return E1000_MRQC_ENABLED(core->mac[MRQC]) && 486 !e1000e_rx_csum_enabled(core) && 487 !e1000e_rx_use_legacy_descriptor(core); 488 } 489 490 typedef struct E1000E_RSSInfo_st { 491 bool enabled; 492 uint32_t hash; 493 uint32_t queue; 494 uint32_t type; 495 } E1000E_RSSInfo; 496 497 static uint32_t 498 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt) 499 { 500 bool isip4, isip6, isudp, istcp; 501 502 assert(e1000e_rss_enabled(core)); 503 504 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 505 506 if (isip4) { 507 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 508 509 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC], 510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]), 511 E1000_MRQC_EN_IPV4(core->mac[MRQC])); 512 513 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) { 514 return E1000_MRQ_RSS_TYPE_IPV4TCP; 515 } 516 517 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) { 518 return E1000_MRQ_RSS_TYPE_IPV4; 519 } 520 } else if (isip6) { 521 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt); 522 523 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS; 524 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS; 525 526 trace_e1000e_rx_rss_ip6(core->mac[RFCTL], 527 ex_dis, new_ex_dis, istcp, 528 ip6info->has_ext_hdrs, 529 ip6info->rss_ex_dst_valid, 530 ip6info->rss_ex_src_valid, 531 core->mac[MRQC], 532 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]), 533 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]), 534 E1000_MRQC_EN_IPV6(core->mac[MRQC])); 535 536 if ((!ex_dis || !ip6info->has_ext_hdrs) && 537 (!new_ex_dis || !(ip6info->rss_ex_dst_valid || 538 ip6info->rss_ex_src_valid))) { 539 540 if (istcp && !ip6info->fragment && 541 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) { 542 return E1000_MRQ_RSS_TYPE_IPV6TCP; 543 } 544 545 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) { 546 return E1000_MRQ_RSS_TYPE_IPV6EX; 547 } 548 549 } 550 551 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) { 552 return E1000_MRQ_RSS_TYPE_IPV6; 553 } 554 555 } 556 557 return E1000_MRQ_RSS_TYPE_NONE; 558 } 559 560 static uint32_t 561 e1000e_rss_calc_hash(E1000ECore *core, 562 struct NetRxPkt *pkt, 563 E1000E_RSSInfo *info) 564 { 565 NetRxPktRssType type; 566 567 assert(e1000e_rss_enabled(core)); 568 569 switch (info->type) { 570 case E1000_MRQ_RSS_TYPE_IPV4: 571 type = NetPktRssIpV4; 572 break; 573 case E1000_MRQ_RSS_TYPE_IPV4TCP: 574 type = NetPktRssIpV4Tcp; 575 break; 576 case E1000_MRQ_RSS_TYPE_IPV6TCP: 577 type = NetPktRssIpV6Tcp; 578 break; 579 case E1000_MRQ_RSS_TYPE_IPV6: 580 type = NetPktRssIpV6; 581 break; 582 case E1000_MRQ_RSS_TYPE_IPV6EX: 583 type = NetPktRssIpV6Ex; 584 break; 585 default: 586 assert(false); 587 return 0; 588 } 589 590 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]); 591 } 592 593 static void 594 e1000e_rss_parse_packet(E1000ECore *core, 595 struct NetRxPkt *pkt, 596 E1000E_RSSInfo *info) 597 { 598 trace_e1000e_rx_rss_started(); 599 600 if (!e1000e_rss_enabled(core)) { 601 info->enabled = false; 602 info->hash = 0; 603 info->queue = 0; 604 info->type = 0; 605 trace_e1000e_rx_rss_disabled(); 606 return; 607 } 608 609 info->enabled = true; 610 611 info->type = e1000e_rss_get_hash_type(core, pkt); 612 613 trace_e1000e_rx_rss_type(info->type); 614 615 if (info->type == E1000_MRQ_RSS_TYPE_NONE) { 616 info->hash = 0; 617 info->queue = 0; 618 return; 619 } 620 621 info->hash = e1000e_rss_calc_hash(core, pkt, info); 622 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash); 623 } 624 625 static void 626 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx) 627 { 628 if (tx->props.tse && tx->props.cptse) { 629 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss); 630 net_tx_pkt_update_ip_checksums(tx->tx_pkt); 631 e1000x_inc_reg_if_not_full(core->mac, TSCTC); 632 return; 633 } 634 635 if (tx->props.sum_needed & E1000_TXD_POPTS_TXSM) { 636 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0); 637 } 638 639 if (tx->props.sum_needed & E1000_TXD_POPTS_IXSM) { 640 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt); 641 } 642 } 643 644 static bool 645 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index) 646 { 647 int target_queue = MIN(core->max_queue_num, queue_index); 648 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue); 649 650 e1000e_setup_tx_offloads(core, tx); 651 652 net_tx_pkt_dump(tx->tx_pkt); 653 654 if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) || 655 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) { 656 return net_tx_pkt_send_loopback(tx->tx_pkt, queue); 657 } else { 658 return net_tx_pkt_send(tx->tx_pkt, queue); 659 } 660 } 661 662 static void 663 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt) 664 { 665 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511, 666 PTC1023, PTC1522 }; 667 668 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt); 669 670 e1000x_increase_size_stats(core->mac, PTCregs, tot_len); 671 e1000x_inc_reg_if_not_full(core->mac, TPT); 672 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len); 673 674 switch (net_tx_pkt_get_packet_type(tx_pkt)) { 675 case ETH_PKT_BCAST: 676 e1000x_inc_reg_if_not_full(core->mac, BPTC); 677 break; 678 case ETH_PKT_MCAST: 679 e1000x_inc_reg_if_not_full(core->mac, MPTC); 680 break; 681 case ETH_PKT_UCAST: 682 break; 683 default: 684 g_assert_not_reached(); 685 } 686 687 core->mac[GPTC] = core->mac[TPT]; 688 core->mac[GOTCL] = core->mac[TOTL]; 689 core->mac[GOTCH] = core->mac[TOTH]; 690 } 691 692 static void 693 e1000e_process_tx_desc(E1000ECore *core, 694 struct e1000e_tx *tx, 695 struct e1000_tx_desc *dp, 696 int queue_index) 697 { 698 uint32_t txd_lower = le32_to_cpu(dp->lower.data); 699 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D); 700 unsigned int split_size = txd_lower & 0xffff; 701 uint64_t addr; 702 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp; 703 bool eop = txd_lower & E1000_TXD_CMD_EOP; 704 705 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */ 706 e1000x_read_tx_ctx_descr(xp, &tx->props); 707 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length)); 708 return; 709 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) { 710 /* data descriptor */ 711 tx->props.sum_needed = le32_to_cpu(dp->upper.data) >> 8; 712 tx->props.cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0; 713 e1000e_process_ts_option(core, dp); 714 } else { 715 /* legacy descriptor */ 716 e1000e_process_ts_option(core, dp); 717 tx->props.cptse = 0; 718 } 719 720 addr = le64_to_cpu(dp->buffer_addr); 721 722 if (!tx->skip_cp) { 723 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) { 724 tx->skip_cp = true; 725 } 726 } 727 728 if (eop) { 729 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) { 730 if (e1000x_vlan_enabled(core->mac) && 731 e1000x_is_vlan_txd(txd_lower)) { 732 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, 733 le16_to_cpu(dp->upper.fields.special), core->vet); 734 } 735 if (e1000e_tx_pkt_send(core, tx, queue_index)) { 736 e1000e_on_tx_done_update_stats(core, tx->tx_pkt); 737 } 738 } 739 740 tx->skip_cp = false; 741 net_tx_pkt_reset(tx->tx_pkt); 742 743 tx->props.sum_needed = 0; 744 tx->props.cptse = 0; 745 } 746 } 747 748 static inline uint32_t 749 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx) 750 { 751 if (!msix_enabled(core->owner)) { 752 return E1000_ICR_TXDW; 753 } 754 755 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1; 756 } 757 758 static inline uint32_t 759 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx, 760 bool min_threshold_hit) 761 { 762 if (!msix_enabled(core->owner)) { 763 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0); 764 } 765 766 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1; 767 } 768 769 static uint32_t 770 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base, 771 struct e1000_tx_desc *dp, bool *ide, int queue_idx) 772 { 773 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data); 774 775 if (!(txd_lower & E1000_TXD_CMD_RS) && 776 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) { 777 return 0; 778 } 779 780 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false; 781 782 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD; 783 784 dp->upper.data = cpu_to_le32(txd_upper); 785 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp), 786 &dp->upper, sizeof(dp->upper)); 787 return e1000e_tx_wb_interrupt_cause(core, queue_idx); 788 } 789 790 typedef struct E1000E_RingInfo_st { 791 int dbah; 792 int dbal; 793 int dlen; 794 int dh; 795 int dt; 796 int idx; 797 } E1000E_RingInfo; 798 799 static inline bool 800 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r) 801 { 802 return core->mac[r->dh] == core->mac[r->dt]; 803 } 804 805 static inline uint64_t 806 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r) 807 { 808 uint64_t bah = core->mac[r->dbah]; 809 uint64_t bal = core->mac[r->dbal]; 810 811 return (bah << 32) + bal; 812 } 813 814 static inline uint64_t 815 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r) 816 { 817 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh]; 818 } 819 820 static inline void 821 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count) 822 { 823 core->mac[r->dh] += count; 824 825 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) { 826 core->mac[r->dh] = 0; 827 } 828 } 829 830 static inline uint32_t 831 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r) 832 { 833 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen], 834 core->mac[r->dh], core->mac[r->dt]); 835 836 if (core->mac[r->dh] <= core->mac[r->dt]) { 837 return core->mac[r->dt] - core->mac[r->dh]; 838 } 839 840 if (core->mac[r->dh] > core->mac[r->dt]) { 841 return core->mac[r->dlen] / E1000_RING_DESC_LEN + 842 core->mac[r->dt] - core->mac[r->dh]; 843 } 844 845 g_assert_not_reached(); 846 return 0; 847 } 848 849 static inline bool 850 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r) 851 { 852 return core->mac[r->dlen] > 0; 853 } 854 855 static inline uint32_t 856 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r) 857 { 858 return core->mac[r->dlen]; 859 } 860 861 typedef struct E1000E_TxRing_st { 862 const E1000E_RingInfo *i; 863 struct e1000e_tx *tx; 864 } E1000E_TxRing; 865 866 static inline int 867 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx) 868 { 869 return (reg_idx - base_reg_idx) / (0x100 >> 2); 870 } 871 872 static inline void 873 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx) 874 { 875 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 876 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 }, 877 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 } 878 }; 879 880 assert(idx < ARRAY_SIZE(i)); 881 882 txr->i = &i[idx]; 883 txr->tx = &core->tx[idx]; 884 } 885 886 typedef struct E1000E_RxRing_st { 887 const E1000E_RingInfo *i; 888 } E1000E_RxRing; 889 890 static inline void 891 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx) 892 { 893 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = { 894 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 }, 895 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 } 896 }; 897 898 assert(idx < ARRAY_SIZE(i)); 899 900 rxr->i = &i[idx]; 901 } 902 903 static void 904 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr) 905 { 906 dma_addr_t base; 907 struct e1000_tx_desc desc; 908 bool ide = false; 909 const E1000E_RingInfo *txi = txr->i; 910 uint32_t cause = E1000_ICS_TXQE; 911 912 if (!(core->mac[TCTL] & E1000_TCTL_EN)) { 913 trace_e1000e_tx_disabled(); 914 return; 915 } 916 917 while (!e1000e_ring_empty(core, txi)) { 918 base = e1000e_ring_head_descr(core, txi); 919 920 pci_dma_read(core->owner, base, &desc, sizeof(desc)); 921 922 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr, 923 desc.lower.data, desc.upper.data); 924 925 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx); 926 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx); 927 928 e1000e_ring_advance(core, txi, 1); 929 } 930 931 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) { 932 e1000e_set_interrupt_cause(core, cause); 933 } 934 } 935 936 static bool 937 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r, 938 size_t total_size) 939 { 940 uint32_t bufs = e1000e_ring_free_descr_num(core, r); 941 942 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, 943 core->rx_desc_buf_size); 944 945 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) * 946 core->rx_desc_buf_size; 947 } 948 949 static inline void 950 e1000e_start_recv(E1000ECore *core) 951 { 952 int i; 953 954 trace_e1000e_rx_start_recv(); 955 956 for (i = 0; i <= core->max_queue_num; i++) { 957 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i)); 958 } 959 } 960 961 int 962 e1000e_can_receive(E1000ECore *core) 963 { 964 int i; 965 966 if (!e1000x_rx_ready(core->owner, core->mac)) { 967 return false; 968 } 969 970 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 971 E1000E_RxRing rxr; 972 973 e1000e_rx_ring_init(core, &rxr, i); 974 if (e1000e_ring_enabled(core, rxr.i) && 975 e1000e_has_rxbufs(core, rxr.i, 1)) { 976 trace_e1000e_rx_can_recv(); 977 return true; 978 } 979 } 980 981 trace_e1000e_rx_can_recv_rings_full(); 982 return false; 983 } 984 985 ssize_t 986 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size) 987 { 988 const struct iovec iov = { 989 .iov_base = (uint8_t *)buf, 990 .iov_len = size 991 }; 992 993 return e1000e_receive_iov(core, &iov, 1); 994 } 995 996 static inline bool 997 e1000e_rx_l3_cso_enabled(E1000ECore *core) 998 { 999 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD); 1000 } 1001 1002 static inline bool 1003 e1000e_rx_l4_cso_enabled(E1000ECore *core) 1004 { 1005 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD); 1006 } 1007 1008 static bool 1009 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size) 1010 { 1011 uint32_t rctl = core->mac[RCTL]; 1012 1013 if (e1000x_is_vlan_packet(buf, core->vet) && 1014 e1000x_vlan_rx_filter_enabled(core->mac)) { 1015 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14)); 1016 uint32_t vfta = le32_to_cpup((uint32_t *)(core->mac + VFTA) + 1017 ((vid >> 5) & 0x7f)); 1018 if ((vfta & (1 << (vid & 0x1f))) == 0) { 1019 trace_e1000e_rx_flt_vlan_mismatch(vid); 1020 return false; 1021 } else { 1022 trace_e1000e_rx_flt_vlan_match(vid); 1023 } 1024 } 1025 1026 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1027 case ETH_PKT_UCAST: 1028 if (rctl & E1000_RCTL_UPE) { 1029 return true; /* promiscuous ucast */ 1030 } 1031 break; 1032 1033 case ETH_PKT_BCAST: 1034 if (rctl & E1000_RCTL_BAM) { 1035 return true; /* broadcast enabled */ 1036 } 1037 break; 1038 1039 case ETH_PKT_MCAST: 1040 if (rctl & E1000_RCTL_MPE) { 1041 return true; /* promiscuous mcast */ 1042 } 1043 break; 1044 1045 default: 1046 g_assert_not_reached(); 1047 } 1048 1049 return e1000x_rx_group_filter(core->mac, buf); 1050 } 1051 1052 static inline void 1053 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr) 1054 { 1055 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc; 1056 *buff_addr = le64_to_cpu(d->buffer_addr); 1057 } 1058 1059 static inline void 1060 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr) 1061 { 1062 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc; 1063 *buff_addr = le64_to_cpu(d->read.buffer_addr); 1064 } 1065 1066 static inline void 1067 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc, 1068 hwaddr (*buff_addr)[MAX_PS_BUFFERS]) 1069 { 1070 int i; 1071 union e1000_rx_desc_packet_split *d = 1072 (union e1000_rx_desc_packet_split *) desc; 1073 1074 for (i = 0; i < MAX_PS_BUFFERS; i++) { 1075 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]); 1076 } 1077 1078 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1], 1079 (*buff_addr)[2], (*buff_addr)[3]); 1080 } 1081 1082 static inline void 1083 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc, 1084 hwaddr (*buff_addr)[MAX_PS_BUFFERS]) 1085 { 1086 if (e1000e_rx_use_legacy_descriptor(core)) { 1087 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]); 1088 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0; 1089 } else { 1090 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1091 e1000e_read_ps_rx_descr(core, desc, buff_addr); 1092 } else { 1093 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]); 1094 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0; 1095 } 1096 } 1097 } 1098 1099 static void 1100 e1000e_verify_csum_in_sw(E1000ECore *core, 1101 struct NetRxPkt *pkt, 1102 uint32_t *status_flags, 1103 bool istcp, bool isudp) 1104 { 1105 bool csum_valid; 1106 uint32_t csum_error; 1107 1108 if (e1000e_rx_l3_cso_enabled(core)) { 1109 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) { 1110 trace_e1000e_rx_metadata_l3_csum_validation_failed(); 1111 } else { 1112 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE; 1113 *status_flags |= E1000_RXD_STAT_IPCS | csum_error; 1114 } 1115 } else { 1116 trace_e1000e_rx_metadata_l3_cso_disabled(); 1117 } 1118 1119 if (!e1000e_rx_l4_cso_enabled(core)) { 1120 trace_e1000e_rx_metadata_l4_cso_disabled(); 1121 return; 1122 } 1123 1124 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) { 1125 trace_e1000e_rx_metadata_l4_csum_validation_failed(); 1126 return; 1127 } 1128 1129 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE; 1130 1131 if (istcp) { 1132 *status_flags |= E1000_RXD_STAT_TCPCS | 1133 csum_error; 1134 } else if (isudp) { 1135 *status_flags |= E1000_RXD_STAT_TCPCS | 1136 E1000_RXD_STAT_UDPCS | 1137 csum_error; 1138 } 1139 } 1140 1141 static inline bool 1142 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt) 1143 { 1144 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) { 1145 return false; 1146 } 1147 1148 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) { 1149 return !net_rx_pkt_has_tcp_data(rx_pkt); 1150 } 1151 1152 return true; 1153 } 1154 1155 static void 1156 e1000e_build_rx_metadata(E1000ECore *core, 1157 struct NetRxPkt *pkt, 1158 bool is_eop, 1159 const E1000E_RSSInfo *rss_info, 1160 uint32_t *rss, uint32_t *mrq, 1161 uint32_t *status_flags, 1162 uint16_t *ip_id, 1163 uint16_t *vlan_tag) 1164 { 1165 struct virtio_net_hdr *vhdr; 1166 bool isip4, isip6, istcp, isudp; 1167 uint32_t pkt_type; 1168 1169 *status_flags = E1000_RXD_STAT_DD; 1170 1171 /* No additional metadata needed for non-EOP descriptors */ 1172 if (!is_eop) { 1173 goto func_exit; 1174 } 1175 1176 *status_flags |= E1000_RXD_STAT_EOP; 1177 1178 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1179 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp); 1180 1181 /* VLAN state */ 1182 if (net_rx_pkt_is_vlan_stripped(pkt)) { 1183 *status_flags |= E1000_RXD_STAT_VP; 1184 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt)); 1185 trace_e1000e_rx_metadata_vlan(*vlan_tag); 1186 } 1187 1188 /* Packet parsing results */ 1189 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) { 1190 if (rss_info->enabled) { 1191 *rss = cpu_to_le32(rss_info->hash); 1192 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8)); 1193 trace_e1000e_rx_metadata_rss(*rss, *mrq); 1194 } 1195 } else if (isip4) { 1196 *status_flags |= E1000_RXD_STAT_IPIDV; 1197 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); 1198 trace_e1000e_rx_metadata_ip_id(*ip_id); 1199 } 1200 1201 if (istcp && e1000e_is_tcp_ack(core, pkt)) { 1202 *status_flags |= E1000_RXD_STAT_ACK; 1203 trace_e1000e_rx_metadata_ack(); 1204 } 1205 1206 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { 1207 trace_e1000e_rx_metadata_ipv6_filtering_disabled(); 1208 pkt_type = E1000_RXD_PKT_MAC; 1209 } else if (istcp || isudp) { 1210 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP; 1211 } else if (isip4 || isip6) { 1212 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6; 1213 } else { 1214 pkt_type = E1000_RXD_PKT_MAC; 1215 } 1216 1217 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type); 1218 trace_e1000e_rx_metadata_pkt_type(pkt_type); 1219 1220 /* RX CSO information */ 1221 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { 1222 trace_e1000e_rx_metadata_ipv6_sum_disabled(); 1223 goto func_exit; 1224 } 1225 1226 if (!net_rx_pkt_has_virt_hdr(pkt)) { 1227 trace_e1000e_rx_metadata_no_virthdr(); 1228 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp); 1229 goto func_exit; 1230 } 1231 1232 vhdr = net_rx_pkt_get_vhdr(pkt); 1233 1234 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) && 1235 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) { 1236 trace_e1000e_rx_metadata_virthdr_no_csum_info(); 1237 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp); 1238 goto func_exit; 1239 } 1240 1241 if (e1000e_rx_l3_cso_enabled(core)) { 1242 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0; 1243 } else { 1244 trace_e1000e_rx_metadata_l3_cso_disabled(); 1245 } 1246 1247 if (e1000e_rx_l4_cso_enabled(core)) { 1248 if (istcp) { 1249 *status_flags |= E1000_RXD_STAT_TCPCS; 1250 } else if (isudp) { 1251 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS; 1252 } 1253 } else { 1254 trace_e1000e_rx_metadata_l4_cso_disabled(); 1255 } 1256 1257 trace_e1000e_rx_metadata_status_flags(*status_flags); 1258 1259 func_exit: 1260 *status_flags = cpu_to_le32(*status_flags); 1261 } 1262 1263 static inline void 1264 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, 1265 struct NetRxPkt *pkt, 1266 const E1000E_RSSInfo *rss_info, 1267 uint16_t length) 1268 { 1269 uint32_t status_flags, rss, mrq; 1270 uint16_t ip_id; 1271 1272 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc; 1273 1274 memset(d, 0, sizeof(*d)); 1275 1276 assert(!rss_info->enabled); 1277 1278 d->length = cpu_to_le16(length); 1279 1280 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1281 rss_info, 1282 &rss, &mrq, 1283 &status_flags, &ip_id, 1284 &d->special); 1285 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24); 1286 d->status = (uint8_t) le32_to_cpu(status_flags); 1287 } 1288 1289 static inline void 1290 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc, 1291 struct NetRxPkt *pkt, 1292 const E1000E_RSSInfo *rss_info, 1293 uint16_t length) 1294 { 1295 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc; 1296 1297 memset(d, 0, sizeof(*d)); 1298 1299 d->wb.upper.length = cpu_to_le16(length); 1300 1301 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1302 rss_info, 1303 &d->wb.lower.hi_dword.rss, 1304 &d->wb.lower.mrq, 1305 &d->wb.upper.status_error, 1306 &d->wb.lower.hi_dword.csum_ip.ip_id, 1307 &d->wb.upper.vlan); 1308 } 1309 1310 static inline void 1311 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc, 1312 struct NetRxPkt *pkt, 1313 const E1000E_RSSInfo *rss_info, 1314 size_t ps_hdr_len, 1315 uint16_t(*written)[MAX_PS_BUFFERS]) 1316 { 1317 int i; 1318 union e1000_rx_desc_packet_split *d = 1319 (union e1000_rx_desc_packet_split *) desc; 1320 1321 memset(d, 0, sizeof(*d)); 1322 1323 d->wb.middle.length0 = cpu_to_le16((*written)[0]); 1324 1325 for (i = 0; i < PS_PAGE_BUFFERS; i++) { 1326 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]); 1327 } 1328 1329 e1000e_build_rx_metadata(core, pkt, pkt != NULL, 1330 rss_info, 1331 &d->wb.lower.hi_dword.rss, 1332 &d->wb.lower.mrq, 1333 &d->wb.middle.status_error, 1334 &d->wb.lower.hi_dword.csum_ip.ip_id, 1335 &d->wb.middle.vlan); 1336 1337 d->wb.upper.header_status = 1338 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0)); 1339 1340 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1], 1341 (*written)[2], (*written)[3]); 1342 } 1343 1344 static inline void 1345 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc, 1346 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, 1347 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS]) 1348 { 1349 if (e1000e_rx_use_legacy_descriptor(core)) { 1350 assert(ps_hdr_len == 0); 1351 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]); 1352 } else { 1353 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1354 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info, 1355 ps_hdr_len, written); 1356 } else { 1357 assert(ps_hdr_len == 0); 1358 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info, 1359 (*written)[0]); 1360 } 1361 } 1362 } 1363 1364 typedef struct e1000e_ba_state_st { 1365 uint16_t written[MAX_PS_BUFFERS]; 1366 uint8_t cur_idx; 1367 } e1000e_ba_state; 1368 1369 static inline void 1370 e1000e_write_hdr_to_rx_buffers(E1000ECore *core, 1371 hwaddr (*ba)[MAX_PS_BUFFERS], 1372 e1000e_ba_state *bastate, 1373 const char *data, 1374 dma_addr_t data_len) 1375 { 1376 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]); 1377 1378 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len); 1379 bastate->written[0] += data_len; 1380 1381 bastate->cur_idx = 1; 1382 } 1383 1384 static void 1385 e1000e_write_to_rx_buffers(E1000ECore *core, 1386 hwaddr (*ba)[MAX_PS_BUFFERS], 1387 e1000e_ba_state *bastate, 1388 const char *data, 1389 dma_addr_t data_len) 1390 { 1391 while (data_len > 0) { 1392 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx]; 1393 uint32_t cur_buf_bytes_left = cur_buf_len - 1394 bastate->written[bastate->cur_idx]; 1395 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left); 1396 1397 trace_e1000e_rx_desc_buff_write(bastate->cur_idx, 1398 (*ba)[bastate->cur_idx], 1399 bastate->written[bastate->cur_idx], 1400 data, 1401 bytes_to_write); 1402 1403 pci_dma_write(core->owner, 1404 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx], 1405 data, bytes_to_write); 1406 1407 bastate->written[bastate->cur_idx] += bytes_to_write; 1408 data += bytes_to_write; 1409 data_len -= bytes_to_write; 1410 1411 if (bastate->written[bastate->cur_idx] == cur_buf_len) { 1412 bastate->cur_idx++; 1413 } 1414 1415 assert(bastate->cur_idx < MAX_PS_BUFFERS); 1416 } 1417 } 1418 1419 static void 1420 e1000e_update_rx_stats(E1000ECore *core, 1421 size_t data_size, 1422 size_t data_fcs_size) 1423 { 1424 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size); 1425 1426 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) { 1427 case ETH_PKT_BCAST: 1428 e1000x_inc_reg_if_not_full(core->mac, BPRC); 1429 break; 1430 1431 case ETH_PKT_MCAST: 1432 e1000x_inc_reg_if_not_full(core->mac, MPRC); 1433 break; 1434 1435 default: 1436 break; 1437 } 1438 } 1439 1440 static inline bool 1441 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi) 1442 { 1443 return e1000e_ring_free_descr_num(core, rxi) == 1444 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift; 1445 } 1446 1447 static bool 1448 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len) 1449 { 1450 bool isip4, isip6, isudp, istcp; 1451 bool fragment; 1452 1453 if (!e1000e_rx_use_ps_descriptor(core)) { 1454 return false; 1455 } 1456 1457 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp); 1458 1459 if (isip4) { 1460 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment; 1461 } else if (isip6) { 1462 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment; 1463 } else { 1464 return false; 1465 } 1466 1467 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) { 1468 return false; 1469 } 1470 1471 if (!fragment && (isudp || istcp)) { 1472 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt); 1473 } else { 1474 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt); 1475 } 1476 1477 if ((*hdr_len > core->rxbuf_sizes[0]) || 1478 (*hdr_len > net_rx_pkt_get_total_len(pkt))) { 1479 return false; 1480 } 1481 1482 return true; 1483 } 1484 1485 static void 1486 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt, 1487 const E1000E_RxRing *rxr, 1488 const E1000E_RSSInfo *rss_info) 1489 { 1490 PCIDevice *d = core->owner; 1491 dma_addr_t base; 1492 uint8_t desc[E1000_MAX_RX_DESC_LEN]; 1493 size_t desc_size; 1494 size_t desc_offset = 0; 1495 size_t iov_ofs = 0; 1496 1497 struct iovec *iov = net_rx_pkt_get_iovec(pkt); 1498 size_t size = net_rx_pkt_get_total_len(pkt); 1499 size_t total_size = size + e1000x_fcs_len(core->mac); 1500 const E1000E_RingInfo *rxi; 1501 size_t ps_hdr_len = 0; 1502 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len); 1503 1504 rxi = rxr->i; 1505 1506 do { 1507 hwaddr ba[MAX_PS_BUFFERS]; 1508 e1000e_ba_state bastate = { { 0 } }; 1509 bool is_last = false; 1510 bool is_first = true; 1511 1512 desc_size = total_size - desc_offset; 1513 1514 if (desc_size > core->rx_desc_buf_size) { 1515 desc_size = core->rx_desc_buf_size; 1516 } 1517 1518 base = e1000e_ring_head_descr(core, rxi); 1519 1520 pci_dma_read(d, base, &desc, core->rx_desc_len); 1521 1522 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); 1523 1524 e1000e_read_rx_descr(core, desc, &ba); 1525 1526 if (ba[0]) { 1527 if (desc_offset < size) { 1528 static const uint32_t fcs_pad; 1529 size_t iov_copy; 1530 size_t copy_size = size - desc_offset; 1531 if (copy_size > core->rx_desc_buf_size) { 1532 copy_size = core->rx_desc_buf_size; 1533 } 1534 1535 /* For PS mode copy the packet header first */ 1536 if (do_ps) { 1537 if (is_first) { 1538 size_t ps_hdr_copied = 0; 1539 do { 1540 iov_copy = MIN(ps_hdr_len - ps_hdr_copied, 1541 iov->iov_len - iov_ofs); 1542 1543 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate, 1544 iov->iov_base, iov_copy); 1545 1546 copy_size -= iov_copy; 1547 ps_hdr_copied += iov_copy; 1548 1549 iov_ofs += iov_copy; 1550 if (iov_ofs == iov->iov_len) { 1551 iov++; 1552 iov_ofs = 0; 1553 } 1554 } while (ps_hdr_copied < ps_hdr_len); 1555 1556 is_first = false; 1557 } else { 1558 /* Leave buffer 0 of each descriptor except first */ 1559 /* empty as per spec 7.1.5.1 */ 1560 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate, 1561 NULL, 0); 1562 } 1563 } 1564 1565 /* Copy packet payload */ 1566 while (copy_size) { 1567 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs); 1568 1569 e1000e_write_to_rx_buffers(core, &ba, &bastate, 1570 iov->iov_base + iov_ofs, iov_copy); 1571 1572 copy_size -= iov_copy; 1573 iov_ofs += iov_copy; 1574 if (iov_ofs == iov->iov_len) { 1575 iov++; 1576 iov_ofs = 0; 1577 } 1578 } 1579 1580 if (desc_offset + desc_size >= total_size) { 1581 /* Simulate FCS checksum presence in the last descriptor */ 1582 e1000e_write_to_rx_buffers(core, &ba, &bastate, 1583 (const char *) &fcs_pad, e1000x_fcs_len(core->mac)); 1584 } 1585 } 1586 desc_offset += desc_size; 1587 if (desc_offset >= total_size) { 1588 is_last = true; 1589 } 1590 } else { /* as per intel docs; skip descriptors with null buf addr */ 1591 trace_e1000e_rx_null_descriptor(); 1592 } 1593 1594 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL, 1595 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written); 1596 pci_dma_write(d, base, &desc, core->rx_desc_len); 1597 1598 e1000e_ring_advance(core, rxi, 1599 core->rx_desc_len / E1000_MIN_RX_DESC_LEN); 1600 1601 } while (desc_offset < total_size); 1602 1603 e1000e_update_rx_stats(core, size, total_size); 1604 } 1605 1606 static inline void 1607 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt) 1608 { 1609 if (net_rx_pkt_has_virt_hdr(pkt)) { 1610 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt); 1611 1612 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) { 1613 net_rx_pkt_fix_l4_csum(pkt); 1614 } 1615 } 1616 } 1617 1618 ssize_t 1619 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt) 1620 { 1621 static const int maximum_ethernet_hdr_len = (14 + 4); 1622 /* Min. octets in an ethernet frame sans FCS */ 1623 static const int min_buf_size = 60; 1624 1625 uint32_t n = 0; 1626 uint8_t min_buf[min_buf_size]; 1627 struct iovec min_iov; 1628 uint8_t *filter_buf; 1629 size_t size, orig_size; 1630 size_t iov_ofs = 0; 1631 E1000E_RxRing rxr; 1632 E1000E_RSSInfo rss_info; 1633 size_t total_size; 1634 ssize_t retval; 1635 bool rdmts_hit; 1636 1637 trace_e1000e_rx_receive_iov(iovcnt); 1638 1639 if (!e1000x_hw_rx_enabled(core->mac)) { 1640 return -1; 1641 } 1642 1643 /* Pull virtio header in */ 1644 if (core->has_vnet) { 1645 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt); 1646 iov_ofs = sizeof(struct virtio_net_hdr); 1647 } 1648 1649 filter_buf = iov->iov_base + iov_ofs; 1650 orig_size = iov_size(iov, iovcnt); 1651 size = orig_size - iov_ofs; 1652 1653 /* Pad to minimum Ethernet frame length */ 1654 if (size < sizeof(min_buf)) { 1655 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size); 1656 memset(&min_buf[size], 0, sizeof(min_buf) - size); 1657 e1000x_inc_reg_if_not_full(core->mac, RUC); 1658 min_iov.iov_base = filter_buf = min_buf; 1659 min_iov.iov_len = size = sizeof(min_buf); 1660 iovcnt = 1; 1661 iov = &min_iov; 1662 iov_ofs = 0; 1663 } else if (iov->iov_len < maximum_ethernet_hdr_len) { 1664 /* This is very unlikely, but may happen. */ 1665 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len); 1666 filter_buf = min_buf; 1667 } 1668 1669 /* Discard oversized packets if !LPE and !SBP. */ 1670 if (e1000x_is_oversized(core->mac, size)) { 1671 return orig_size; 1672 } 1673 1674 net_rx_pkt_set_packet_type(core->rx_pkt, 1675 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf))); 1676 1677 if (!e1000e_receive_filter(core, filter_buf, size)) { 1678 trace_e1000e_rx_flt_dropped(); 1679 return orig_size; 1680 } 1681 1682 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs, 1683 e1000x_vlan_enabled(core->mac), core->vet); 1684 1685 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info); 1686 e1000e_rx_ring_init(core, &rxr, rss_info.queue); 1687 1688 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx); 1689 1690 total_size = net_rx_pkt_get_total_len(core->rx_pkt) + 1691 e1000x_fcs_len(core->mac); 1692 1693 if (e1000e_has_rxbufs(core, rxr.i, total_size)) { 1694 e1000e_rx_fix_l4_csum(core, core->rx_pkt); 1695 1696 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info); 1697 1698 retval = orig_size; 1699 1700 /* Perform small receive detection (RSRPD) */ 1701 if (total_size < core->mac[RSRPD]) { 1702 n |= E1000_ICS_SRPD; 1703 } 1704 1705 /* Perform ACK receive detection */ 1706 if (e1000e_is_tcp_ack(core, core->rx_pkt)) { 1707 n |= E1000_ICS_ACK; 1708 } 1709 1710 /* Check if receive descriptor minimum threshold hit */ 1711 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i); 1712 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit); 1713 1714 trace_e1000e_rx_written_to_guest(n); 1715 } else { 1716 n |= E1000_ICS_RXO; 1717 retval = 0; 1718 1719 trace_e1000e_rx_not_written_to_guest(n); 1720 } 1721 1722 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) { 1723 trace_e1000e_rx_interrupt_set(n); 1724 e1000e_set_interrupt_cause(core, n); 1725 } else { 1726 trace_e1000e_rx_interrupt_delayed(n); 1727 } 1728 1729 return retval; 1730 } 1731 1732 static inline bool 1733 e1000e_have_autoneg(E1000ECore *core) 1734 { 1735 return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN; 1736 } 1737 1738 static void e1000e_update_flowctl_status(E1000ECore *core) 1739 { 1740 if (e1000e_have_autoneg(core) && 1741 core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) { 1742 trace_e1000e_link_autoneg_flowctl(true); 1743 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE; 1744 } else { 1745 trace_e1000e_link_autoneg_flowctl(false); 1746 } 1747 } 1748 1749 static inline void 1750 e1000e_link_down(E1000ECore *core) 1751 { 1752 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1753 e1000e_update_flowctl_status(core); 1754 } 1755 1756 static inline void 1757 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val) 1758 { 1759 /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */ 1760 core->phy[0][PHY_CTRL] = val & ~(0x3f | 1761 MII_CR_RESET | 1762 MII_CR_RESTART_AUTO_NEG); 1763 1764 if ((val & MII_CR_RESTART_AUTO_NEG) && 1765 e1000e_have_autoneg(core)) { 1766 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1767 } 1768 } 1769 1770 static void 1771 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val) 1772 { 1773 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10); 1774 1775 if (val & BIT(10)) { 1776 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer); 1777 } 1778 } 1779 1780 static void 1781 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val) 1782 { 1783 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK; 1784 } 1785 1786 void 1787 e1000e_core_set_link_status(E1000ECore *core) 1788 { 1789 NetClientState *nc = qemu_get_queue(core->owner_nic); 1790 uint32_t old_status = core->mac[STATUS]; 1791 1792 trace_e1000e_link_status_changed(nc->link_down ? false : true); 1793 1794 if (nc->link_down) { 1795 e1000x_update_regs_on_link_down(core->mac, core->phy[0]); 1796 } else { 1797 if (e1000e_have_autoneg(core) && 1798 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { 1799 e1000x_restart_autoneg(core->mac, core->phy[0], 1800 core->autoneg_timer); 1801 } else { 1802 e1000x_update_regs_on_link_up(core->mac, core->phy[0]); 1803 } 1804 } 1805 1806 if (core->mac[STATUS] != old_status) { 1807 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 1808 } 1809 } 1810 1811 static void 1812 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val) 1813 { 1814 trace_e1000e_core_ctrl_write(index, val); 1815 1816 /* RST is self clearing */ 1817 core->mac[CTRL] = val & ~E1000_CTRL_RST; 1818 core->mac[CTRL_DUP] = core->mac[CTRL]; 1819 1820 trace_e1000e_link_set_params( 1821 !!(val & E1000_CTRL_ASDE), 1822 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 1823 !!(val & E1000_CTRL_FRCSPD), 1824 !!(val & E1000_CTRL_FRCDPX), 1825 !!(val & E1000_CTRL_RFCE), 1826 !!(val & E1000_CTRL_TFCE)); 1827 1828 if (val & E1000_CTRL_RST) { 1829 trace_e1000e_core_ctrl_sw_reset(); 1830 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 1831 } 1832 1833 if (val & E1000_CTRL_PHY_RST) { 1834 trace_e1000e_core_ctrl_phy_reset(); 1835 core->mac[STATUS] |= E1000_STATUS_PHYRA; 1836 } 1837 } 1838 1839 static void 1840 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val) 1841 { 1842 trace_e1000e_rx_set_rfctl(val); 1843 1844 if (!(val & E1000_RFCTL_ISCSI_DIS)) { 1845 trace_e1000e_wrn_iscsi_filtering_not_supported(); 1846 } 1847 1848 if (!(val & E1000_RFCTL_NFSW_DIS)) { 1849 trace_e1000e_wrn_nfsw_filtering_not_supported(); 1850 } 1851 1852 if (!(val & E1000_RFCTL_NFSR_DIS)) { 1853 trace_e1000e_wrn_nfsr_filtering_not_supported(); 1854 } 1855 1856 core->mac[RFCTL] = val; 1857 } 1858 1859 static void 1860 e1000e_calc_per_desc_buf_size(E1000ECore *core) 1861 { 1862 int i; 1863 core->rx_desc_buf_size = 0; 1864 1865 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) { 1866 core->rx_desc_buf_size += core->rxbuf_sizes[i]; 1867 } 1868 } 1869 1870 static void 1871 e1000e_parse_rxbufsize(E1000ECore *core) 1872 { 1873 uint32_t rctl = core->mac[RCTL]; 1874 1875 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes)); 1876 1877 if (rctl & E1000_RCTL_DTYP_MASK) { 1878 uint32_t bsize; 1879 1880 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK; 1881 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128; 1882 1883 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK; 1884 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024; 1885 1886 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK; 1887 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024; 1888 1889 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK; 1890 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024; 1891 } else if (rctl & E1000_RCTL_FLXBUF_MASK) { 1892 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK; 1893 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024; 1894 } else { 1895 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl); 1896 } 1897 1898 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1], 1899 core->rxbuf_sizes[2], core->rxbuf_sizes[3]); 1900 1901 e1000e_calc_per_desc_buf_size(core); 1902 } 1903 1904 static void 1905 e1000e_calc_rxdesclen(E1000ECore *core) 1906 { 1907 if (e1000e_rx_use_legacy_descriptor(core)) { 1908 core->rx_desc_len = sizeof(struct e1000_rx_desc); 1909 } else { 1910 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) { 1911 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split); 1912 } else { 1913 core->rx_desc_len = sizeof(union e1000_rx_desc_extended); 1914 } 1915 } 1916 trace_e1000e_rx_desc_len(core->rx_desc_len); 1917 } 1918 1919 static void 1920 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val) 1921 { 1922 core->mac[RCTL] = val; 1923 trace_e1000e_rx_set_rctl(core->mac[RCTL]); 1924 1925 if (val & E1000_RCTL_EN) { 1926 e1000e_parse_rxbufsize(core); 1927 e1000e_calc_rxdesclen(core); 1928 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 + 1929 E1000_RING_DESC_LEN_SHIFT; 1930 1931 e1000e_start_recv(core); 1932 } 1933 } 1934 1935 static 1936 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE]) 1937 (E1000ECore *, int, uint16_t) = { 1938 [0] = { 1939 [PHY_CTRL] = e1000e_set_phy_ctrl, 1940 [PHY_PAGE] = e1000e_set_phy_page, 1941 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits 1942 } 1943 }; 1944 1945 static inline void 1946 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits) 1947 { 1948 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits); 1949 core->mac[IMS] &= ~bits; 1950 } 1951 1952 static inline bool 1953 e1000e_postpone_interrupt(bool *interrupt_pending, 1954 E1000IntrDelayTimer *timer) 1955 { 1956 if (timer->running) { 1957 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2); 1958 1959 *interrupt_pending = true; 1960 return true; 1961 } 1962 1963 if (timer->core->mac[timer->delay_reg] != 0) { 1964 e1000e_intrmgr_rearm_timer(timer); 1965 } 1966 1967 return false; 1968 } 1969 1970 static inline bool 1971 e1000e_itr_should_postpone(E1000ECore *core) 1972 { 1973 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr); 1974 } 1975 1976 static inline bool 1977 e1000e_eitr_should_postpone(E1000ECore *core, int idx) 1978 { 1979 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx], 1980 &core->eitr[idx]); 1981 } 1982 1983 static void 1984 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 1985 { 1986 uint32_t effective_eiac; 1987 1988 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 1989 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 1990 if (vec < E1000E_MSIX_VEC_NUM) { 1991 if (!e1000e_eitr_should_postpone(core, vec)) { 1992 trace_e1000e_irq_msix_notify_vec(vec); 1993 msix_notify(core->owner, vec); 1994 } 1995 } else { 1996 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 1997 } 1998 } else { 1999 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2000 } 2001 2002 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { 2003 trace_e1000e_irq_ims_clear_eiame(core->mac[IAM], cause); 2004 e1000e_clear_ims_bits(core, core->mac[IAM] & cause); 2005 } 2006 2007 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); 2008 2009 if (core->mac[EIAC] & E1000_ICR_OTHER) { 2010 effective_eiac = (core->mac[EIAC] & E1000_EIAC_MASK) | 2011 E1000_ICR_OTHER_CAUSES; 2012 } else { 2013 effective_eiac = core->mac[EIAC] & E1000_EIAC_MASK; 2014 } 2015 core->mac[ICR] &= ~effective_eiac; 2016 } 2017 2018 static void 2019 e1000e_msix_notify(E1000ECore *core, uint32_t causes) 2020 { 2021 if (causes & E1000_ICR_RXQ0) { 2022 e1000e_msix_notify_one(core, E1000_ICR_RXQ0, 2023 E1000_IVAR_RXQ0(core->mac[IVAR])); 2024 } 2025 2026 if (causes & E1000_ICR_RXQ1) { 2027 e1000e_msix_notify_one(core, E1000_ICR_RXQ1, 2028 E1000_IVAR_RXQ1(core->mac[IVAR])); 2029 } 2030 2031 if (causes & E1000_ICR_TXQ0) { 2032 e1000e_msix_notify_one(core, E1000_ICR_TXQ0, 2033 E1000_IVAR_TXQ0(core->mac[IVAR])); 2034 } 2035 2036 if (causes & E1000_ICR_TXQ1) { 2037 e1000e_msix_notify_one(core, E1000_ICR_TXQ1, 2038 E1000_IVAR_TXQ1(core->mac[IVAR])); 2039 } 2040 2041 if (causes & E1000_ICR_OTHER) { 2042 e1000e_msix_notify_one(core, E1000_ICR_OTHER, 2043 E1000_IVAR_OTHER(core->mac[IVAR])); 2044 } 2045 } 2046 2047 static void 2048 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) 2049 { 2050 if (E1000_IVAR_ENTRY_VALID(int_cfg)) { 2051 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg); 2052 if (vec < E1000E_MSIX_VEC_NUM) { 2053 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec); 2054 msix_clr_pending(core->owner, vec); 2055 } else { 2056 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg); 2057 } 2058 } else { 2059 trace_e1000e_wrn_msix_invalid(cause, int_cfg); 2060 } 2061 } 2062 2063 static void 2064 e1000e_msix_clear(E1000ECore *core, uint32_t causes) 2065 { 2066 if (causes & E1000_ICR_RXQ0) { 2067 e1000e_msix_clear_one(core, E1000_ICR_RXQ0, 2068 E1000_IVAR_RXQ0(core->mac[IVAR])); 2069 } 2070 2071 if (causes & E1000_ICR_RXQ1) { 2072 e1000e_msix_clear_one(core, E1000_ICR_RXQ1, 2073 E1000_IVAR_RXQ1(core->mac[IVAR])); 2074 } 2075 2076 if (causes & E1000_ICR_TXQ0) { 2077 e1000e_msix_clear_one(core, E1000_ICR_TXQ0, 2078 E1000_IVAR_TXQ0(core->mac[IVAR])); 2079 } 2080 2081 if (causes & E1000_ICR_TXQ1) { 2082 e1000e_msix_clear_one(core, E1000_ICR_TXQ1, 2083 E1000_IVAR_TXQ1(core->mac[IVAR])); 2084 } 2085 2086 if (causes & E1000_ICR_OTHER) { 2087 e1000e_msix_clear_one(core, E1000_ICR_OTHER, 2088 E1000_IVAR_OTHER(core->mac[IVAR])); 2089 } 2090 } 2091 2092 static inline void 2093 e1000e_fix_icr_asserted(E1000ECore *core) 2094 { 2095 core->mac[ICR] &= ~E1000_ICR_ASSERTED; 2096 if (core->mac[ICR]) { 2097 core->mac[ICR] |= E1000_ICR_ASSERTED; 2098 } 2099 2100 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); 2101 } 2102 2103 static void 2104 e1000e_send_msi(E1000ECore *core, bool msix) 2105 { 2106 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED; 2107 2108 if (msix) { 2109 e1000e_msix_notify(core, causes); 2110 } else { 2111 if (!e1000e_itr_should_postpone(core)) { 2112 trace_e1000e_irq_msi_notify(causes); 2113 msi_notify(core->owner, 0); 2114 } 2115 } 2116 } 2117 2118 static void 2119 e1000e_update_interrupt_state(E1000ECore *core) 2120 { 2121 bool interrupts_pending; 2122 bool is_msix = msix_enabled(core->owner); 2123 2124 /* Set ICR[OTHER] for MSI-X */ 2125 if (is_msix) { 2126 if (core->mac[ICR] & core->mac[IMS] & E1000_ICR_OTHER_CAUSES) { 2127 core->mac[ICR] |= E1000_ICR_OTHER; 2128 trace_e1000e_irq_add_msi_other(core->mac[ICR]); 2129 } 2130 } 2131 2132 e1000e_fix_icr_asserted(core); 2133 2134 /* 2135 * Make sure ICR and ICS registers have the same value. 2136 * The spec says that the ICS register is write-only. However in practice, 2137 * on real hardware ICS is readable, and for reads it has the same value as 2138 * ICR (except that ICS does not have the clear on read behaviour of ICR). 2139 * 2140 * The VxWorks PRO/1000 driver uses this behaviour. 2141 */ 2142 core->mac[ICS] = core->mac[ICR]; 2143 2144 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false; 2145 2146 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], 2147 core->mac[ICR], core->mac[IMS]); 2148 2149 if (is_msix || msi_enabled(core->owner)) { 2150 if (interrupts_pending) { 2151 e1000e_send_msi(core, is_msix); 2152 } 2153 } else { 2154 if (interrupts_pending) { 2155 if (!e1000e_itr_should_postpone(core)) { 2156 e1000e_raise_legacy_irq(core); 2157 } 2158 } else { 2159 e1000e_lower_legacy_irq(core); 2160 } 2161 } 2162 } 2163 2164 static inline void 2165 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val) 2166 { 2167 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); 2168 2169 val |= e1000e_intmgr_collect_delayed_causes(core); 2170 core->mac[ICR] |= val; 2171 2172 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); 2173 2174 e1000e_update_interrupt_state(core); 2175 } 2176 2177 static inline void 2178 e1000e_autoneg_timer(void *opaque) 2179 { 2180 E1000ECore *core = opaque; 2181 if (!qemu_get_queue(core->owner_nic)->link_down) { 2182 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]); 2183 e1000e_update_flowctl_status(core); 2184 /* signal link status change to the guest */ 2185 e1000e_set_interrupt_cause(core, E1000_ICR_LSC); 2186 } 2187 } 2188 2189 static inline uint16_t 2190 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr) 2191 { 2192 uint16_t index = (addr & 0x1ffff) >> 2; 2193 return index + (mac_reg_access[index] & 0xfffe); 2194 } 2195 2196 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = { 2197 [0] = { 2198 [PHY_CTRL] = PHY_ANYPAGE | PHY_RW, 2199 [PHY_STATUS] = PHY_ANYPAGE | PHY_R, 2200 [PHY_ID1] = PHY_ANYPAGE | PHY_R, 2201 [PHY_ID2] = PHY_ANYPAGE | PHY_R, 2202 [PHY_AUTONEG_ADV] = PHY_ANYPAGE | PHY_RW, 2203 [PHY_LP_ABILITY] = PHY_ANYPAGE | PHY_R, 2204 [PHY_AUTONEG_EXP] = PHY_ANYPAGE | PHY_R, 2205 [PHY_NEXT_PAGE_TX] = PHY_ANYPAGE | PHY_RW, 2206 [PHY_LP_NEXT_PAGE] = PHY_ANYPAGE | PHY_R, 2207 [PHY_1000T_CTRL] = PHY_ANYPAGE | PHY_RW, 2208 [PHY_1000T_STATUS] = PHY_ANYPAGE | PHY_R, 2209 [PHY_EXT_STATUS] = PHY_ANYPAGE | PHY_R, 2210 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW, 2211 2212 [PHY_COPPER_CTRL1] = PHY_RW, 2213 [PHY_COPPER_STAT1] = PHY_R, 2214 [PHY_COPPER_CTRL3] = PHY_RW, 2215 [PHY_RX_ERR_CNTR] = PHY_R, 2216 [PHY_OEM_BITS] = PHY_RW, 2217 [PHY_BIAS_1] = PHY_RW, 2218 [PHY_BIAS_2] = PHY_RW, 2219 [PHY_COPPER_INT_ENABLE] = PHY_RW, 2220 [PHY_COPPER_STAT2] = PHY_R, 2221 [PHY_COPPER_CTRL2] = PHY_RW 2222 }, 2223 [2] = { 2224 [PHY_MAC_CTRL1] = PHY_RW, 2225 [PHY_MAC_INT_ENABLE] = PHY_RW, 2226 [PHY_MAC_STAT] = PHY_R, 2227 [PHY_MAC_CTRL2] = PHY_RW 2228 }, 2229 [3] = { 2230 [PHY_LED_03_FUNC_CTRL1] = PHY_RW, 2231 [PHY_LED_03_POL_CTRL] = PHY_RW, 2232 [PHY_LED_TIMER_CTRL] = PHY_RW, 2233 [PHY_LED_45_CTRL] = PHY_RW 2234 }, 2235 [5] = { 2236 [PHY_1000T_SKEW] = PHY_R, 2237 [PHY_1000T_SWAP] = PHY_R 2238 }, 2239 [6] = { 2240 [PHY_CRC_COUNTERS] = PHY_R 2241 } 2242 }; 2243 2244 static bool 2245 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr, 2246 char cap, uint8_t *page) 2247 { 2248 *page = 2249 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0 2250 : core->phy[0][PHY_PAGE]; 2251 2252 if (*page >= E1000E_PHY_PAGES) { 2253 return false; 2254 } 2255 2256 return e1000e_phy_regcap[*page][addr] & cap; 2257 } 2258 2259 static void 2260 e1000e_phy_reg_write(E1000ECore *core, uint8_t page, 2261 uint32_t addr, uint16_t data) 2262 { 2263 assert(page < E1000E_PHY_PAGES); 2264 assert(addr < E1000E_PHY_PAGE_SIZE); 2265 2266 if (e1000e_phyreg_writeops[page][addr]) { 2267 e1000e_phyreg_writeops[page][addr](core, addr, data); 2268 } else { 2269 core->phy[page][addr] = data; 2270 } 2271 } 2272 2273 static void 2274 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val) 2275 { 2276 uint32_t data = val & E1000_MDIC_DATA_MASK; 2277 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 2278 uint8_t page; 2279 2280 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */ 2281 val = core->mac[MDIC] | E1000_MDIC_ERROR; 2282 } else if (val & E1000_MDIC_OP_READ) { 2283 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) { 2284 trace_e1000e_core_mdic_read_unhandled(page, addr); 2285 val |= E1000_MDIC_ERROR; 2286 } else { 2287 val = (val ^ data) | core->phy[page][addr]; 2288 trace_e1000e_core_mdic_read(page, addr, val); 2289 } 2290 } else if (val & E1000_MDIC_OP_WRITE) { 2291 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) { 2292 trace_e1000e_core_mdic_write_unhandled(page, addr); 2293 val |= E1000_MDIC_ERROR; 2294 } else { 2295 trace_e1000e_core_mdic_write(page, addr, data); 2296 e1000e_phy_reg_write(core, page, addr, data); 2297 } 2298 } 2299 core->mac[MDIC] = val | E1000_MDIC_READY; 2300 2301 if (val & E1000_MDIC_INT_EN) { 2302 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC); 2303 } 2304 } 2305 2306 static void 2307 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val) 2308 { 2309 core->mac[index] = val & 0xffff; 2310 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val); 2311 e1000e_start_recv(core); 2312 } 2313 2314 static void 2315 e1000e_set_status(E1000ECore *core, int index, uint32_t val) 2316 { 2317 if ((val & E1000_STATUS_PHYRA) == 0) { 2318 core->mac[index] &= ~E1000_STATUS_PHYRA; 2319 } 2320 } 2321 2322 static void 2323 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val) 2324 { 2325 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK), 2326 !!(val & E1000_CTRL_EXT_SPD_BYPS)); 2327 2328 /* Zero self-clearing bits */ 2329 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST); 2330 core->mac[CTRL_EXT] = val; 2331 } 2332 2333 static void 2334 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val) 2335 { 2336 int i; 2337 2338 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK; 2339 2340 if (msix_enabled(core->owner)) { 2341 return; 2342 } 2343 2344 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) { 2345 if (core->mac[PBACLR] & BIT(i)) { 2346 msix_clr_pending(core->owner, i); 2347 } 2348 } 2349 } 2350 2351 static void 2352 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val) 2353 { 2354 core->mac[FCRTH] = val & 0xFFF8; 2355 } 2356 2357 static void 2358 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val) 2359 { 2360 core->mac[FCRTL] = val & 0x8000FFF8; 2361 } 2362 2363 static inline void 2364 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val) 2365 { 2366 core->mac[index] = val & 0xffff; 2367 } 2368 2369 static void 2370 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val) 2371 { 2372 core->mac[index] = val & 0xfff; 2373 } 2374 2375 static void 2376 e1000e_set_vet(E1000ECore *core, int index, uint32_t val) 2377 { 2378 core->mac[VET] = val & 0xffff; 2379 core->vet = le16_to_cpu(core->mac[VET]); 2380 trace_e1000e_vlan_vet(core->vet); 2381 } 2382 2383 static void 2384 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val) 2385 { 2386 core->mac[index] = val & E1000_XDLEN_MASK; 2387 } 2388 2389 static void 2390 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val) 2391 { 2392 core->mac[index] = val & E1000_XDBAL_MASK; 2393 } 2394 2395 static void 2396 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val) 2397 { 2398 E1000E_TxRing txr; 2399 core->mac[index] = val; 2400 2401 if (core->mac[TARC0] & E1000_TARC_ENABLE) { 2402 e1000e_tx_ring_init(core, &txr, 0); 2403 e1000e_start_xmit(core, &txr); 2404 } 2405 2406 if (core->mac[TARC1] & E1000_TARC_ENABLE) { 2407 e1000e_tx_ring_init(core, &txr, 1); 2408 e1000e_start_xmit(core, &txr); 2409 } 2410 } 2411 2412 static void 2413 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val) 2414 { 2415 E1000E_TxRing txr; 2416 int qidx = e1000e_mq_queue_idx(TDT, index); 2417 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1; 2418 2419 core->mac[index] = val & 0xffff; 2420 2421 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) { 2422 e1000e_tx_ring_init(core, &txr, qidx); 2423 e1000e_start_xmit(core, &txr); 2424 } 2425 } 2426 2427 static void 2428 e1000e_set_ics(E1000ECore *core, int index, uint32_t val) 2429 { 2430 trace_e1000e_irq_write_ics(val); 2431 e1000e_set_interrupt_cause(core, val); 2432 } 2433 2434 static void 2435 e1000e_set_icr(E1000ECore *core, int index, uint32_t val) 2436 { 2437 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2438 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2439 trace_e1000e_irq_icr_process_iame(); 2440 e1000e_clear_ims_bits(core, core->mac[IAM]); 2441 } 2442 2443 trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & ~val); 2444 core->mac[ICR] &= ~val; 2445 e1000e_update_interrupt_state(core); 2446 } 2447 2448 static void 2449 e1000e_set_imc(E1000ECore *core, int index, uint32_t val) 2450 { 2451 trace_e1000e_irq_ims_clear_set_imc(val); 2452 e1000e_clear_ims_bits(core, val); 2453 e1000e_update_interrupt_state(core); 2454 } 2455 2456 static void 2457 e1000e_set_ims(E1000ECore *core, int index, uint32_t val) 2458 { 2459 static const uint32_t ims_ext_mask = 2460 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 | 2461 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2462 E1000_IMS_OTHER; 2463 2464 static const uint32_t ims_valid_mask = 2465 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC | 2466 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 | 2467 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD | 2468 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 | 2469 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 | 2470 E1000_IMS_OTHER; 2471 2472 uint32_t valid_val = val & ims_valid_mask; 2473 2474 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val); 2475 core->mac[IMS] |= valid_val; 2476 2477 if ((valid_val & ims_ext_mask) && 2478 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) && 2479 msix_enabled(core->owner)) { 2480 e1000e_msix_clear(core, valid_val); 2481 } 2482 2483 if ((valid_val == ims_valid_mask) && 2484 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) { 2485 trace_e1000e_irq_fire_all_timers(val); 2486 e1000e_intrmgr_fire_all_timers(core); 2487 } 2488 2489 e1000e_update_interrupt_state(core); 2490 } 2491 2492 static void 2493 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val) 2494 { 2495 e1000e_set_16bit(core, index, val); 2496 2497 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) { 2498 trace_e1000e_irq_rdtr_fpd_running(); 2499 e1000e_intrmgr_fire_delayed_interrupts(core); 2500 } else { 2501 trace_e1000e_irq_rdtr_fpd_not_running(); 2502 } 2503 } 2504 2505 static void 2506 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val) 2507 { 2508 e1000e_set_16bit(core, index, val); 2509 2510 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) { 2511 trace_e1000e_irq_tidv_fpd_running(); 2512 e1000e_intrmgr_fire_delayed_interrupts(core); 2513 } else { 2514 trace_e1000e_irq_tidv_fpd_not_running(); 2515 } 2516 } 2517 2518 static uint32_t 2519 e1000e_mac_readreg(E1000ECore *core, int index) 2520 { 2521 return core->mac[index]; 2522 } 2523 2524 static uint32_t 2525 e1000e_mac_ics_read(E1000ECore *core, int index) 2526 { 2527 trace_e1000e_irq_read_ics(core->mac[ICS]); 2528 return core->mac[ICS]; 2529 } 2530 2531 static uint32_t 2532 e1000e_mac_ims_read(E1000ECore *core, int index) 2533 { 2534 trace_e1000e_irq_read_ims(core->mac[IMS]); 2535 return core->mac[IMS]; 2536 } 2537 2538 #define E1000E_LOW_BITS_READ_FUNC(num) \ 2539 static uint32_t \ 2540 e1000e_mac_low##num##_read(E1000ECore *core, int index) \ 2541 { \ 2542 return core->mac[index] & (BIT(num) - 1); \ 2543 } \ 2544 2545 #define E1000E_LOW_BITS_READ(num) \ 2546 e1000e_mac_low##num##_read 2547 2548 E1000E_LOW_BITS_READ_FUNC(4); 2549 E1000E_LOW_BITS_READ_FUNC(6); 2550 E1000E_LOW_BITS_READ_FUNC(11); 2551 E1000E_LOW_BITS_READ_FUNC(13); 2552 E1000E_LOW_BITS_READ_FUNC(16); 2553 2554 static uint32_t 2555 e1000e_mac_swsm_read(E1000ECore *core, int index) 2556 { 2557 uint32_t val = core->mac[SWSM]; 2558 core->mac[SWSM] = val | 1; 2559 return val; 2560 } 2561 2562 static uint32_t 2563 e1000e_mac_itr_read(E1000ECore *core, int index) 2564 { 2565 return core->itr_guest_value; 2566 } 2567 2568 static uint32_t 2569 e1000e_mac_eitr_read(E1000ECore *core, int index) 2570 { 2571 return core->eitr_guest_value[index - EITR]; 2572 } 2573 2574 static uint32_t 2575 e1000e_mac_icr_read(E1000ECore *core, int index) 2576 { 2577 uint32_t ret = core->mac[ICR]; 2578 trace_e1000e_irq_icr_read_entry(ret); 2579 2580 if (core->mac[IMS] == 0) { 2581 trace_e1000e_irq_icr_clear_zero_ims(); 2582 core->mac[ICR] = 0; 2583 } 2584 2585 if ((core->mac[ICR] & E1000_ICR_ASSERTED) && 2586 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { 2587 trace_e1000e_irq_icr_clear_iame(); 2588 core->mac[ICR] = 0; 2589 trace_e1000e_irq_icr_process_iame(); 2590 e1000e_clear_ims_bits(core, core->mac[IAM]); 2591 } 2592 2593 trace_e1000e_irq_icr_read_exit(core->mac[ICR]); 2594 e1000e_update_interrupt_state(core); 2595 return ret; 2596 } 2597 2598 static uint32_t 2599 e1000e_mac_read_clr4(E1000ECore *core, int index) 2600 { 2601 uint32_t ret = core->mac[index]; 2602 2603 core->mac[index] = 0; 2604 return ret; 2605 } 2606 2607 static uint32_t 2608 e1000e_mac_read_clr8(E1000ECore *core, int index) 2609 { 2610 uint32_t ret = core->mac[index]; 2611 2612 core->mac[index] = 0; 2613 core->mac[index - 1] = 0; 2614 return ret; 2615 } 2616 2617 static uint32_t 2618 e1000e_get_ctrl(E1000ECore *core, int index) 2619 { 2620 uint32_t val = core->mac[CTRL]; 2621 2622 trace_e1000e_link_read_params( 2623 !!(val & E1000_CTRL_ASDE), 2624 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT, 2625 !!(val & E1000_CTRL_FRCSPD), 2626 !!(val & E1000_CTRL_FRCDPX), 2627 !!(val & E1000_CTRL_RFCE), 2628 !!(val & E1000_CTRL_TFCE)); 2629 2630 return val; 2631 } 2632 2633 static uint32_t 2634 e1000e_get_status(E1000ECore *core, int index) 2635 { 2636 uint32_t res = core->mac[STATUS]; 2637 2638 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) { 2639 res |= E1000_STATUS_GIO_MASTER_ENABLE; 2640 } 2641 2642 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) { 2643 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0; 2644 } else { 2645 res |= E1000_STATUS_FD; 2646 } 2647 2648 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) || 2649 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) { 2650 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) { 2651 case E1000_CTRL_SPD_10: 2652 res |= E1000_STATUS_SPEED_10; 2653 break; 2654 case E1000_CTRL_SPD_100: 2655 res |= E1000_STATUS_SPEED_100; 2656 break; 2657 case E1000_CTRL_SPD_1000: 2658 default: 2659 res |= E1000_STATUS_SPEED_1000; 2660 break; 2661 } 2662 } else { 2663 res |= E1000_STATUS_SPEED_1000; 2664 } 2665 2666 trace_e1000e_link_status( 2667 !!(res & E1000_STATUS_LU), 2668 !!(res & E1000_STATUS_FD), 2669 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT, 2670 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT); 2671 2672 return res; 2673 } 2674 2675 static uint32_t 2676 e1000e_get_tarc(E1000ECore *core, int index) 2677 { 2678 return core->mac[index] & ((BIT(11) - 1) | 2679 BIT(27) | 2680 BIT(28) | 2681 BIT(29) | 2682 BIT(30)); 2683 } 2684 2685 static void 2686 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val) 2687 { 2688 core->mac[index] = val; 2689 } 2690 2691 static void 2692 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val) 2693 { 2694 uint32_t macaddr[2]; 2695 2696 core->mac[index] = val; 2697 2698 macaddr[0] = cpu_to_le32(core->mac[RA]); 2699 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); 2700 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic), 2701 (uint8_t *) macaddr); 2702 2703 trace_e1000e_mac_set_sw(MAC_ARG(macaddr)); 2704 } 2705 2706 static void 2707 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val) 2708 { 2709 static const uint32_t ro_bits = E1000_EECD_PRES | 2710 E1000_EECD_AUTO_RD | 2711 E1000_EECD_SIZE_EX_MASK; 2712 2713 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits); 2714 } 2715 2716 static void 2717 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val) 2718 { 2719 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2720 uint32_t flags = 0; 2721 uint32_t data = 0; 2722 2723 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2724 data = core->eeprom[addr]; 2725 flags = E1000_EERW_DONE; 2726 } 2727 2728 core->mac[EERD] = flags | 2729 (addr << E1000_EERW_ADDR_SHIFT) | 2730 (data << E1000_EERW_DATA_SHIFT); 2731 } 2732 2733 static void 2734 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val) 2735 { 2736 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK; 2737 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK; 2738 uint32_t flags = 0; 2739 2740 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) { 2741 core->eeprom[addr] = data; 2742 flags = E1000_EERW_DONE; 2743 } 2744 2745 core->mac[EERD] = flags | 2746 (addr << E1000_EERW_ADDR_SHIFT) | 2747 (data << E1000_EERW_DATA_SHIFT); 2748 } 2749 2750 static void 2751 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val) 2752 { 2753 core->mac[RXDCTL] = core->mac[RXDCTL1] = val; 2754 } 2755 2756 static void 2757 e1000e_set_itr(E1000ECore *core, int index, uint32_t val) 2758 { 2759 uint32_t interval = val & 0xffff; 2760 2761 trace_e1000e_irq_itr_set(val); 2762 2763 core->itr_guest_value = interval; 2764 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2765 } 2766 2767 static void 2768 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val) 2769 { 2770 uint32_t interval = val & 0xffff; 2771 uint32_t eitr_num = index - EITR; 2772 2773 trace_e1000e_irq_eitr_set(eitr_num, val); 2774 2775 core->eitr_guest_value[eitr_num] = interval; 2776 core->mac[index] = MAX(interval, E1000E_MIN_XITR); 2777 } 2778 2779 static void 2780 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val) 2781 { 2782 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) { 2783 hw_error("e1000e: PSRCTL.BSIZE0 cannot be zero"); 2784 } 2785 2786 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) { 2787 hw_error("e1000e: PSRCTL.BSIZE1 cannot be zero"); 2788 } 2789 2790 core->mac[PSRCTL] = val; 2791 } 2792 2793 static void 2794 e1000e_update_rx_offloads(E1000ECore *core) 2795 { 2796 int cso_state = e1000e_rx_l4_cso_enabled(core); 2797 2798 trace_e1000e_rx_set_cso(cso_state); 2799 2800 if (core->has_vnet) { 2801 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer, 2802 cso_state, 0, 0, 0, 0); 2803 } 2804 } 2805 2806 static void 2807 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val) 2808 { 2809 core->mac[RXCSUM] = val; 2810 e1000e_update_rx_offloads(core); 2811 } 2812 2813 static void 2814 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val) 2815 { 2816 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS; 2817 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits; 2818 } 2819 2820 #define e1000e_getreg(x) [x] = e1000e_mac_readreg 2821 static uint32_t (*e1000e_macreg_readops[])(E1000ECore *, int) = { 2822 e1000e_getreg(PBA), 2823 e1000e_getreg(WUFC), 2824 e1000e_getreg(MANC), 2825 e1000e_getreg(TOTL), 2826 e1000e_getreg(RDT0), 2827 e1000e_getreg(RDBAH0), 2828 e1000e_getreg(TDBAL1), 2829 e1000e_getreg(RDLEN0), 2830 e1000e_getreg(RDH1), 2831 e1000e_getreg(LATECOL), 2832 e1000e_getreg(SEC), 2833 e1000e_getreg(XONTXC), 2834 e1000e_getreg(WUS), 2835 e1000e_getreg(GORCL), 2836 e1000e_getreg(MGTPRC), 2837 e1000e_getreg(EERD), 2838 e1000e_getreg(EIAC), 2839 e1000e_getreg(PSRCTL), 2840 e1000e_getreg(MANC2H), 2841 e1000e_getreg(RXCSUM), 2842 e1000e_getreg(GSCL_3), 2843 e1000e_getreg(GSCN_2), 2844 e1000e_getreg(RSRPD), 2845 e1000e_getreg(RDBAL1), 2846 e1000e_getreg(FCAH), 2847 e1000e_getreg(FCRTH), 2848 e1000e_getreg(FLOP), 2849 e1000e_getreg(FLASHT), 2850 e1000e_getreg(RXSTMPH), 2851 e1000e_getreg(TXSTMPL), 2852 e1000e_getreg(TIMADJL), 2853 e1000e_getreg(TXDCTL), 2854 e1000e_getreg(RDH0), 2855 e1000e_getreg(TDT1), 2856 e1000e_getreg(TNCRS), 2857 e1000e_getreg(RJC), 2858 e1000e_getreg(IAM), 2859 e1000e_getreg(GSCL_2), 2860 e1000e_getreg(RDBAH1), 2861 e1000e_getreg(FLSWDATA), 2862 e1000e_getreg(RXSATRH), 2863 e1000e_getreg(TIPG), 2864 e1000e_getreg(FLMNGCTL), 2865 e1000e_getreg(FLMNGCNT), 2866 e1000e_getreg(TSYNCTXCTL), 2867 e1000e_getreg(EXTCNF_SIZE), 2868 e1000e_getreg(EXTCNF_CTRL), 2869 e1000e_getreg(EEMNGDATA), 2870 e1000e_getreg(CTRL_EXT), 2871 e1000e_getreg(SYSTIMH), 2872 e1000e_getreg(EEMNGCTL), 2873 e1000e_getreg(FLMNGDATA), 2874 e1000e_getreg(TSYNCRXCTL), 2875 e1000e_getreg(TDH), 2876 e1000e_getreg(LEDCTL), 2877 e1000e_getreg(STATUS), 2878 e1000e_getreg(TCTL), 2879 e1000e_getreg(TDBAL), 2880 e1000e_getreg(TDLEN), 2881 e1000e_getreg(TDH1), 2882 e1000e_getreg(RADV), 2883 e1000e_getreg(ECOL), 2884 e1000e_getreg(DC), 2885 e1000e_getreg(RLEC), 2886 e1000e_getreg(XOFFTXC), 2887 e1000e_getreg(RFC), 2888 e1000e_getreg(RNBC), 2889 e1000e_getreg(MGTPTC), 2890 e1000e_getreg(TIMINCA), 2891 e1000e_getreg(RXCFGL), 2892 e1000e_getreg(MFUTP01), 2893 e1000e_getreg(FACTPS), 2894 e1000e_getreg(GSCL_1), 2895 e1000e_getreg(GSCN_0), 2896 e1000e_getreg(GCR2), 2897 e1000e_getreg(RDT1), 2898 e1000e_getreg(PBACLR), 2899 e1000e_getreg(FCTTV), 2900 e1000e_getreg(EEWR), 2901 e1000e_getreg(FLSWCTL), 2902 e1000e_getreg(RXDCTL1), 2903 e1000e_getreg(RXSATRL), 2904 e1000e_getreg(SYSTIML), 2905 e1000e_getreg(RXUDP), 2906 e1000e_getreg(TORL), 2907 e1000e_getreg(TDLEN1), 2908 e1000e_getreg(MCC), 2909 e1000e_getreg(WUC), 2910 e1000e_getreg(EECD), 2911 e1000e_getreg(MFUTP23), 2912 e1000e_getreg(RAID), 2913 e1000e_getreg(FCRTV), 2914 e1000e_getreg(TXDCTL1), 2915 e1000e_getreg(RCTL), 2916 e1000e_getreg(TDT), 2917 e1000e_getreg(MDIC), 2918 e1000e_getreg(FCRUC), 2919 e1000e_getreg(VET), 2920 e1000e_getreg(RDBAL0), 2921 e1000e_getreg(TDBAH1), 2922 e1000e_getreg(RDTR), 2923 e1000e_getreg(SCC), 2924 e1000e_getreg(COLC), 2925 e1000e_getreg(CEXTERR), 2926 e1000e_getreg(XOFFRXC), 2927 e1000e_getreg(IPAV), 2928 e1000e_getreg(GOTCL), 2929 e1000e_getreg(MGTPDC), 2930 e1000e_getreg(GCR), 2931 e1000e_getreg(IVAR), 2932 e1000e_getreg(POEMB), 2933 e1000e_getreg(MFVAL), 2934 e1000e_getreg(FUNCTAG), 2935 e1000e_getreg(GSCL_4), 2936 e1000e_getreg(GSCN_3), 2937 e1000e_getreg(MRQC), 2938 e1000e_getreg(RDLEN1), 2939 e1000e_getreg(FCT), 2940 e1000e_getreg(FLA), 2941 e1000e_getreg(FLOL), 2942 e1000e_getreg(RXDCTL), 2943 e1000e_getreg(RXSTMPL), 2944 e1000e_getreg(TXSTMPH), 2945 e1000e_getreg(TIMADJH), 2946 e1000e_getreg(FCRTL), 2947 e1000e_getreg(TDBAH), 2948 e1000e_getreg(TADV), 2949 e1000e_getreg(XONRXC), 2950 e1000e_getreg(TSCTFC), 2951 e1000e_getreg(RFCTL), 2952 e1000e_getreg(GSCN_1), 2953 e1000e_getreg(FCAL), 2954 e1000e_getreg(FLSWCNT), 2955 2956 [TOTH] = e1000e_mac_read_clr8, 2957 [GOTCH] = e1000e_mac_read_clr8, 2958 [PRC64] = e1000e_mac_read_clr4, 2959 [PRC255] = e1000e_mac_read_clr4, 2960 [PRC1023] = e1000e_mac_read_clr4, 2961 [PTC64] = e1000e_mac_read_clr4, 2962 [PTC255] = e1000e_mac_read_clr4, 2963 [PTC1023] = e1000e_mac_read_clr4, 2964 [GPRC] = e1000e_mac_read_clr4, 2965 [TPT] = e1000e_mac_read_clr4, 2966 [RUC] = e1000e_mac_read_clr4, 2967 [BPRC] = e1000e_mac_read_clr4, 2968 [MPTC] = e1000e_mac_read_clr4, 2969 [IAC] = e1000e_mac_read_clr4, 2970 [ICR] = e1000e_mac_icr_read, 2971 [RDFH] = E1000E_LOW_BITS_READ(13), 2972 [RDFHS] = E1000E_LOW_BITS_READ(13), 2973 [RDFPC] = E1000E_LOW_BITS_READ(13), 2974 [TDFH] = E1000E_LOW_BITS_READ(13), 2975 [TDFHS] = E1000E_LOW_BITS_READ(13), 2976 [STATUS] = e1000e_get_status, 2977 [TARC0] = e1000e_get_tarc, 2978 [PBS] = E1000E_LOW_BITS_READ(6), 2979 [ICS] = e1000e_mac_ics_read, 2980 [AIT] = E1000E_LOW_BITS_READ(16), 2981 [TORH] = e1000e_mac_read_clr8, 2982 [GORCH] = e1000e_mac_read_clr8, 2983 [PRC127] = e1000e_mac_read_clr4, 2984 [PRC511] = e1000e_mac_read_clr4, 2985 [PRC1522] = e1000e_mac_read_clr4, 2986 [PTC127] = e1000e_mac_read_clr4, 2987 [PTC511] = e1000e_mac_read_clr4, 2988 [PTC1522] = e1000e_mac_read_clr4, 2989 [GPTC] = e1000e_mac_read_clr4, 2990 [TPR] = e1000e_mac_read_clr4, 2991 [ROC] = e1000e_mac_read_clr4, 2992 [MPRC] = e1000e_mac_read_clr4, 2993 [BPTC] = e1000e_mac_read_clr4, 2994 [TSCTC] = e1000e_mac_read_clr4, 2995 [ITR] = e1000e_mac_itr_read, 2996 [RDFT] = E1000E_LOW_BITS_READ(13), 2997 [RDFTS] = E1000E_LOW_BITS_READ(13), 2998 [TDFPC] = E1000E_LOW_BITS_READ(13), 2999 [TDFT] = E1000E_LOW_BITS_READ(13), 3000 [TDFTS] = E1000E_LOW_BITS_READ(13), 3001 [CTRL] = e1000e_get_ctrl, 3002 [TARC1] = e1000e_get_tarc, 3003 [SWSM] = e1000e_mac_swsm_read, 3004 [IMS] = e1000e_mac_ims_read, 3005 3006 [CRCERRS ... MPC] = e1000e_mac_readreg, 3007 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg, 3008 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg, 3009 [RA ... RA + 31] = e1000e_mac_readreg, 3010 [WUPM ... WUPM + 31] = e1000e_mac_readreg, 3011 [MTA ... MTA + 127] = e1000e_mac_readreg, 3012 [VFTA ... VFTA + 127] = e1000e_mac_readreg, 3013 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4), 3014 [FFVT ... FFVT + 254] = e1000e_mac_readreg, 3015 [MDEF ... MDEF + 7] = e1000e_mac_readreg, 3016 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11), 3017 [FTFT ... FTFT + 254] = e1000e_mac_readreg, 3018 [PBM ... PBM + 10239] = e1000e_mac_readreg, 3019 [RETA ... RETA + 31] = e1000e_mac_readreg, 3020 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg, 3021 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg, 3022 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read 3023 }; 3024 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) }; 3025 3026 #define e1000e_putreg(x) [x] = e1000e_mac_writereg 3027 static void (*e1000e_macreg_writeops[])(E1000ECore *, int, uint32_t) = { 3028 e1000e_putreg(PBA), 3029 e1000e_putreg(SWSM), 3030 e1000e_putreg(WUFC), 3031 e1000e_putreg(RDBAH1), 3032 e1000e_putreg(TDBAH), 3033 e1000e_putreg(TXDCTL), 3034 e1000e_putreg(RDBAH0), 3035 e1000e_putreg(LEDCTL), 3036 e1000e_putreg(FCAL), 3037 e1000e_putreg(FCRUC), 3038 e1000e_putreg(AIT), 3039 e1000e_putreg(TDFH), 3040 e1000e_putreg(TDFT), 3041 e1000e_putreg(TDFHS), 3042 e1000e_putreg(TDFTS), 3043 e1000e_putreg(TDFPC), 3044 e1000e_putreg(WUC), 3045 e1000e_putreg(WUS), 3046 e1000e_putreg(RDFH), 3047 e1000e_putreg(RDFT), 3048 e1000e_putreg(RDFHS), 3049 e1000e_putreg(RDFTS), 3050 e1000e_putreg(RDFPC), 3051 e1000e_putreg(IPAV), 3052 e1000e_putreg(TDBAH1), 3053 e1000e_putreg(TIMINCA), 3054 e1000e_putreg(IAM), 3055 e1000e_putreg(EIAC), 3056 e1000e_putreg(IVAR), 3057 e1000e_putreg(TARC0), 3058 e1000e_putreg(TARC1), 3059 e1000e_putreg(FLSWDATA), 3060 e1000e_putreg(POEMB), 3061 e1000e_putreg(PBS), 3062 e1000e_putreg(MFUTP01), 3063 e1000e_putreg(MFUTP23), 3064 e1000e_putreg(MANC), 3065 e1000e_putreg(MANC2H), 3066 e1000e_putreg(MFVAL), 3067 e1000e_putreg(EXTCNF_CTRL), 3068 e1000e_putreg(FACTPS), 3069 e1000e_putreg(FUNCTAG), 3070 e1000e_putreg(GSCL_1), 3071 e1000e_putreg(GSCL_2), 3072 e1000e_putreg(GSCL_3), 3073 e1000e_putreg(GSCL_4), 3074 e1000e_putreg(GSCN_0), 3075 e1000e_putreg(GSCN_1), 3076 e1000e_putreg(GSCN_2), 3077 e1000e_putreg(GSCN_3), 3078 e1000e_putreg(GCR2), 3079 e1000e_putreg(MRQC), 3080 e1000e_putreg(FLOP), 3081 e1000e_putreg(FLOL), 3082 e1000e_putreg(FLSWCTL), 3083 e1000e_putreg(FLSWCNT), 3084 e1000e_putreg(FLA), 3085 e1000e_putreg(RXDCTL1), 3086 e1000e_putreg(TXDCTL1), 3087 e1000e_putreg(TIPG), 3088 e1000e_putreg(RXSTMPH), 3089 e1000e_putreg(RXSTMPL), 3090 e1000e_putreg(RXSATRL), 3091 e1000e_putreg(RXSATRH), 3092 e1000e_putreg(TXSTMPL), 3093 e1000e_putreg(TXSTMPH), 3094 e1000e_putreg(SYSTIML), 3095 e1000e_putreg(SYSTIMH), 3096 e1000e_putreg(TIMADJL), 3097 e1000e_putreg(TIMADJH), 3098 e1000e_putreg(RXUDP), 3099 e1000e_putreg(RXCFGL), 3100 e1000e_putreg(TSYNCRXCTL), 3101 e1000e_putreg(TSYNCTXCTL), 3102 e1000e_putreg(FLSWDATA), 3103 e1000e_putreg(EXTCNF_SIZE), 3104 e1000e_putreg(EEMNGCTL), 3105 e1000e_putreg(RA), 3106 3107 [TDH1] = e1000e_set_16bit, 3108 [TDT1] = e1000e_set_tdt, 3109 [TCTL] = e1000e_set_tctl, 3110 [TDT] = e1000e_set_tdt, 3111 [MDIC] = e1000e_set_mdic, 3112 [ICS] = e1000e_set_ics, 3113 [TDH] = e1000e_set_16bit, 3114 [RDH0] = e1000e_set_16bit, 3115 [RDT0] = e1000e_set_rdt, 3116 [IMC] = e1000e_set_imc, 3117 [IMS] = e1000e_set_ims, 3118 [ICR] = e1000e_set_icr, 3119 [EECD] = e1000e_set_eecd, 3120 [RCTL] = e1000e_set_rx_control, 3121 [CTRL] = e1000e_set_ctrl, 3122 [RDTR] = e1000e_set_rdtr, 3123 [RADV] = e1000e_set_16bit, 3124 [TADV] = e1000e_set_16bit, 3125 [ITR] = e1000e_set_itr, 3126 [EERD] = e1000e_set_eerd, 3127 [GCR] = e1000e_set_gcr, 3128 [PSRCTL] = e1000e_set_psrctl, 3129 [RXCSUM] = e1000e_set_rxcsum, 3130 [RAID] = e1000e_set_16bit, 3131 [RSRPD] = e1000e_set_12bit, 3132 [TIDV] = e1000e_set_tidv, 3133 [TDLEN1] = e1000e_set_dlen, 3134 [TDLEN] = e1000e_set_dlen, 3135 [RDLEN0] = e1000e_set_dlen, 3136 [RDLEN1] = e1000e_set_dlen, 3137 [TDBAL] = e1000e_set_dbal, 3138 [TDBAL1] = e1000e_set_dbal, 3139 [RDBAL0] = e1000e_set_dbal, 3140 [RDBAL1] = e1000e_set_dbal, 3141 [RDH1] = e1000e_set_16bit, 3142 [RDT1] = e1000e_set_rdt, 3143 [STATUS] = e1000e_set_status, 3144 [PBACLR] = e1000e_set_pbaclr, 3145 [CTRL_EXT] = e1000e_set_ctrlext, 3146 [FCAH] = e1000e_set_16bit, 3147 [FCT] = e1000e_set_16bit, 3148 [FCTTV] = e1000e_set_16bit, 3149 [FCRTV] = e1000e_set_16bit, 3150 [FCRTH] = e1000e_set_fcrth, 3151 [FCRTL] = e1000e_set_fcrtl, 3152 [VET] = e1000e_set_vet, 3153 [RXDCTL] = e1000e_set_rxdctl, 3154 [FLASHT] = e1000e_set_16bit, 3155 [EEWR] = e1000e_set_eewr, 3156 [CTRL_DUP] = e1000e_set_ctrl, 3157 [RFCTL] = e1000e_set_rfctl, 3158 [RA + 1] = e1000e_mac_setmacaddr, 3159 3160 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg, 3161 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg, 3162 [RA + 2 ... RA + 31] = e1000e_mac_writereg, 3163 [WUPM ... WUPM + 31] = e1000e_mac_writereg, 3164 [MTA ... MTA + 127] = e1000e_mac_writereg, 3165 [VFTA ... VFTA + 127] = e1000e_mac_writereg, 3166 [FFMT ... FFMT + 254] = e1000e_mac_writereg, 3167 [FFVT ... FFVT + 254] = e1000e_mac_writereg, 3168 [PBM ... PBM + 10239] = e1000e_mac_writereg, 3169 [MDEF ... MDEF + 7] = e1000e_mac_writereg, 3170 [FFLT ... FFLT + 10] = e1000e_mac_writereg, 3171 [FTFT ... FTFT + 254] = e1000e_mac_writereg, 3172 [RETA ... RETA + 31] = e1000e_mac_writereg, 3173 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg, 3174 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg, 3175 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr 3176 }; 3177 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) }; 3178 3179 enum { MAC_ACCESS_PARTIAL = 1 }; 3180 3181 /* The array below combines alias offsets of the index values for the 3182 * MAC registers that have aliases, with the indication of not fully 3183 * implemented registers (lowest bit). This combination is possible 3184 * because all of the offsets are even. */ 3185 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = { 3186 /* Alias index offsets */ 3187 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802, 3188 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6, 3189 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904, 3190 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8, 3191 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00, 3192 [RA_A ... RA_A + 31] = 0x14f0, 3193 [VFTA_A ... VFTA_A + 127] = 0x1400, 3194 [RDBAL0_A ... RDLEN0_A] = 0x09bc, 3195 [TDBAL_A ... TDLEN_A] = 0x0cf8, 3196 /* Access options */ 3197 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL, 3198 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL, 3199 [RDFPC] = MAC_ACCESS_PARTIAL, 3200 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL, 3201 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL, 3202 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL, 3203 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL, 3204 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL, 3205 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL, 3206 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL, 3207 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL, 3208 [TXDCTL1] = MAC_ACCESS_PARTIAL, 3209 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL 3210 }; 3211 3212 void 3213 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size) 3214 { 3215 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3216 3217 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) { 3218 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3219 trace_e1000e_wrn_regs_write_trivial(index << 2); 3220 } 3221 trace_e1000e_core_write(index << 2, size, val); 3222 e1000e_macreg_writeops[index](core, index, val); 3223 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3224 trace_e1000e_wrn_regs_write_ro(index << 2, size, val); 3225 } else { 3226 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val); 3227 } 3228 } 3229 3230 uint64_t 3231 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size) 3232 { 3233 uint64_t val; 3234 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr); 3235 3236 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) { 3237 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) { 3238 trace_e1000e_wrn_regs_read_trivial(index << 2); 3239 } 3240 val = e1000e_macreg_readops[index](core, index); 3241 trace_e1000e_core_read(index << 2, size, val); 3242 return val; 3243 } else { 3244 trace_e1000e_wrn_regs_read_unknown(index << 2, size); 3245 } 3246 return 0; 3247 } 3248 3249 static inline void 3250 e1000e_autoneg_pause(E1000ECore *core) 3251 { 3252 timer_del(core->autoneg_timer); 3253 } 3254 3255 static void 3256 e1000e_autoneg_resume(E1000ECore *core) 3257 { 3258 if (e1000e_have_autoneg(core) && 3259 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) { 3260 qemu_get_queue(core->owner_nic)->link_down = false; 3261 timer_mod(core->autoneg_timer, 3262 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 3263 } 3264 } 3265 3266 static void 3267 e1000e_vm_state_change(void *opaque, int running, RunState state) 3268 { 3269 E1000ECore *core = opaque; 3270 3271 if (running) { 3272 trace_e1000e_vm_state_running(); 3273 e1000e_intrmgr_resume(core); 3274 e1000e_autoneg_resume(core); 3275 } else { 3276 trace_e1000e_vm_state_stopped(); 3277 e1000e_autoneg_pause(core); 3278 e1000e_intrmgr_pause(core); 3279 } 3280 } 3281 3282 void 3283 e1000e_core_pci_realize(E1000ECore *core, 3284 const uint16_t *eeprom_templ, 3285 uint32_t eeprom_size, 3286 const uint8_t *macaddr) 3287 { 3288 int i; 3289 3290 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3291 e1000e_autoneg_timer, core); 3292 e1000e_intrmgr_pci_realize(core); 3293 3294 core->vmstate = 3295 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core); 3296 3297 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3298 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner, 3299 E1000E_MAX_TX_FRAGS, core->has_vnet); 3300 } 3301 3302 net_rx_pkt_init(&core->rx_pkt, core->has_vnet); 3303 3304 e1000x_core_prepare_eeprom(core->eeprom, 3305 eeprom_templ, 3306 eeprom_size, 3307 PCI_DEVICE_GET_CLASS(core->owner)->device_id, 3308 macaddr); 3309 e1000e_update_rx_offloads(core); 3310 } 3311 3312 void 3313 e1000e_core_pci_uninit(E1000ECore *core) 3314 { 3315 int i; 3316 3317 timer_del(core->autoneg_timer); 3318 timer_free(core->autoneg_timer); 3319 3320 e1000e_intrmgr_pci_unint(core); 3321 3322 qemu_del_vm_change_state_handler(core->vmstate); 3323 3324 for (i = 0; i < E1000E_NUM_QUEUES; i++) { 3325 net_tx_pkt_reset(core->tx[i].tx_pkt); 3326 net_tx_pkt_uninit(core->tx[i].tx_pkt); 3327 } 3328 3329 net_rx_pkt_uninit(core->rx_pkt); 3330 } 3331 3332 static const uint16_t 3333 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = { 3334 [0] = { 3335 [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB | 3336 MII_CR_FULL_DUPLEX | 3337 MII_CR_AUTO_NEG_EN, 3338 3339 [PHY_STATUS] = MII_SR_EXTENDED_CAPS | 3340 MII_SR_LINK_STATUS | 3341 MII_SR_AUTONEG_CAPS | 3342 MII_SR_PREAMBLE_SUPPRESS | 3343 MII_SR_EXTENDED_STATUS | 3344 MII_SR_10T_HD_CAPS | 3345 MII_SR_10T_FD_CAPS | 3346 MII_SR_100X_HD_CAPS | 3347 MII_SR_100X_FD_CAPS, 3348 3349 [PHY_ID1] = 0x141, 3350 [PHY_ID2] = E1000_PHY_ID2_82574x, 3351 [PHY_AUTONEG_ADV] = 0xde1, 3352 [PHY_LP_ABILITY] = 0x7e0, 3353 [PHY_AUTONEG_EXP] = BIT(2), 3354 [PHY_NEXT_PAGE_TX] = BIT(0) | BIT(13), 3355 [PHY_1000T_CTRL] = BIT(8) | BIT(9) | BIT(10) | BIT(11), 3356 [PHY_1000T_STATUS] = 0x3c00, 3357 [PHY_EXT_STATUS] = BIT(12) | BIT(13), 3358 3359 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) | 3360 BIT(12) | BIT(13), 3361 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15) 3362 }, 3363 [2] = { 3364 [PHY_MAC_CTRL1] = BIT(3) | BIT(7), 3365 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12) 3366 }, 3367 [3] = { 3368 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14) 3369 } 3370 }; 3371 3372 static const uint32_t e1000e_mac_reg_init[] = { 3373 [PBA] = 0x00140014, 3374 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18), 3375 [EXTCNF_CTRL] = BIT(3), 3376 [EEMNGCTL] = BIT(31), 3377 [FLASHT] = 0x2, 3378 [FLSWCTL] = BIT(30) | BIT(31), 3379 [FLOL] = BIT(0), 3380 [RXDCTL] = BIT(16), 3381 [RXDCTL1] = BIT(16), 3382 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20), 3383 [RXCFGL] = 0x88F7, 3384 [RXUDP] = 0x319, 3385 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 | 3386 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU | 3387 E1000_CTRL_ADVD3WUC, 3388 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU, 3389 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) | 3390 (4 << E1000_PSRCTL_BSIZE1_SHIFT) | 3391 (4 << E1000_PSRCTL_BSIZE2_SHIFT), 3392 [TARC0] = 0x3 | E1000_TARC_ENABLE, 3393 [TARC1] = 0x3 | E1000_TARC_ENABLE, 3394 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES, 3395 [EERD] = E1000_EERW_DONE, 3396 [EEWR] = E1000_EERW_DONE, 3397 [GCR] = E1000_L0S_ADJUST | 3398 E1000_L1_ENTRY_LATENCY_MSB | 3399 E1000_L1_ENTRY_LATENCY_LSB, 3400 [TDFH] = 0x600, 3401 [TDFT] = 0x600, 3402 [TDFHS] = 0x600, 3403 [TDFTS] = 0x600, 3404 [POEMB] = 0x30D, 3405 [PBS] = 0x028, 3406 [MANC] = E1000_MANC_DIS_IP_CHK_ARP, 3407 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000, 3408 [SWSM] = 1, 3409 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD, 3410 [ITR] = E1000E_MIN_XITR, 3411 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR, 3412 }; 3413 3414 void 3415 e1000e_core_reset(E1000ECore *core) 3416 { 3417 int i; 3418 3419 timer_del(core->autoneg_timer); 3420 3421 e1000e_intrmgr_reset(core); 3422 3423 memset(core->phy, 0, sizeof core->phy); 3424 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init); 3425 memset(core->mac, 0, sizeof core->mac); 3426 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init); 3427 3428 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT; 3429 3430 if (qemu_get_queue(core->owner_nic)->link_down) { 3431 e1000e_link_down(core); 3432 } 3433 3434 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac); 3435 3436 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3437 net_tx_pkt_reset(core->tx[i].tx_pkt); 3438 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props)); 3439 core->tx[i].skip_cp = false; 3440 } 3441 } 3442 3443 void e1000e_core_pre_save(E1000ECore *core) 3444 { 3445 int i; 3446 NetClientState *nc = qemu_get_queue(core->owner_nic); 3447 3448 /* 3449 * If link is down and auto-negotiation is supported and ongoing, 3450 * complete auto-negotiation immediately. This allows us to look 3451 * at MII_SR_AUTONEG_COMPLETE to infer link status on load. 3452 */ 3453 if (nc->link_down && e1000e_have_autoneg(core)) { 3454 core->phy[0][PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE; 3455 e1000e_update_flowctl_status(core); 3456 } 3457 3458 for (i = 0; i < ARRAY_SIZE(core->tx); i++) { 3459 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) { 3460 core->tx[i].skip_cp = true; 3461 } 3462 } 3463 } 3464 3465 int 3466 e1000e_core_post_load(E1000ECore *core) 3467 { 3468 NetClientState *nc = qemu_get_queue(core->owner_nic); 3469 3470 /* nc.link_down can't be migrated, so infer link_down according 3471 * to link status bit in core.mac[STATUS]. 3472 */ 3473 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0; 3474 3475 return 0; 3476 } 3477