1 /* 2 * QEMU INTEL 82574 GbE NIC emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/units.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "qemu/module.h" 41 #include "qemu/range.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/hw.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci/msix.h" 46 #include "migration/vmstate.h" 47 48 #include "e1000_regs.h" 49 50 #include "e1000x_common.h" 51 #include "e1000e_core.h" 52 53 #include "trace.h" 54 #include "qapi/error.h" 55 56 #define TYPE_E1000E "e1000e" 57 #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E) 58 59 typedef struct E1000EState { 60 PCIDevice parent_obj; 61 NICState *nic; 62 NICConf conf; 63 64 MemoryRegion mmio; 65 MemoryRegion flash; 66 MemoryRegion io; 67 MemoryRegion msix; 68 69 uint32_t ioaddr; 70 71 uint16_t subsys_ven; 72 uint16_t subsys; 73 74 uint16_t subsys_ven_used; 75 uint16_t subsys_used; 76 77 bool disable_vnet; 78 79 E1000ECore core; 80 81 } E1000EState; 82 83 #define E1000E_MMIO_IDX 0 84 #define E1000E_FLASH_IDX 1 85 #define E1000E_IO_IDX 2 86 #define E1000E_MSIX_IDX 3 87 88 #define E1000E_MMIO_SIZE (128 * KiB) 89 #define E1000E_FLASH_SIZE (128 * KiB) 90 #define E1000E_IO_SIZE (32) 91 #define E1000E_MSIX_SIZE (16 * KiB) 92 93 #define E1000E_MSIX_TABLE (0x0000) 94 #define E1000E_MSIX_PBA (0x2000) 95 96 static uint64_t 97 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size) 98 { 99 E1000EState *s = opaque; 100 return e1000e_core_read(&s->core, addr, size); 101 } 102 103 static void 104 e1000e_mmio_write(void *opaque, hwaddr addr, 105 uint64_t val, unsigned size) 106 { 107 E1000EState *s = opaque; 108 e1000e_core_write(&s->core, addr, val, size); 109 } 110 111 static bool 112 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx) 113 { 114 if (s->ioaddr < 0x1FFFF) { 115 *idx = s->ioaddr; 116 return true; 117 } 118 119 if (s->ioaddr < 0x7FFFF) { 120 trace_e1000e_wrn_io_addr_undefined(s->ioaddr); 121 return false; 122 } 123 124 if (s->ioaddr < 0xFFFFF) { 125 trace_e1000e_wrn_io_addr_flash(s->ioaddr); 126 return false; 127 } 128 129 trace_e1000e_wrn_io_addr_unknown(s->ioaddr); 130 return false; 131 } 132 133 static uint64_t 134 e1000e_io_read(void *opaque, hwaddr addr, unsigned size) 135 { 136 E1000EState *s = opaque; 137 uint32_t idx = 0; 138 uint64_t val; 139 140 switch (addr) { 141 case E1000_IOADDR: 142 trace_e1000e_io_read_addr(s->ioaddr); 143 return s->ioaddr; 144 case E1000_IODATA: 145 if (e1000e_io_get_reg_index(s, &idx)) { 146 val = e1000e_core_read(&s->core, idx, sizeof(val)); 147 trace_e1000e_io_read_data(idx, val); 148 return val; 149 } 150 return 0; 151 default: 152 trace_e1000e_wrn_io_read_unknown(addr); 153 return 0; 154 } 155 } 156 157 static void 158 e1000e_io_write(void *opaque, hwaddr addr, 159 uint64_t val, unsigned size) 160 { 161 E1000EState *s = opaque; 162 uint32_t idx = 0; 163 164 switch (addr) { 165 case E1000_IOADDR: 166 trace_e1000e_io_write_addr(val); 167 s->ioaddr = (uint32_t) val; 168 return; 169 case E1000_IODATA: 170 if (e1000e_io_get_reg_index(s, &idx)) { 171 trace_e1000e_io_write_data(idx, val); 172 e1000e_core_write(&s->core, idx, val, sizeof(val)); 173 } 174 return; 175 default: 176 trace_e1000e_wrn_io_write_unknown(addr); 177 return; 178 } 179 } 180 181 static const MemoryRegionOps mmio_ops = { 182 .read = e1000e_mmio_read, 183 .write = e1000e_mmio_write, 184 .endianness = DEVICE_LITTLE_ENDIAN, 185 .impl = { 186 .min_access_size = 4, 187 .max_access_size = 4, 188 }, 189 }; 190 191 static const MemoryRegionOps io_ops = { 192 .read = e1000e_io_read, 193 .write = e1000e_io_write, 194 .endianness = DEVICE_LITTLE_ENDIAN, 195 .impl = { 196 .min_access_size = 4, 197 .max_access_size = 4, 198 }, 199 }; 200 201 static int 202 e1000e_nc_can_receive(NetClientState *nc) 203 { 204 E1000EState *s = qemu_get_nic_opaque(nc); 205 return e1000e_can_receive(&s->core); 206 } 207 208 static ssize_t 209 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) 210 { 211 E1000EState *s = qemu_get_nic_opaque(nc); 212 return e1000e_receive_iov(&s->core, iov, iovcnt); 213 } 214 215 static ssize_t 216 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size) 217 { 218 E1000EState *s = qemu_get_nic_opaque(nc); 219 return e1000e_receive(&s->core, buf, size); 220 } 221 222 static void 223 e1000e_set_link_status(NetClientState *nc) 224 { 225 E1000EState *s = qemu_get_nic_opaque(nc); 226 e1000e_core_set_link_status(&s->core); 227 } 228 229 static NetClientInfo net_e1000e_info = { 230 .type = NET_CLIENT_DRIVER_NIC, 231 .size = sizeof(NICState), 232 .can_receive = e1000e_nc_can_receive, 233 .receive = e1000e_nc_receive, 234 .receive_iov = e1000e_nc_receive_iov, 235 .link_status_changed = e1000e_set_link_status, 236 }; 237 238 /* 239 * EEPROM (NVM) contents documented in Table 36, section 6.1 240 * and generally 6.1.2 Software accessed words. 241 */ 242 static const uint16_t e1000e_eeprom_template[64] = { 243 /* Address | Compat. | ImVer | Compat. */ 244 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff, 245 /* PBA |ICtrl1 | SSID | SVID | DevID |-------|ICtrl2 */ 246 0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058, 247 /* NVM words 1,2,3 |-------------------------------|PCI-EID*/ 248 0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704, 249 /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */ 250 0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706, 251 /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/ 252 0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff, 253 /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP */ 254 0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff, 255 /* SW Section */ 256 0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff, 257 /* SW Section |CHKSUM */ 258 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000, 259 }; 260 261 static void e1000e_core_realize(E1000EState *s) 262 { 263 s->core.owner = &s->parent_obj; 264 s->core.owner_nic = s->nic; 265 } 266 267 static void 268 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors) 269 { 270 int i; 271 for (i = 0; i < num_vectors; i++) { 272 msix_vector_unuse(PCI_DEVICE(s), i); 273 } 274 } 275 276 static bool 277 e1000e_use_msix_vectors(E1000EState *s, int num_vectors) 278 { 279 int i; 280 for (i = 0; i < num_vectors; i++) { 281 int res = msix_vector_use(PCI_DEVICE(s), i); 282 if (res < 0) { 283 trace_e1000e_msix_use_vector_fail(i, res); 284 e1000e_unuse_msix_vectors(s, i); 285 return false; 286 } 287 } 288 return true; 289 } 290 291 static void 292 e1000e_init_msix(E1000EState *s) 293 { 294 PCIDevice *d = PCI_DEVICE(s); 295 int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM, 296 &s->msix, 297 E1000E_MSIX_IDX, E1000E_MSIX_TABLE, 298 &s->msix, 299 E1000E_MSIX_IDX, E1000E_MSIX_PBA, 300 0xA0, NULL); 301 302 if (res < 0) { 303 trace_e1000e_msix_init_fail(res); 304 } else { 305 if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) { 306 msix_uninit(d, &s->msix, &s->msix); 307 } 308 } 309 } 310 311 static void 312 e1000e_cleanup_msix(E1000EState *s) 313 { 314 if (msix_present(PCI_DEVICE(s))) { 315 e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM); 316 msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix); 317 } 318 } 319 320 static void 321 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr) 322 { 323 DeviceState *dev = DEVICE(pci_dev); 324 NetClientState *nc; 325 int i; 326 327 s->nic = qemu_new_nic(&net_e1000e_info, &s->conf, 328 object_get_typename(OBJECT(s)), dev->id, s); 329 330 s->core.max_queue_num = s->conf.peers.queues - 1; 331 332 trace_e1000e_mac_set_permanent(MAC_ARG(macaddr)); 333 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac)); 334 335 qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr); 336 337 /* Setup virtio headers */ 338 if (s->disable_vnet) { 339 s->core.has_vnet = false; 340 trace_e1000e_cfg_support_virtio(false); 341 return; 342 } else { 343 s->core.has_vnet = true; 344 } 345 346 for (i = 0; i < s->conf.peers.queues; i++) { 347 nc = qemu_get_subqueue(s->nic, i); 348 if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) { 349 s->core.has_vnet = false; 350 trace_e1000e_cfg_support_virtio(false); 351 return; 352 } 353 } 354 355 trace_e1000e_cfg_support_virtio(true); 356 357 for (i = 0; i < s->conf.peers.queues; i++) { 358 nc = qemu_get_subqueue(s->nic, i); 359 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr)); 360 qemu_using_vnet_hdr(nc->peer, true); 361 } 362 } 363 364 static inline uint64_t 365 e1000e_gen_dsn(uint8_t *mac) 366 { 367 return (uint64_t)(mac[5]) | 368 (uint64_t)(mac[4]) << 8 | 369 (uint64_t)(mac[3]) << 16 | 370 (uint64_t)(0x00FF) << 24 | 371 (uint64_t)(0x00FF) << 32 | 372 (uint64_t)(mac[2]) << 40 | 373 (uint64_t)(mac[1]) << 48 | 374 (uint64_t)(mac[0]) << 56; 375 } 376 377 static int 378 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) 379 { 380 Error *local_err = NULL; 381 int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, 382 PCI_PM_SIZEOF, &local_err); 383 384 if (local_err) { 385 error_report_err(local_err); 386 return ret; 387 } 388 389 pci_set_word(pdev->config + offset + PCI_PM_PMC, 390 PCI_PM_CAP_VER_1_1 | 391 pmc); 392 393 pci_set_word(pdev->wmask + offset + PCI_PM_CTRL, 394 PCI_PM_CTRL_STATE_MASK | 395 PCI_PM_CTRL_PME_ENABLE | 396 PCI_PM_CTRL_DATA_SEL_MASK); 397 398 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, 399 PCI_PM_CTRL_PME_STATUS); 400 401 return ret; 402 } 403 404 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, 405 uint32_t val, int len) 406 { 407 E1000EState *s = E1000E(pci_dev); 408 409 pci_default_write_config(pci_dev, address, val, len); 410 411 if (range_covers_byte(address, len, PCI_COMMAND) && 412 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { 413 e1000e_start_recv(&s->core); 414 } 415 } 416 417 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) 418 { 419 static const uint16_t e1000e_pmrb_offset = 0x0C8; 420 static const uint16_t e1000e_pcie_offset = 0x0E0; 421 static const uint16_t e1000e_aer_offset = 0x100; 422 static const uint16_t e1000e_dsn_offset = 0x140; 423 E1000EState *s = E1000E(pci_dev); 424 uint8_t *macaddr; 425 int ret; 426 427 trace_e1000e_cb_pci_realize(); 428 429 pci_dev->config_write = e1000e_write_config; 430 431 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 432 pci_dev->config[PCI_INTERRUPT_PIN] = 1; 433 434 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven); 435 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys); 436 437 s->subsys_ven_used = s->subsys_ven; 438 s->subsys_used = s->subsys; 439 440 /* Define IO/MMIO regions */ 441 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s, 442 "e1000e-mmio", E1000E_MMIO_SIZE); 443 pci_register_bar(pci_dev, E1000E_MMIO_IDX, 444 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio); 445 446 /* 447 * We provide a dummy implementation for the flash BAR 448 * for drivers that may theoretically probe for its presence. 449 */ 450 memory_region_init(&s->flash, OBJECT(s), 451 "e1000e-flash", E1000E_FLASH_SIZE); 452 pci_register_bar(pci_dev, E1000E_FLASH_IDX, 453 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash); 454 455 memory_region_init_io(&s->io, OBJECT(s), &io_ops, s, 456 "e1000e-io", E1000E_IO_SIZE); 457 pci_register_bar(pci_dev, E1000E_IO_IDX, 458 PCI_BASE_ADDRESS_SPACE_IO, &s->io); 459 460 memory_region_init(&s->msix, OBJECT(s), "e1000e-msix", 461 E1000E_MSIX_SIZE); 462 pci_register_bar(pci_dev, E1000E_MSIX_IDX, 463 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix); 464 465 /* Create networking backend */ 466 qemu_macaddr_default_if_unset(&s->conf.macaddr); 467 macaddr = s->conf.macaddr.a; 468 469 e1000e_init_msix(s); 470 471 if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { 472 hw_error("Failed to initialize PCIe capability"); 473 } 474 475 ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); 476 if (ret) { 477 trace_e1000e_msi_init_fail(ret); 478 } 479 480 if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, 481 PCI_PM_CAP_DSI) < 0) { 482 hw_error("Failed to initialize PM capability"); 483 } 484 485 if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, 486 PCI_ERR_SIZEOF, NULL) < 0) { 487 hw_error("Failed to initialize AER capability"); 488 } 489 490 pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset, 491 e1000e_gen_dsn(macaddr)); 492 493 e1000e_init_net_peer(s, pci_dev, macaddr); 494 495 /* Initialize core */ 496 e1000e_core_realize(s); 497 498 e1000e_core_pci_realize(&s->core, 499 e1000e_eeprom_template, 500 sizeof(e1000e_eeprom_template), 501 macaddr); 502 } 503 504 static void e1000e_pci_uninit(PCIDevice *pci_dev) 505 { 506 E1000EState *s = E1000E(pci_dev); 507 508 trace_e1000e_cb_pci_uninit(); 509 510 e1000e_core_pci_uninit(&s->core); 511 512 pcie_aer_exit(pci_dev); 513 pcie_cap_exit(pci_dev); 514 515 qemu_del_nic(s->nic); 516 517 e1000e_cleanup_msix(s); 518 msi_uninit(pci_dev); 519 } 520 521 static void e1000e_qdev_reset(DeviceState *dev) 522 { 523 E1000EState *s = E1000E(dev); 524 525 trace_e1000e_cb_qdev_reset(); 526 527 e1000e_core_reset(&s->core); 528 } 529 530 static int e1000e_pre_save(void *opaque) 531 { 532 E1000EState *s = opaque; 533 534 trace_e1000e_cb_pre_save(); 535 536 e1000e_core_pre_save(&s->core); 537 538 return 0; 539 } 540 541 static int e1000e_post_load(void *opaque, int version_id) 542 { 543 E1000EState *s = opaque; 544 545 trace_e1000e_cb_post_load(); 546 547 if ((s->subsys != s->subsys_used) || 548 (s->subsys_ven != s->subsys_ven_used)) { 549 fprintf(stderr, 550 "ERROR: Cannot migrate while device properties " 551 "(subsys/subsys_ven) differ"); 552 return -1; 553 } 554 555 return e1000e_core_post_load(&s->core); 556 } 557 558 static const VMStateDescription e1000e_vmstate_tx = { 559 .name = "e1000e-tx", 560 .version_id = 1, 561 .minimum_version_id = 1, 562 .fields = (VMStateField[]) { 563 VMSTATE_UINT8(sum_needed, struct e1000e_tx), 564 VMSTATE_UINT8(props.ipcss, struct e1000e_tx), 565 VMSTATE_UINT8(props.ipcso, struct e1000e_tx), 566 VMSTATE_UINT16(props.ipcse, struct e1000e_tx), 567 VMSTATE_UINT8(props.tucss, struct e1000e_tx), 568 VMSTATE_UINT8(props.tucso, struct e1000e_tx), 569 VMSTATE_UINT16(props.tucse, struct e1000e_tx), 570 VMSTATE_UINT8(props.hdr_len, struct e1000e_tx), 571 VMSTATE_UINT16(props.mss, struct e1000e_tx), 572 VMSTATE_UINT32(props.paylen, struct e1000e_tx), 573 VMSTATE_INT8(props.ip, struct e1000e_tx), 574 VMSTATE_INT8(props.tcp, struct e1000e_tx), 575 VMSTATE_BOOL(props.tse, struct e1000e_tx), 576 VMSTATE_BOOL(cptse, struct e1000e_tx), 577 VMSTATE_BOOL(skip_cp, struct e1000e_tx), 578 VMSTATE_END_OF_LIST() 579 } 580 }; 581 582 static const VMStateDescription e1000e_vmstate_intr_timer = { 583 .name = "e1000e-intr-timer", 584 .version_id = 1, 585 .minimum_version_id = 1, 586 .fields = (VMStateField[]) { 587 VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer), 588 VMSTATE_BOOL(running, E1000IntrDelayTimer), 589 VMSTATE_END_OF_LIST() 590 } 591 }; 592 593 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \ 594 VMSTATE_STRUCT(_f, _s, 0, \ 595 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 596 597 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \ 598 VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \ 599 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 600 601 static const VMStateDescription e1000e_vmstate = { 602 .name = "e1000e", 603 .version_id = 1, 604 .minimum_version_id = 1, 605 .pre_save = e1000e_pre_save, 606 .post_load = e1000e_post_load, 607 .fields = (VMStateField[]) { 608 VMSTATE_PCI_DEVICE(parent_obj, E1000EState), 609 VMSTATE_MSIX(parent_obj, E1000EState), 610 611 VMSTATE_UINT32(ioaddr, E1000EState), 612 VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState), 613 VMSTATE_UINT8(core.rx_desc_len, E1000EState), 614 VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState, 615 E1000_PSRCTL_BUFFS_PER_DESC), 616 VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState), 617 VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE), 618 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState, 619 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE), 620 VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE), 621 VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN), 622 623 VMSTATE_UINT32(core.delayed_causes, E1000EState), 624 625 VMSTATE_UINT16(subsys, E1000EState), 626 VMSTATE_UINT16(subsys_ven, E1000EState), 627 628 VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState), 629 VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState), 630 VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState), 631 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState), 632 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState), 633 634 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState), 635 VMSTATE_BOOL(core.itr_intr_pending, E1000EState), 636 637 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState, 638 E1000E_MSIX_VEC_NUM), 639 VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState, 640 E1000E_MSIX_VEC_NUM), 641 642 VMSTATE_UINT32(core.itr_guest_value, E1000EState), 643 VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState, 644 E1000E_MSIX_VEC_NUM), 645 646 VMSTATE_UINT16(core.vet, E1000EState), 647 648 VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0, 649 e1000e_vmstate_tx, struct e1000e_tx), 650 VMSTATE_END_OF_LIST() 651 } 652 }; 653 654 static PropertyInfo e1000e_prop_disable_vnet, 655 e1000e_prop_subsys_ven, 656 e1000e_prop_subsys; 657 658 static Property e1000e_properties[] = { 659 DEFINE_NIC_PROPERTIES(E1000EState, conf), 660 DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false, 661 e1000e_prop_disable_vnet, bool), 662 DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven, 663 PCI_VENDOR_ID_INTEL, 664 e1000e_prop_subsys_ven, uint16_t), 665 DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0, 666 e1000e_prop_subsys, uint16_t), 667 DEFINE_PROP_END_OF_LIST(), 668 }; 669 670 static void e1000e_class_init(ObjectClass *class, void *data) 671 { 672 DeviceClass *dc = DEVICE_CLASS(class); 673 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 674 675 c->realize = e1000e_pci_realize; 676 c->exit = e1000e_pci_uninit; 677 c->vendor_id = PCI_VENDOR_ID_INTEL; 678 c->device_id = E1000_DEV_ID_82574L; 679 c->revision = 0; 680 c->romfile = "efi-e1000e.rom"; 681 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 682 683 dc->desc = "Intel 82574L GbE Controller"; 684 dc->reset = e1000e_qdev_reset; 685 dc->vmsd = &e1000e_vmstate; 686 dc->props = e1000e_properties; 687 688 e1000e_prop_disable_vnet = qdev_prop_uint8; 689 e1000e_prop_disable_vnet.description = "Do not use virtio headers, " 690 "perform SW offloads emulation " 691 "instead"; 692 693 e1000e_prop_subsys_ven = qdev_prop_uint16; 694 e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID"; 695 696 e1000e_prop_subsys = qdev_prop_uint16; 697 e1000e_prop_subsys.description = "PCI device Subsystem ID"; 698 699 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 700 } 701 702 static void e1000e_instance_init(Object *obj) 703 { 704 E1000EState *s = E1000E(obj); 705 device_add_bootindex_property(obj, &s->conf.bootindex, 706 "bootindex", "/ethernet-phy@0", 707 DEVICE(obj), NULL); 708 } 709 710 static const TypeInfo e1000e_info = { 711 .name = TYPE_E1000E, 712 .parent = TYPE_PCI_DEVICE, 713 .instance_size = sizeof(E1000EState), 714 .class_init = e1000e_class_init, 715 .instance_init = e1000e_instance_init, 716 .interfaces = (InterfaceInfo[]) { 717 { INTERFACE_PCIE_DEVICE }, 718 { } 719 }, 720 }; 721 722 static void e1000e_register_types(void) 723 { 724 type_register_static(&e1000e_info); 725 } 726 727 type_init(e1000e_register_types) 728