xref: /openbmc/qemu/hw/net/e1000e.c (revision 988717b46b6424907618cb845ace9d69062703af)
1  /*
2  * QEMU INTEL 82574 GbE NIC emulation
3  *
4  * Software developer's manuals:
5  * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6  *
7  * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8  * Developed by Daynix Computing LTD (http://www.daynix.com)
9  *
10  * Authors:
11  * Dmitry Fleytman <dmitry@daynix.com>
12  * Leonid Bloch <leonid@daynix.com>
13  * Yan Vugenfirer <yan@daynix.com>
14  *
15  * Based on work done by:
16  * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17  * Copyright (c) 2008 Qumranet
18  * Based on work done by:
19  * Copyright (c) 2007 Dan Aloni
20  * Copyright (c) 2004 Antony T Curtis
21  *
22  * This library is free software; you can redistribute it and/or
23  * modify it under the terms of the GNU Lesser General Public
24  * License as published by the Free Software Foundation; either
25  * version 2 of the License, or (at your option) any later version.
26  *
27  * This library is distributed in the hope that it will be useful,
28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
30  * Lesser General Public License for more details.
31  *
32  * You should have received a copy of the GNU Lesser General Public
33  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34  */
35  
36  #include "qemu/osdep.h"
37  #include "qemu/units.h"
38  #include "net/net.h"
39  #include "net/tap.h"
40  #include "qemu/module.h"
41  #include "qemu/range.h"
42  #include "sysemu/sysemu.h"
43  #include "hw/hw.h"
44  #include "hw/pci/msi.h"
45  #include "hw/pci/msix.h"
46  #include "hw/qdev-properties.h"
47  #include "migration/vmstate.h"
48  
49  #include "e1000_regs.h"
50  
51  #include "e1000x_common.h"
52  #include "e1000e_core.h"
53  
54  #include "trace.h"
55  #include "qapi/error.h"
56  
57  #define TYPE_E1000E "e1000e"
58  #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
59  
60  typedef struct E1000EState {
61      PCIDevice parent_obj;
62      NICState *nic;
63      NICConf conf;
64  
65      MemoryRegion mmio;
66      MemoryRegion flash;
67      MemoryRegion io;
68      MemoryRegion msix;
69  
70      uint32_t ioaddr;
71  
72      uint16_t subsys_ven;
73      uint16_t subsys;
74  
75      uint16_t subsys_ven_used;
76      uint16_t subsys_used;
77  
78      bool disable_vnet;
79  
80      E1000ECore core;
81  
82  } E1000EState;
83  
84  #define E1000E_MMIO_IDX     0
85  #define E1000E_FLASH_IDX    1
86  #define E1000E_IO_IDX       2
87  #define E1000E_MSIX_IDX     3
88  
89  #define E1000E_MMIO_SIZE    (128 * KiB)
90  #define E1000E_FLASH_SIZE   (128 * KiB)
91  #define E1000E_IO_SIZE      (32)
92  #define E1000E_MSIX_SIZE    (16 * KiB)
93  
94  #define E1000E_MSIX_TABLE   (0x0000)
95  #define E1000E_MSIX_PBA     (0x2000)
96  
97  static uint64_t
98  e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
99  {
100      E1000EState *s = opaque;
101      return e1000e_core_read(&s->core, addr, size);
102  }
103  
104  static void
105  e1000e_mmio_write(void *opaque, hwaddr addr,
106                     uint64_t val, unsigned size)
107  {
108      E1000EState *s = opaque;
109      e1000e_core_write(&s->core, addr, val, size);
110  }
111  
112  static bool
113  e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
114  {
115      if (s->ioaddr < 0x1FFFF) {
116          *idx = s->ioaddr;
117          return true;
118      }
119  
120      if (s->ioaddr < 0x7FFFF) {
121          trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
122          return false;
123      }
124  
125      if (s->ioaddr < 0xFFFFF) {
126          trace_e1000e_wrn_io_addr_flash(s->ioaddr);
127          return false;
128      }
129  
130      trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
131      return false;
132  }
133  
134  static uint64_t
135  e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
136  {
137      E1000EState *s = opaque;
138      uint32_t idx = 0;
139      uint64_t val;
140  
141      switch (addr) {
142      case E1000_IOADDR:
143          trace_e1000e_io_read_addr(s->ioaddr);
144          return s->ioaddr;
145      case E1000_IODATA:
146          if (e1000e_io_get_reg_index(s, &idx)) {
147              val = e1000e_core_read(&s->core, idx, sizeof(val));
148              trace_e1000e_io_read_data(idx, val);
149              return val;
150          }
151          return 0;
152      default:
153          trace_e1000e_wrn_io_read_unknown(addr);
154          return 0;
155      }
156  }
157  
158  static void
159  e1000e_io_write(void *opaque, hwaddr addr,
160                  uint64_t val, unsigned size)
161  {
162      E1000EState *s = opaque;
163      uint32_t idx = 0;
164  
165      switch (addr) {
166      case E1000_IOADDR:
167          trace_e1000e_io_write_addr(val);
168          s->ioaddr = (uint32_t) val;
169          return;
170      case E1000_IODATA:
171          if (e1000e_io_get_reg_index(s, &idx)) {
172              trace_e1000e_io_write_data(idx, val);
173              e1000e_core_write(&s->core, idx, val, sizeof(val));
174          }
175          return;
176      default:
177          trace_e1000e_wrn_io_write_unknown(addr);
178          return;
179      }
180  }
181  
182  static const MemoryRegionOps mmio_ops = {
183      .read = e1000e_mmio_read,
184      .write = e1000e_mmio_write,
185      .endianness = DEVICE_LITTLE_ENDIAN,
186      .impl = {
187          .min_access_size = 4,
188          .max_access_size = 4,
189      },
190  };
191  
192  static const MemoryRegionOps io_ops = {
193      .read = e1000e_io_read,
194      .write = e1000e_io_write,
195      .endianness = DEVICE_LITTLE_ENDIAN,
196      .impl = {
197          .min_access_size = 4,
198          .max_access_size = 4,
199      },
200  };
201  
202  static int
203  e1000e_nc_can_receive(NetClientState *nc)
204  {
205      E1000EState *s = qemu_get_nic_opaque(nc);
206      return e1000e_can_receive(&s->core);
207  }
208  
209  static ssize_t
210  e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
211  {
212      E1000EState *s = qemu_get_nic_opaque(nc);
213      return e1000e_receive_iov(&s->core, iov, iovcnt);
214  }
215  
216  static ssize_t
217  e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
218  {
219      E1000EState *s = qemu_get_nic_opaque(nc);
220      return e1000e_receive(&s->core, buf, size);
221  }
222  
223  static void
224  e1000e_set_link_status(NetClientState *nc)
225  {
226      E1000EState *s = qemu_get_nic_opaque(nc);
227      e1000e_core_set_link_status(&s->core);
228  }
229  
230  static NetClientInfo net_e1000e_info = {
231      .type = NET_CLIENT_DRIVER_NIC,
232      .size = sizeof(NICState),
233      .can_receive = e1000e_nc_can_receive,
234      .receive = e1000e_nc_receive,
235      .receive_iov = e1000e_nc_receive_iov,
236      .link_status_changed = e1000e_set_link_status,
237  };
238  
239  /*
240  * EEPROM (NVM) contents documented in Table 36, section 6.1
241  * and generally 6.1.2 Software accessed words.
242  */
243  static const uint16_t e1000e_eeprom_template[64] = {
244    /*        Address        |    Compat.    | ImVer |   Compat.     */
245      0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
246    /*      PBA      |ICtrl1 | SSID  | SVID  | DevID |-------|ICtrl2 */
247      0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
248    /*    NVM words 1,2,3    |-------------------------------|PCI-EID*/
249      0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
250    /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
251      0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
252    /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/
253      0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
254    /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP  */
255      0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
256    /*                            SW Section                         */
257      0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
258    /*                      SW Section                       |CHKSUM */
259      0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
260  };
261  
262  static void e1000e_core_realize(E1000EState *s)
263  {
264      s->core.owner = &s->parent_obj;
265      s->core.owner_nic = s->nic;
266  }
267  
268  static void
269  e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
270  {
271      int i;
272      for (i = 0; i < num_vectors; i++) {
273          msix_vector_unuse(PCI_DEVICE(s), i);
274      }
275  }
276  
277  static bool
278  e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
279  {
280      int i;
281      for (i = 0; i < num_vectors; i++) {
282          int res = msix_vector_use(PCI_DEVICE(s), i);
283          if (res < 0) {
284              trace_e1000e_msix_use_vector_fail(i, res);
285              e1000e_unuse_msix_vectors(s, i);
286              return false;
287          }
288      }
289      return true;
290  }
291  
292  static void
293  e1000e_init_msix(E1000EState *s)
294  {
295      PCIDevice *d = PCI_DEVICE(s);
296      int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
297                          &s->msix,
298                          E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
299                          &s->msix,
300                          E1000E_MSIX_IDX, E1000E_MSIX_PBA,
301                          0xA0, NULL);
302  
303      if (res < 0) {
304          trace_e1000e_msix_init_fail(res);
305      } else {
306          if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) {
307              msix_uninit(d, &s->msix, &s->msix);
308          }
309      }
310  }
311  
312  static void
313  e1000e_cleanup_msix(E1000EState *s)
314  {
315      if (msix_present(PCI_DEVICE(s))) {
316          e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
317          msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
318      }
319  }
320  
321  static void
322  e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
323  {
324      DeviceState *dev = DEVICE(pci_dev);
325      NetClientState *nc;
326      int i;
327  
328      s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
329          object_get_typename(OBJECT(s)), dev->id, s);
330  
331      s->core.max_queue_num = s->conf.peers.queues - 1;
332  
333      trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
334      memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
335  
336      qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
337  
338      /* Setup virtio headers */
339      if (s->disable_vnet) {
340          s->core.has_vnet = false;
341          trace_e1000e_cfg_support_virtio(false);
342          return;
343      } else {
344          s->core.has_vnet = true;
345      }
346  
347      for (i = 0; i < s->conf.peers.queues; i++) {
348          nc = qemu_get_subqueue(s->nic, i);
349          if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
350              s->core.has_vnet = false;
351              trace_e1000e_cfg_support_virtio(false);
352              return;
353          }
354      }
355  
356      trace_e1000e_cfg_support_virtio(true);
357  
358      for (i = 0; i < s->conf.peers.queues; i++) {
359          nc = qemu_get_subqueue(s->nic, i);
360          qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
361          qemu_using_vnet_hdr(nc->peer, true);
362      }
363  }
364  
365  static inline uint64_t
366  e1000e_gen_dsn(uint8_t *mac)
367  {
368      return (uint64_t)(mac[5])        |
369             (uint64_t)(mac[4])  << 8  |
370             (uint64_t)(mac[3])  << 16 |
371             (uint64_t)(0x00FF)  << 24 |
372             (uint64_t)(0x00FF)  << 32 |
373             (uint64_t)(mac[2])  << 40 |
374             (uint64_t)(mac[1])  << 48 |
375             (uint64_t)(mac[0])  << 56;
376  }
377  
378  static int
379  e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
380  {
381      Error *local_err = NULL;
382      int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
383                                   PCI_PM_SIZEOF, &local_err);
384  
385      if (local_err) {
386          error_report_err(local_err);
387          return ret;
388      }
389  
390      pci_set_word(pdev->config + offset + PCI_PM_PMC,
391                   PCI_PM_CAP_VER_1_1 |
392                   pmc);
393  
394      pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
395                   PCI_PM_CTRL_STATE_MASK |
396                   PCI_PM_CTRL_PME_ENABLE |
397                   PCI_PM_CTRL_DATA_SEL_MASK);
398  
399      pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
400                   PCI_PM_CTRL_PME_STATUS);
401  
402      return ret;
403  }
404  
405  static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
406                                  uint32_t val, int len)
407  {
408      E1000EState *s = E1000E(pci_dev);
409  
410      pci_default_write_config(pci_dev, address, val, len);
411  
412      if (range_covers_byte(address, len, PCI_COMMAND) &&
413          (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
414          e1000e_start_recv(&s->core);
415      }
416  }
417  
418  static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
419  {
420      static const uint16_t e1000e_pmrb_offset = 0x0C8;
421      static const uint16_t e1000e_pcie_offset = 0x0E0;
422      static const uint16_t e1000e_aer_offset =  0x100;
423      static const uint16_t e1000e_dsn_offset =  0x140;
424      E1000EState *s = E1000E(pci_dev);
425      uint8_t *macaddr;
426      int ret;
427  
428      trace_e1000e_cb_pci_realize();
429  
430      pci_dev->config_write = e1000e_write_config;
431  
432      pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
433      pci_dev->config[PCI_INTERRUPT_PIN] = 1;
434  
435      pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
436      pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
437  
438      s->subsys_ven_used = s->subsys_ven;
439      s->subsys_used = s->subsys;
440  
441      /* Define IO/MMIO regions */
442      memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
443                            "e1000e-mmio", E1000E_MMIO_SIZE);
444      pci_register_bar(pci_dev, E1000E_MMIO_IDX,
445                       PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
446  
447      /*
448       * We provide a dummy implementation for the flash BAR
449       * for drivers that may theoretically probe for its presence.
450       */
451      memory_region_init(&s->flash, OBJECT(s),
452                         "e1000e-flash", E1000E_FLASH_SIZE);
453      pci_register_bar(pci_dev, E1000E_FLASH_IDX,
454                       PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
455  
456      memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
457                            "e1000e-io", E1000E_IO_SIZE);
458      pci_register_bar(pci_dev, E1000E_IO_IDX,
459                       PCI_BASE_ADDRESS_SPACE_IO, &s->io);
460  
461      memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
462                         E1000E_MSIX_SIZE);
463      pci_register_bar(pci_dev, E1000E_MSIX_IDX,
464                       PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
465  
466      /* Create networking backend */
467      qemu_macaddr_default_if_unset(&s->conf.macaddr);
468      macaddr = s->conf.macaddr.a;
469  
470      e1000e_init_msix(s);
471  
472      if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
473          hw_error("Failed to initialize PCIe capability");
474      }
475  
476      ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
477      if (ret) {
478          trace_e1000e_msi_init_fail(ret);
479      }
480  
481      if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
482                                    PCI_PM_CAP_DSI) < 0) {
483          hw_error("Failed to initialize PM capability");
484      }
485  
486      if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
487                        PCI_ERR_SIZEOF, NULL) < 0) {
488          hw_error("Failed to initialize AER capability");
489      }
490  
491      pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
492                            e1000e_gen_dsn(macaddr));
493  
494      e1000e_init_net_peer(s, pci_dev, macaddr);
495  
496      /* Initialize core */
497      e1000e_core_realize(s);
498  
499      e1000e_core_pci_realize(&s->core,
500                              e1000e_eeprom_template,
501                              sizeof(e1000e_eeprom_template),
502                              macaddr);
503  }
504  
505  static void e1000e_pci_uninit(PCIDevice *pci_dev)
506  {
507      E1000EState *s = E1000E(pci_dev);
508  
509      trace_e1000e_cb_pci_uninit();
510  
511      e1000e_core_pci_uninit(&s->core);
512  
513      pcie_aer_exit(pci_dev);
514      pcie_cap_exit(pci_dev);
515  
516      qemu_del_nic(s->nic);
517  
518      e1000e_cleanup_msix(s);
519      msi_uninit(pci_dev);
520  }
521  
522  static void e1000e_qdev_reset(DeviceState *dev)
523  {
524      E1000EState *s = E1000E(dev);
525  
526      trace_e1000e_cb_qdev_reset();
527  
528      e1000e_core_reset(&s->core);
529  }
530  
531  static int e1000e_pre_save(void *opaque)
532  {
533      E1000EState *s = opaque;
534  
535      trace_e1000e_cb_pre_save();
536  
537      e1000e_core_pre_save(&s->core);
538  
539      return 0;
540  }
541  
542  static int e1000e_post_load(void *opaque, int version_id)
543  {
544      E1000EState *s = opaque;
545  
546      trace_e1000e_cb_post_load();
547  
548      if ((s->subsys != s->subsys_used) ||
549          (s->subsys_ven != s->subsys_ven_used)) {
550          fprintf(stderr,
551              "ERROR: Cannot migrate while device properties "
552              "(subsys/subsys_ven) differ");
553          return -1;
554      }
555  
556      return e1000e_core_post_load(&s->core);
557  }
558  
559  static const VMStateDescription e1000e_vmstate_tx = {
560      .name = "e1000e-tx",
561      .version_id = 1,
562      .minimum_version_id = 1,
563      .fields = (VMStateField[]) {
564          VMSTATE_UINT8(sum_needed, struct e1000e_tx),
565          VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
566          VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
567          VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
568          VMSTATE_UINT8(props.tucss, struct e1000e_tx),
569          VMSTATE_UINT8(props.tucso, struct e1000e_tx),
570          VMSTATE_UINT16(props.tucse, struct e1000e_tx),
571          VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
572          VMSTATE_UINT16(props.mss, struct e1000e_tx),
573          VMSTATE_UINT32(props.paylen, struct e1000e_tx),
574          VMSTATE_INT8(props.ip, struct e1000e_tx),
575          VMSTATE_INT8(props.tcp, struct e1000e_tx),
576          VMSTATE_BOOL(props.tse, struct e1000e_tx),
577          VMSTATE_BOOL(cptse, struct e1000e_tx),
578          VMSTATE_BOOL(skip_cp, struct e1000e_tx),
579          VMSTATE_END_OF_LIST()
580      }
581  };
582  
583  static const VMStateDescription e1000e_vmstate_intr_timer = {
584      .name = "e1000e-intr-timer",
585      .version_id = 1,
586      .minimum_version_id = 1,
587      .fields = (VMStateField[]) {
588          VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
589          VMSTATE_BOOL(running, E1000IntrDelayTimer),
590          VMSTATE_END_OF_LIST()
591      }
592  };
593  
594  #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s)                     \
595      VMSTATE_STRUCT(_f, _s, 0,                                       \
596                     e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
597  
598  #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num)         \
599      VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
600                           e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
601  
602  static const VMStateDescription e1000e_vmstate = {
603      .name = "e1000e",
604      .version_id = 1,
605      .minimum_version_id = 1,
606      .pre_save = e1000e_pre_save,
607      .post_load = e1000e_post_load,
608      .fields = (VMStateField[]) {
609          VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
610          VMSTATE_MSIX(parent_obj, E1000EState),
611  
612          VMSTATE_UINT32(ioaddr, E1000EState),
613          VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
614          VMSTATE_UINT8(core.rx_desc_len, E1000EState),
615          VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
616                               E1000_PSRCTL_BUFFS_PER_DESC),
617          VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
618          VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
619          VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
620                                 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
621          VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
622          VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
623  
624          VMSTATE_UINT32(core.delayed_causes, E1000EState),
625  
626          VMSTATE_UINT16(subsys, E1000EState),
627          VMSTATE_UINT16(subsys_ven, E1000EState),
628  
629          VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
630          VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
631          VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
632          VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
633          VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
634  
635          VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
636          VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
637  
638          VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
639                                                E1000E_MSIX_VEC_NUM),
640          VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
641                             E1000E_MSIX_VEC_NUM),
642  
643          VMSTATE_UINT32(core.itr_guest_value, E1000EState),
644          VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
645                               E1000E_MSIX_VEC_NUM),
646  
647          VMSTATE_UINT16(core.vet, E1000EState),
648  
649          VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
650                               e1000e_vmstate_tx, struct e1000e_tx),
651          VMSTATE_END_OF_LIST()
652      }
653  };
654  
655  static PropertyInfo e1000e_prop_disable_vnet,
656                      e1000e_prop_subsys_ven,
657                      e1000e_prop_subsys;
658  
659  static Property e1000e_properties[] = {
660      DEFINE_NIC_PROPERTIES(E1000EState, conf),
661      DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
662                          e1000e_prop_disable_vnet, bool),
663      DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
664                          PCI_VENDOR_ID_INTEL,
665                          e1000e_prop_subsys_ven, uint16_t),
666      DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
667                          e1000e_prop_subsys, uint16_t),
668      DEFINE_PROP_END_OF_LIST(),
669  };
670  
671  static void e1000e_class_init(ObjectClass *class, void *data)
672  {
673      DeviceClass *dc = DEVICE_CLASS(class);
674      PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
675  
676      c->realize = e1000e_pci_realize;
677      c->exit = e1000e_pci_uninit;
678      c->vendor_id = PCI_VENDOR_ID_INTEL;
679      c->device_id = E1000_DEV_ID_82574L;
680      c->revision = 0;
681      c->romfile = "efi-e1000e.rom";
682      c->class_id = PCI_CLASS_NETWORK_ETHERNET;
683  
684      dc->desc = "Intel 82574L GbE Controller";
685      dc->reset = e1000e_qdev_reset;
686      dc->vmsd = &e1000e_vmstate;
687  
688      e1000e_prop_disable_vnet = qdev_prop_uint8;
689      e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
690                                             "perform SW offloads emulation "
691                                             "instead";
692  
693      e1000e_prop_subsys_ven = qdev_prop_uint16;
694      e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
695  
696      e1000e_prop_subsys = qdev_prop_uint16;
697      e1000e_prop_subsys.description = "PCI device Subsystem ID";
698  
699      device_class_set_props(dc, e1000e_properties);
700      set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
701  }
702  
703  static void e1000e_instance_init(Object *obj)
704  {
705      E1000EState *s = E1000E(obj);
706      device_add_bootindex_property(obj, &s->conf.bootindex,
707                                    "bootindex", "/ethernet-phy@0",
708                                    DEVICE(obj), NULL);
709  }
710  
711  static const TypeInfo e1000e_info = {
712      .name = TYPE_E1000E,
713      .parent = TYPE_PCI_DEVICE,
714      .instance_size = sizeof(E1000EState),
715      .class_init = e1000e_class_init,
716      .instance_init = e1000e_instance_init,
717      .interfaces = (InterfaceInfo[]) {
718          { INTERFACE_PCIE_DEVICE },
719          { }
720      },
721  };
722  
723  static void e1000e_register_types(void)
724  {
725      type_register_static(&e1000e_info);
726  }
727  
728  type_init(e1000e_register_types)
729