1 /* 2 * QEMU INTEL 82574 GbE NIC emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/units.h" 38 #include "net/eth.h" 39 #include "net/net.h" 40 #include "net/tap.h" 41 #include "qemu/module.h" 42 #include "qemu/range.h" 43 #include "sysemu/sysemu.h" 44 #include "hw/hw.h" 45 #include "hw/net/mii.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci/msix.h" 48 #include "hw/qdev-properties.h" 49 #include "migration/vmstate.h" 50 51 #include "e1000_regs.h" 52 53 #include "e1000x_common.h" 54 #include "e1000e_core.h" 55 56 #include "trace.h" 57 #include "qapi/error.h" 58 #include "qom/object.h" 59 60 #define TYPE_E1000E "e1000e" 61 OBJECT_DECLARE_SIMPLE_TYPE(E1000EState, E1000E) 62 63 struct E1000EState { 64 PCIDevice parent_obj; 65 NICState *nic; 66 NICConf conf; 67 68 MemoryRegion mmio; 69 MemoryRegion flash; 70 MemoryRegion io; 71 MemoryRegion msix; 72 73 uint32_t ioaddr; 74 75 uint16_t subsys_ven; 76 uint16_t subsys; 77 78 uint16_t subsys_ven_used; 79 uint16_t subsys_used; 80 81 bool disable_vnet; 82 83 E1000ECore core; 84 bool init_vet; 85 bool timadj; 86 }; 87 88 #define E1000E_MMIO_IDX 0 89 #define E1000E_FLASH_IDX 1 90 #define E1000E_IO_IDX 2 91 #define E1000E_MSIX_IDX 3 92 93 #define E1000E_MMIO_SIZE (128 * KiB) 94 #define E1000E_FLASH_SIZE (128 * KiB) 95 #define E1000E_IO_SIZE (32) 96 #define E1000E_MSIX_SIZE (16 * KiB) 97 98 #define E1000E_MSIX_TABLE (0x0000) 99 #define E1000E_MSIX_PBA (0x2000) 100 101 static uint64_t 102 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size) 103 { 104 E1000EState *s = opaque; 105 return e1000e_core_read(&s->core, addr, size); 106 } 107 108 static void 109 e1000e_mmio_write(void *opaque, hwaddr addr, 110 uint64_t val, unsigned size) 111 { 112 E1000EState *s = opaque; 113 e1000e_core_write(&s->core, addr, val, size); 114 } 115 116 static bool 117 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx) 118 { 119 if (s->ioaddr < 0x1FFFF) { 120 *idx = s->ioaddr; 121 return true; 122 } 123 124 if (s->ioaddr < 0x7FFFF) { 125 trace_e1000e_wrn_io_addr_undefined(s->ioaddr); 126 return false; 127 } 128 129 if (s->ioaddr < 0xFFFFF) { 130 trace_e1000e_wrn_io_addr_flash(s->ioaddr); 131 return false; 132 } 133 134 trace_e1000e_wrn_io_addr_unknown(s->ioaddr); 135 return false; 136 } 137 138 static uint64_t 139 e1000e_io_read(void *opaque, hwaddr addr, unsigned size) 140 { 141 E1000EState *s = opaque; 142 uint32_t idx = 0; 143 uint64_t val; 144 145 switch (addr) { 146 case E1000_IOADDR: 147 trace_e1000e_io_read_addr(s->ioaddr); 148 return s->ioaddr; 149 case E1000_IODATA: 150 if (e1000e_io_get_reg_index(s, &idx)) { 151 val = e1000e_core_read(&s->core, idx, sizeof(val)); 152 trace_e1000e_io_read_data(idx, val); 153 return val; 154 } 155 return 0; 156 default: 157 trace_e1000e_wrn_io_read_unknown(addr); 158 return 0; 159 } 160 } 161 162 static void 163 e1000e_io_write(void *opaque, hwaddr addr, 164 uint64_t val, unsigned size) 165 { 166 E1000EState *s = opaque; 167 uint32_t idx = 0; 168 169 switch (addr) { 170 case E1000_IOADDR: 171 trace_e1000e_io_write_addr(val); 172 s->ioaddr = (uint32_t) val; 173 return; 174 case E1000_IODATA: 175 if (e1000e_io_get_reg_index(s, &idx)) { 176 trace_e1000e_io_write_data(idx, val); 177 e1000e_core_write(&s->core, idx, val, sizeof(val)); 178 } 179 return; 180 default: 181 trace_e1000e_wrn_io_write_unknown(addr); 182 return; 183 } 184 } 185 186 static const MemoryRegionOps mmio_ops = { 187 .read = e1000e_mmio_read, 188 .write = e1000e_mmio_write, 189 .endianness = DEVICE_LITTLE_ENDIAN, 190 .impl = { 191 .min_access_size = 4, 192 .max_access_size = 4, 193 }, 194 }; 195 196 static const MemoryRegionOps io_ops = { 197 .read = e1000e_io_read, 198 .write = e1000e_io_write, 199 .endianness = DEVICE_LITTLE_ENDIAN, 200 .impl = { 201 .min_access_size = 4, 202 .max_access_size = 4, 203 }, 204 }; 205 206 static bool 207 e1000e_nc_can_receive(NetClientState *nc) 208 { 209 E1000EState *s = qemu_get_nic_opaque(nc); 210 return e1000e_can_receive(&s->core); 211 } 212 213 static ssize_t 214 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) 215 { 216 E1000EState *s = qemu_get_nic_opaque(nc); 217 return e1000e_receive_iov(&s->core, iov, iovcnt); 218 } 219 220 static ssize_t 221 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size) 222 { 223 E1000EState *s = qemu_get_nic_opaque(nc); 224 return e1000e_receive(&s->core, buf, size); 225 } 226 227 static void 228 e1000e_set_link_status(NetClientState *nc) 229 { 230 E1000EState *s = qemu_get_nic_opaque(nc); 231 e1000e_core_set_link_status(&s->core); 232 } 233 234 static NetClientInfo net_e1000e_info = { 235 .type = NET_CLIENT_DRIVER_NIC, 236 .size = sizeof(NICState), 237 .can_receive = e1000e_nc_can_receive, 238 .receive = e1000e_nc_receive, 239 .receive_iov = e1000e_nc_receive_iov, 240 .link_status_changed = e1000e_set_link_status, 241 }; 242 243 /* 244 * EEPROM (NVM) contents documented in Table 36, section 6.1 245 * and generally 6.1.2 Software accessed words. 246 */ 247 static const uint16_t e1000e_eeprom_template[64] = { 248 /* Address | Compat. | ImVer | Compat. */ 249 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff, 250 /* PBA |ICtrl1 | SSID | SVID | DevID |-------|ICtrl2 */ 251 0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058, 252 /* NVM words 1,2,3 |-------------------------------|PCI-EID*/ 253 0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704, 254 /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */ 255 0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706, 256 /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/ 257 0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff, 258 /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP */ 259 0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff, 260 /* SW Section */ 261 0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff, 262 /* SW Section |CHKSUM */ 263 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000, 264 }; 265 266 static void e1000e_core_realize(E1000EState *s) 267 { 268 s->core.owner = &s->parent_obj; 269 s->core.owner_nic = s->nic; 270 } 271 272 static void 273 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors) 274 { 275 int i; 276 for (i = 0; i < num_vectors; i++) { 277 msix_vector_unuse(PCI_DEVICE(s), i); 278 } 279 } 280 281 static void 282 e1000e_use_msix_vectors(E1000EState *s, int num_vectors) 283 { 284 int i; 285 for (i = 0; i < num_vectors; i++) { 286 msix_vector_use(PCI_DEVICE(s), i); 287 } 288 } 289 290 static void 291 e1000e_init_msix(E1000EState *s) 292 { 293 int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM, 294 &s->msix, 295 E1000E_MSIX_IDX, E1000E_MSIX_TABLE, 296 &s->msix, 297 E1000E_MSIX_IDX, E1000E_MSIX_PBA, 298 0xA0, NULL); 299 300 if (res < 0) { 301 trace_e1000e_msix_init_fail(res); 302 } else { 303 e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM); 304 } 305 } 306 307 static void 308 e1000e_cleanup_msix(E1000EState *s) 309 { 310 if (msix_present(PCI_DEVICE(s))) { 311 e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM); 312 msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix); 313 } 314 } 315 316 static void 317 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr) 318 { 319 DeviceState *dev = DEVICE(pci_dev); 320 NetClientState *nc; 321 int i; 322 323 s->nic = qemu_new_nic(&net_e1000e_info, &s->conf, 324 object_get_typename(OBJECT(s)), dev->id, s); 325 326 s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0; 327 328 trace_e1000e_mac_set_permanent(MAC_ARG(macaddr)); 329 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac)); 330 331 qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr); 332 333 /* Setup virtio headers */ 334 if (s->disable_vnet) { 335 s->core.has_vnet = false; 336 trace_e1000e_cfg_support_virtio(false); 337 return; 338 } else { 339 s->core.has_vnet = true; 340 } 341 342 for (i = 0; i < s->conf.peers.queues; i++) { 343 nc = qemu_get_subqueue(s->nic, i); 344 if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) { 345 s->core.has_vnet = false; 346 trace_e1000e_cfg_support_virtio(false); 347 return; 348 } 349 } 350 351 trace_e1000e_cfg_support_virtio(true); 352 353 for (i = 0; i < s->conf.peers.queues; i++) { 354 nc = qemu_get_subqueue(s->nic, i); 355 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr)); 356 qemu_using_vnet_hdr(nc->peer, true); 357 } 358 } 359 360 static inline uint64_t 361 e1000e_gen_dsn(uint8_t *mac) 362 { 363 return (uint64_t)(mac[5]) | 364 (uint64_t)(mac[4]) << 8 | 365 (uint64_t)(mac[3]) << 16 | 366 (uint64_t)(0x00FF) << 24 | 367 (uint64_t)(0x00FF) << 32 | 368 (uint64_t)(mac[2]) << 40 | 369 (uint64_t)(mac[1]) << 48 | 370 (uint64_t)(mac[0]) << 56; 371 } 372 373 static int 374 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) 375 { 376 Error *local_err = NULL; 377 int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, 378 PCI_PM_SIZEOF, &local_err); 379 380 if (local_err) { 381 error_report_err(local_err); 382 return ret; 383 } 384 385 pci_set_word(pdev->config + offset + PCI_PM_PMC, 386 PCI_PM_CAP_VER_1_1 | 387 pmc); 388 389 pci_set_word(pdev->wmask + offset + PCI_PM_CTRL, 390 PCI_PM_CTRL_STATE_MASK | 391 PCI_PM_CTRL_PME_ENABLE | 392 PCI_PM_CTRL_DATA_SEL_MASK); 393 394 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, 395 PCI_PM_CTRL_PME_STATUS); 396 397 return ret; 398 } 399 400 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, 401 uint32_t val, int len) 402 { 403 E1000EState *s = E1000E(pci_dev); 404 405 pci_default_write_config(pci_dev, address, val, len); 406 407 if (range_covers_byte(address, len, PCI_COMMAND) && 408 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { 409 e1000e_start_recv(&s->core); 410 } 411 } 412 413 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) 414 { 415 static const uint16_t e1000e_pmrb_offset = 0x0C8; 416 static const uint16_t e1000e_pcie_offset = 0x0E0; 417 static const uint16_t e1000e_aer_offset = 0x100; 418 static const uint16_t e1000e_dsn_offset = 0x140; 419 E1000EState *s = E1000E(pci_dev); 420 uint8_t *macaddr; 421 int ret; 422 423 trace_e1000e_cb_pci_realize(); 424 425 pci_dev->config_write = e1000e_write_config; 426 427 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 428 pci_dev->config[PCI_INTERRUPT_PIN] = 1; 429 430 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven); 431 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys); 432 433 s->subsys_ven_used = s->subsys_ven; 434 s->subsys_used = s->subsys; 435 436 /* Define IO/MMIO regions */ 437 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s, 438 "e1000e-mmio", E1000E_MMIO_SIZE); 439 pci_register_bar(pci_dev, E1000E_MMIO_IDX, 440 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio); 441 442 /* 443 * We provide a dummy implementation for the flash BAR 444 * for drivers that may theoretically probe for its presence. 445 */ 446 memory_region_init(&s->flash, OBJECT(s), 447 "e1000e-flash", E1000E_FLASH_SIZE); 448 pci_register_bar(pci_dev, E1000E_FLASH_IDX, 449 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash); 450 451 memory_region_init_io(&s->io, OBJECT(s), &io_ops, s, 452 "e1000e-io", E1000E_IO_SIZE); 453 pci_register_bar(pci_dev, E1000E_IO_IDX, 454 PCI_BASE_ADDRESS_SPACE_IO, &s->io); 455 456 memory_region_init(&s->msix, OBJECT(s), "e1000e-msix", 457 E1000E_MSIX_SIZE); 458 pci_register_bar(pci_dev, E1000E_MSIX_IDX, 459 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix); 460 461 /* Create networking backend */ 462 qemu_macaddr_default_if_unset(&s->conf.macaddr); 463 macaddr = s->conf.macaddr.a; 464 465 e1000e_init_msix(s); 466 467 if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { 468 hw_error("Failed to initialize PCIe capability"); 469 } 470 471 ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); 472 if (ret) { 473 trace_e1000e_msi_init_fail(ret); 474 } 475 476 if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, 477 PCI_PM_CAP_DSI) < 0) { 478 hw_error("Failed to initialize PM capability"); 479 } 480 481 if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, 482 PCI_ERR_SIZEOF, NULL) < 0) { 483 hw_error("Failed to initialize AER capability"); 484 } 485 486 pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset, 487 e1000e_gen_dsn(macaddr)); 488 489 e1000e_init_net_peer(s, pci_dev, macaddr); 490 491 /* Initialize core */ 492 e1000e_core_realize(s); 493 494 e1000e_core_pci_realize(&s->core, 495 e1000e_eeprom_template, 496 sizeof(e1000e_eeprom_template), 497 macaddr); 498 } 499 500 static void e1000e_pci_uninit(PCIDevice *pci_dev) 501 { 502 E1000EState *s = E1000E(pci_dev); 503 504 trace_e1000e_cb_pci_uninit(); 505 506 e1000e_core_pci_uninit(&s->core); 507 508 pcie_aer_exit(pci_dev); 509 pcie_cap_exit(pci_dev); 510 511 qemu_del_nic(s->nic); 512 513 e1000e_cleanup_msix(s); 514 msi_uninit(pci_dev); 515 } 516 517 static void e1000e_qdev_reset_hold(Object *obj) 518 { 519 E1000EState *s = E1000E(obj); 520 521 trace_e1000e_cb_qdev_reset_hold(); 522 523 e1000e_core_reset(&s->core); 524 525 if (s->init_vet) { 526 s->core.mac[VET] = ETH_P_VLAN; 527 } 528 } 529 530 static int e1000e_pre_save(void *opaque) 531 { 532 E1000EState *s = opaque; 533 534 trace_e1000e_cb_pre_save(); 535 536 e1000e_core_pre_save(&s->core); 537 538 return 0; 539 } 540 541 static int e1000e_post_load(void *opaque, int version_id) 542 { 543 E1000EState *s = opaque; 544 545 trace_e1000e_cb_post_load(); 546 547 if ((s->subsys != s->subsys_used) || 548 (s->subsys_ven != s->subsys_ven_used)) { 549 fprintf(stderr, 550 "ERROR: Cannot migrate while device properties " 551 "(subsys/subsys_ven) differ"); 552 return -1; 553 } 554 555 return e1000e_core_post_load(&s->core); 556 } 557 558 static bool e1000e_migrate_timadj(void *opaque, int version_id) 559 { 560 E1000EState *s = opaque; 561 return s->timadj; 562 } 563 564 static const VMStateDescription e1000e_vmstate_tx = { 565 .name = "e1000e-tx", 566 .version_id = 1, 567 .minimum_version_id = 1, 568 .fields = (VMStateField[]) { 569 VMSTATE_UINT8(sum_needed, struct e1000e_tx), 570 VMSTATE_UINT8(props.ipcss, struct e1000e_tx), 571 VMSTATE_UINT8(props.ipcso, struct e1000e_tx), 572 VMSTATE_UINT16(props.ipcse, struct e1000e_tx), 573 VMSTATE_UINT8(props.tucss, struct e1000e_tx), 574 VMSTATE_UINT8(props.tucso, struct e1000e_tx), 575 VMSTATE_UINT16(props.tucse, struct e1000e_tx), 576 VMSTATE_UINT8(props.hdr_len, struct e1000e_tx), 577 VMSTATE_UINT16(props.mss, struct e1000e_tx), 578 VMSTATE_UINT32(props.paylen, struct e1000e_tx), 579 VMSTATE_INT8(props.ip, struct e1000e_tx), 580 VMSTATE_INT8(props.tcp, struct e1000e_tx), 581 VMSTATE_BOOL(props.tse, struct e1000e_tx), 582 VMSTATE_BOOL(cptse, struct e1000e_tx), 583 VMSTATE_BOOL(skip_cp, struct e1000e_tx), 584 VMSTATE_END_OF_LIST() 585 } 586 }; 587 588 static const VMStateDescription e1000e_vmstate_intr_timer = { 589 .name = "e1000e-intr-timer", 590 .version_id = 1, 591 .minimum_version_id = 1, 592 .fields = (VMStateField[]) { 593 VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer), 594 VMSTATE_BOOL(running, E1000IntrDelayTimer), 595 VMSTATE_END_OF_LIST() 596 } 597 }; 598 599 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \ 600 VMSTATE_STRUCT(_f, _s, 0, \ 601 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 602 603 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \ 604 VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \ 605 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 606 607 static const VMStateDescription e1000e_vmstate = { 608 .name = "e1000e", 609 .version_id = 1, 610 .minimum_version_id = 1, 611 .pre_save = e1000e_pre_save, 612 .post_load = e1000e_post_load, 613 .fields = (VMStateField[]) { 614 VMSTATE_PCI_DEVICE(parent_obj, E1000EState), 615 VMSTATE_MSIX(parent_obj, E1000EState), 616 617 VMSTATE_UINT32(ioaddr, E1000EState), 618 VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState), 619 VMSTATE_UINT8(core.rx_desc_len, E1000EState), 620 VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState, 621 E1000_PSRCTL_BUFFS_PER_DESC), 622 VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState), 623 VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE), 624 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState, 625 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE), 626 VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE), 627 VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN), 628 629 VMSTATE_UINT32(core.delayed_causes, E1000EState), 630 631 VMSTATE_UINT16(subsys, E1000EState), 632 VMSTATE_UINT16(subsys_ven, E1000EState), 633 634 VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState), 635 VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState), 636 VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState), 637 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState), 638 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState), 639 640 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState), 641 VMSTATE_UNUSED(1), 642 643 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState, 644 E1000E_MSIX_VEC_NUM), 645 VMSTATE_UNUSED(E1000E_MSIX_VEC_NUM), 646 647 VMSTATE_UINT32(core.itr_guest_value, E1000EState), 648 VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState, 649 E1000E_MSIX_VEC_NUM), 650 651 VMSTATE_UINT16(core.vet, E1000EState), 652 653 VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0, 654 e1000e_vmstate_tx, struct e1000e_tx), 655 656 VMSTATE_INT64_TEST(core.timadj, E1000EState, e1000e_migrate_timadj), 657 658 VMSTATE_END_OF_LIST() 659 } 660 }; 661 662 static PropertyInfo e1000e_prop_disable_vnet, 663 e1000e_prop_subsys_ven, 664 e1000e_prop_subsys; 665 666 static Property e1000e_properties[] = { 667 DEFINE_NIC_PROPERTIES(E1000EState, conf), 668 DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false, 669 e1000e_prop_disable_vnet, bool), 670 DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven, 671 PCI_VENDOR_ID_INTEL, 672 e1000e_prop_subsys_ven, uint16_t), 673 DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0, 674 e1000e_prop_subsys, uint16_t), 675 DEFINE_PROP_BOOL("init-vet", E1000EState, init_vet, true), 676 DEFINE_PROP_BOOL("migrate-timadj", E1000EState, timadj, true), 677 DEFINE_PROP_END_OF_LIST(), 678 }; 679 680 static void e1000e_class_init(ObjectClass *class, void *data) 681 { 682 DeviceClass *dc = DEVICE_CLASS(class); 683 ResettableClass *rc = RESETTABLE_CLASS(class); 684 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 685 686 c->realize = e1000e_pci_realize; 687 c->exit = e1000e_pci_uninit; 688 c->vendor_id = PCI_VENDOR_ID_INTEL; 689 c->device_id = E1000_DEV_ID_82574L; 690 c->revision = 0; 691 c->romfile = "efi-e1000e.rom"; 692 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 693 694 rc->phases.hold = e1000e_qdev_reset_hold; 695 696 dc->desc = "Intel 82574L GbE Controller"; 697 dc->vmsd = &e1000e_vmstate; 698 699 e1000e_prop_disable_vnet = qdev_prop_uint8; 700 e1000e_prop_disable_vnet.description = "Do not use virtio headers, " 701 "perform SW offloads emulation " 702 "instead"; 703 704 e1000e_prop_subsys_ven = qdev_prop_uint16; 705 e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID"; 706 707 e1000e_prop_subsys = qdev_prop_uint16; 708 e1000e_prop_subsys.description = "PCI device Subsystem ID"; 709 710 device_class_set_props(dc, e1000e_properties); 711 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 712 } 713 714 static void e1000e_instance_init(Object *obj) 715 { 716 E1000EState *s = E1000E(obj); 717 device_add_bootindex_property(obj, &s->conf.bootindex, 718 "bootindex", "/ethernet-phy@0", 719 DEVICE(obj)); 720 } 721 722 static const TypeInfo e1000e_info = { 723 .name = TYPE_E1000E, 724 .parent = TYPE_PCI_DEVICE, 725 .instance_size = sizeof(E1000EState), 726 .class_init = e1000e_class_init, 727 .instance_init = e1000e_instance_init, 728 .interfaces = (InterfaceInfo[]) { 729 { INTERFACE_PCIE_DEVICE }, 730 { } 731 }, 732 }; 733 734 static void e1000e_register_types(void) 735 { 736 type_register_static(&e1000e_info); 737 } 738 739 type_init(e1000e_register_types) 740