1 /* 2 * QEMU INTEL 82574 GbE NIC emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2.1 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/units.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "qemu/module.h" 41 #include "qemu/range.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/hw.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci/msix.h" 46 #include "hw/qdev-properties.h" 47 #include "migration/vmstate.h" 48 49 #include "e1000_regs.h" 50 51 #include "e1000x_common.h" 52 #include "e1000e_core.h" 53 54 #include "trace.h" 55 #include "qapi/error.h" 56 #include "qom/object.h" 57 58 #define TYPE_E1000E "e1000e" 59 OBJECT_DECLARE_SIMPLE_TYPE(E1000EState, E1000E) 60 61 struct E1000EState { 62 PCIDevice parent_obj; 63 NICState *nic; 64 NICConf conf; 65 66 MemoryRegion mmio; 67 MemoryRegion flash; 68 MemoryRegion io; 69 MemoryRegion msix; 70 71 uint32_t ioaddr; 72 73 uint16_t subsys_ven; 74 uint16_t subsys; 75 76 uint16_t subsys_ven_used; 77 uint16_t subsys_used; 78 79 bool disable_vnet; 80 81 E1000ECore core; 82 83 }; 84 85 #define E1000E_MMIO_IDX 0 86 #define E1000E_FLASH_IDX 1 87 #define E1000E_IO_IDX 2 88 #define E1000E_MSIX_IDX 3 89 90 #define E1000E_MMIO_SIZE (128 * KiB) 91 #define E1000E_FLASH_SIZE (128 * KiB) 92 #define E1000E_IO_SIZE (32) 93 #define E1000E_MSIX_SIZE (16 * KiB) 94 95 #define E1000E_MSIX_TABLE (0x0000) 96 #define E1000E_MSIX_PBA (0x2000) 97 98 static uint64_t 99 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size) 100 { 101 E1000EState *s = opaque; 102 return e1000e_core_read(&s->core, addr, size); 103 } 104 105 static void 106 e1000e_mmio_write(void *opaque, hwaddr addr, 107 uint64_t val, unsigned size) 108 { 109 E1000EState *s = opaque; 110 e1000e_core_write(&s->core, addr, val, size); 111 } 112 113 static bool 114 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx) 115 { 116 if (s->ioaddr < 0x1FFFF) { 117 *idx = s->ioaddr; 118 return true; 119 } 120 121 if (s->ioaddr < 0x7FFFF) { 122 trace_e1000e_wrn_io_addr_undefined(s->ioaddr); 123 return false; 124 } 125 126 if (s->ioaddr < 0xFFFFF) { 127 trace_e1000e_wrn_io_addr_flash(s->ioaddr); 128 return false; 129 } 130 131 trace_e1000e_wrn_io_addr_unknown(s->ioaddr); 132 return false; 133 } 134 135 static uint64_t 136 e1000e_io_read(void *opaque, hwaddr addr, unsigned size) 137 { 138 E1000EState *s = opaque; 139 uint32_t idx = 0; 140 uint64_t val; 141 142 switch (addr) { 143 case E1000_IOADDR: 144 trace_e1000e_io_read_addr(s->ioaddr); 145 return s->ioaddr; 146 case E1000_IODATA: 147 if (e1000e_io_get_reg_index(s, &idx)) { 148 val = e1000e_core_read(&s->core, idx, sizeof(val)); 149 trace_e1000e_io_read_data(idx, val); 150 return val; 151 } 152 return 0; 153 default: 154 trace_e1000e_wrn_io_read_unknown(addr); 155 return 0; 156 } 157 } 158 159 static void 160 e1000e_io_write(void *opaque, hwaddr addr, 161 uint64_t val, unsigned size) 162 { 163 E1000EState *s = opaque; 164 uint32_t idx = 0; 165 166 switch (addr) { 167 case E1000_IOADDR: 168 trace_e1000e_io_write_addr(val); 169 s->ioaddr = (uint32_t) val; 170 return; 171 case E1000_IODATA: 172 if (e1000e_io_get_reg_index(s, &idx)) { 173 trace_e1000e_io_write_data(idx, val); 174 e1000e_core_write(&s->core, idx, val, sizeof(val)); 175 } 176 return; 177 default: 178 trace_e1000e_wrn_io_write_unknown(addr); 179 return; 180 } 181 } 182 183 static const MemoryRegionOps mmio_ops = { 184 .read = e1000e_mmio_read, 185 .write = e1000e_mmio_write, 186 .endianness = DEVICE_LITTLE_ENDIAN, 187 .impl = { 188 .min_access_size = 4, 189 .max_access_size = 4, 190 }, 191 }; 192 193 static const MemoryRegionOps io_ops = { 194 .read = e1000e_io_read, 195 .write = e1000e_io_write, 196 .endianness = DEVICE_LITTLE_ENDIAN, 197 .impl = { 198 .min_access_size = 4, 199 .max_access_size = 4, 200 }, 201 }; 202 203 static bool 204 e1000e_nc_can_receive(NetClientState *nc) 205 { 206 E1000EState *s = qemu_get_nic_opaque(nc); 207 return e1000e_can_receive(&s->core); 208 } 209 210 static ssize_t 211 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) 212 { 213 E1000EState *s = qemu_get_nic_opaque(nc); 214 return e1000e_receive_iov(&s->core, iov, iovcnt); 215 } 216 217 static ssize_t 218 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size) 219 { 220 E1000EState *s = qemu_get_nic_opaque(nc); 221 return e1000e_receive(&s->core, buf, size); 222 } 223 224 static void 225 e1000e_set_link_status(NetClientState *nc) 226 { 227 E1000EState *s = qemu_get_nic_opaque(nc); 228 e1000e_core_set_link_status(&s->core); 229 } 230 231 static NetClientInfo net_e1000e_info = { 232 .type = NET_CLIENT_DRIVER_NIC, 233 .size = sizeof(NICState), 234 .can_receive = e1000e_nc_can_receive, 235 .receive = e1000e_nc_receive, 236 .receive_iov = e1000e_nc_receive_iov, 237 .link_status_changed = e1000e_set_link_status, 238 }; 239 240 /* 241 * EEPROM (NVM) contents documented in Table 36, section 6.1 242 * and generally 6.1.2 Software accessed words. 243 */ 244 static const uint16_t e1000e_eeprom_template[64] = { 245 /* Address | Compat. | ImVer | Compat. */ 246 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff, 247 /* PBA |ICtrl1 | SSID | SVID | DevID |-------|ICtrl2 */ 248 0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058, 249 /* NVM words 1,2,3 |-------------------------------|PCI-EID*/ 250 0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704, 251 /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */ 252 0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706, 253 /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/ 254 0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff, 255 /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP */ 256 0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff, 257 /* SW Section */ 258 0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff, 259 /* SW Section |CHKSUM */ 260 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000, 261 }; 262 263 static void e1000e_core_realize(E1000EState *s) 264 { 265 s->core.owner = &s->parent_obj; 266 s->core.owner_nic = s->nic; 267 } 268 269 static void 270 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors) 271 { 272 int i; 273 for (i = 0; i < num_vectors; i++) { 274 msix_vector_unuse(PCI_DEVICE(s), i); 275 } 276 } 277 278 static bool 279 e1000e_use_msix_vectors(E1000EState *s, int num_vectors) 280 { 281 int i; 282 for (i = 0; i < num_vectors; i++) { 283 int res = msix_vector_use(PCI_DEVICE(s), i); 284 if (res < 0) { 285 trace_e1000e_msix_use_vector_fail(i, res); 286 e1000e_unuse_msix_vectors(s, i); 287 return false; 288 } 289 } 290 return true; 291 } 292 293 static void 294 e1000e_init_msix(E1000EState *s) 295 { 296 PCIDevice *d = PCI_DEVICE(s); 297 int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM, 298 &s->msix, 299 E1000E_MSIX_IDX, E1000E_MSIX_TABLE, 300 &s->msix, 301 E1000E_MSIX_IDX, E1000E_MSIX_PBA, 302 0xA0, NULL); 303 304 if (res < 0) { 305 trace_e1000e_msix_init_fail(res); 306 } else { 307 if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) { 308 msix_uninit(d, &s->msix, &s->msix); 309 } 310 } 311 } 312 313 static void 314 e1000e_cleanup_msix(E1000EState *s) 315 { 316 if (msix_present(PCI_DEVICE(s))) { 317 e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM); 318 msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix); 319 } 320 } 321 322 static void 323 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr) 324 { 325 DeviceState *dev = DEVICE(pci_dev); 326 NetClientState *nc; 327 int i; 328 329 s->nic = qemu_new_nic(&net_e1000e_info, &s->conf, 330 object_get_typename(OBJECT(s)), dev->id, s); 331 332 s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0; 333 334 trace_e1000e_mac_set_permanent(MAC_ARG(macaddr)); 335 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac)); 336 337 qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr); 338 339 /* Setup virtio headers */ 340 if (s->disable_vnet) { 341 s->core.has_vnet = false; 342 trace_e1000e_cfg_support_virtio(false); 343 return; 344 } else { 345 s->core.has_vnet = true; 346 } 347 348 for (i = 0; i < s->conf.peers.queues; i++) { 349 nc = qemu_get_subqueue(s->nic, i); 350 if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) { 351 s->core.has_vnet = false; 352 trace_e1000e_cfg_support_virtio(false); 353 return; 354 } 355 } 356 357 trace_e1000e_cfg_support_virtio(true); 358 359 for (i = 0; i < s->conf.peers.queues; i++) { 360 nc = qemu_get_subqueue(s->nic, i); 361 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr)); 362 qemu_using_vnet_hdr(nc->peer, true); 363 } 364 } 365 366 static inline uint64_t 367 e1000e_gen_dsn(uint8_t *mac) 368 { 369 return (uint64_t)(mac[5]) | 370 (uint64_t)(mac[4]) << 8 | 371 (uint64_t)(mac[3]) << 16 | 372 (uint64_t)(0x00FF) << 24 | 373 (uint64_t)(0x00FF) << 32 | 374 (uint64_t)(mac[2]) << 40 | 375 (uint64_t)(mac[1]) << 48 | 376 (uint64_t)(mac[0]) << 56; 377 } 378 379 static int 380 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) 381 { 382 Error *local_err = NULL; 383 int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, 384 PCI_PM_SIZEOF, &local_err); 385 386 if (local_err) { 387 error_report_err(local_err); 388 return ret; 389 } 390 391 pci_set_word(pdev->config + offset + PCI_PM_PMC, 392 PCI_PM_CAP_VER_1_1 | 393 pmc); 394 395 pci_set_word(pdev->wmask + offset + PCI_PM_CTRL, 396 PCI_PM_CTRL_STATE_MASK | 397 PCI_PM_CTRL_PME_ENABLE | 398 PCI_PM_CTRL_DATA_SEL_MASK); 399 400 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, 401 PCI_PM_CTRL_PME_STATUS); 402 403 return ret; 404 } 405 406 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, 407 uint32_t val, int len) 408 { 409 E1000EState *s = E1000E(pci_dev); 410 411 pci_default_write_config(pci_dev, address, val, len); 412 413 if (range_covers_byte(address, len, PCI_COMMAND) && 414 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { 415 e1000e_start_recv(&s->core); 416 } 417 } 418 419 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) 420 { 421 static const uint16_t e1000e_pmrb_offset = 0x0C8; 422 static const uint16_t e1000e_pcie_offset = 0x0E0; 423 static const uint16_t e1000e_aer_offset = 0x100; 424 static const uint16_t e1000e_dsn_offset = 0x140; 425 E1000EState *s = E1000E(pci_dev); 426 uint8_t *macaddr; 427 int ret; 428 429 trace_e1000e_cb_pci_realize(); 430 431 pci_dev->config_write = e1000e_write_config; 432 433 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 434 pci_dev->config[PCI_INTERRUPT_PIN] = 1; 435 436 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven); 437 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys); 438 439 s->subsys_ven_used = s->subsys_ven; 440 s->subsys_used = s->subsys; 441 442 /* Define IO/MMIO regions */ 443 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s, 444 "e1000e-mmio", E1000E_MMIO_SIZE); 445 pci_register_bar(pci_dev, E1000E_MMIO_IDX, 446 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio); 447 448 /* 449 * We provide a dummy implementation for the flash BAR 450 * for drivers that may theoretically probe for its presence. 451 */ 452 memory_region_init(&s->flash, OBJECT(s), 453 "e1000e-flash", E1000E_FLASH_SIZE); 454 pci_register_bar(pci_dev, E1000E_FLASH_IDX, 455 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash); 456 457 memory_region_init_io(&s->io, OBJECT(s), &io_ops, s, 458 "e1000e-io", E1000E_IO_SIZE); 459 pci_register_bar(pci_dev, E1000E_IO_IDX, 460 PCI_BASE_ADDRESS_SPACE_IO, &s->io); 461 462 memory_region_init(&s->msix, OBJECT(s), "e1000e-msix", 463 E1000E_MSIX_SIZE); 464 pci_register_bar(pci_dev, E1000E_MSIX_IDX, 465 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix); 466 467 /* Create networking backend */ 468 qemu_macaddr_default_if_unset(&s->conf.macaddr); 469 macaddr = s->conf.macaddr.a; 470 471 e1000e_init_msix(s); 472 473 if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { 474 hw_error("Failed to initialize PCIe capability"); 475 } 476 477 ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); 478 if (ret) { 479 trace_e1000e_msi_init_fail(ret); 480 } 481 482 if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, 483 PCI_PM_CAP_DSI) < 0) { 484 hw_error("Failed to initialize PM capability"); 485 } 486 487 if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, 488 PCI_ERR_SIZEOF, NULL) < 0) { 489 hw_error("Failed to initialize AER capability"); 490 } 491 492 pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset, 493 e1000e_gen_dsn(macaddr)); 494 495 e1000e_init_net_peer(s, pci_dev, macaddr); 496 497 /* Initialize core */ 498 e1000e_core_realize(s); 499 500 e1000e_core_pci_realize(&s->core, 501 e1000e_eeprom_template, 502 sizeof(e1000e_eeprom_template), 503 macaddr); 504 } 505 506 static void e1000e_pci_uninit(PCIDevice *pci_dev) 507 { 508 E1000EState *s = E1000E(pci_dev); 509 510 trace_e1000e_cb_pci_uninit(); 511 512 e1000e_core_pci_uninit(&s->core); 513 514 pcie_aer_exit(pci_dev); 515 pcie_cap_exit(pci_dev); 516 517 qemu_del_nic(s->nic); 518 519 e1000e_cleanup_msix(s); 520 msi_uninit(pci_dev); 521 } 522 523 static void e1000e_qdev_reset(DeviceState *dev) 524 { 525 E1000EState *s = E1000E(dev); 526 527 trace_e1000e_cb_qdev_reset(); 528 529 e1000e_core_reset(&s->core); 530 } 531 532 static int e1000e_pre_save(void *opaque) 533 { 534 E1000EState *s = opaque; 535 536 trace_e1000e_cb_pre_save(); 537 538 e1000e_core_pre_save(&s->core); 539 540 return 0; 541 } 542 543 static int e1000e_post_load(void *opaque, int version_id) 544 { 545 E1000EState *s = opaque; 546 547 trace_e1000e_cb_post_load(); 548 549 if ((s->subsys != s->subsys_used) || 550 (s->subsys_ven != s->subsys_ven_used)) { 551 fprintf(stderr, 552 "ERROR: Cannot migrate while device properties " 553 "(subsys/subsys_ven) differ"); 554 return -1; 555 } 556 557 return e1000e_core_post_load(&s->core); 558 } 559 560 static const VMStateDescription e1000e_vmstate_tx = { 561 .name = "e1000e-tx", 562 .version_id = 1, 563 .minimum_version_id = 1, 564 .fields = (VMStateField[]) { 565 VMSTATE_UINT8(sum_needed, struct e1000e_tx), 566 VMSTATE_UINT8(props.ipcss, struct e1000e_tx), 567 VMSTATE_UINT8(props.ipcso, struct e1000e_tx), 568 VMSTATE_UINT16(props.ipcse, struct e1000e_tx), 569 VMSTATE_UINT8(props.tucss, struct e1000e_tx), 570 VMSTATE_UINT8(props.tucso, struct e1000e_tx), 571 VMSTATE_UINT16(props.tucse, struct e1000e_tx), 572 VMSTATE_UINT8(props.hdr_len, struct e1000e_tx), 573 VMSTATE_UINT16(props.mss, struct e1000e_tx), 574 VMSTATE_UINT32(props.paylen, struct e1000e_tx), 575 VMSTATE_INT8(props.ip, struct e1000e_tx), 576 VMSTATE_INT8(props.tcp, struct e1000e_tx), 577 VMSTATE_BOOL(props.tse, struct e1000e_tx), 578 VMSTATE_BOOL(cptse, struct e1000e_tx), 579 VMSTATE_BOOL(skip_cp, struct e1000e_tx), 580 VMSTATE_END_OF_LIST() 581 } 582 }; 583 584 static const VMStateDescription e1000e_vmstate_intr_timer = { 585 .name = "e1000e-intr-timer", 586 .version_id = 1, 587 .minimum_version_id = 1, 588 .fields = (VMStateField[]) { 589 VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer), 590 VMSTATE_BOOL(running, E1000IntrDelayTimer), 591 VMSTATE_END_OF_LIST() 592 } 593 }; 594 595 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \ 596 VMSTATE_STRUCT(_f, _s, 0, \ 597 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 598 599 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \ 600 VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \ 601 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 602 603 static const VMStateDescription e1000e_vmstate = { 604 .name = "e1000e", 605 .version_id = 1, 606 .minimum_version_id = 1, 607 .pre_save = e1000e_pre_save, 608 .post_load = e1000e_post_load, 609 .fields = (VMStateField[]) { 610 VMSTATE_PCI_DEVICE(parent_obj, E1000EState), 611 VMSTATE_MSIX(parent_obj, E1000EState), 612 613 VMSTATE_UINT32(ioaddr, E1000EState), 614 VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState), 615 VMSTATE_UINT8(core.rx_desc_len, E1000EState), 616 VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState, 617 E1000_PSRCTL_BUFFS_PER_DESC), 618 VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState), 619 VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE), 620 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState, 621 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE), 622 VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE), 623 VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN), 624 625 VMSTATE_UINT32(core.delayed_causes, E1000EState), 626 627 VMSTATE_UINT16(subsys, E1000EState), 628 VMSTATE_UINT16(subsys_ven, E1000EState), 629 630 VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState), 631 VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState), 632 VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState), 633 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState), 634 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState), 635 636 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState), 637 VMSTATE_BOOL(core.itr_intr_pending, E1000EState), 638 639 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState, 640 E1000E_MSIX_VEC_NUM), 641 VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState, 642 E1000E_MSIX_VEC_NUM), 643 644 VMSTATE_UINT32(core.itr_guest_value, E1000EState), 645 VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState, 646 E1000E_MSIX_VEC_NUM), 647 648 VMSTATE_UINT16(core.vet, E1000EState), 649 650 VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0, 651 e1000e_vmstate_tx, struct e1000e_tx), 652 VMSTATE_END_OF_LIST() 653 } 654 }; 655 656 static PropertyInfo e1000e_prop_disable_vnet, 657 e1000e_prop_subsys_ven, 658 e1000e_prop_subsys; 659 660 static Property e1000e_properties[] = { 661 DEFINE_NIC_PROPERTIES(E1000EState, conf), 662 DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false, 663 e1000e_prop_disable_vnet, bool), 664 DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven, 665 PCI_VENDOR_ID_INTEL, 666 e1000e_prop_subsys_ven, uint16_t), 667 DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0, 668 e1000e_prop_subsys, uint16_t), 669 DEFINE_PROP_END_OF_LIST(), 670 }; 671 672 static void e1000e_class_init(ObjectClass *class, void *data) 673 { 674 DeviceClass *dc = DEVICE_CLASS(class); 675 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 676 677 c->realize = e1000e_pci_realize; 678 c->exit = e1000e_pci_uninit; 679 c->vendor_id = PCI_VENDOR_ID_INTEL; 680 c->device_id = E1000_DEV_ID_82574L; 681 c->revision = 0; 682 c->romfile = "efi-e1000e.rom"; 683 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 684 685 dc->desc = "Intel 82574L GbE Controller"; 686 dc->reset = e1000e_qdev_reset; 687 dc->vmsd = &e1000e_vmstate; 688 689 e1000e_prop_disable_vnet = qdev_prop_uint8; 690 e1000e_prop_disable_vnet.description = "Do not use virtio headers, " 691 "perform SW offloads emulation " 692 "instead"; 693 694 e1000e_prop_subsys_ven = qdev_prop_uint16; 695 e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID"; 696 697 e1000e_prop_subsys = qdev_prop_uint16; 698 e1000e_prop_subsys.description = "PCI device Subsystem ID"; 699 700 device_class_set_props(dc, e1000e_properties); 701 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 702 } 703 704 static void e1000e_instance_init(Object *obj) 705 { 706 E1000EState *s = E1000E(obj); 707 device_add_bootindex_property(obj, &s->conf.bootindex, 708 "bootindex", "/ethernet-phy@0", 709 DEVICE(obj)); 710 } 711 712 static const TypeInfo e1000e_info = { 713 .name = TYPE_E1000E, 714 .parent = TYPE_PCI_DEVICE, 715 .instance_size = sizeof(E1000EState), 716 .class_init = e1000e_class_init, 717 .instance_init = e1000e_instance_init, 718 .interfaces = (InterfaceInfo[]) { 719 { INTERFACE_PCIE_DEVICE }, 720 { } 721 }, 722 }; 723 724 static void e1000e_register_types(void) 725 { 726 type_register_static(&e1000e_info); 727 } 728 729 type_init(e1000e_register_types) 730