xref: /openbmc/qemu/hw/net/e1000e.c (revision 4b52d632)
1 /*
2  * QEMU INTEL 82574 GbE NIC emulation
3  *
4  * Software developer's manuals:
5  * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6  *
7  * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8  * Developed by Daynix Computing LTD (http://www.daynix.com)
9  *
10  * Authors:
11  * Dmitry Fleytman <dmitry@daynix.com>
12  * Leonid Bloch <leonid@daynix.com>
13  * Yan Vugenfirer <yan@daynix.com>
14  *
15  * Based on work done by:
16  * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17  * Copyright (c) 2008 Qumranet
18  * Based on work done by:
19  * Copyright (c) 2007 Dan Aloni
20  * Copyright (c) 2004 Antony T Curtis
21  *
22  * This library is free software; you can redistribute it and/or
23  * modify it under the terms of the GNU Lesser General Public
24  * License as published by the Free Software Foundation; either
25  * version 2.1 of the License, or (at your option) any later version.
26  *
27  * This library is distributed in the hope that it will be useful,
28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
30  * Lesser General Public License for more details.
31  *
32  * You should have received a copy of the GNU Lesser General Public
33  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34  */
35 
36 #include "qemu/osdep.h"
37 #include "qemu/units.h"
38 #include "net/eth.h"
39 #include "net/net.h"
40 #include "net/tap.h"
41 #include "qemu/module.h"
42 #include "qemu/range.h"
43 #include "sysemu/sysemu.h"
44 #include "hw/hw.h"
45 #include "hw/net/mii.h"
46 #include "hw/pci/msi.h"
47 #include "hw/pci/msix.h"
48 #include "hw/qdev-properties.h"
49 #include "migration/vmstate.h"
50 
51 #include "e1000_common.h"
52 #include "e1000x_common.h"
53 #include "e1000e_core.h"
54 
55 #include "trace.h"
56 #include "qapi/error.h"
57 #include "qom/object.h"
58 
59 #define TYPE_E1000E "e1000e"
60 OBJECT_DECLARE_SIMPLE_TYPE(E1000EState, E1000E)
61 
62 struct E1000EState {
63     PCIDevice parent_obj;
64     NICState *nic;
65     NICConf conf;
66 
67     MemoryRegion mmio;
68     MemoryRegion flash;
69     MemoryRegion io;
70     MemoryRegion msix;
71 
72     uint32_t ioaddr;
73 
74     uint16_t subsys_ven;
75     uint16_t subsys;
76 
77     uint16_t subsys_ven_used;
78     uint16_t subsys_used;
79 
80     bool disable_vnet;
81 
82     E1000ECore core;
83     bool init_vet;
84     bool timadj;
85 };
86 
87 #define E1000E_MMIO_IDX     0
88 #define E1000E_FLASH_IDX    1
89 #define E1000E_IO_IDX       2
90 #define E1000E_MSIX_IDX     3
91 
92 #define E1000E_MMIO_SIZE    (128 * KiB)
93 #define E1000E_FLASH_SIZE   (128 * KiB)
94 #define E1000E_IO_SIZE      (32)
95 #define E1000E_MSIX_SIZE    (16 * KiB)
96 
97 #define E1000E_MSIX_TABLE   (0x0000)
98 #define E1000E_MSIX_PBA     (0x2000)
99 
100 static uint64_t
e1000e_mmio_read(void * opaque,hwaddr addr,unsigned size)101 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
102 {
103     E1000EState *s = opaque;
104     return e1000e_core_read(&s->core, addr, size);
105 }
106 
107 static void
e1000e_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)108 e1000e_mmio_write(void *opaque, hwaddr addr,
109                    uint64_t val, unsigned size)
110 {
111     E1000EState *s = opaque;
112     e1000e_core_write(&s->core, addr, val, size);
113 }
114 
115 static bool
e1000e_io_get_reg_index(E1000EState * s,uint32_t * idx)116 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
117 {
118     if (s->ioaddr < 0x1FFFF) {
119         *idx = s->ioaddr;
120         return true;
121     }
122 
123     if (s->ioaddr < 0x7FFFF) {
124         trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
125         return false;
126     }
127 
128     if (s->ioaddr < 0xFFFFF) {
129         trace_e1000e_wrn_io_addr_flash(s->ioaddr);
130         return false;
131     }
132 
133     trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
134     return false;
135 }
136 
137 static uint64_t
e1000e_io_read(void * opaque,hwaddr addr,unsigned size)138 e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
139 {
140     E1000EState *s = opaque;
141     uint32_t idx = 0;
142     uint64_t val;
143 
144     switch (addr) {
145     case E1000_IOADDR:
146         trace_e1000e_io_read_addr(s->ioaddr);
147         return s->ioaddr;
148     case E1000_IODATA:
149         if (e1000e_io_get_reg_index(s, &idx)) {
150             val = e1000e_core_read(&s->core, idx, sizeof(val));
151             trace_e1000e_io_read_data(idx, val);
152             return val;
153         }
154         return 0;
155     default:
156         trace_e1000e_wrn_io_read_unknown(addr);
157         return 0;
158     }
159 }
160 
161 static void
e1000e_io_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)162 e1000e_io_write(void *opaque, hwaddr addr,
163                 uint64_t val, unsigned size)
164 {
165     E1000EState *s = opaque;
166     uint32_t idx = 0;
167 
168     switch (addr) {
169     case E1000_IOADDR:
170         trace_e1000e_io_write_addr(val);
171         s->ioaddr = (uint32_t) val;
172         return;
173     case E1000_IODATA:
174         if (e1000e_io_get_reg_index(s, &idx)) {
175             trace_e1000e_io_write_data(idx, val);
176             e1000e_core_write(&s->core, idx, val, sizeof(val));
177         }
178         return;
179     default:
180         trace_e1000e_wrn_io_write_unknown(addr);
181         return;
182     }
183 }
184 
185 static const MemoryRegionOps mmio_ops = {
186     .read = e1000e_mmio_read,
187     .write = e1000e_mmio_write,
188     .endianness = DEVICE_LITTLE_ENDIAN,
189     .impl = {
190         .min_access_size = 4,
191         .max_access_size = 4,
192     },
193 };
194 
195 static const MemoryRegionOps io_ops = {
196     .read = e1000e_io_read,
197     .write = e1000e_io_write,
198     .endianness = DEVICE_LITTLE_ENDIAN,
199     .impl = {
200         .min_access_size = 4,
201         .max_access_size = 4,
202     },
203 };
204 
205 static bool
e1000e_nc_can_receive(NetClientState * nc)206 e1000e_nc_can_receive(NetClientState *nc)
207 {
208     E1000EState *s = qemu_get_nic_opaque(nc);
209     return e1000e_can_receive(&s->core);
210 }
211 
212 static ssize_t
e1000e_nc_receive_iov(NetClientState * nc,const struct iovec * iov,int iovcnt)213 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
214 {
215     E1000EState *s = qemu_get_nic_opaque(nc);
216     return e1000e_receive_iov(&s->core, iov, iovcnt);
217 }
218 
219 static ssize_t
e1000e_nc_receive(NetClientState * nc,const uint8_t * buf,size_t size)220 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
221 {
222     E1000EState *s = qemu_get_nic_opaque(nc);
223     return e1000e_receive(&s->core, buf, size);
224 }
225 
226 static void
e1000e_set_link_status(NetClientState * nc)227 e1000e_set_link_status(NetClientState *nc)
228 {
229     E1000EState *s = qemu_get_nic_opaque(nc);
230     e1000e_core_set_link_status(&s->core);
231 }
232 
233 static NetClientInfo net_e1000e_info = {
234     .type = NET_CLIENT_DRIVER_NIC,
235     .size = sizeof(NICState),
236     .can_receive = e1000e_nc_can_receive,
237     .receive = e1000e_nc_receive,
238     .receive_iov = e1000e_nc_receive_iov,
239     .link_status_changed = e1000e_set_link_status,
240 };
241 
242 /*
243  * EEPROM (NVM) contents documented in Table 36, section 6.1
244  * and generally 6.1.2 Software accessed words.
245  */
246 static const uint16_t e1000e_eeprom_template[64] = {
247   /*        Address        |    Compat.    | ImVer |   Compat.     */
248     0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
249   /*      PBA      |ICtrl1 | SSID  | SVID  | DevID |-------|ICtrl2 */
250     0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
251   /*    NVM words 1,2,3    |-------------------------------|PCI-EID*/
252     0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
253   /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
254     0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
255   /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/
256     0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
257   /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP  */
258     0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
259   /*                            SW Section                         */
260     0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
261   /*                      SW Section                       |CHKSUM */
262     0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
263 };
264 
e1000e_core_realize(E1000EState * s)265 static void e1000e_core_realize(E1000EState *s)
266 {
267     s->core.owner = &s->parent_obj;
268     s->core.owner_nic = s->nic;
269 }
270 
271 static void
e1000e_unuse_msix_vectors(E1000EState * s,int num_vectors)272 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
273 {
274     int i;
275     for (i = 0; i < num_vectors; i++) {
276         msix_vector_unuse(PCI_DEVICE(s), i);
277     }
278 }
279 
280 static void
e1000e_use_msix_vectors(E1000EState * s,int num_vectors)281 e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
282 {
283     int i;
284     for (i = 0; i < num_vectors; i++) {
285         msix_vector_use(PCI_DEVICE(s), i);
286     }
287 }
288 
289 static void
e1000e_init_msix(E1000EState * s)290 e1000e_init_msix(E1000EState *s)
291 {
292     int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
293                         &s->msix,
294                         E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
295                         &s->msix,
296                         E1000E_MSIX_IDX, E1000E_MSIX_PBA,
297                         0xA0, NULL);
298 
299     if (res < 0) {
300         trace_e1000e_msix_init_fail(res);
301     } else {
302         e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM);
303     }
304 }
305 
306 static void
e1000e_cleanup_msix(E1000EState * s)307 e1000e_cleanup_msix(E1000EState *s)
308 {
309     if (msix_present(PCI_DEVICE(s))) {
310         e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
311         msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
312     }
313 }
314 
315 static void
e1000e_init_net_peer(E1000EState * s,PCIDevice * pci_dev,uint8_t * macaddr)316 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
317 {
318     DeviceState *dev = DEVICE(pci_dev);
319     NetClientState *nc;
320     int i;
321 
322     s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
323         object_get_typename(OBJECT(s)), dev->id, &dev->mem_reentrancy_guard, s);
324 
325     s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0;
326 
327     trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
328     memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
329 
330     qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
331 
332     /* Setup virtio headers */
333     if (s->disable_vnet) {
334         s->core.has_vnet = false;
335         trace_e1000e_cfg_support_virtio(false);
336         return;
337     } else {
338         s->core.has_vnet = true;
339     }
340 
341     for (i = 0; i < s->conf.peers.queues; i++) {
342         nc = qemu_get_subqueue(s->nic, i);
343         if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
344             s->core.has_vnet = false;
345             trace_e1000e_cfg_support_virtio(false);
346             return;
347         }
348     }
349 
350     trace_e1000e_cfg_support_virtio(true);
351 
352     for (i = 0; i < s->conf.peers.queues; i++) {
353         nc = qemu_get_subqueue(s->nic, i);
354         qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
355     }
356 }
357 
358 static inline uint64_t
e1000e_gen_dsn(uint8_t * mac)359 e1000e_gen_dsn(uint8_t *mac)
360 {
361     return (uint64_t)(mac[5])        |
362            (uint64_t)(mac[4])  << 8  |
363            (uint64_t)(mac[3])  << 16 |
364            (uint64_t)(0x00FF)  << 24 |
365            (uint64_t)(0x00FF)  << 32 |
366            (uint64_t)(mac[2])  << 40 |
367            (uint64_t)(mac[1])  << 48 |
368            (uint64_t)(mac[0])  << 56;
369 }
370 
371 static int
e1000e_add_pm_capability(PCIDevice * pdev,uint8_t offset,uint16_t pmc)372 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
373 {
374     Error *local_err = NULL;
375     int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
376                                  PCI_PM_SIZEOF, &local_err);
377 
378     if (local_err) {
379         error_report_err(local_err);
380         return ret;
381     }
382 
383     pci_set_word(pdev->config + offset + PCI_PM_PMC,
384                  PCI_PM_CAP_VER_1_1 |
385                  pmc);
386 
387     pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
388                  PCI_PM_CTRL_STATE_MASK |
389                  PCI_PM_CTRL_PME_ENABLE |
390                  PCI_PM_CTRL_DATA_SEL_MASK);
391 
392     pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
393                  PCI_PM_CTRL_PME_STATUS);
394 
395     return ret;
396 }
397 
e1000e_write_config(PCIDevice * pci_dev,uint32_t address,uint32_t val,int len)398 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
399                                 uint32_t val, int len)
400 {
401     E1000EState *s = E1000E(pci_dev);
402 
403     pci_default_write_config(pci_dev, address, val, len);
404 
405     if (range_covers_byte(address, len, PCI_COMMAND) &&
406         (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
407         e1000e_start_recv(&s->core);
408     }
409 }
410 
e1000e_pci_realize(PCIDevice * pci_dev,Error ** errp)411 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
412 {
413     static const uint16_t e1000e_pmrb_offset = 0x0C8;
414     static const uint16_t e1000e_pcie_offset = 0x0E0;
415     static const uint16_t e1000e_aer_offset =  0x100;
416     static const uint16_t e1000e_dsn_offset =  0x140;
417     E1000EState *s = E1000E(pci_dev);
418     uint8_t *macaddr;
419     int ret;
420 
421     trace_e1000e_cb_pci_realize();
422 
423     pci_dev->config_write = e1000e_write_config;
424 
425     pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
426     pci_dev->config[PCI_INTERRUPT_PIN] = 1;
427 
428     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
429     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
430 
431     s->subsys_ven_used = s->subsys_ven;
432     s->subsys_used = s->subsys;
433 
434     /* Define IO/MMIO regions */
435     memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
436                           "e1000e-mmio", E1000E_MMIO_SIZE);
437     pci_register_bar(pci_dev, E1000E_MMIO_IDX,
438                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
439 
440     /*
441      * We provide a dummy implementation for the flash BAR
442      * for drivers that may theoretically probe for its presence.
443      */
444     memory_region_init(&s->flash, OBJECT(s),
445                        "e1000e-flash", E1000E_FLASH_SIZE);
446     pci_register_bar(pci_dev, E1000E_FLASH_IDX,
447                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
448 
449     memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
450                           "e1000e-io", E1000E_IO_SIZE);
451     pci_register_bar(pci_dev, E1000E_IO_IDX,
452                      PCI_BASE_ADDRESS_SPACE_IO, &s->io);
453 
454     memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
455                        E1000E_MSIX_SIZE);
456     pci_register_bar(pci_dev, E1000E_MSIX_IDX,
457                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
458 
459     /* Create networking backend */
460     qemu_macaddr_default_if_unset(&s->conf.macaddr);
461     macaddr = s->conf.macaddr.a;
462 
463     e1000e_init_msix(s);
464 
465     if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
466         hw_error("Failed to initialize PCIe capability");
467     }
468 
469     ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
470     if (ret) {
471         trace_e1000e_msi_init_fail(ret);
472     }
473 
474     if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
475                                   PCI_PM_CAP_DSI) < 0) {
476         hw_error("Failed to initialize PM capability");
477     }
478 
479     if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
480                       PCI_ERR_SIZEOF, NULL) < 0) {
481         hw_error("Failed to initialize AER capability");
482     }
483 
484     pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
485                           e1000e_gen_dsn(macaddr));
486 
487     e1000e_init_net_peer(s, pci_dev, macaddr);
488 
489     /* Initialize core */
490     e1000e_core_realize(s);
491 
492     e1000e_core_pci_realize(&s->core,
493                             e1000e_eeprom_template,
494                             sizeof(e1000e_eeprom_template),
495                             macaddr);
496 }
497 
e1000e_pci_uninit(PCIDevice * pci_dev)498 static void e1000e_pci_uninit(PCIDevice *pci_dev)
499 {
500     E1000EState *s = E1000E(pci_dev);
501 
502     trace_e1000e_cb_pci_uninit();
503 
504     e1000e_core_pci_uninit(&s->core);
505 
506     pcie_aer_exit(pci_dev);
507     pcie_cap_exit(pci_dev);
508 
509     qemu_del_nic(s->nic);
510 
511     e1000e_cleanup_msix(s);
512     msi_uninit(pci_dev);
513 }
514 
e1000e_qdev_reset_hold(Object * obj,ResetType type)515 static void e1000e_qdev_reset_hold(Object *obj, ResetType type)
516 {
517     E1000EState *s = E1000E(obj);
518 
519     trace_e1000e_cb_qdev_reset_hold();
520 
521     e1000e_core_reset(&s->core);
522 
523     if (s->init_vet) {
524         s->core.mac[VET] = ETH_P_VLAN;
525     }
526 }
527 
e1000e_pre_save(void * opaque)528 static int e1000e_pre_save(void *opaque)
529 {
530     E1000EState *s = opaque;
531 
532     trace_e1000e_cb_pre_save();
533 
534     e1000e_core_pre_save(&s->core);
535 
536     return 0;
537 }
538 
e1000e_post_load(void * opaque,int version_id)539 static int e1000e_post_load(void *opaque, int version_id)
540 {
541     E1000EState *s = opaque;
542 
543     trace_e1000e_cb_post_load();
544 
545     if ((s->subsys != s->subsys_used) ||
546         (s->subsys_ven != s->subsys_ven_used)) {
547         fprintf(stderr,
548             "ERROR: Cannot migrate while device properties "
549             "(subsys/subsys_ven) differ");
550         return -1;
551     }
552 
553     return e1000e_core_post_load(&s->core);
554 }
555 
e1000e_migrate_timadj(void * opaque,int version_id)556 static bool e1000e_migrate_timadj(void *opaque, int version_id)
557 {
558     E1000EState *s = opaque;
559     return s->timadj;
560 }
561 
562 static const VMStateDescription e1000e_vmstate_tx = {
563     .name = "e1000e-tx",
564     .version_id = 1,
565     .minimum_version_id = 1,
566     .fields = (const VMStateField[]) {
567         VMSTATE_UINT8(sum_needed, struct e1000e_tx),
568         VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
569         VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
570         VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
571         VMSTATE_UINT8(props.tucss, struct e1000e_tx),
572         VMSTATE_UINT8(props.tucso, struct e1000e_tx),
573         VMSTATE_UINT16(props.tucse, struct e1000e_tx),
574         VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
575         VMSTATE_UINT16(props.mss, struct e1000e_tx),
576         VMSTATE_UINT32(props.paylen, struct e1000e_tx),
577         VMSTATE_INT8(props.ip, struct e1000e_tx),
578         VMSTATE_INT8(props.tcp, struct e1000e_tx),
579         VMSTATE_BOOL(props.tse, struct e1000e_tx),
580         VMSTATE_BOOL(cptse, struct e1000e_tx),
581         VMSTATE_BOOL(skip_cp, struct e1000e_tx),
582         VMSTATE_END_OF_LIST()
583     }
584 };
585 
586 static const VMStateDescription e1000e_vmstate_intr_timer = {
587     .name = "e1000e-intr-timer",
588     .version_id = 1,
589     .minimum_version_id = 1,
590     .fields = (const VMStateField[]) {
591         VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
592         VMSTATE_BOOL(running, E1000IntrDelayTimer),
593         VMSTATE_END_OF_LIST()
594     }
595 };
596 
597 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s)                     \
598     VMSTATE_STRUCT(_f, _s, 0,                                       \
599                    e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
600 
601 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num)         \
602     VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
603                          e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
604 
605 static const VMStateDescription e1000e_vmstate = {
606     .name = "e1000e",
607     .version_id = 1,
608     .minimum_version_id = 1,
609     .pre_save = e1000e_pre_save,
610     .post_load = e1000e_post_load,
611     .fields = (const VMStateField[]) {
612         VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
613         VMSTATE_MSIX(parent_obj, E1000EState),
614 
615         VMSTATE_UINT32(ioaddr, E1000EState),
616         VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
617         VMSTATE_UINT8(core.rx_desc_len, E1000EState),
618         VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
619                              E1000_PSRCTL_BUFFS_PER_DESC),
620         VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
621         VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
622         VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
623                                E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
624         VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
625         VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
626 
627         VMSTATE_UINT32(core.delayed_causes, E1000EState),
628 
629         VMSTATE_UINT16(subsys, E1000EState),
630         VMSTATE_UINT16(subsys_ven, E1000EState),
631 
632         VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
633         VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
634         VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
635         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
636         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
637 
638         VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
639         VMSTATE_UNUSED(1),
640 
641         VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
642                                               E1000E_MSIX_VEC_NUM),
643         VMSTATE_UNUSED(E1000E_MSIX_VEC_NUM),
644 
645         VMSTATE_UINT32(core.itr_guest_value, E1000EState),
646         VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
647                              E1000E_MSIX_VEC_NUM),
648 
649         VMSTATE_UINT16(core.vet, E1000EState),
650 
651         VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
652                              e1000e_vmstate_tx, struct e1000e_tx),
653 
654         VMSTATE_INT64_TEST(core.timadj, E1000EState, e1000e_migrate_timadj),
655 
656         VMSTATE_END_OF_LIST()
657     }
658 };
659 
660 static PropertyInfo e1000e_prop_disable_vnet,
661                     e1000e_prop_subsys_ven,
662                     e1000e_prop_subsys;
663 
664 static Property e1000e_properties[] = {
665     DEFINE_NIC_PROPERTIES(E1000EState, conf),
666     DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
667                         e1000e_prop_disable_vnet, bool),
668     DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
669                         PCI_VENDOR_ID_INTEL,
670                         e1000e_prop_subsys_ven, uint16_t),
671     DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
672                         e1000e_prop_subsys, uint16_t),
673     DEFINE_PROP_BOOL("init-vet", E1000EState, init_vet, true),
674     DEFINE_PROP_BOOL("migrate-timadj", E1000EState, timadj, true),
675     DEFINE_PROP_END_OF_LIST(),
676 };
677 
e1000e_class_init(ObjectClass * class,void * data)678 static void e1000e_class_init(ObjectClass *class, void *data)
679 {
680     DeviceClass *dc = DEVICE_CLASS(class);
681     ResettableClass *rc = RESETTABLE_CLASS(class);
682     PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
683 
684     c->realize = e1000e_pci_realize;
685     c->exit = e1000e_pci_uninit;
686     c->vendor_id = PCI_VENDOR_ID_INTEL;
687     c->device_id = E1000_DEV_ID_82574L;
688     c->revision = 0;
689     c->romfile = "efi-e1000e.rom";
690     c->class_id = PCI_CLASS_NETWORK_ETHERNET;
691 
692     rc->phases.hold = e1000e_qdev_reset_hold;
693 
694     dc->desc = "Intel 82574L GbE Controller";
695     dc->vmsd = &e1000e_vmstate;
696 
697     e1000e_prop_disable_vnet = qdev_prop_uint8;
698     e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
699                                            "perform SW offloads emulation "
700                                            "instead";
701 
702     e1000e_prop_subsys_ven = qdev_prop_uint16;
703     e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
704 
705     e1000e_prop_subsys = qdev_prop_uint16;
706     e1000e_prop_subsys.description = "PCI device Subsystem ID";
707 
708     device_class_set_props(dc, e1000e_properties);
709     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
710 }
711 
e1000e_instance_init(Object * obj)712 static void e1000e_instance_init(Object *obj)
713 {
714     E1000EState *s = E1000E(obj);
715     device_add_bootindex_property(obj, &s->conf.bootindex,
716                                   "bootindex", "/ethernet-phy@0",
717                                   DEVICE(obj));
718 }
719 
720 static const TypeInfo e1000e_info = {
721     .name = TYPE_E1000E,
722     .parent = TYPE_PCI_DEVICE,
723     .instance_size = sizeof(E1000EState),
724     .class_init = e1000e_class_init,
725     .instance_init = e1000e_instance_init,
726     .interfaces = (InterfaceInfo[]) {
727         { INTERFACE_PCIE_DEVICE },
728         { }
729     },
730 };
731 
e1000e_register_types(void)732 static void e1000e_register_types(void)
733 {
734     type_register_static(&e1000e_info);
735 }
736 
737 type_init(e1000e_register_types)
738