1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 #include "qom/object.h" 31 #include "trace.h" 32 33 static const char *reg_names[] = { 34 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 35 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 36 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 37 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 38 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 39 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 40 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 41 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 42 43 #define SONIC_CR 0x00 44 #define SONIC_DCR 0x01 45 #define SONIC_RCR 0x02 46 #define SONIC_TCR 0x03 47 #define SONIC_IMR 0x04 48 #define SONIC_ISR 0x05 49 #define SONIC_UTDA 0x06 50 #define SONIC_CTDA 0x07 51 #define SONIC_TPS 0x08 52 #define SONIC_TFC 0x09 53 #define SONIC_TSA0 0x0a 54 #define SONIC_TSA1 0x0b 55 #define SONIC_TFS 0x0c 56 #define SONIC_URDA 0x0d 57 #define SONIC_CRDA 0x0e 58 #define SONIC_CRBA0 0x0f 59 #define SONIC_CRBA1 0x10 60 #define SONIC_RBWC0 0x11 61 #define SONIC_RBWC1 0x12 62 #define SONIC_EOBC 0x13 63 #define SONIC_URRA 0x14 64 #define SONIC_RSA 0x15 65 #define SONIC_REA 0x16 66 #define SONIC_RRP 0x17 67 #define SONIC_RWP 0x18 68 #define SONIC_TRBA0 0x19 69 #define SONIC_TRBA1 0x1a 70 #define SONIC_LLFA 0x1f 71 #define SONIC_TTDA 0x20 72 #define SONIC_CEP 0x21 73 #define SONIC_CAP2 0x22 74 #define SONIC_CAP1 0x23 75 #define SONIC_CAP0 0x24 76 #define SONIC_CE 0x25 77 #define SONIC_CDP 0x26 78 #define SONIC_CDC 0x27 79 #define SONIC_SR 0x28 80 #define SONIC_WT0 0x29 81 #define SONIC_WT1 0x2a 82 #define SONIC_RSC 0x2b 83 #define SONIC_CRCT 0x2c 84 #define SONIC_FAET 0x2d 85 #define SONIC_MPT 0x2e 86 #define SONIC_MDT 0x2f 87 #define SONIC_DCR2 0x3f 88 89 #define SONIC_CR_HTX 0x0001 90 #define SONIC_CR_TXP 0x0002 91 #define SONIC_CR_RXDIS 0x0004 92 #define SONIC_CR_RXEN 0x0008 93 #define SONIC_CR_STP 0x0010 94 #define SONIC_CR_ST 0x0020 95 #define SONIC_CR_RST 0x0080 96 #define SONIC_CR_RRRA 0x0100 97 #define SONIC_CR_LCAM 0x0200 98 #define SONIC_CR_MASK 0x03bf 99 100 #define SONIC_DCR_DW 0x0020 101 #define SONIC_DCR_LBR 0x2000 102 #define SONIC_DCR_EXBUS 0x8000 103 104 #define SONIC_RCR_PRX 0x0001 105 #define SONIC_RCR_LBK 0x0002 106 #define SONIC_RCR_FAER 0x0004 107 #define SONIC_RCR_CRCR 0x0008 108 #define SONIC_RCR_CRS 0x0020 109 #define SONIC_RCR_LPKT 0x0040 110 #define SONIC_RCR_BC 0x0080 111 #define SONIC_RCR_MC 0x0100 112 #define SONIC_RCR_LB0 0x0200 113 #define SONIC_RCR_LB1 0x0400 114 #define SONIC_RCR_AMC 0x0800 115 #define SONIC_RCR_PRO 0x1000 116 #define SONIC_RCR_BRD 0x2000 117 #define SONIC_RCR_RNT 0x4000 118 119 #define SONIC_TCR_PTX 0x0001 120 #define SONIC_TCR_BCM 0x0002 121 #define SONIC_TCR_FU 0x0004 122 #define SONIC_TCR_EXC 0x0040 123 #define SONIC_TCR_CRSL 0x0080 124 #define SONIC_TCR_NCRS 0x0100 125 #define SONIC_TCR_EXD 0x0400 126 #define SONIC_TCR_CRCI 0x2000 127 #define SONIC_TCR_PINT 0x8000 128 129 #define SONIC_ISR_RBAE 0x0010 130 #define SONIC_ISR_RBE 0x0020 131 #define SONIC_ISR_RDE 0x0040 132 #define SONIC_ISR_TC 0x0080 133 #define SONIC_ISR_TXDN 0x0200 134 #define SONIC_ISR_PKTRX 0x0400 135 #define SONIC_ISR_PINT 0x0800 136 #define SONIC_ISR_LCD 0x1000 137 138 #define SONIC_DESC_EOL 0x0001 139 #define SONIC_DESC_ADDR 0xFFFE 140 141 #define TYPE_DP8393X "dp8393x" 142 OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X) 143 144 struct dp8393xState { 145 SysBusDevice parent_obj; 146 147 /* Hardware */ 148 uint8_t it_shift; 149 bool big_endian; 150 bool last_rba_is_full; 151 qemu_irq irq; 152 int irq_level; 153 QEMUTimer *watchdog; 154 int64_t wt_last_update; 155 NICConf conf; 156 NICState *nic; 157 MemoryRegion mmio; 158 159 /* Registers */ 160 uint8_t cam[16][6]; 161 uint16_t regs[0x40]; 162 163 /* Temporaries */ 164 uint8_t tx_buffer[0x10000]; 165 uint16_t data[12]; 166 int loopback_packet; 167 168 /* Memory access */ 169 MemoryRegion *dma_mr; 170 AddressSpace as; 171 }; 172 173 /* 174 * Accessor functions for values which are formed by 175 * concatenating two 16 bit device registers. By putting these 176 * in their own functions with a uint32_t return type we avoid the 177 * pitfall of implicit sign extension where ((x << 16) | y) is a 178 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 179 */ 180 static uint32_t dp8393x_cdp(dp8393xState *s) 181 { 182 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 183 } 184 185 static uint32_t dp8393x_crba(dp8393xState *s) 186 { 187 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 188 } 189 190 static uint32_t dp8393x_crda(dp8393xState *s) 191 { 192 return (s->regs[SONIC_URDA] << 16) | 193 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); 194 } 195 196 static uint32_t dp8393x_rbwc(dp8393xState *s) 197 { 198 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 199 } 200 201 static uint32_t dp8393x_rrp(dp8393xState *s) 202 { 203 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 204 } 205 206 static uint32_t dp8393x_tsa(dp8393xState *s) 207 { 208 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 209 } 210 211 static uint32_t dp8393x_ttda(dp8393xState *s) 212 { 213 return (s->regs[SONIC_UTDA] << 16) | 214 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); 215 } 216 217 static uint32_t dp8393x_wt(dp8393xState *s) 218 { 219 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 220 } 221 222 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 223 { 224 uint16_t val; 225 226 if (s->big_endian) { 227 val = be16_to_cpu(s->data[offset * width + width - 1]); 228 } else { 229 val = le16_to_cpu(s->data[offset * width]); 230 } 231 return val; 232 } 233 234 static void dp8393x_put(dp8393xState *s, int width, int offset, 235 uint16_t val) 236 { 237 if (s->big_endian) { 238 if (width == 2) { 239 s->data[offset * 2] = 0; 240 s->data[offset * 2 + 1] = cpu_to_be16(val); 241 } else { 242 s->data[offset] = cpu_to_be16(val); 243 } 244 } else { 245 if (width == 2) { 246 s->data[offset * 2] = cpu_to_le16(val); 247 s->data[offset * 2 + 1] = 0; 248 } else { 249 s->data[offset] = cpu_to_le16(val); 250 } 251 } 252 } 253 254 static void dp8393x_update_irq(dp8393xState *s) 255 { 256 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 257 258 if (level != s->irq_level) { 259 s->irq_level = level; 260 if (level) { 261 trace_dp8393x_raise_irq(s->regs[SONIC_ISR]); 262 } else { 263 trace_dp8393x_lower_irq(); 264 } 265 } 266 267 qemu_set_irq(s->irq, level); 268 } 269 270 static void dp8393x_do_load_cam(dp8393xState *s) 271 { 272 int width, size; 273 uint16_t index = 0; 274 275 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 276 size = sizeof(uint16_t) * 4 * width; 277 278 while (s->regs[SONIC_CDC] & 0x1f) { 279 /* Fill current entry */ 280 address_space_read(&s->as, dp8393x_cdp(s), 281 MEMTXATTRS_UNSPECIFIED, s->data, size); 282 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 283 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 284 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 285 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 286 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 287 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 288 trace_dp8393x_load_cam(index, s->cam[index][0], s->cam[index][1], 289 s->cam[index][2], s->cam[index][3], 290 s->cam[index][4], s->cam[index][5]); 291 /* Move to next entry */ 292 s->regs[SONIC_CDC]--; 293 s->regs[SONIC_CDP] += size; 294 index++; 295 } 296 297 /* Read CAM enable */ 298 address_space_read(&s->as, dp8393x_cdp(s), 299 MEMTXATTRS_UNSPECIFIED, s->data, size); 300 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 301 trace_dp8393x_load_cam_done(s->regs[SONIC_CE]); 302 303 /* Done */ 304 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 305 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 306 dp8393x_update_irq(s); 307 } 308 309 static void dp8393x_do_read_rra(dp8393xState *s) 310 { 311 int width, size; 312 313 /* Read memory */ 314 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 315 size = sizeof(uint16_t) * 4 * width; 316 address_space_read(&s->as, dp8393x_rrp(s), 317 MEMTXATTRS_UNSPECIFIED, s->data, size); 318 319 /* Update SONIC registers */ 320 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 321 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 322 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 323 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 324 trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 325 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 326 327 /* Go to next entry */ 328 s->regs[SONIC_RRP] += size; 329 330 /* Handle wrap */ 331 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 332 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 333 } 334 335 /* Warn the host if CRBA now has the last available resource */ 336 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) { 337 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 338 dp8393x_update_irq(s); 339 } 340 341 /* Allow packet reception */ 342 s->last_rba_is_full = false; 343 } 344 345 static void dp8393x_do_software_reset(dp8393xState *s) 346 { 347 timer_del(s->watchdog); 348 349 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | 350 SONIC_CR_HTX); 351 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 352 } 353 354 static void dp8393x_set_next_tick(dp8393xState *s) 355 { 356 uint32_t ticks; 357 int64_t delay; 358 359 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 360 timer_del(s->watchdog); 361 return; 362 } 363 364 ticks = dp8393x_wt(s); 365 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 366 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 367 timer_mod(s->watchdog, s->wt_last_update + delay); 368 } 369 370 static void dp8393x_update_wt_regs(dp8393xState *s) 371 { 372 int64_t elapsed; 373 uint32_t val; 374 375 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 376 timer_del(s->watchdog); 377 return; 378 } 379 380 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 381 val = dp8393x_wt(s); 382 val -= elapsed / 5000000; 383 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 384 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 385 dp8393x_set_next_tick(s); 386 387 } 388 389 static void dp8393x_do_start_timer(dp8393xState *s) 390 { 391 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 392 dp8393x_set_next_tick(s); 393 } 394 395 static void dp8393x_do_stop_timer(dp8393xState *s) 396 { 397 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 398 dp8393x_update_wt_regs(s); 399 } 400 401 static bool dp8393x_can_receive(NetClientState *nc); 402 403 static void dp8393x_do_receiver_enable(dp8393xState *s) 404 { 405 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 406 if (dp8393x_can_receive(s->nic->ncs)) { 407 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 408 } 409 } 410 411 static void dp8393x_do_receiver_disable(dp8393xState *s) 412 { 413 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 414 } 415 416 static void dp8393x_do_transmit_packets(dp8393xState *s) 417 { 418 NetClientState *nc = qemu_get_queue(s->nic); 419 int width, size; 420 int tx_len, len; 421 uint16_t i; 422 423 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 424 425 while (1) { 426 /* Read memory */ 427 size = sizeof(uint16_t) * 6 * width; 428 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 429 trace_dp8393x_transmit_packet(dp8393x_ttda(s)); 430 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 431 MEMTXATTRS_UNSPECIFIED, s->data, size); 432 tx_len = 0; 433 434 /* Update registers */ 435 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 436 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 437 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 438 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 439 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 440 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 441 442 /* Handle programmable interrupt */ 443 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 444 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 445 } else { 446 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 447 } 448 449 for (i = 0; i < s->regs[SONIC_TFC]; ) { 450 /* Append fragment */ 451 len = s->regs[SONIC_TFS]; 452 if (tx_len + len > sizeof(s->tx_buffer)) { 453 len = sizeof(s->tx_buffer) - tx_len; 454 } 455 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 456 &s->tx_buffer[tx_len], len); 457 tx_len += len; 458 459 i++; 460 if (i != s->regs[SONIC_TFC]) { 461 /* Read next fragment details */ 462 size = sizeof(uint16_t) * 3 * width; 463 address_space_read(&s->as, 464 dp8393x_ttda(s) 465 + sizeof(uint16_t) * width * (4 + 3 * i), 466 MEMTXATTRS_UNSPECIFIED, s->data, 467 size); 468 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 469 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 470 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 471 } 472 } 473 474 /* Handle Ethernet checksum */ 475 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 476 /* 477 * Don't append FCS there, to look like slirp packets 478 * which don't have one 479 */ 480 } else { 481 /* Remove existing FCS */ 482 tx_len -= 4; 483 if (tx_len < 0) { 484 trace_dp8393x_transmit_txlen_error(tx_len); 485 break; 486 } 487 } 488 489 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 490 /* Loopback */ 491 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 492 if (nc->info->can_receive(nc)) { 493 s->loopback_packet = 1; 494 qemu_receive_packet(nc, s->tx_buffer, tx_len); 495 } 496 } else { 497 /* Transmit packet */ 498 qemu_send_packet(nc, s->tx_buffer, tx_len); 499 } 500 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 501 502 /* Write status */ 503 dp8393x_put(s, width, 0, 504 s->regs[SONIC_TCR] & 0x0fff); /* status */ 505 size = sizeof(uint16_t) * width; 506 address_space_write(&s->as, dp8393x_ttda(s), 507 MEMTXATTRS_UNSPECIFIED, s->data, size); 508 509 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 510 /* Read footer of packet */ 511 size = sizeof(uint16_t) * width; 512 address_space_read(&s->as, 513 dp8393x_ttda(s) 514 + sizeof(uint16_t) * width 515 * (4 + 3 * s->regs[SONIC_TFC]), 516 MEMTXATTRS_UNSPECIFIED, s->data, 517 size); 518 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0); 519 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) { 520 /* EOL detected */ 521 break; 522 } 523 } 524 } 525 526 /* Done */ 527 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 528 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 529 dp8393x_update_irq(s); 530 } 531 532 static void dp8393x_do_halt_transmission(dp8393xState *s) 533 { 534 /* Nothing to do */ 535 } 536 537 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 538 { 539 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 540 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 541 return; 542 } 543 544 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 545 546 if (command & SONIC_CR_HTX) { 547 dp8393x_do_halt_transmission(s); 548 } 549 if (command & SONIC_CR_TXP) { 550 dp8393x_do_transmit_packets(s); 551 } 552 if (command & SONIC_CR_RXDIS) { 553 dp8393x_do_receiver_disable(s); 554 } 555 if (command & SONIC_CR_RXEN) { 556 dp8393x_do_receiver_enable(s); 557 } 558 if (command & SONIC_CR_STP) { 559 dp8393x_do_stop_timer(s); 560 } 561 if (command & SONIC_CR_ST) { 562 dp8393x_do_start_timer(s); 563 } 564 if (command & SONIC_CR_RST) { 565 dp8393x_do_software_reset(s); 566 } 567 if (command & SONIC_CR_RRRA) { 568 dp8393x_do_read_rra(s); 569 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 570 } 571 if (command & SONIC_CR_LCAM) { 572 dp8393x_do_load_cam(s); 573 } 574 } 575 576 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 577 { 578 dp8393xState *s = opaque; 579 int reg = addr >> s->it_shift; 580 uint16_t val = 0; 581 582 switch (reg) { 583 /* Update data before reading it */ 584 case SONIC_WT0: 585 case SONIC_WT1: 586 dp8393x_update_wt_regs(s); 587 val = s->regs[reg]; 588 break; 589 /* Accept read to some registers only when in reset mode */ 590 case SONIC_CAP2: 591 case SONIC_CAP1: 592 case SONIC_CAP0: 593 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 594 val = s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg) + 1] << 8; 595 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg)]; 596 } 597 break; 598 /* All other registers have no special contraints */ 599 default: 600 val = s->regs[reg]; 601 } 602 603 trace_dp8393x_read(reg, reg_names[reg], val, size); 604 605 return s->big_endian ? val << 16 : val; 606 } 607 608 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 609 unsigned int size) 610 { 611 dp8393xState *s = opaque; 612 int reg = addr >> s->it_shift; 613 uint32_t val = s->big_endian ? data >> 16 : data; 614 615 trace_dp8393x_write(reg, reg_names[reg], val, size); 616 617 switch (reg) { 618 /* Command register */ 619 case SONIC_CR: 620 dp8393x_do_command(s, val); 621 break; 622 /* Prevent write to read-only registers */ 623 case SONIC_CAP2: 624 case SONIC_CAP1: 625 case SONIC_CAP0: 626 case SONIC_SR: 627 case SONIC_MDT: 628 trace_dp8393x_write_invalid(reg); 629 break; 630 /* Accept write to some registers only when in reset mode */ 631 case SONIC_DCR: 632 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 633 s->regs[reg] = val & 0xbfff; 634 } else { 635 trace_dp8393x_write_invalid_dcr("DCR"); 636 } 637 break; 638 case SONIC_DCR2: 639 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 640 s->regs[reg] = val & 0xf017; 641 } else { 642 trace_dp8393x_write_invalid_dcr("DCR2"); 643 } 644 break; 645 /* 12 lower bytes are Read Only */ 646 case SONIC_TCR: 647 s->regs[reg] = val & 0xf000; 648 break; 649 /* 9 lower bytes are Read Only */ 650 case SONIC_RCR: 651 s->regs[reg] = val & 0xffe0; 652 break; 653 /* Ignore most significant bit */ 654 case SONIC_IMR: 655 s->regs[reg] = val & 0x7fff; 656 dp8393x_update_irq(s); 657 break; 658 /* Clear bits by writing 1 to them */ 659 case SONIC_ISR: 660 val &= s->regs[reg]; 661 s->regs[reg] &= ~val; 662 if (val & SONIC_ISR_RBE) { 663 dp8393x_do_read_rra(s); 664 } 665 dp8393x_update_irq(s); 666 break; 667 /* The guest is required to store aligned pointers here */ 668 case SONIC_RSA: 669 case SONIC_REA: 670 case SONIC_RRP: 671 case SONIC_RWP: 672 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 673 s->regs[reg] = val & 0xfffc; 674 } else { 675 s->regs[reg] = val & 0xfffe; 676 } 677 break; 678 /* Invert written value for some registers */ 679 case SONIC_CRCT: 680 case SONIC_FAET: 681 case SONIC_MPT: 682 s->regs[reg] = val ^ 0xffff; 683 break; 684 /* All other registers have no special contrainst */ 685 default: 686 s->regs[reg] = val; 687 } 688 689 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 690 dp8393x_set_next_tick(s); 691 } 692 } 693 694 static const MemoryRegionOps dp8393x_ops = { 695 .read = dp8393x_read, 696 .write = dp8393x_write, 697 .impl.min_access_size = 4, 698 .impl.max_access_size = 4, 699 .endianness = DEVICE_NATIVE_ENDIAN, 700 }; 701 702 static void dp8393x_watchdog(void *opaque) 703 { 704 dp8393xState *s = opaque; 705 706 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 707 return; 708 } 709 710 s->regs[SONIC_WT1] = 0xffff; 711 s->regs[SONIC_WT0] = 0xffff; 712 dp8393x_set_next_tick(s); 713 714 /* Signal underflow */ 715 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 716 dp8393x_update_irq(s); 717 } 718 719 static bool dp8393x_can_receive(NetClientState *nc) 720 { 721 dp8393xState *s = qemu_get_nic_opaque(nc); 722 723 return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN); 724 } 725 726 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 727 int size) 728 { 729 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 730 int i; 731 732 /* Check promiscuous mode */ 733 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 734 return 0; 735 } 736 737 /* Check multicast packets */ 738 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 739 return SONIC_RCR_MC; 740 } 741 742 /* Check broadcast */ 743 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && 744 !memcmp(buf, bcast, sizeof(bcast))) { 745 return SONIC_RCR_BC; 746 } 747 748 /* Check CAM */ 749 for (i = 0; i < 16; i++) { 750 if (s->regs[SONIC_CE] & (1 << i)) { 751 /* Entry enabled */ 752 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 753 return 0; 754 } 755 } 756 } 757 758 return -1; 759 } 760 761 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 762 size_t pkt_size) 763 { 764 dp8393xState *s = qemu_get_nic_opaque(nc); 765 int packet_type; 766 uint32_t available, address; 767 int width, rx_len, padded_len; 768 uint32_t checksum; 769 int size; 770 771 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 772 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 773 774 if (s->last_rba_is_full) { 775 return pkt_size; 776 } 777 778 rx_len = pkt_size + sizeof(checksum); 779 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 780 width = 2; 781 padded_len = ((rx_len - 1) | 3) + 1; 782 } else { 783 width = 1; 784 padded_len = ((rx_len - 1) | 1) + 1; 785 } 786 787 if (padded_len > dp8393x_rbwc(s) * 2) { 788 trace_dp8393x_receive_oversize(pkt_size); 789 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE; 790 dp8393x_update_irq(s); 791 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 792 goto done; 793 } 794 795 packet_type = dp8393x_receive_filter(s, buf, pkt_size); 796 if (packet_type < 0) { 797 trace_dp8393x_receive_not_netcard(); 798 return -1; 799 } 800 801 /* Check for EOL */ 802 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 803 /* Are we still in resource exhaustion? */ 804 size = sizeof(uint16_t) * 1 * width; 805 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 806 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 807 s->data, size); 808 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 809 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 810 /* Still EOL ; stop reception */ 811 return -1; 812 } 813 /* Link has been updated by host */ 814 815 /* Clear in_use */ 816 size = sizeof(uint16_t) * width; 817 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 818 dp8393x_put(s, width, 0, 0); 819 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 820 (uint8_t *)s->data, size, 1); 821 822 /* Move to next descriptor */ 823 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 824 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 825 } 826 827 /* Save current position */ 828 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 829 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 830 831 /* Calculate the ethernet checksum */ 832 checksum = cpu_to_le32(crc32(0, buf, pkt_size)); 833 834 /* Put packet into RBA */ 835 trace_dp8393x_receive_packet(dp8393x_crba(s)); 836 address = dp8393x_crba(s); 837 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 838 buf, pkt_size); 839 address += pkt_size; 840 841 /* Put frame checksum into RBA */ 842 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 843 &checksum, sizeof(checksum)); 844 address += sizeof(checksum); 845 846 /* Pad short packets to keep pointers aligned */ 847 if (rx_len < padded_len) { 848 size = padded_len - rx_len; 849 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 850 (uint8_t *)"\xFF\xFF\xFF", size, 1); 851 address += size; 852 } 853 854 s->regs[SONIC_CRBA1] = address >> 16; 855 s->regs[SONIC_CRBA0] = address & 0xffff; 856 available = dp8393x_rbwc(s); 857 available -= padded_len >> 1; 858 s->regs[SONIC_RBWC1] = available >> 16; 859 s->regs[SONIC_RBWC0] = available & 0xffff; 860 861 /* Update status */ 862 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 863 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 864 } 865 s->regs[SONIC_RCR] |= packet_type; 866 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 867 if (s->loopback_packet) { 868 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 869 s->loopback_packet = 0; 870 } 871 872 /* Write status to memory */ 873 trace_dp8393x_receive_write_status(dp8393x_crda(s)); 874 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 875 dp8393x_put(s, width, 1, rx_len); /* byte count */ 876 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 877 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 878 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 879 size = sizeof(uint16_t) * 5 * width; 880 address_space_write(&s->as, dp8393x_crda(s), 881 MEMTXATTRS_UNSPECIFIED, 882 s->data, size); 883 884 /* Check link field */ 885 size = sizeof(uint16_t) * width; 886 address_space_read(&s->as, 887 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 888 MEMTXATTRS_UNSPECIFIED, s->data, size); 889 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 890 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 891 /* EOL detected */ 892 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 893 } else { 894 /* Clear in_use */ 895 size = sizeof(uint16_t) * width; 896 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 897 dp8393x_put(s, width, 0, 0); 898 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 899 s->data, size); 900 901 /* Move to next descriptor */ 902 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 903 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 904 } 905 906 dp8393x_update_irq(s); 907 908 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | 909 ((s->regs[SONIC_RSC] + 1) & 0x00ff); 910 911 done: 912 913 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 914 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) { 915 /* Stop packet reception */ 916 s->last_rba_is_full = true; 917 } else { 918 /* Read next resource */ 919 dp8393x_do_read_rra(s); 920 } 921 } 922 923 return pkt_size; 924 } 925 926 static void dp8393x_reset(DeviceState *dev) 927 { 928 dp8393xState *s = DP8393X(dev); 929 timer_del(s->watchdog); 930 931 memset(s->regs, 0, sizeof(s->regs)); 932 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */ 933 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 934 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 935 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | 936 SONIC_RCR_RNT); 937 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 938 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 939 s->regs[SONIC_IMR] = 0; 940 s->regs[SONIC_ISR] = 0; 941 s->regs[SONIC_DCR2] = 0; 942 s->regs[SONIC_EOBC] = 0x02F8; 943 s->regs[SONIC_RSC] = 0; 944 s->regs[SONIC_CE] = 0; 945 s->regs[SONIC_RSC] = 0; 946 947 /* Network cable is connected */ 948 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 949 950 dp8393x_update_irq(s); 951 } 952 953 static NetClientInfo net_dp83932_info = { 954 .type = NET_CLIENT_DRIVER_NIC, 955 .size = sizeof(NICState), 956 .can_receive = dp8393x_can_receive, 957 .receive = dp8393x_receive, 958 }; 959 960 static void dp8393x_instance_init(Object *obj) 961 { 962 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 963 dp8393xState *s = DP8393X(obj); 964 965 sysbus_init_mmio(sbd, &s->mmio); 966 sysbus_init_irq(sbd, &s->irq); 967 } 968 969 static void dp8393x_realize(DeviceState *dev, Error **errp) 970 { 971 dp8393xState *s = DP8393X(dev); 972 973 address_space_init(&s->as, s->dma_mr, "dp8393x"); 974 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 975 "dp8393x-regs", 0x40 << s->it_shift); 976 977 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 978 object_get_typename(OBJECT(dev)), dev->id, s); 979 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 980 981 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 982 } 983 984 static const VMStateDescription vmstate_dp8393x = { 985 .name = "dp8393x", 986 .version_id = 0, 987 .minimum_version_id = 0, 988 .fields = (VMStateField []) { 989 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 990 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 991 VMSTATE_END_OF_LIST() 992 } 993 }; 994 995 static Property dp8393x_properties[] = { 996 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 997 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 998 TYPE_MEMORY_REGION, MemoryRegion *), 999 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 1000 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 1001 DEFINE_PROP_END_OF_LIST(), 1002 }; 1003 1004 static void dp8393x_class_init(ObjectClass *klass, void *data) 1005 { 1006 DeviceClass *dc = DEVICE_CLASS(klass); 1007 1008 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1009 dc->realize = dp8393x_realize; 1010 dc->reset = dp8393x_reset; 1011 dc->vmsd = &vmstate_dp8393x; 1012 device_class_set_props(dc, dp8393x_properties); 1013 } 1014 1015 static const TypeInfo dp8393x_info = { 1016 .name = TYPE_DP8393X, 1017 .parent = TYPE_SYS_BUS_DEVICE, 1018 .instance_size = sizeof(dp8393xState), 1019 .instance_init = dp8393x_instance_init, 1020 .class_init = dp8393x_class_init, 1021 }; 1022 1023 static void dp8393x_register_types(void) 1024 { 1025 type_register_static(&dp8393x_info); 1026 } 1027 1028 type_init(dp8393x_register_types) 1029