1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "hw/sysbus.h" 21 #include "hw/devices.h" 22 #include "net/net.h" 23 #include "qemu/timer.h" 24 #include <zlib.h> 25 26 //#define DEBUG_SONIC 27 28 #define SONIC_PROM_SIZE 0x1000 29 30 #ifdef DEBUG_SONIC 31 #define DPRINTF(fmt, ...) \ 32 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 33 static const char* reg_names[] = { 34 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 35 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 36 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 37 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 38 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 39 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 40 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 41 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 42 #else 43 #define DPRINTF(fmt, ...) do {} while (0) 44 #endif 45 46 #define SONIC_ERROR(fmt, ...) \ 47 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 48 49 #define SONIC_CR 0x00 50 #define SONIC_DCR 0x01 51 #define SONIC_RCR 0x02 52 #define SONIC_TCR 0x03 53 #define SONIC_IMR 0x04 54 #define SONIC_ISR 0x05 55 #define SONIC_UTDA 0x06 56 #define SONIC_CTDA 0x07 57 #define SONIC_TPS 0x08 58 #define SONIC_TFC 0x09 59 #define SONIC_TSA0 0x0a 60 #define SONIC_TSA1 0x0b 61 #define SONIC_TFS 0x0c 62 #define SONIC_URDA 0x0d 63 #define SONIC_CRDA 0x0e 64 #define SONIC_CRBA0 0x0f 65 #define SONIC_CRBA1 0x10 66 #define SONIC_RBWC0 0x11 67 #define SONIC_RBWC1 0x12 68 #define SONIC_EOBC 0x13 69 #define SONIC_URRA 0x14 70 #define SONIC_RSA 0x15 71 #define SONIC_REA 0x16 72 #define SONIC_RRP 0x17 73 #define SONIC_RWP 0x18 74 #define SONIC_TRBA0 0x19 75 #define SONIC_TRBA1 0x1a 76 #define SONIC_LLFA 0x1f 77 #define SONIC_TTDA 0x20 78 #define SONIC_CEP 0x21 79 #define SONIC_CAP2 0x22 80 #define SONIC_CAP1 0x23 81 #define SONIC_CAP0 0x24 82 #define SONIC_CE 0x25 83 #define SONIC_CDP 0x26 84 #define SONIC_CDC 0x27 85 #define SONIC_SR 0x28 86 #define SONIC_WT0 0x29 87 #define SONIC_WT1 0x2a 88 #define SONIC_RSC 0x2b 89 #define SONIC_CRCT 0x2c 90 #define SONIC_FAET 0x2d 91 #define SONIC_MPT 0x2e 92 #define SONIC_MDT 0x2f 93 #define SONIC_DCR2 0x3f 94 95 #define SONIC_CR_HTX 0x0001 96 #define SONIC_CR_TXP 0x0002 97 #define SONIC_CR_RXDIS 0x0004 98 #define SONIC_CR_RXEN 0x0008 99 #define SONIC_CR_STP 0x0010 100 #define SONIC_CR_ST 0x0020 101 #define SONIC_CR_RST 0x0080 102 #define SONIC_CR_RRRA 0x0100 103 #define SONIC_CR_LCAM 0x0200 104 #define SONIC_CR_MASK 0x03bf 105 106 #define SONIC_DCR_DW 0x0020 107 #define SONIC_DCR_LBR 0x2000 108 #define SONIC_DCR_EXBUS 0x8000 109 110 #define SONIC_RCR_PRX 0x0001 111 #define SONIC_RCR_LBK 0x0002 112 #define SONIC_RCR_FAER 0x0004 113 #define SONIC_RCR_CRCR 0x0008 114 #define SONIC_RCR_CRS 0x0020 115 #define SONIC_RCR_LPKT 0x0040 116 #define SONIC_RCR_BC 0x0080 117 #define SONIC_RCR_MC 0x0100 118 #define SONIC_RCR_LB0 0x0200 119 #define SONIC_RCR_LB1 0x0400 120 #define SONIC_RCR_AMC 0x0800 121 #define SONIC_RCR_PRO 0x1000 122 #define SONIC_RCR_BRD 0x2000 123 #define SONIC_RCR_RNT 0x4000 124 125 #define SONIC_TCR_PTX 0x0001 126 #define SONIC_TCR_BCM 0x0002 127 #define SONIC_TCR_FU 0x0004 128 #define SONIC_TCR_EXC 0x0040 129 #define SONIC_TCR_CRSL 0x0080 130 #define SONIC_TCR_NCRS 0x0100 131 #define SONIC_TCR_EXD 0x0400 132 #define SONIC_TCR_CRCI 0x2000 133 #define SONIC_TCR_PINT 0x8000 134 135 #define SONIC_ISR_RBE 0x0020 136 #define SONIC_ISR_RDE 0x0040 137 #define SONIC_ISR_TC 0x0080 138 #define SONIC_ISR_TXDN 0x0200 139 #define SONIC_ISR_PKTRX 0x0400 140 #define SONIC_ISR_PINT 0x0800 141 #define SONIC_ISR_LCD 0x1000 142 143 #define TYPE_DP8393X "dp8393x" 144 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 145 146 typedef struct dp8393xState { 147 SysBusDevice parent_obj; 148 149 /* Hardware */ 150 uint8_t it_shift; 151 qemu_irq irq; 152 #ifdef DEBUG_SONIC 153 int irq_level; 154 #endif 155 QEMUTimer *watchdog; 156 int64_t wt_last_update; 157 NICConf conf; 158 NICState *nic; 159 MemoryRegion mmio; 160 MemoryRegion prom; 161 162 /* Registers */ 163 uint8_t cam[16][6]; 164 uint16_t regs[0x40]; 165 166 /* Temporaries */ 167 uint8_t tx_buffer[0x10000]; 168 int loopback_packet; 169 170 /* Memory access */ 171 void *dma_mr; 172 AddressSpace as; 173 } dp8393xState; 174 175 static void dp8393x_update_irq(dp8393xState *s) 176 { 177 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 178 179 #ifdef DEBUG_SONIC 180 if (level != s->irq_level) { 181 s->irq_level = level; 182 if (level) { 183 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 184 } else { 185 DPRINTF("lower irq\n"); 186 } 187 } 188 #endif 189 190 qemu_set_irq(s->irq, level); 191 } 192 193 static void dp8393x_do_load_cam(dp8393xState *s) 194 { 195 uint16_t data[8]; 196 int width, size; 197 uint16_t index = 0; 198 199 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 200 size = sizeof(uint16_t) * 4 * width; 201 202 while (s->regs[SONIC_CDC] & 0x1f) { 203 /* Fill current entry */ 204 address_space_rw(&s->as, 205 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP], 206 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 207 s->cam[index][0] = data[1 * width] & 0xff; 208 s->cam[index][1] = data[1 * width] >> 8; 209 s->cam[index][2] = data[2 * width] & 0xff; 210 s->cam[index][3] = data[2 * width] >> 8; 211 s->cam[index][4] = data[3 * width] & 0xff; 212 s->cam[index][5] = data[3 * width] >> 8; 213 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 214 s->cam[index][0], s->cam[index][1], s->cam[index][2], 215 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 216 /* Move to next entry */ 217 s->regs[SONIC_CDC]--; 218 s->regs[SONIC_CDP] += size; 219 index++; 220 } 221 222 /* Read CAM enable */ 223 address_space_rw(&s->as, 224 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP], 225 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 226 s->regs[SONIC_CE] = data[0 * width]; 227 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 228 229 /* Done */ 230 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 231 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 232 dp8393x_update_irq(s); 233 } 234 235 static void dp8393x_do_read_rra(dp8393xState *s) 236 { 237 uint16_t data[8]; 238 int width, size; 239 240 /* Read memory */ 241 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 242 size = sizeof(uint16_t) * 4 * width; 243 address_space_rw(&s->as, 244 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP], 245 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 246 247 /* Update SONIC registers */ 248 s->regs[SONIC_CRBA0] = data[0 * width]; 249 s->regs[SONIC_CRBA1] = data[1 * width]; 250 s->regs[SONIC_RBWC0] = data[2 * width]; 251 s->regs[SONIC_RBWC1] = data[3 * width]; 252 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 253 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 254 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 255 256 /* Go to next entry */ 257 s->regs[SONIC_RRP] += size; 258 259 /* Handle wrap */ 260 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 261 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 262 } 263 264 /* Check resource exhaustion */ 265 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 266 { 267 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 268 dp8393x_update_irq(s); 269 } 270 271 /* Done */ 272 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 273 } 274 275 static void dp8393x_do_software_reset(dp8393xState *s) 276 { 277 timer_del(s->watchdog); 278 279 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 280 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 281 } 282 283 static void dp8393x_set_next_tick(dp8393xState *s) 284 { 285 uint32_t ticks; 286 int64_t delay; 287 288 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 289 timer_del(s->watchdog); 290 return; 291 } 292 293 ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 294 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 295 delay = get_ticks_per_sec() * ticks / 5000000; 296 timer_mod(s->watchdog, s->wt_last_update + delay); 297 } 298 299 static void dp8393x_update_wt_regs(dp8393xState *s) 300 { 301 int64_t elapsed; 302 uint32_t val; 303 304 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 305 timer_del(s->watchdog); 306 return; 307 } 308 309 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 310 val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 311 val -= elapsed / 5000000; 312 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 313 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 314 dp8393x_set_next_tick(s); 315 316 } 317 318 static void dp8393x_do_start_timer(dp8393xState *s) 319 { 320 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 321 dp8393x_set_next_tick(s); 322 } 323 324 static void dp8393x_do_stop_timer(dp8393xState *s) 325 { 326 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 327 dp8393x_update_wt_regs(s); 328 } 329 330 static int dp8393x_can_receive(NetClientState *nc); 331 332 static void dp8393x_do_receiver_enable(dp8393xState *s) 333 { 334 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 335 if (dp8393x_can_receive(s->nic->ncs)) { 336 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 337 } 338 } 339 340 static void dp8393x_do_receiver_disable(dp8393xState *s) 341 { 342 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 343 } 344 345 static void dp8393x_do_transmit_packets(dp8393xState *s) 346 { 347 NetClientState *nc = qemu_get_queue(s->nic); 348 uint16_t data[12]; 349 int width, size; 350 int tx_len, len; 351 uint16_t i; 352 353 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 354 355 while (1) { 356 /* Read memory */ 357 DPRINTF("Transmit packet at %08x\n", 358 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_CTDA]); 359 size = sizeof(uint16_t) * 6 * width; 360 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 361 address_space_rw(&s->as, 362 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * width, 363 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 364 tx_len = 0; 365 366 /* Update registers */ 367 s->regs[SONIC_TCR] = data[0 * width] & 0xf000; 368 s->regs[SONIC_TPS] = data[1 * width]; 369 s->regs[SONIC_TFC] = data[2 * width]; 370 s->regs[SONIC_TSA0] = data[3 * width]; 371 s->regs[SONIC_TSA1] = data[4 * width]; 372 s->regs[SONIC_TFS] = data[5 * width]; 373 374 /* Handle programmable interrupt */ 375 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 376 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 377 } else { 378 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 379 } 380 381 for (i = 0; i < s->regs[SONIC_TFC]; ) { 382 /* Append fragment */ 383 len = s->regs[SONIC_TFS]; 384 if (tx_len + len > sizeof(s->tx_buffer)) { 385 len = sizeof(s->tx_buffer) - tx_len; 386 } 387 address_space_rw(&s->as, 388 (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0], 389 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0); 390 tx_len += len; 391 392 i++; 393 if (i != s->regs[SONIC_TFC]) { 394 /* Read next fragment details */ 395 size = sizeof(uint16_t) * 3 * width; 396 address_space_rw(&s->as, 397 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * i) * width, 398 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 399 s->regs[SONIC_TSA0] = data[0 * width]; 400 s->regs[SONIC_TSA1] = data[1 * width]; 401 s->regs[SONIC_TFS] = data[2 * width]; 402 } 403 } 404 405 /* Handle Ethernet checksum */ 406 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 407 /* Don't append FCS there, to look like slirp packets 408 * which don't have one */ 409 } else { 410 /* Remove existing FCS */ 411 tx_len -= 4; 412 } 413 414 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 415 /* Loopback */ 416 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 417 if (nc->info->can_receive(nc)) { 418 s->loopback_packet = 1; 419 nc->info->receive(nc, s->tx_buffer, tx_len); 420 } 421 } else { 422 /* Transmit packet */ 423 qemu_send_packet(nc, s->tx_buffer, tx_len); 424 } 425 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 426 427 /* Write status */ 428 data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */ 429 size = sizeof(uint16_t) * width; 430 address_space_rw(&s->as, 431 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA], 432 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 433 434 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 435 /* Read footer of packet */ 436 size = sizeof(uint16_t) * width; 437 address_space_rw(&s->as, 438 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, 439 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 440 s->regs[SONIC_CTDA] = data[0 * width] & ~0x1; 441 if (data[0 * width] & 0x1) { 442 /* EOL detected */ 443 break; 444 } 445 } 446 } 447 448 /* Done */ 449 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 450 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 451 dp8393x_update_irq(s); 452 } 453 454 static void dp8393x_do_halt_transmission(dp8393xState *s) 455 { 456 /* Nothing to do */ 457 } 458 459 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 460 { 461 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 462 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 463 return; 464 } 465 466 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 467 468 if (command & SONIC_CR_HTX) 469 dp8393x_do_halt_transmission(s); 470 if (command & SONIC_CR_TXP) 471 dp8393x_do_transmit_packets(s); 472 if (command & SONIC_CR_RXDIS) 473 dp8393x_do_receiver_disable(s); 474 if (command & SONIC_CR_RXEN) 475 dp8393x_do_receiver_enable(s); 476 if (command & SONIC_CR_STP) 477 dp8393x_do_stop_timer(s); 478 if (command & SONIC_CR_ST) 479 dp8393x_do_start_timer(s); 480 if (command & SONIC_CR_RST) 481 dp8393x_do_software_reset(s); 482 if (command & SONIC_CR_RRRA) 483 dp8393x_do_read_rra(s); 484 if (command & SONIC_CR_LCAM) 485 dp8393x_do_load_cam(s); 486 } 487 488 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 489 { 490 dp8393xState *s = opaque; 491 int reg = addr >> s->it_shift; 492 uint16_t val = 0; 493 494 switch (reg) { 495 /* Update data before reading it */ 496 case SONIC_WT0: 497 case SONIC_WT1: 498 dp8393x_update_wt_regs(s); 499 val = s->regs[reg]; 500 break; 501 /* Accept read to some registers only when in reset mode */ 502 case SONIC_CAP2: 503 case SONIC_CAP1: 504 case SONIC_CAP0: 505 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 506 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 507 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 508 } 509 break; 510 /* All other registers have no special contrainst */ 511 default: 512 val = s->regs[reg]; 513 } 514 515 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 516 517 return val; 518 } 519 520 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 521 unsigned int size) 522 { 523 dp8393xState *s = opaque; 524 int reg = addr >> s->it_shift; 525 526 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); 527 528 switch (reg) { 529 /* Command register */ 530 case SONIC_CR: 531 dp8393x_do_command(s, data); 532 break; 533 /* Prevent write to read-only registers */ 534 case SONIC_CAP2: 535 case SONIC_CAP1: 536 case SONIC_CAP0: 537 case SONIC_SR: 538 case SONIC_MDT: 539 DPRINTF("writing to reg %d invalid\n", reg); 540 break; 541 /* Accept write to some registers only when in reset mode */ 542 case SONIC_DCR: 543 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 544 s->regs[reg] = data & 0xbfff; 545 } else { 546 DPRINTF("writing to DCR invalid\n"); 547 } 548 break; 549 case SONIC_DCR2: 550 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 551 s->regs[reg] = data & 0xf017; 552 } else { 553 DPRINTF("writing to DCR2 invalid\n"); 554 } 555 break; 556 /* 12 lower bytes are Read Only */ 557 case SONIC_TCR: 558 s->regs[reg] = data & 0xf000; 559 break; 560 /* 9 lower bytes are Read Only */ 561 case SONIC_RCR: 562 s->regs[reg] = data & 0xffe0; 563 break; 564 /* Ignore most significant bit */ 565 case SONIC_IMR: 566 s->regs[reg] = data & 0x7fff; 567 dp8393x_update_irq(s); 568 break; 569 /* Clear bits by writing 1 to them */ 570 case SONIC_ISR: 571 data &= s->regs[reg]; 572 s->regs[reg] &= ~data; 573 if (data & SONIC_ISR_RBE) { 574 dp8393x_do_read_rra(s); 575 } 576 dp8393x_update_irq(s); 577 if (dp8393x_can_receive(s->nic->ncs)) { 578 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 579 } 580 break; 581 /* Ignore least significant bit */ 582 case SONIC_RSA: 583 case SONIC_REA: 584 case SONIC_RRP: 585 case SONIC_RWP: 586 s->regs[reg] = data & 0xfffe; 587 break; 588 /* Invert written value for some registers */ 589 case SONIC_CRCT: 590 case SONIC_FAET: 591 case SONIC_MPT: 592 s->regs[reg] = data ^ 0xffff; 593 break; 594 /* All other registers have no special contrainst */ 595 default: 596 s->regs[reg] = data; 597 } 598 599 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 600 dp8393x_set_next_tick(s); 601 } 602 } 603 604 static const MemoryRegionOps dp8393x_ops = { 605 .read = dp8393x_read, 606 .write = dp8393x_write, 607 .impl.min_access_size = 2, 608 .impl.max_access_size = 2, 609 .endianness = DEVICE_NATIVE_ENDIAN, 610 }; 611 612 static void dp8393x_watchdog(void *opaque) 613 { 614 dp8393xState *s = opaque; 615 616 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 617 return; 618 } 619 620 s->regs[SONIC_WT1] = 0xffff; 621 s->regs[SONIC_WT0] = 0xffff; 622 dp8393x_set_next_tick(s); 623 624 /* Signal underflow */ 625 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 626 dp8393x_update_irq(s); 627 } 628 629 static int dp8393x_can_receive(NetClientState *nc) 630 { 631 dp8393xState *s = qemu_get_nic_opaque(nc); 632 633 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 634 return 0; 635 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 636 return 0; 637 return 1; 638 } 639 640 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 641 int size) 642 { 643 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 644 int i; 645 646 /* Check promiscuous mode */ 647 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 648 return 0; 649 } 650 651 /* Check multicast packets */ 652 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 653 return SONIC_RCR_MC; 654 } 655 656 /* Check broadcast */ 657 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 658 return SONIC_RCR_BC; 659 } 660 661 /* Check CAM */ 662 for (i = 0; i < 16; i++) { 663 if (s->regs[SONIC_CE] & (1 << i)) { 664 /* Entry enabled */ 665 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 666 return 0; 667 } 668 } 669 } 670 671 return -1; 672 } 673 674 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 675 size_t size) 676 { 677 dp8393xState *s = qemu_get_nic_opaque(nc); 678 uint16_t data[10]; 679 int packet_type; 680 uint32_t available, address; 681 int width, rx_len = size; 682 uint32_t checksum; 683 684 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 685 686 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 687 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 688 689 packet_type = dp8393x_receive_filter(s, buf, size); 690 if (packet_type < 0) { 691 DPRINTF("packet not for netcard\n"); 692 return -1; 693 } 694 695 /* XXX: Check byte ordering */ 696 697 /* Check for EOL */ 698 if (s->regs[SONIC_LLFA] & 0x1) { 699 /* Are we still in resource exhaustion? */ 700 size = sizeof(uint16_t) * 1 * width; 701 address = ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width; 702 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 703 (uint8_t *)data, size, 0); 704 if (data[0 * width] & 0x1) { 705 /* Still EOL ; stop reception */ 706 return -1; 707 } else { 708 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 709 } 710 } 711 712 /* Save current position */ 713 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 714 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 715 716 /* Calculate the ethernet checksum */ 717 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 718 719 /* Put packet into RBA */ 720 DPRINTF("Receive packet at %08x\n", (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]); 721 address = (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 722 address_space_rw(&s->as, address, 723 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1); 724 address += rx_len; 725 address_space_rw(&s->as, address, 726 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); 727 rx_len += 4; 728 s->regs[SONIC_CRBA1] = address >> 16; 729 s->regs[SONIC_CRBA0] = address & 0xffff; 730 available = (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 731 available -= rx_len / 2; 732 s->regs[SONIC_RBWC1] = available >> 16; 733 s->regs[SONIC_RBWC0] = available & 0xffff; 734 735 /* Update status */ 736 if (((s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]) < s->regs[SONIC_EOBC]) { 737 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 738 } 739 s->regs[SONIC_RCR] |= packet_type; 740 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 741 if (s->loopback_packet) { 742 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 743 s->loopback_packet = 0; 744 } 745 746 /* Write status to memory */ 747 DPRINTF("Write status at %08x\n", (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]); 748 data[0 * width] = s->regs[SONIC_RCR]; /* status */ 749 data[1 * width] = rx_len; /* byte count */ 750 data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */ 751 data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */ 752 data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */ 753 size = sizeof(uint16_t) * 5 * width; 754 address_space_rw(&s->as, (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA], 755 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 756 757 /* Move to next descriptor */ 758 size = sizeof(uint16_t) * width; 759 address_space_rw(&s->as, 760 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width, 761 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 762 s->regs[SONIC_LLFA] = data[0 * width]; 763 if (s->regs[SONIC_LLFA] & 0x1) { 764 /* EOL detected */ 765 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 766 } else { 767 data[0 * width] = 0; /* in_use */ 768 address_space_rw(&s->as, 769 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 6 * width, 770 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1); 771 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 772 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 773 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 774 775 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 776 /* Read next RRA */ 777 dp8393x_do_read_rra(s); 778 } 779 } 780 781 /* Done */ 782 dp8393x_update_irq(s); 783 784 return size; 785 } 786 787 static void dp8393x_reset(DeviceState *dev) 788 { 789 dp8393xState *s = DP8393X(dev); 790 timer_del(s->watchdog); 791 792 memset(s->regs, 0, sizeof(s->regs)); 793 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 794 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 795 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 796 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 797 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 798 s->regs[SONIC_IMR] = 0; 799 s->regs[SONIC_ISR] = 0; 800 s->regs[SONIC_DCR2] = 0; 801 s->regs[SONIC_EOBC] = 0x02F8; 802 s->regs[SONIC_RSC] = 0; 803 s->regs[SONIC_CE] = 0; 804 s->regs[SONIC_RSC] = 0; 805 806 /* Network cable is connected */ 807 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 808 809 dp8393x_update_irq(s); 810 } 811 812 static NetClientInfo net_dp83932_info = { 813 .type = NET_CLIENT_OPTIONS_KIND_NIC, 814 .size = sizeof(NICState), 815 .can_receive = dp8393x_can_receive, 816 .receive = dp8393x_receive, 817 }; 818 819 static void dp8393x_instance_init(Object *obj) 820 { 821 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 822 dp8393xState *s = DP8393X(obj); 823 824 sysbus_init_mmio(sbd, &s->mmio); 825 sysbus_init_mmio(sbd, &s->prom); 826 sysbus_init_irq(sbd, &s->irq); 827 } 828 829 static void dp8393x_realize(DeviceState *dev, Error **errp) 830 { 831 dp8393xState *s = DP8393X(dev); 832 int i, checksum; 833 uint8_t *prom; 834 Error *local_err = NULL; 835 836 address_space_init(&s->as, s->dma_mr, "dp8393x"); 837 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 838 "dp8393x-regs", 0x40 << s->it_shift); 839 840 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 841 object_get_typename(OBJECT(dev)), dev->id, s); 842 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 843 844 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 845 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 846 847 memory_region_init_ram(&s->prom, OBJECT(dev), 848 "dp8393x-prom", SONIC_PROM_SIZE, &local_err); 849 if (local_err) { 850 error_propagate(errp, local_err); 851 return; 852 } 853 memory_region_set_readonly(&s->prom, true); 854 prom = memory_region_get_ram_ptr(&s->prom); 855 checksum = 0; 856 for (i = 0; i < 6; i++) { 857 prom[i] = s->conf.macaddr.a[i]; 858 checksum += prom[i]; 859 if (checksum > 0xff) { 860 checksum = (checksum + 1) & 0xff; 861 } 862 } 863 prom[7] = 0xff - checksum; 864 } 865 866 static const VMStateDescription vmstate_dp8393x = { 867 .name = "dp8393x", 868 .version_id = 0, 869 .minimum_version_id = 0, 870 .fields = (VMStateField []) { 871 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 872 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 873 VMSTATE_END_OF_LIST() 874 } 875 }; 876 877 static Property dp8393x_properties[] = { 878 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 879 DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), 880 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 881 DEFINE_PROP_END_OF_LIST(), 882 }; 883 884 static void dp8393x_class_init(ObjectClass *klass, void *data) 885 { 886 DeviceClass *dc = DEVICE_CLASS(klass); 887 888 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 889 dc->realize = dp8393x_realize; 890 dc->reset = dp8393x_reset; 891 dc->vmsd = &vmstate_dp8393x; 892 dc->props = dp8393x_properties; 893 /* Reason: dma_mr property can't be set */ 894 dc->cannot_instantiate_with_device_add_yet = true; 895 } 896 897 static const TypeInfo dp8393x_info = { 898 .name = TYPE_DP8393X, 899 .parent = TYPE_SYS_BUS_DEVICE, 900 .instance_size = sizeof(dp8393xState), 901 .instance_init = dp8393x_instance_init, 902 .class_init = dp8393x_class_init, 903 }; 904 905 static void dp8393x_register_types(void) 906 { 907 type_register_static(&dp8393x_info); 908 } 909 910 type_init(dp8393x_register_types) 911