1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 #include "qom/object.h" 31 32 //#define DEBUG_SONIC 33 34 #define SONIC_PROM_SIZE 0x1000 35 36 #ifdef DEBUG_SONIC 37 #define DPRINTF(fmt, ...) \ 38 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 39 static const char* reg_names[] = { 40 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 41 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 42 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 43 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 44 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 45 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 46 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 47 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 48 #else 49 #define DPRINTF(fmt, ...) do {} while (0) 50 #endif 51 52 #define SONIC_ERROR(fmt, ...) \ 53 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 54 55 #define SONIC_CR 0x00 56 #define SONIC_DCR 0x01 57 #define SONIC_RCR 0x02 58 #define SONIC_TCR 0x03 59 #define SONIC_IMR 0x04 60 #define SONIC_ISR 0x05 61 #define SONIC_UTDA 0x06 62 #define SONIC_CTDA 0x07 63 #define SONIC_TPS 0x08 64 #define SONIC_TFC 0x09 65 #define SONIC_TSA0 0x0a 66 #define SONIC_TSA1 0x0b 67 #define SONIC_TFS 0x0c 68 #define SONIC_URDA 0x0d 69 #define SONIC_CRDA 0x0e 70 #define SONIC_CRBA0 0x0f 71 #define SONIC_CRBA1 0x10 72 #define SONIC_RBWC0 0x11 73 #define SONIC_RBWC1 0x12 74 #define SONIC_EOBC 0x13 75 #define SONIC_URRA 0x14 76 #define SONIC_RSA 0x15 77 #define SONIC_REA 0x16 78 #define SONIC_RRP 0x17 79 #define SONIC_RWP 0x18 80 #define SONIC_TRBA0 0x19 81 #define SONIC_TRBA1 0x1a 82 #define SONIC_LLFA 0x1f 83 #define SONIC_TTDA 0x20 84 #define SONIC_CEP 0x21 85 #define SONIC_CAP2 0x22 86 #define SONIC_CAP1 0x23 87 #define SONIC_CAP0 0x24 88 #define SONIC_CE 0x25 89 #define SONIC_CDP 0x26 90 #define SONIC_CDC 0x27 91 #define SONIC_SR 0x28 92 #define SONIC_WT0 0x29 93 #define SONIC_WT1 0x2a 94 #define SONIC_RSC 0x2b 95 #define SONIC_CRCT 0x2c 96 #define SONIC_FAET 0x2d 97 #define SONIC_MPT 0x2e 98 #define SONIC_MDT 0x2f 99 #define SONIC_DCR2 0x3f 100 101 #define SONIC_CR_HTX 0x0001 102 #define SONIC_CR_TXP 0x0002 103 #define SONIC_CR_RXDIS 0x0004 104 #define SONIC_CR_RXEN 0x0008 105 #define SONIC_CR_STP 0x0010 106 #define SONIC_CR_ST 0x0020 107 #define SONIC_CR_RST 0x0080 108 #define SONIC_CR_RRRA 0x0100 109 #define SONIC_CR_LCAM 0x0200 110 #define SONIC_CR_MASK 0x03bf 111 112 #define SONIC_DCR_DW 0x0020 113 #define SONIC_DCR_LBR 0x2000 114 #define SONIC_DCR_EXBUS 0x8000 115 116 #define SONIC_RCR_PRX 0x0001 117 #define SONIC_RCR_LBK 0x0002 118 #define SONIC_RCR_FAER 0x0004 119 #define SONIC_RCR_CRCR 0x0008 120 #define SONIC_RCR_CRS 0x0020 121 #define SONIC_RCR_LPKT 0x0040 122 #define SONIC_RCR_BC 0x0080 123 #define SONIC_RCR_MC 0x0100 124 #define SONIC_RCR_LB0 0x0200 125 #define SONIC_RCR_LB1 0x0400 126 #define SONIC_RCR_AMC 0x0800 127 #define SONIC_RCR_PRO 0x1000 128 #define SONIC_RCR_BRD 0x2000 129 #define SONIC_RCR_RNT 0x4000 130 131 #define SONIC_TCR_PTX 0x0001 132 #define SONIC_TCR_BCM 0x0002 133 #define SONIC_TCR_FU 0x0004 134 #define SONIC_TCR_EXC 0x0040 135 #define SONIC_TCR_CRSL 0x0080 136 #define SONIC_TCR_NCRS 0x0100 137 #define SONIC_TCR_EXD 0x0400 138 #define SONIC_TCR_CRCI 0x2000 139 #define SONIC_TCR_PINT 0x8000 140 141 #define SONIC_ISR_RBAE 0x0010 142 #define SONIC_ISR_RBE 0x0020 143 #define SONIC_ISR_RDE 0x0040 144 #define SONIC_ISR_TC 0x0080 145 #define SONIC_ISR_TXDN 0x0200 146 #define SONIC_ISR_PKTRX 0x0400 147 #define SONIC_ISR_PINT 0x0800 148 #define SONIC_ISR_LCD 0x1000 149 150 #define SONIC_DESC_EOL 0x0001 151 #define SONIC_DESC_ADDR 0xFFFE 152 153 #define TYPE_DP8393X "dp8393x" 154 OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X) 155 156 struct dp8393xState { 157 SysBusDevice parent_obj; 158 159 /* Hardware */ 160 uint8_t it_shift; 161 bool big_endian; 162 bool last_rba_is_full; 163 qemu_irq irq; 164 #ifdef DEBUG_SONIC 165 int irq_level; 166 #endif 167 QEMUTimer *watchdog; 168 int64_t wt_last_update; 169 NICConf conf; 170 NICState *nic; 171 MemoryRegion mmio; 172 MemoryRegion prom; 173 174 /* Registers */ 175 uint8_t cam[16][6]; 176 uint16_t regs[0x40]; 177 178 /* Temporaries */ 179 uint8_t tx_buffer[0x10000]; 180 uint16_t data[12]; 181 int loopback_packet; 182 183 /* Memory access */ 184 MemoryRegion *dma_mr; 185 AddressSpace as; 186 }; 187 188 /* Accessor functions for values which are formed by 189 * concatenating two 16 bit device registers. By putting these 190 * in their own functions with a uint32_t return type we avoid the 191 * pitfall of implicit sign extension where ((x << 16) | y) is a 192 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 193 */ 194 static uint32_t dp8393x_cdp(dp8393xState *s) 195 { 196 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 197 } 198 199 static uint32_t dp8393x_crba(dp8393xState *s) 200 { 201 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 202 } 203 204 static uint32_t dp8393x_crda(dp8393xState *s) 205 { 206 return (s->regs[SONIC_URDA] << 16) | 207 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); 208 } 209 210 static uint32_t dp8393x_rbwc(dp8393xState *s) 211 { 212 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 213 } 214 215 static uint32_t dp8393x_rrp(dp8393xState *s) 216 { 217 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 218 } 219 220 static uint32_t dp8393x_tsa(dp8393xState *s) 221 { 222 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 223 } 224 225 static uint32_t dp8393x_ttda(dp8393xState *s) 226 { 227 return (s->regs[SONIC_UTDA] << 16) | 228 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); 229 } 230 231 static uint32_t dp8393x_wt(dp8393xState *s) 232 { 233 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 234 } 235 236 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 237 { 238 uint16_t val; 239 240 if (s->big_endian) { 241 val = be16_to_cpu(s->data[offset * width + width - 1]); 242 } else { 243 val = le16_to_cpu(s->data[offset * width]); 244 } 245 return val; 246 } 247 248 static void dp8393x_put(dp8393xState *s, int width, int offset, 249 uint16_t val) 250 { 251 if (s->big_endian) { 252 if (width == 2) { 253 s->data[offset * 2] = 0; 254 s->data[offset * 2 + 1] = cpu_to_be16(val); 255 } else { 256 s->data[offset] = cpu_to_be16(val); 257 } 258 } else { 259 if (width == 2) { 260 s->data[offset * 2] = cpu_to_le16(val); 261 s->data[offset * 2 + 1] = 0; 262 } else { 263 s->data[offset] = cpu_to_le16(val); 264 } 265 } 266 } 267 268 static void dp8393x_update_irq(dp8393xState *s) 269 { 270 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 271 272 #ifdef DEBUG_SONIC 273 if (level != s->irq_level) { 274 s->irq_level = level; 275 if (level) { 276 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 277 } else { 278 DPRINTF("lower irq\n"); 279 } 280 } 281 #endif 282 283 qemu_set_irq(s->irq, level); 284 } 285 286 static void dp8393x_do_load_cam(dp8393xState *s) 287 { 288 int width, size; 289 uint16_t index = 0; 290 291 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 292 size = sizeof(uint16_t) * 4 * width; 293 294 while (s->regs[SONIC_CDC] & 0x1f) { 295 /* Fill current entry */ 296 address_space_read(&s->as, dp8393x_cdp(s), 297 MEMTXATTRS_UNSPECIFIED, s->data, size); 298 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 299 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 300 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 301 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 302 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 303 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 304 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 305 s->cam[index][0], s->cam[index][1], s->cam[index][2], 306 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 307 /* Move to next entry */ 308 s->regs[SONIC_CDC]--; 309 s->regs[SONIC_CDP] += size; 310 index++; 311 } 312 313 /* Read CAM enable */ 314 address_space_read(&s->as, dp8393x_cdp(s), 315 MEMTXATTRS_UNSPECIFIED, s->data, size); 316 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 317 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 318 319 /* Done */ 320 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 321 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 322 dp8393x_update_irq(s); 323 } 324 325 static void dp8393x_do_read_rra(dp8393xState *s) 326 { 327 int width, size; 328 329 /* Read memory */ 330 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 331 size = sizeof(uint16_t) * 4 * width; 332 address_space_read(&s->as, dp8393x_rrp(s), 333 MEMTXATTRS_UNSPECIFIED, s->data, size); 334 335 /* Update SONIC registers */ 336 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 337 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 338 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 339 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 340 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 341 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 342 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 343 344 /* Go to next entry */ 345 s->regs[SONIC_RRP] += size; 346 347 /* Handle wrap */ 348 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 349 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 350 } 351 352 /* Warn the host if CRBA now has the last available resource */ 353 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 354 { 355 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 356 dp8393x_update_irq(s); 357 } 358 359 /* Allow packet reception */ 360 s->last_rba_is_full = false; 361 } 362 363 static void dp8393x_do_software_reset(dp8393xState *s) 364 { 365 timer_del(s->watchdog); 366 367 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 368 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 369 } 370 371 static void dp8393x_set_next_tick(dp8393xState *s) 372 { 373 uint32_t ticks; 374 int64_t delay; 375 376 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 377 timer_del(s->watchdog); 378 return; 379 } 380 381 ticks = dp8393x_wt(s); 382 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 383 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 384 timer_mod(s->watchdog, s->wt_last_update + delay); 385 } 386 387 static void dp8393x_update_wt_regs(dp8393xState *s) 388 { 389 int64_t elapsed; 390 uint32_t val; 391 392 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 393 timer_del(s->watchdog); 394 return; 395 } 396 397 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 398 val = dp8393x_wt(s); 399 val -= elapsed / 5000000; 400 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 401 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 402 dp8393x_set_next_tick(s); 403 404 } 405 406 static void dp8393x_do_start_timer(dp8393xState *s) 407 { 408 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 409 dp8393x_set_next_tick(s); 410 } 411 412 static void dp8393x_do_stop_timer(dp8393xState *s) 413 { 414 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 415 dp8393x_update_wt_regs(s); 416 } 417 418 static bool dp8393x_can_receive(NetClientState *nc); 419 420 static void dp8393x_do_receiver_enable(dp8393xState *s) 421 { 422 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 423 if (dp8393x_can_receive(s->nic->ncs)) { 424 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 425 } 426 } 427 428 static void dp8393x_do_receiver_disable(dp8393xState *s) 429 { 430 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 431 } 432 433 static void dp8393x_do_transmit_packets(dp8393xState *s) 434 { 435 NetClientState *nc = qemu_get_queue(s->nic); 436 int width, size; 437 int tx_len, len; 438 uint16_t i; 439 440 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 441 442 while (1) { 443 /* Read memory */ 444 size = sizeof(uint16_t) * 6 * width; 445 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 446 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 447 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 448 MEMTXATTRS_UNSPECIFIED, s->data, size); 449 tx_len = 0; 450 451 /* Update registers */ 452 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 453 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 454 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 455 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 456 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 457 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 458 459 /* Handle programmable interrupt */ 460 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 461 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 462 } else { 463 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 464 } 465 466 for (i = 0; i < s->regs[SONIC_TFC]; ) { 467 /* Append fragment */ 468 len = s->regs[SONIC_TFS]; 469 if (tx_len + len > sizeof(s->tx_buffer)) { 470 len = sizeof(s->tx_buffer) - tx_len; 471 } 472 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 473 &s->tx_buffer[tx_len], len); 474 tx_len += len; 475 476 i++; 477 if (i != s->regs[SONIC_TFC]) { 478 /* Read next fragment details */ 479 size = sizeof(uint16_t) * 3 * width; 480 address_space_read(&s->as, 481 dp8393x_ttda(s) 482 + sizeof(uint16_t) * width * (4 + 3 * i), 483 MEMTXATTRS_UNSPECIFIED, s->data, 484 size); 485 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 486 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 487 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 488 } 489 } 490 491 /* Handle Ethernet checksum */ 492 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 493 /* Don't append FCS there, to look like slirp packets 494 * which don't have one */ 495 } else { 496 /* Remove existing FCS */ 497 tx_len -= 4; 498 if (tx_len < 0) { 499 SONIC_ERROR("tx_len is %d\n", tx_len); 500 break; 501 } 502 } 503 504 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 505 /* Loopback */ 506 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 507 if (nc->info->can_receive(nc)) { 508 s->loopback_packet = 1; 509 qemu_receive_packet(nc, s->tx_buffer, tx_len); 510 } 511 } else { 512 /* Transmit packet */ 513 qemu_send_packet(nc, s->tx_buffer, tx_len); 514 } 515 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 516 517 /* Write status */ 518 dp8393x_put(s, width, 0, 519 s->regs[SONIC_TCR] & 0x0fff); /* status */ 520 size = sizeof(uint16_t) * width; 521 address_space_write(&s->as, dp8393x_ttda(s), 522 MEMTXATTRS_UNSPECIFIED, s->data, size); 523 524 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 525 /* Read footer of packet */ 526 size = sizeof(uint16_t) * width; 527 address_space_read(&s->as, 528 dp8393x_ttda(s) 529 + sizeof(uint16_t) * width 530 * (4 + 3 * s->regs[SONIC_TFC]), 531 MEMTXATTRS_UNSPECIFIED, s->data, 532 size); 533 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0); 534 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) { 535 /* EOL detected */ 536 break; 537 } 538 } 539 } 540 541 /* Done */ 542 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 543 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 544 dp8393x_update_irq(s); 545 } 546 547 static void dp8393x_do_halt_transmission(dp8393xState *s) 548 { 549 /* Nothing to do */ 550 } 551 552 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 553 { 554 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 555 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 556 return; 557 } 558 559 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 560 561 if (command & SONIC_CR_HTX) 562 dp8393x_do_halt_transmission(s); 563 if (command & SONIC_CR_TXP) 564 dp8393x_do_transmit_packets(s); 565 if (command & SONIC_CR_RXDIS) 566 dp8393x_do_receiver_disable(s); 567 if (command & SONIC_CR_RXEN) 568 dp8393x_do_receiver_enable(s); 569 if (command & SONIC_CR_STP) 570 dp8393x_do_stop_timer(s); 571 if (command & SONIC_CR_ST) 572 dp8393x_do_start_timer(s); 573 if (command & SONIC_CR_RST) 574 dp8393x_do_software_reset(s); 575 if (command & SONIC_CR_RRRA) { 576 dp8393x_do_read_rra(s); 577 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 578 } 579 if (command & SONIC_CR_LCAM) 580 dp8393x_do_load_cam(s); 581 } 582 583 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 584 { 585 dp8393xState *s = opaque; 586 int reg = addr >> s->it_shift; 587 uint16_t val = 0; 588 589 switch (reg) { 590 /* Update data before reading it */ 591 case SONIC_WT0: 592 case SONIC_WT1: 593 dp8393x_update_wt_regs(s); 594 val = s->regs[reg]; 595 break; 596 /* Accept read to some registers only when in reset mode */ 597 case SONIC_CAP2: 598 case SONIC_CAP1: 599 case SONIC_CAP0: 600 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 601 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 602 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 603 } 604 break; 605 /* All other registers have no special contrainst */ 606 default: 607 val = s->regs[reg]; 608 } 609 610 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 611 612 return s->big_endian ? val << 16 : val; 613 } 614 615 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 616 unsigned int size) 617 { 618 dp8393xState *s = opaque; 619 int reg = addr >> s->it_shift; 620 uint32_t val = s->big_endian ? data >> 16 : data; 621 622 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); 623 624 switch (reg) { 625 /* Command register */ 626 case SONIC_CR: 627 dp8393x_do_command(s, val); 628 break; 629 /* Prevent write to read-only registers */ 630 case SONIC_CAP2: 631 case SONIC_CAP1: 632 case SONIC_CAP0: 633 case SONIC_SR: 634 case SONIC_MDT: 635 DPRINTF("writing to reg %d invalid\n", reg); 636 break; 637 /* Accept write to some registers only when in reset mode */ 638 case SONIC_DCR: 639 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 640 s->regs[reg] = val & 0xbfff; 641 } else { 642 DPRINTF("writing to DCR invalid\n"); 643 } 644 break; 645 case SONIC_DCR2: 646 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 647 s->regs[reg] = val & 0xf017; 648 } else { 649 DPRINTF("writing to DCR2 invalid\n"); 650 } 651 break; 652 /* 12 lower bytes are Read Only */ 653 case SONIC_TCR: 654 s->regs[reg] = val & 0xf000; 655 break; 656 /* 9 lower bytes are Read Only */ 657 case SONIC_RCR: 658 s->regs[reg] = val & 0xffe0; 659 break; 660 /* Ignore most significant bit */ 661 case SONIC_IMR: 662 s->regs[reg] = val & 0x7fff; 663 dp8393x_update_irq(s); 664 break; 665 /* Clear bits by writing 1 to them */ 666 case SONIC_ISR: 667 val &= s->regs[reg]; 668 s->regs[reg] &= ~val; 669 if (val & SONIC_ISR_RBE) { 670 dp8393x_do_read_rra(s); 671 } 672 dp8393x_update_irq(s); 673 break; 674 /* The guest is required to store aligned pointers here */ 675 case SONIC_RSA: 676 case SONIC_REA: 677 case SONIC_RRP: 678 case SONIC_RWP: 679 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 680 s->regs[reg] = val & 0xfffc; 681 } else { 682 s->regs[reg] = val & 0xfffe; 683 } 684 break; 685 /* Invert written value for some registers */ 686 case SONIC_CRCT: 687 case SONIC_FAET: 688 case SONIC_MPT: 689 s->regs[reg] = val ^ 0xffff; 690 break; 691 /* All other registers have no special contrainst */ 692 default: 693 s->regs[reg] = val; 694 } 695 696 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 697 dp8393x_set_next_tick(s); 698 } 699 } 700 701 static const MemoryRegionOps dp8393x_ops = { 702 .read = dp8393x_read, 703 .write = dp8393x_write, 704 .impl.min_access_size = 4, 705 .impl.max_access_size = 4, 706 .endianness = DEVICE_NATIVE_ENDIAN, 707 }; 708 709 static void dp8393x_watchdog(void *opaque) 710 { 711 dp8393xState *s = opaque; 712 713 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 714 return; 715 } 716 717 s->regs[SONIC_WT1] = 0xffff; 718 s->regs[SONIC_WT0] = 0xffff; 719 dp8393x_set_next_tick(s); 720 721 /* Signal underflow */ 722 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 723 dp8393x_update_irq(s); 724 } 725 726 static bool dp8393x_can_receive(NetClientState *nc) 727 { 728 dp8393xState *s = qemu_get_nic_opaque(nc); 729 730 return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN); 731 } 732 733 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 734 int size) 735 { 736 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 737 int i; 738 739 /* Check promiscuous mode */ 740 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 741 return 0; 742 } 743 744 /* Check multicast packets */ 745 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 746 return SONIC_RCR_MC; 747 } 748 749 /* Check broadcast */ 750 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 751 return SONIC_RCR_BC; 752 } 753 754 /* Check CAM */ 755 for (i = 0; i < 16; i++) { 756 if (s->regs[SONIC_CE] & (1 << i)) { 757 /* Entry enabled */ 758 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 759 return 0; 760 } 761 } 762 } 763 764 return -1; 765 } 766 767 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 768 size_t pkt_size) 769 { 770 dp8393xState *s = qemu_get_nic_opaque(nc); 771 int packet_type; 772 uint32_t available, address; 773 int width, rx_len, padded_len; 774 uint32_t checksum; 775 int size; 776 777 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 778 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 779 780 if (s->last_rba_is_full) { 781 return pkt_size; 782 } 783 784 rx_len = pkt_size + sizeof(checksum); 785 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 786 width = 2; 787 padded_len = ((rx_len - 1) | 3) + 1; 788 } else { 789 width = 1; 790 padded_len = ((rx_len - 1) | 1) + 1; 791 } 792 793 if (padded_len > dp8393x_rbwc(s) * 2) { 794 DPRINTF("oversize packet, pkt_size is %d\n", pkt_size); 795 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE; 796 dp8393x_update_irq(s); 797 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 798 goto done; 799 } 800 801 packet_type = dp8393x_receive_filter(s, buf, pkt_size); 802 if (packet_type < 0) { 803 DPRINTF("packet not for netcard\n"); 804 return -1; 805 } 806 807 /* Check for EOL */ 808 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 809 /* Are we still in resource exhaustion? */ 810 size = sizeof(uint16_t) * 1 * width; 811 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 812 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 813 s->data, size); 814 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 815 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 816 /* Still EOL ; stop reception */ 817 return -1; 818 } 819 /* Link has been updated by host */ 820 821 /* Clear in_use */ 822 size = sizeof(uint16_t) * width; 823 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 824 dp8393x_put(s, width, 0, 0); 825 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 826 (uint8_t *)s->data, size, 1); 827 828 /* Move to next descriptor */ 829 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 830 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 831 } 832 833 /* Save current position */ 834 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 835 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 836 837 /* Calculate the ethernet checksum */ 838 checksum = cpu_to_le32(crc32(0, buf, pkt_size)); 839 840 /* Put packet into RBA */ 841 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 842 address = dp8393x_crba(s); 843 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 844 buf, pkt_size); 845 address += pkt_size; 846 847 /* Put frame checksum into RBA */ 848 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 849 &checksum, sizeof(checksum)); 850 address += sizeof(checksum); 851 852 /* Pad short packets to keep pointers aligned */ 853 if (rx_len < padded_len) { 854 size = padded_len - rx_len; 855 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 856 (uint8_t *)"\xFF\xFF\xFF", size, 1); 857 address += size; 858 } 859 860 s->regs[SONIC_CRBA1] = address >> 16; 861 s->regs[SONIC_CRBA0] = address & 0xffff; 862 available = dp8393x_rbwc(s); 863 available -= padded_len >> 1; 864 s->regs[SONIC_RBWC1] = available >> 16; 865 s->regs[SONIC_RBWC0] = available & 0xffff; 866 867 /* Update status */ 868 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 869 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 870 } 871 s->regs[SONIC_RCR] |= packet_type; 872 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 873 if (s->loopback_packet) { 874 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 875 s->loopback_packet = 0; 876 } 877 878 /* Write status to memory */ 879 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 880 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 881 dp8393x_put(s, width, 1, rx_len); /* byte count */ 882 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 883 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 884 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 885 size = sizeof(uint16_t) * 5 * width; 886 address_space_write(&s->as, dp8393x_crda(s), 887 MEMTXATTRS_UNSPECIFIED, 888 s->data, size); 889 890 /* Check link field */ 891 size = sizeof(uint16_t) * width; 892 address_space_read(&s->as, 893 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 894 MEMTXATTRS_UNSPECIFIED, s->data, size); 895 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 896 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 897 /* EOL detected */ 898 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 899 } else { 900 /* Clear in_use */ 901 size = sizeof(uint16_t) * width; 902 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 903 dp8393x_put(s, width, 0, 0); 904 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 905 s->data, size); 906 907 /* Move to next descriptor */ 908 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 909 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 910 } 911 912 dp8393x_update_irq(s); 913 914 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | 915 ((s->regs[SONIC_RSC] + 1) & 0x00ff); 916 917 done: 918 919 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 920 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) { 921 /* Stop packet reception */ 922 s->last_rba_is_full = true; 923 } else { 924 /* Read next resource */ 925 dp8393x_do_read_rra(s); 926 } 927 } 928 929 return pkt_size; 930 } 931 932 static void dp8393x_reset(DeviceState *dev) 933 { 934 dp8393xState *s = DP8393X(dev); 935 timer_del(s->watchdog); 936 937 memset(s->regs, 0, sizeof(s->regs)); 938 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */ 939 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 940 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 941 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 942 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 943 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 944 s->regs[SONIC_IMR] = 0; 945 s->regs[SONIC_ISR] = 0; 946 s->regs[SONIC_DCR2] = 0; 947 s->regs[SONIC_EOBC] = 0x02F8; 948 s->regs[SONIC_RSC] = 0; 949 s->regs[SONIC_CE] = 0; 950 s->regs[SONIC_RSC] = 0; 951 952 /* Network cable is connected */ 953 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 954 955 dp8393x_update_irq(s); 956 } 957 958 static NetClientInfo net_dp83932_info = { 959 .type = NET_CLIENT_DRIVER_NIC, 960 .size = sizeof(NICState), 961 .can_receive = dp8393x_can_receive, 962 .receive = dp8393x_receive, 963 }; 964 965 static void dp8393x_instance_init(Object *obj) 966 { 967 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 968 dp8393xState *s = DP8393X(obj); 969 970 sysbus_init_mmio(sbd, &s->mmio); 971 sysbus_init_mmio(sbd, &s->prom); 972 sysbus_init_irq(sbd, &s->irq); 973 } 974 975 static void dp8393x_realize(DeviceState *dev, Error **errp) 976 { 977 dp8393xState *s = DP8393X(dev); 978 int i, checksum; 979 uint8_t *prom; 980 Error *local_err = NULL; 981 982 address_space_init(&s->as, s->dma_mr, "dp8393x"); 983 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 984 "dp8393x-regs", 0x40 << s->it_shift); 985 986 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 987 object_get_typename(OBJECT(dev)), dev->id, s); 988 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 989 990 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 991 992 memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom", 993 SONIC_PROM_SIZE, &local_err); 994 if (local_err) { 995 error_propagate(errp, local_err); 996 return; 997 } 998 prom = memory_region_get_ram_ptr(&s->prom); 999 checksum = 0; 1000 for (i = 0; i < 6; i++) { 1001 prom[i] = s->conf.macaddr.a[i]; 1002 checksum += prom[i]; 1003 if (checksum > 0xff) { 1004 checksum = (checksum + 1) & 0xff; 1005 } 1006 } 1007 prom[7] = 0xff - checksum; 1008 } 1009 1010 static const VMStateDescription vmstate_dp8393x = { 1011 .name = "dp8393x", 1012 .version_id = 0, 1013 .minimum_version_id = 0, 1014 .fields = (VMStateField []) { 1015 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 1016 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 1017 VMSTATE_END_OF_LIST() 1018 } 1019 }; 1020 1021 static Property dp8393x_properties[] = { 1022 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 1023 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 1024 TYPE_MEMORY_REGION, MemoryRegion *), 1025 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 1026 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 1027 DEFINE_PROP_END_OF_LIST(), 1028 }; 1029 1030 static void dp8393x_class_init(ObjectClass *klass, void *data) 1031 { 1032 DeviceClass *dc = DEVICE_CLASS(klass); 1033 1034 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1035 dc->realize = dp8393x_realize; 1036 dc->reset = dp8393x_reset; 1037 dc->vmsd = &vmstate_dp8393x; 1038 device_class_set_props(dc, dp8393x_properties); 1039 } 1040 1041 static const TypeInfo dp8393x_info = { 1042 .name = TYPE_DP8393X, 1043 .parent = TYPE_SYS_BUS_DEVICE, 1044 .instance_size = sizeof(dp8393xState), 1045 .instance_init = dp8393x_instance_init, 1046 .class_init = dp8393x_class_init, 1047 }; 1048 1049 static void dp8393x_register_types(void) 1050 { 1051 type_register_static(&dp8393x_info); 1052 } 1053 1054 type_init(dp8393x_register_types) 1055