1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "net/net.h" 25 #include "qapi/error.h" 26 #include "qemu/module.h" 27 #include "qemu/timer.h" 28 #include <zlib.h> 29 30 //#define DEBUG_SONIC 31 32 #define SONIC_PROM_SIZE 0x1000 33 34 #ifdef DEBUG_SONIC 35 #define DPRINTF(fmt, ...) \ 36 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 37 static const char* reg_names[] = { 38 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 39 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 40 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 41 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 42 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 43 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 44 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 45 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 46 #else 47 #define DPRINTF(fmt, ...) do {} while (0) 48 #endif 49 50 #define SONIC_ERROR(fmt, ...) \ 51 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 52 53 #define SONIC_CR 0x00 54 #define SONIC_DCR 0x01 55 #define SONIC_RCR 0x02 56 #define SONIC_TCR 0x03 57 #define SONIC_IMR 0x04 58 #define SONIC_ISR 0x05 59 #define SONIC_UTDA 0x06 60 #define SONIC_CTDA 0x07 61 #define SONIC_TPS 0x08 62 #define SONIC_TFC 0x09 63 #define SONIC_TSA0 0x0a 64 #define SONIC_TSA1 0x0b 65 #define SONIC_TFS 0x0c 66 #define SONIC_URDA 0x0d 67 #define SONIC_CRDA 0x0e 68 #define SONIC_CRBA0 0x0f 69 #define SONIC_CRBA1 0x10 70 #define SONIC_RBWC0 0x11 71 #define SONIC_RBWC1 0x12 72 #define SONIC_EOBC 0x13 73 #define SONIC_URRA 0x14 74 #define SONIC_RSA 0x15 75 #define SONIC_REA 0x16 76 #define SONIC_RRP 0x17 77 #define SONIC_RWP 0x18 78 #define SONIC_TRBA0 0x19 79 #define SONIC_TRBA1 0x1a 80 #define SONIC_LLFA 0x1f 81 #define SONIC_TTDA 0x20 82 #define SONIC_CEP 0x21 83 #define SONIC_CAP2 0x22 84 #define SONIC_CAP1 0x23 85 #define SONIC_CAP0 0x24 86 #define SONIC_CE 0x25 87 #define SONIC_CDP 0x26 88 #define SONIC_CDC 0x27 89 #define SONIC_SR 0x28 90 #define SONIC_WT0 0x29 91 #define SONIC_WT1 0x2a 92 #define SONIC_RSC 0x2b 93 #define SONIC_CRCT 0x2c 94 #define SONIC_FAET 0x2d 95 #define SONIC_MPT 0x2e 96 #define SONIC_MDT 0x2f 97 #define SONIC_DCR2 0x3f 98 99 #define SONIC_CR_HTX 0x0001 100 #define SONIC_CR_TXP 0x0002 101 #define SONIC_CR_RXDIS 0x0004 102 #define SONIC_CR_RXEN 0x0008 103 #define SONIC_CR_STP 0x0010 104 #define SONIC_CR_ST 0x0020 105 #define SONIC_CR_RST 0x0080 106 #define SONIC_CR_RRRA 0x0100 107 #define SONIC_CR_LCAM 0x0200 108 #define SONIC_CR_MASK 0x03bf 109 110 #define SONIC_DCR_DW 0x0020 111 #define SONIC_DCR_LBR 0x2000 112 #define SONIC_DCR_EXBUS 0x8000 113 114 #define SONIC_RCR_PRX 0x0001 115 #define SONIC_RCR_LBK 0x0002 116 #define SONIC_RCR_FAER 0x0004 117 #define SONIC_RCR_CRCR 0x0008 118 #define SONIC_RCR_CRS 0x0020 119 #define SONIC_RCR_LPKT 0x0040 120 #define SONIC_RCR_BC 0x0080 121 #define SONIC_RCR_MC 0x0100 122 #define SONIC_RCR_LB0 0x0200 123 #define SONIC_RCR_LB1 0x0400 124 #define SONIC_RCR_AMC 0x0800 125 #define SONIC_RCR_PRO 0x1000 126 #define SONIC_RCR_BRD 0x2000 127 #define SONIC_RCR_RNT 0x4000 128 129 #define SONIC_TCR_PTX 0x0001 130 #define SONIC_TCR_BCM 0x0002 131 #define SONIC_TCR_FU 0x0004 132 #define SONIC_TCR_EXC 0x0040 133 #define SONIC_TCR_CRSL 0x0080 134 #define SONIC_TCR_NCRS 0x0100 135 #define SONIC_TCR_EXD 0x0400 136 #define SONIC_TCR_CRCI 0x2000 137 #define SONIC_TCR_PINT 0x8000 138 139 #define SONIC_ISR_RBE 0x0020 140 #define SONIC_ISR_RDE 0x0040 141 #define SONIC_ISR_TC 0x0080 142 #define SONIC_ISR_TXDN 0x0200 143 #define SONIC_ISR_PKTRX 0x0400 144 #define SONIC_ISR_PINT 0x0800 145 #define SONIC_ISR_LCD 0x1000 146 147 #define TYPE_DP8393X "dp8393x" 148 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 149 150 typedef struct dp8393xState { 151 SysBusDevice parent_obj; 152 153 /* Hardware */ 154 uint8_t it_shift; 155 qemu_irq irq; 156 #ifdef DEBUG_SONIC 157 int irq_level; 158 #endif 159 QEMUTimer *watchdog; 160 int64_t wt_last_update; 161 NICConf conf; 162 NICState *nic; 163 MemoryRegion mmio; 164 MemoryRegion prom; 165 166 /* Registers */ 167 uint8_t cam[16][6]; 168 uint16_t regs[0x40]; 169 170 /* Temporaries */ 171 uint8_t tx_buffer[0x10000]; 172 int loopback_packet; 173 174 /* Memory access */ 175 void *dma_mr; 176 AddressSpace as; 177 } dp8393xState; 178 179 /* Accessor functions for values which are formed by 180 * concatenating two 16 bit device registers. By putting these 181 * in their own functions with a uint32_t return type we avoid the 182 * pitfall of implicit sign extension where ((x << 16) | y) is a 183 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 184 */ 185 static uint32_t dp8393x_cdp(dp8393xState *s) 186 { 187 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 188 } 189 190 static uint32_t dp8393x_crba(dp8393xState *s) 191 { 192 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 193 } 194 195 static uint32_t dp8393x_crda(dp8393xState *s) 196 { 197 return (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]; 198 } 199 200 static uint32_t dp8393x_rbwc(dp8393xState *s) 201 { 202 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 203 } 204 205 static uint32_t dp8393x_rrp(dp8393xState *s) 206 { 207 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 208 } 209 210 static uint32_t dp8393x_tsa(dp8393xState *s) 211 { 212 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 213 } 214 215 static uint32_t dp8393x_ttda(dp8393xState *s) 216 { 217 return (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]; 218 } 219 220 static uint32_t dp8393x_wt(dp8393xState *s) 221 { 222 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 223 } 224 225 static void dp8393x_update_irq(dp8393xState *s) 226 { 227 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 228 229 #ifdef DEBUG_SONIC 230 if (level != s->irq_level) { 231 s->irq_level = level; 232 if (level) { 233 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 234 } else { 235 DPRINTF("lower irq\n"); 236 } 237 } 238 #endif 239 240 qemu_set_irq(s->irq, level); 241 } 242 243 static void dp8393x_do_load_cam(dp8393xState *s) 244 { 245 uint16_t data[8]; 246 int width, size; 247 uint16_t index = 0; 248 249 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 250 size = sizeof(uint16_t) * 4 * width; 251 252 while (s->regs[SONIC_CDC] & 0x1f) { 253 /* Fill current entry */ 254 address_space_rw(&s->as, dp8393x_cdp(s), 255 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 256 s->cam[index][0] = data[1 * width] & 0xff; 257 s->cam[index][1] = data[1 * width] >> 8; 258 s->cam[index][2] = data[2 * width] & 0xff; 259 s->cam[index][3] = data[2 * width] >> 8; 260 s->cam[index][4] = data[3 * width] & 0xff; 261 s->cam[index][5] = data[3 * width] >> 8; 262 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 263 s->cam[index][0], s->cam[index][1], s->cam[index][2], 264 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 265 /* Move to next entry */ 266 s->regs[SONIC_CDC]--; 267 s->regs[SONIC_CDP] += size; 268 index++; 269 } 270 271 /* Read CAM enable */ 272 address_space_rw(&s->as, dp8393x_cdp(s), 273 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 274 s->regs[SONIC_CE] = data[0 * width]; 275 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 276 277 /* Done */ 278 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 279 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 280 dp8393x_update_irq(s); 281 } 282 283 static void dp8393x_do_read_rra(dp8393xState *s) 284 { 285 uint16_t data[8]; 286 int width, size; 287 288 /* Read memory */ 289 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 290 size = sizeof(uint16_t) * 4 * width; 291 address_space_rw(&s->as, dp8393x_rrp(s), 292 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 293 294 /* Update SONIC registers */ 295 s->regs[SONIC_CRBA0] = data[0 * width]; 296 s->regs[SONIC_CRBA1] = data[1 * width]; 297 s->regs[SONIC_RBWC0] = data[2 * width]; 298 s->regs[SONIC_RBWC1] = data[3 * width]; 299 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 300 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 301 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 302 303 /* Go to next entry */ 304 s->regs[SONIC_RRP] += size; 305 306 /* Handle wrap */ 307 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 308 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 309 } 310 311 /* Check resource exhaustion */ 312 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 313 { 314 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 315 dp8393x_update_irq(s); 316 } 317 318 /* Done */ 319 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 320 } 321 322 static void dp8393x_do_software_reset(dp8393xState *s) 323 { 324 timer_del(s->watchdog); 325 326 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 327 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 328 } 329 330 static void dp8393x_set_next_tick(dp8393xState *s) 331 { 332 uint32_t ticks; 333 int64_t delay; 334 335 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 336 timer_del(s->watchdog); 337 return; 338 } 339 340 ticks = dp8393x_wt(s); 341 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 342 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 343 timer_mod(s->watchdog, s->wt_last_update + delay); 344 } 345 346 static void dp8393x_update_wt_regs(dp8393xState *s) 347 { 348 int64_t elapsed; 349 uint32_t val; 350 351 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 352 timer_del(s->watchdog); 353 return; 354 } 355 356 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 357 val = dp8393x_wt(s); 358 val -= elapsed / 5000000; 359 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 360 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 361 dp8393x_set_next_tick(s); 362 363 } 364 365 static void dp8393x_do_start_timer(dp8393xState *s) 366 { 367 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 368 dp8393x_set_next_tick(s); 369 } 370 371 static void dp8393x_do_stop_timer(dp8393xState *s) 372 { 373 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 374 dp8393x_update_wt_regs(s); 375 } 376 377 static int dp8393x_can_receive(NetClientState *nc); 378 379 static void dp8393x_do_receiver_enable(dp8393xState *s) 380 { 381 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 382 if (dp8393x_can_receive(s->nic->ncs)) { 383 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 384 } 385 } 386 387 static void dp8393x_do_receiver_disable(dp8393xState *s) 388 { 389 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 390 } 391 392 static void dp8393x_do_transmit_packets(dp8393xState *s) 393 { 394 NetClientState *nc = qemu_get_queue(s->nic); 395 uint16_t data[12]; 396 int width, size; 397 int tx_len, len; 398 uint16_t i; 399 400 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 401 402 while (1) { 403 /* Read memory */ 404 size = sizeof(uint16_t) * 6 * width; 405 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 406 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 407 address_space_rw(&s->as, 408 dp8393x_ttda(s) + sizeof(uint16_t) * width, 409 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 410 tx_len = 0; 411 412 /* Update registers */ 413 s->regs[SONIC_TCR] = data[0 * width] & 0xf000; 414 s->regs[SONIC_TPS] = data[1 * width]; 415 s->regs[SONIC_TFC] = data[2 * width]; 416 s->regs[SONIC_TSA0] = data[3 * width]; 417 s->regs[SONIC_TSA1] = data[4 * width]; 418 s->regs[SONIC_TFS] = data[5 * width]; 419 420 /* Handle programmable interrupt */ 421 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 422 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 423 } else { 424 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 425 } 426 427 for (i = 0; i < s->regs[SONIC_TFC]; ) { 428 /* Append fragment */ 429 len = s->regs[SONIC_TFS]; 430 if (tx_len + len > sizeof(s->tx_buffer)) { 431 len = sizeof(s->tx_buffer) - tx_len; 432 } 433 address_space_rw(&s->as, dp8393x_tsa(s), 434 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0); 435 tx_len += len; 436 437 i++; 438 if (i != s->regs[SONIC_TFC]) { 439 /* Read next fragment details */ 440 size = sizeof(uint16_t) * 3 * width; 441 address_space_rw(&s->as, 442 dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, 443 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 444 s->regs[SONIC_TSA0] = data[0 * width]; 445 s->regs[SONIC_TSA1] = data[1 * width]; 446 s->regs[SONIC_TFS] = data[2 * width]; 447 } 448 } 449 450 /* Handle Ethernet checksum */ 451 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 452 /* Don't append FCS there, to look like slirp packets 453 * which don't have one */ 454 } else { 455 /* Remove existing FCS */ 456 tx_len -= 4; 457 } 458 459 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 460 /* Loopback */ 461 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 462 if (nc->info->can_receive(nc)) { 463 s->loopback_packet = 1; 464 nc->info->receive(nc, s->tx_buffer, tx_len); 465 } 466 } else { 467 /* Transmit packet */ 468 qemu_send_packet(nc, s->tx_buffer, tx_len); 469 } 470 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 471 472 /* Write status */ 473 data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */ 474 size = sizeof(uint16_t) * width; 475 address_space_rw(&s->as, 476 dp8393x_ttda(s), 477 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 478 479 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 480 /* Read footer of packet */ 481 size = sizeof(uint16_t) * width; 482 address_space_rw(&s->as, 483 dp8393x_ttda(s) + 484 sizeof(uint16_t) * 485 (4 + 3 * s->regs[SONIC_TFC]) * width, 486 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 487 s->regs[SONIC_CTDA] = data[0 * width] & ~0x1; 488 if (data[0 * width] & 0x1) { 489 /* EOL detected */ 490 break; 491 } 492 } 493 } 494 495 /* Done */ 496 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 497 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 498 dp8393x_update_irq(s); 499 } 500 501 static void dp8393x_do_halt_transmission(dp8393xState *s) 502 { 503 /* Nothing to do */ 504 } 505 506 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 507 { 508 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 509 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 510 return; 511 } 512 513 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 514 515 if (command & SONIC_CR_HTX) 516 dp8393x_do_halt_transmission(s); 517 if (command & SONIC_CR_TXP) 518 dp8393x_do_transmit_packets(s); 519 if (command & SONIC_CR_RXDIS) 520 dp8393x_do_receiver_disable(s); 521 if (command & SONIC_CR_RXEN) 522 dp8393x_do_receiver_enable(s); 523 if (command & SONIC_CR_STP) 524 dp8393x_do_stop_timer(s); 525 if (command & SONIC_CR_ST) 526 dp8393x_do_start_timer(s); 527 if (command & SONIC_CR_RST) 528 dp8393x_do_software_reset(s); 529 if (command & SONIC_CR_RRRA) 530 dp8393x_do_read_rra(s); 531 if (command & SONIC_CR_LCAM) 532 dp8393x_do_load_cam(s); 533 } 534 535 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 536 { 537 dp8393xState *s = opaque; 538 int reg = addr >> s->it_shift; 539 uint16_t val = 0; 540 541 switch (reg) { 542 /* Update data before reading it */ 543 case SONIC_WT0: 544 case SONIC_WT1: 545 dp8393x_update_wt_regs(s); 546 val = s->regs[reg]; 547 break; 548 /* Accept read to some registers only when in reset mode */ 549 case SONIC_CAP2: 550 case SONIC_CAP1: 551 case SONIC_CAP0: 552 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 553 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 554 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 555 } 556 break; 557 /* All other registers have no special contrainst */ 558 default: 559 val = s->regs[reg]; 560 } 561 562 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 563 564 return val; 565 } 566 567 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 568 unsigned int size) 569 { 570 dp8393xState *s = opaque; 571 int reg = addr >> s->it_shift; 572 573 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); 574 575 switch (reg) { 576 /* Command register */ 577 case SONIC_CR: 578 dp8393x_do_command(s, data); 579 break; 580 /* Prevent write to read-only registers */ 581 case SONIC_CAP2: 582 case SONIC_CAP1: 583 case SONIC_CAP0: 584 case SONIC_SR: 585 case SONIC_MDT: 586 DPRINTF("writing to reg %d invalid\n", reg); 587 break; 588 /* Accept write to some registers only when in reset mode */ 589 case SONIC_DCR: 590 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 591 s->regs[reg] = data & 0xbfff; 592 } else { 593 DPRINTF("writing to DCR invalid\n"); 594 } 595 break; 596 case SONIC_DCR2: 597 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 598 s->regs[reg] = data & 0xf017; 599 } else { 600 DPRINTF("writing to DCR2 invalid\n"); 601 } 602 break; 603 /* 12 lower bytes are Read Only */ 604 case SONIC_TCR: 605 s->regs[reg] = data & 0xf000; 606 break; 607 /* 9 lower bytes are Read Only */ 608 case SONIC_RCR: 609 s->regs[reg] = data & 0xffe0; 610 break; 611 /* Ignore most significant bit */ 612 case SONIC_IMR: 613 s->regs[reg] = data & 0x7fff; 614 dp8393x_update_irq(s); 615 break; 616 /* Clear bits by writing 1 to them */ 617 case SONIC_ISR: 618 data &= s->regs[reg]; 619 s->regs[reg] &= ~data; 620 if (data & SONIC_ISR_RBE) { 621 dp8393x_do_read_rra(s); 622 } 623 dp8393x_update_irq(s); 624 if (dp8393x_can_receive(s->nic->ncs)) { 625 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 626 } 627 break; 628 /* Ignore least significant bit */ 629 case SONIC_RSA: 630 case SONIC_REA: 631 case SONIC_RRP: 632 case SONIC_RWP: 633 s->regs[reg] = data & 0xfffe; 634 break; 635 /* Invert written value for some registers */ 636 case SONIC_CRCT: 637 case SONIC_FAET: 638 case SONIC_MPT: 639 s->regs[reg] = data ^ 0xffff; 640 break; 641 /* All other registers have no special contrainst */ 642 default: 643 s->regs[reg] = data; 644 } 645 646 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 647 dp8393x_set_next_tick(s); 648 } 649 } 650 651 static const MemoryRegionOps dp8393x_ops = { 652 .read = dp8393x_read, 653 .write = dp8393x_write, 654 .impl.min_access_size = 2, 655 .impl.max_access_size = 2, 656 .endianness = DEVICE_NATIVE_ENDIAN, 657 }; 658 659 static void dp8393x_watchdog(void *opaque) 660 { 661 dp8393xState *s = opaque; 662 663 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 664 return; 665 } 666 667 s->regs[SONIC_WT1] = 0xffff; 668 s->regs[SONIC_WT0] = 0xffff; 669 dp8393x_set_next_tick(s); 670 671 /* Signal underflow */ 672 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 673 dp8393x_update_irq(s); 674 } 675 676 static int dp8393x_can_receive(NetClientState *nc) 677 { 678 dp8393xState *s = qemu_get_nic_opaque(nc); 679 680 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 681 return 0; 682 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 683 return 0; 684 return 1; 685 } 686 687 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 688 int size) 689 { 690 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 691 int i; 692 693 /* Check promiscuous mode */ 694 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 695 return 0; 696 } 697 698 /* Check multicast packets */ 699 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 700 return SONIC_RCR_MC; 701 } 702 703 /* Check broadcast */ 704 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 705 return SONIC_RCR_BC; 706 } 707 708 /* Check CAM */ 709 for (i = 0; i < 16; i++) { 710 if (s->regs[SONIC_CE] & (1 << i)) { 711 /* Entry enabled */ 712 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 713 return 0; 714 } 715 } 716 } 717 718 return -1; 719 } 720 721 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 722 size_t size) 723 { 724 dp8393xState *s = qemu_get_nic_opaque(nc); 725 uint16_t data[10]; 726 int packet_type; 727 uint32_t available, address; 728 int width, rx_len = size; 729 uint32_t checksum; 730 731 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 732 733 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 734 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 735 736 packet_type = dp8393x_receive_filter(s, buf, size); 737 if (packet_type < 0) { 738 DPRINTF("packet not for netcard\n"); 739 return -1; 740 } 741 742 /* XXX: Check byte ordering */ 743 744 /* Check for EOL */ 745 if (s->regs[SONIC_LLFA] & 0x1) { 746 /* Are we still in resource exhaustion? */ 747 size = sizeof(uint16_t) * 1 * width; 748 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 749 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 750 (uint8_t *)data, size, 0); 751 if (data[0 * width] & 0x1) { 752 /* Still EOL ; stop reception */ 753 return -1; 754 } else { 755 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 756 } 757 } 758 759 /* Save current position */ 760 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 761 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 762 763 /* Calculate the ethernet checksum */ 764 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 765 766 /* Put packet into RBA */ 767 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 768 address = dp8393x_crba(s); 769 address_space_rw(&s->as, address, 770 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1); 771 address += rx_len; 772 address_space_rw(&s->as, address, 773 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); 774 rx_len += 4; 775 s->regs[SONIC_CRBA1] = address >> 16; 776 s->regs[SONIC_CRBA0] = address & 0xffff; 777 available = dp8393x_rbwc(s); 778 available -= rx_len / 2; 779 s->regs[SONIC_RBWC1] = available >> 16; 780 s->regs[SONIC_RBWC0] = available & 0xffff; 781 782 /* Update status */ 783 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 784 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 785 } 786 s->regs[SONIC_RCR] |= packet_type; 787 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 788 if (s->loopback_packet) { 789 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 790 s->loopback_packet = 0; 791 } 792 793 /* Write status to memory */ 794 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 795 data[0 * width] = s->regs[SONIC_RCR]; /* status */ 796 data[1 * width] = rx_len; /* byte count */ 797 data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */ 798 data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */ 799 data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */ 800 size = sizeof(uint16_t) * 5 * width; 801 address_space_rw(&s->as, dp8393x_crda(s), 802 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 803 804 /* Move to next descriptor */ 805 size = sizeof(uint16_t) * width; 806 address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 807 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 808 s->regs[SONIC_LLFA] = data[0 * width]; 809 if (s->regs[SONIC_LLFA] & 0x1) { 810 /* EOL detected */ 811 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 812 } else { 813 data[0 * width] = 0; /* in_use */ 814 address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width, 815 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1); 816 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 817 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 818 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 819 820 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 821 /* Read next RRA */ 822 dp8393x_do_read_rra(s); 823 } 824 } 825 826 /* Done */ 827 dp8393x_update_irq(s); 828 829 return size; 830 } 831 832 static void dp8393x_reset(DeviceState *dev) 833 { 834 dp8393xState *s = DP8393X(dev); 835 timer_del(s->watchdog); 836 837 memset(s->regs, 0, sizeof(s->regs)); 838 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 839 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 840 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 841 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 842 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 843 s->regs[SONIC_IMR] = 0; 844 s->regs[SONIC_ISR] = 0; 845 s->regs[SONIC_DCR2] = 0; 846 s->regs[SONIC_EOBC] = 0x02F8; 847 s->regs[SONIC_RSC] = 0; 848 s->regs[SONIC_CE] = 0; 849 s->regs[SONIC_RSC] = 0; 850 851 /* Network cable is connected */ 852 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 853 854 dp8393x_update_irq(s); 855 } 856 857 static NetClientInfo net_dp83932_info = { 858 .type = NET_CLIENT_DRIVER_NIC, 859 .size = sizeof(NICState), 860 .can_receive = dp8393x_can_receive, 861 .receive = dp8393x_receive, 862 }; 863 864 static void dp8393x_instance_init(Object *obj) 865 { 866 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 867 dp8393xState *s = DP8393X(obj); 868 869 sysbus_init_mmio(sbd, &s->mmio); 870 sysbus_init_mmio(sbd, &s->prom); 871 sysbus_init_irq(sbd, &s->irq); 872 } 873 874 static void dp8393x_realize(DeviceState *dev, Error **errp) 875 { 876 dp8393xState *s = DP8393X(dev); 877 int i, checksum; 878 uint8_t *prom; 879 Error *local_err = NULL; 880 881 address_space_init(&s->as, s->dma_mr, "dp8393x"); 882 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 883 "dp8393x-regs", 0x40 << s->it_shift); 884 885 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 886 object_get_typename(OBJECT(dev)), dev->id, s); 887 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 888 889 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 890 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 891 892 memory_region_init_ram(&s->prom, OBJECT(dev), 893 "dp8393x-prom", SONIC_PROM_SIZE, &local_err); 894 if (local_err) { 895 error_propagate(errp, local_err); 896 return; 897 } 898 memory_region_set_readonly(&s->prom, true); 899 prom = memory_region_get_ram_ptr(&s->prom); 900 checksum = 0; 901 for (i = 0; i < 6; i++) { 902 prom[i] = s->conf.macaddr.a[i]; 903 checksum += prom[i]; 904 if (checksum > 0xff) { 905 checksum = (checksum + 1) & 0xff; 906 } 907 } 908 prom[7] = 0xff - checksum; 909 } 910 911 static const VMStateDescription vmstate_dp8393x = { 912 .name = "dp8393x", 913 .version_id = 0, 914 .minimum_version_id = 0, 915 .fields = (VMStateField []) { 916 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 917 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 918 VMSTATE_END_OF_LIST() 919 } 920 }; 921 922 static Property dp8393x_properties[] = { 923 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 924 DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr), 925 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 926 DEFINE_PROP_END_OF_LIST(), 927 }; 928 929 static void dp8393x_class_init(ObjectClass *klass, void *data) 930 { 931 DeviceClass *dc = DEVICE_CLASS(klass); 932 933 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 934 dc->realize = dp8393x_realize; 935 dc->reset = dp8393x_reset; 936 dc->vmsd = &vmstate_dp8393x; 937 dc->props = dp8393x_properties; 938 /* Reason: dma_mr property can't be set */ 939 dc->user_creatable = false; 940 } 941 942 static const TypeInfo dp8393x_info = { 943 .name = TYPE_DP8393X, 944 .parent = TYPE_SYS_BUS_DEVICE, 945 .instance_size = sizeof(dp8393xState), 946 .instance_init = dp8393x_instance_init, 947 .class_init = dp8393x_class_init, 948 }; 949 950 static void dp8393x_register_types(void) 951 { 952 type_register_static(&dp8393x_info); 953 } 954 955 type_init(dp8393x_register_types) 956