1 /* 2 * QEMU model of the Xilinx Versal CANFD device. 3 * 4 * This implementation is based on the following datasheet: 5 * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd 6 * 7 * Copyright (c) 2023 Advanced Micro Devices, Inc. 8 * 9 * Written-by: Vikram Garhwal <vikram.garhwal@amd.com> 10 * 11 * Based on QEMU CANFD Device emulation implemented by Jin Yang, Deniz Eren and 12 * Pavel Pisa 13 * 14 * Permission is hereby granted, free of charge, to any person obtaining a copy 15 * of this software and associated documentation files (the "Software"), to deal 16 * in the Software without restriction, including without limitation the rights 17 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 18 * copies of the Software, and to permit persons to whom the Software is 19 * furnished to do so, subject to the following conditions: 20 * 21 * The above copyright notice and this permission notice shall be included in 22 * all copies or substantial portions of the Software. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 27 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 28 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 29 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 30 * THE SOFTWARE. 31 */ 32 33 #include "qemu/osdep.h" 34 #include "hw/sysbus.h" 35 #include "hw/irq.h" 36 #include "hw/register.h" 37 #include "qapi/error.h" 38 #include "qemu/bitops.h" 39 #include "qemu/log.h" 40 #include "qemu/cutils.h" 41 #include "qemu/event_notifier.h" 42 #include "hw/qdev-properties.h" 43 #include "qom/object_interfaces.h" 44 #include "migration/vmstate.h" 45 #include "hw/net/xlnx-versal-canfd.h" 46 #include "trace.h" 47 48 REG32(SOFTWARE_RESET_REGISTER, 0x0) 49 FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1) 50 FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1) 51 REG32(MODE_SELECT_REGISTER, 0x4) 52 FIELD(MODE_SELECT_REGISTER, ITO, 8, 8) 53 FIELD(MODE_SELECT_REGISTER, ABR, 7, 1) 54 FIELD(MODE_SELECT_REGISTER, SBR, 6, 1) 55 FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1) 56 FIELD(MODE_SELECT_REGISTER, DAR, 4, 1) 57 FIELD(MODE_SELECT_REGISTER, BRSD, 3, 1) 58 FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1) 59 FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1) 60 FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1) 61 REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8) 62 FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8) 63 REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc) 64 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 16, 7) 65 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 8, 7) 66 FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 8) 67 REG32(ERROR_COUNTER_REGISTER, 0x10) 68 FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8) 69 FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8) 70 REG32(ERROR_STATUS_REGISTER, 0x14) 71 FIELD(ERROR_STATUS_REGISTER, F_BERR, 11, 1) 72 FIELD(ERROR_STATUS_REGISTER, F_STER, 10, 1) 73 FIELD(ERROR_STATUS_REGISTER, F_FMER, 9, 1) 74 FIELD(ERROR_STATUS_REGISTER, F_CRCER, 8, 1) 75 FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1) 76 FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1) 77 FIELD(ERROR_STATUS_REGISTER, STER, 2, 1) 78 FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1) 79 FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1) 80 REG32(STATUS_REGISTER, 0x18) 81 FIELD(STATUS_REGISTER, TDCV, 16, 7) 82 FIELD(STATUS_REGISTER, SNOOP, 12, 1) 83 FIELD(STATUS_REGISTER, BSFR_CONFIG, 10, 1) 84 FIELD(STATUS_REGISTER, PEE_CONFIG, 9, 1) 85 FIELD(STATUS_REGISTER, ESTAT, 7, 2) 86 FIELD(STATUS_REGISTER, ERRWRN, 6, 1) 87 FIELD(STATUS_REGISTER, BBSY, 5, 1) 88 FIELD(STATUS_REGISTER, BIDLE, 4, 1) 89 FIELD(STATUS_REGISTER, NORMAL, 3, 1) 90 FIELD(STATUS_REGISTER, SLEEP, 2, 1) 91 FIELD(STATUS_REGISTER, LBACK, 1, 1) 92 FIELD(STATUS_REGISTER, CONFIG, 0, 1) 93 REG32(INTERRUPT_STATUS_REGISTER, 0x1c) 94 FIELD(INTERRUPT_STATUS_REGISTER, TXEWMFLL, 31, 1) 95 FIELD(INTERRUPT_STATUS_REGISTER, TXEOFLW, 30, 1) 96 FIELD(INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 24, 6) 97 FIELD(INTERRUPT_STATUS_REGISTER, RXLRM_BI, 18, 6) 98 FIELD(INTERRUPT_STATUS_REGISTER, RXMNF, 17, 1) 99 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 16, 1) 100 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 15, 1) 101 FIELD(INTERRUPT_STATUS_REGISTER, TXCRS, 14, 1) 102 FIELD(INTERRUPT_STATUS_REGISTER, TXRRS, 13, 1) 103 FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1) 104 FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1) 105 FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1) 106 FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1) 107 /* 108 * In the original HW description below bit is named as ERROR but an ERROR 109 * field name collides with a macro in Windows build. To avoid Windows build 110 * failures, the bit is renamed to ERROR_BIT. 111 */ 112 FIELD(INTERRUPT_STATUS_REGISTER, ERROR_BIT, 8, 1) 113 FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW, 6, 1) 114 FIELD(INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 5, 1) 115 FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1) 116 FIELD(INTERRUPT_STATUS_REGISTER, BSFRD, 3, 1) 117 FIELD(INTERRUPT_STATUS_REGISTER, PEE, 2, 1) 118 FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1) 119 FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1) 120 REG32(INTERRUPT_ENABLE_REGISTER, 0x20) 121 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEWMFLL, 31, 1) 122 FIELD(INTERRUPT_ENABLE_REGISTER, ETXEOFLW, 30, 1) 123 FIELD(INTERRUPT_ENABLE_REGISTER, ERXMNF, 17, 1) 124 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL_1, 16, 1) 125 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFOFLW_1, 15, 1) 126 FIELD(INTERRUPT_ENABLE_REGISTER, ETXCRS, 14, 1) 127 FIELD(INTERRUPT_ENABLE_REGISTER, ETXRRS, 13, 1) 128 FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1) 129 FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1) 130 FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1) 131 FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1) 132 FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1) 133 FIELD(INTERRUPT_ENABLE_REGISTER, ERFXOFLW, 6, 1) 134 FIELD(INTERRUPT_ENABLE_REGISTER, ETSCNT_OFLW, 5, 1) 135 FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1) 136 FIELD(INTERRUPT_ENABLE_REGISTER, EBSFRD, 3, 1) 137 FIELD(INTERRUPT_ENABLE_REGISTER, EPEE, 2, 1) 138 FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1) 139 FIELD(INTERRUPT_ENABLE_REGISTER, EARBLOST, 0, 1) 140 REG32(INTERRUPT_CLEAR_REGISTER, 0x24) 141 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEWMFLL, 31, 1) 142 FIELD(INTERRUPT_CLEAR_REGISTER, CTXEOFLW, 30, 1) 143 FIELD(INTERRUPT_CLEAR_REGISTER, CRXMNF, 17, 1) 144 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL_1, 16, 1) 145 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFOFLW_1, 15, 1) 146 FIELD(INTERRUPT_CLEAR_REGISTER, CTXCRS, 14, 1) 147 FIELD(INTERRUPT_CLEAR_REGISTER, CTXRRS, 13, 1) 148 FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1) 149 FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1) 150 FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1) 151 FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1) 152 FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1) 153 FIELD(INTERRUPT_CLEAR_REGISTER, CRFXOFLW, 6, 1) 154 FIELD(INTERRUPT_CLEAR_REGISTER, CTSCNT_OFLW, 5, 1) 155 FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1) 156 FIELD(INTERRUPT_CLEAR_REGISTER, CBSFRD, 3, 1) 157 FIELD(INTERRUPT_CLEAR_REGISTER, CPEE, 2, 1) 158 FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1) 159 FIELD(INTERRUPT_CLEAR_REGISTER, CARBLOST, 0, 1) 160 REG32(TIMESTAMP_REGISTER, 0x28) 161 FIELD(TIMESTAMP_REGISTER, TIMESTAMP_CNT, 16, 16) 162 FIELD(TIMESTAMP_REGISTER, CTS, 0, 1) 163 REG32(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x88) 164 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDC, 16, 1) 165 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDCOFF, 8, 6) 166 FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, DP_BRP, 0, 8) 167 REG32(DATA_PHASE_BIT_TIMING_REGISTER, 0x8c) 168 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_SJW, 16, 4) 169 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS2, 8, 4) 170 FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS1, 0, 5) 171 REG32(TX_BUFFER_READY_REQUEST_REGISTER, 0x90) 172 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR31, 31, 1) 173 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR30, 30, 1) 174 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR29, 29, 1) 175 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR28, 28, 1) 176 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR27, 27, 1) 177 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR26, 26, 1) 178 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR25, 25, 1) 179 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR24, 24, 1) 180 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR23, 23, 1) 181 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR22, 22, 1) 182 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR21, 21, 1) 183 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR20, 20, 1) 184 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR19, 19, 1) 185 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR18, 18, 1) 186 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR17, 17, 1) 187 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR16, 16, 1) 188 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR15, 15, 1) 189 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR14, 14, 1) 190 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR13, 13, 1) 191 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR12, 12, 1) 192 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR11, 11, 1) 193 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR10, 10, 1) 194 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR9, 9, 1) 195 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR8, 8, 1) 196 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR7, 7, 1) 197 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR6, 6, 1) 198 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR5, 5, 1) 199 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR4, 4, 1) 200 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR3, 3, 1) 201 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR2, 2, 1) 202 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR1, 1, 1) 203 FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR0, 0, 1) 204 REG32(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, 0x94) 205 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS31, 31, 1) 206 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS30, 30, 1) 207 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS29, 29, 1) 208 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS28, 28, 1) 209 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS27, 27, 1) 210 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS26, 26, 1) 211 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS25, 25, 1) 212 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS24, 24, 1) 213 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS23, 23, 1) 214 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS22, 22, 1) 215 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS21, 21, 1) 216 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS20, 20, 1) 217 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS19, 19, 1) 218 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS18, 18, 1) 219 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS17, 17, 1) 220 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS16, 16, 1) 221 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS15, 15, 1) 222 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS14, 14, 1) 223 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS13, 13, 1) 224 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS12, 12, 1) 225 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS11, 11, 1) 226 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS10, 10, 1) 227 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS9, 9, 1) 228 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS8, 8, 1) 229 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS7, 7, 1) 230 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS6, 6, 1) 231 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS5, 5, 1) 232 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS4, 4, 1) 233 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS3, 3, 1) 234 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS2, 2, 1) 235 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS1, 1, 1) 236 FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS0, 0, 1) 237 REG32(TX_BUFFER_CANCEL_REQUEST_REGISTER, 0x98) 238 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR31, 31, 1) 239 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR30, 30, 1) 240 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR29, 29, 1) 241 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR28, 28, 1) 242 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR27, 27, 1) 243 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR26, 26, 1) 244 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR25, 25, 1) 245 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR24, 24, 1) 246 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR23, 23, 1) 247 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR22, 22, 1) 248 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR21, 21, 1) 249 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR20, 20, 1) 250 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR19, 19, 1) 251 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR18, 18, 1) 252 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR17, 17, 1) 253 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR16, 16, 1) 254 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR15, 15, 1) 255 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR14, 14, 1) 256 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR13, 13, 1) 257 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR12, 12, 1) 258 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR11, 11, 1) 259 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR10, 10, 1) 260 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR9, 9, 1) 261 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR8, 8, 1) 262 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR7, 7, 1) 263 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR6, 6, 1) 264 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR5, 5, 1) 265 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR4, 4, 1) 266 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR3, 3, 1) 267 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR2, 2, 1) 268 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR1, 1, 1) 269 FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR0, 0, 1) 270 REG32(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, 0x9c) 271 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS31, 31, 272 1) 273 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS30, 30, 274 1) 275 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS29, 29, 276 1) 277 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS28, 28, 278 1) 279 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS27, 27, 280 1) 281 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS26, 26, 282 1) 283 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS25, 25, 284 1) 285 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS24, 24, 286 1) 287 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS23, 23, 288 1) 289 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS22, 22, 290 1) 291 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS21, 21, 292 1) 293 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS20, 20, 294 1) 295 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS19, 19, 296 1) 297 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS18, 18, 298 1) 299 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS17, 17, 300 1) 301 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS16, 16, 302 1) 303 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS15, 15, 304 1) 305 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS14, 14, 306 1) 307 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS13, 13, 308 1) 309 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS12, 12, 310 1) 311 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS11, 11, 312 1) 313 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS10, 10, 314 1) 315 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS9, 9, 1) 316 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS8, 8, 1) 317 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS7, 7, 1) 318 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS6, 6, 1) 319 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS5, 5, 1) 320 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS4, 4, 1) 321 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS3, 3, 1) 322 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS2, 2, 1) 323 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS1, 1, 1) 324 FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS0, 0, 1) 325 REG32(TX_EVENT_FIFO_STATUS_REGISTER, 0xa0) 326 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, 8, 6) 327 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI, 7, 1) 328 FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, 0, 5) 329 REG32(TX_EVENT_FIFO_WATERMARK_REGISTER, 0xa4) 330 FIELD(TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM, 0, 5) 331 REG32(ACCEPTANCE_FILTER_CONTROL_REGISTER, 0xe0) 332 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF31, 31, 1) 333 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF30, 30, 1) 334 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF29, 29, 1) 335 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF28, 28, 1) 336 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF27, 27, 1) 337 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF26, 26, 1) 338 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF25, 25, 1) 339 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF24, 24, 1) 340 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF23, 23, 1) 341 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF22, 22, 1) 342 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF21, 21, 1) 343 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF20, 20, 1) 344 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF19, 19, 1) 345 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF18, 18, 1) 346 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF17, 17, 1) 347 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF16, 16, 1) 348 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF15, 15, 1) 349 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF14, 14, 1) 350 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF13, 13, 1) 351 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF12, 12, 1) 352 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF11, 11, 1) 353 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF10, 10, 1) 354 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF9, 9, 1) 355 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF8, 8, 1) 356 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF7, 7, 1) 357 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF6, 6, 1) 358 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF5, 5, 1) 359 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF4, 4, 1) 360 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF3, 3, 1) 361 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF2, 2, 1) 362 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF1, 1, 1) 363 FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF0, 0, 1) 364 REG32(RX_FIFO_STATUS_REGISTER, 0xe8) 365 FIELD(RX_FIFO_STATUS_REGISTER, FL_1, 24, 7) 366 FIELD(RX_FIFO_STATUS_REGISTER, IRI_1, 23, 1) 367 FIELD(RX_FIFO_STATUS_REGISTER, RI_1, 16, 6) 368 FIELD(RX_FIFO_STATUS_REGISTER, FL, 8, 7) 369 FIELD(RX_FIFO_STATUS_REGISTER, IRI, 7, 1) 370 FIELD(RX_FIFO_STATUS_REGISTER, RI, 0, 6) 371 REG32(RX_FIFO_WATERMARK_REGISTER, 0xec) 372 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFP, 16, 5) 373 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM_1, 8, 6) 374 FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM, 0, 6) 375 REG32(TB_ID_REGISTER, 0x100) 376 FIELD(TB_ID_REGISTER, ID, 21, 11) 377 FIELD(TB_ID_REGISTER, SRR_RTR_RRS, 20, 1) 378 FIELD(TB_ID_REGISTER, IDE, 19, 1) 379 FIELD(TB_ID_REGISTER, ID_EXT, 1, 18) 380 FIELD(TB_ID_REGISTER, RTR_RRS, 0, 1) 381 REG32(TB0_DLC_REGISTER, 0x104) 382 FIELD(TB0_DLC_REGISTER, DLC, 28, 4) 383 FIELD(TB0_DLC_REGISTER, FDF, 27, 1) 384 FIELD(TB0_DLC_REGISTER, BRS, 26, 1) 385 FIELD(TB0_DLC_REGISTER, RSVD2, 25, 1) 386 FIELD(TB0_DLC_REGISTER, EFC, 24, 1) 387 FIELD(TB0_DLC_REGISTER, MM, 16, 8) 388 FIELD(TB0_DLC_REGISTER, RSVD1, 0, 16) 389 REG32(TB_DW0_REGISTER, 0x108) 390 FIELD(TB_DW0_REGISTER, DATA_BYTES0, 24, 8) 391 FIELD(TB_DW0_REGISTER, DATA_BYTES1, 16, 8) 392 FIELD(TB_DW0_REGISTER, DATA_BYTES2, 8, 8) 393 FIELD(TB_DW0_REGISTER, DATA_BYTES3, 0, 8) 394 REG32(TB_DW1_REGISTER, 0x10c) 395 FIELD(TB_DW1_REGISTER, DATA_BYTES4, 24, 8) 396 FIELD(TB_DW1_REGISTER, DATA_BYTES5, 16, 8) 397 FIELD(TB_DW1_REGISTER, DATA_BYTES6, 8, 8) 398 FIELD(TB_DW1_REGISTER, DATA_BYTES7, 0, 8) 399 REG32(TB_DW2_REGISTER, 0x110) 400 FIELD(TB_DW2_REGISTER, DATA_BYTES8, 24, 8) 401 FIELD(TB_DW2_REGISTER, DATA_BYTES9, 16, 8) 402 FIELD(TB_DW2_REGISTER, DATA_BYTES10, 8, 8) 403 FIELD(TB_DW2_REGISTER, DATA_BYTES11, 0, 8) 404 REG32(TB_DW3_REGISTER, 0x114) 405 FIELD(TB_DW3_REGISTER, DATA_BYTES12, 24, 8) 406 FIELD(TB_DW3_REGISTER, DATA_BYTES13, 16, 8) 407 FIELD(TB_DW3_REGISTER, DATA_BYTES14, 8, 8) 408 FIELD(TB_DW3_REGISTER, DATA_BYTES15, 0, 8) 409 REG32(TB_DW4_REGISTER, 0x118) 410 FIELD(TB_DW4_REGISTER, DATA_BYTES16, 24, 8) 411 FIELD(TB_DW4_REGISTER, DATA_BYTES17, 16, 8) 412 FIELD(TB_DW4_REGISTER, DATA_BYTES18, 8, 8) 413 FIELD(TB_DW4_REGISTER, DATA_BYTES19, 0, 8) 414 REG32(TB_DW5_REGISTER, 0x11c) 415 FIELD(TB_DW5_REGISTER, DATA_BYTES20, 24, 8) 416 FIELD(TB_DW5_REGISTER, DATA_BYTES21, 16, 8) 417 FIELD(TB_DW5_REGISTER, DATA_BYTES22, 8, 8) 418 FIELD(TB_DW5_REGISTER, DATA_BYTES23, 0, 8) 419 REG32(TB_DW6_REGISTER, 0x120) 420 FIELD(TB_DW6_REGISTER, DATA_BYTES24, 24, 8) 421 FIELD(TB_DW6_REGISTER, DATA_BYTES25, 16, 8) 422 FIELD(TB_DW6_REGISTER, DATA_BYTES26, 8, 8) 423 FIELD(TB_DW6_REGISTER, DATA_BYTES27, 0, 8) 424 REG32(TB_DW7_REGISTER, 0x124) 425 FIELD(TB_DW7_REGISTER, DATA_BYTES28, 24, 8) 426 FIELD(TB_DW7_REGISTER, DATA_BYTES29, 16, 8) 427 FIELD(TB_DW7_REGISTER, DATA_BYTES30, 8, 8) 428 FIELD(TB_DW7_REGISTER, DATA_BYTES31, 0, 8) 429 REG32(TB_DW8_REGISTER, 0x128) 430 FIELD(TB_DW8_REGISTER, DATA_BYTES32, 24, 8) 431 FIELD(TB_DW8_REGISTER, DATA_BYTES33, 16, 8) 432 FIELD(TB_DW8_REGISTER, DATA_BYTES34, 8, 8) 433 FIELD(TB_DW8_REGISTER, DATA_BYTES35, 0, 8) 434 REG32(TB_DW9_REGISTER, 0x12c) 435 FIELD(TB_DW9_REGISTER, DATA_BYTES36, 24, 8) 436 FIELD(TB_DW9_REGISTER, DATA_BYTES37, 16, 8) 437 FIELD(TB_DW9_REGISTER, DATA_BYTES38, 8, 8) 438 FIELD(TB_DW9_REGISTER, DATA_BYTES39, 0, 8) 439 REG32(TB_DW10_REGISTER, 0x130) 440 FIELD(TB_DW10_REGISTER, DATA_BYTES40, 24, 8) 441 FIELD(TB_DW10_REGISTER, DATA_BYTES41, 16, 8) 442 FIELD(TB_DW10_REGISTER, DATA_BYTES42, 8, 8) 443 FIELD(TB_DW10_REGISTER, DATA_BYTES43, 0, 8) 444 REG32(TB_DW11_REGISTER, 0x134) 445 FIELD(TB_DW11_REGISTER, DATA_BYTES44, 24, 8) 446 FIELD(TB_DW11_REGISTER, DATA_BYTES45, 16, 8) 447 FIELD(TB_DW11_REGISTER, DATA_BYTES46, 8, 8) 448 FIELD(TB_DW11_REGISTER, DATA_BYTES47, 0, 8) 449 REG32(TB_DW12_REGISTER, 0x138) 450 FIELD(TB_DW12_REGISTER, DATA_BYTES48, 24, 8) 451 FIELD(TB_DW12_REGISTER, DATA_BYTES49, 16, 8) 452 FIELD(TB_DW12_REGISTER, DATA_BYTES50, 8, 8) 453 FIELD(TB_DW12_REGISTER, DATA_BYTES51, 0, 8) 454 REG32(TB_DW13_REGISTER, 0x13c) 455 FIELD(TB_DW13_REGISTER, DATA_BYTES52, 24, 8) 456 FIELD(TB_DW13_REGISTER, DATA_BYTES53, 16, 8) 457 FIELD(TB_DW13_REGISTER, DATA_BYTES54, 8, 8) 458 FIELD(TB_DW13_REGISTER, DATA_BYTES55, 0, 8) 459 REG32(TB_DW14_REGISTER, 0x140) 460 FIELD(TB_DW14_REGISTER, DATA_BYTES56, 24, 8) 461 FIELD(TB_DW14_REGISTER, DATA_BYTES57, 16, 8) 462 FIELD(TB_DW14_REGISTER, DATA_BYTES58, 8, 8) 463 FIELD(TB_DW14_REGISTER, DATA_BYTES59, 0, 8) 464 REG32(TB_DW15_REGISTER, 0x144) 465 FIELD(TB_DW15_REGISTER, DATA_BYTES60, 24, 8) 466 FIELD(TB_DW15_REGISTER, DATA_BYTES61, 16, 8) 467 FIELD(TB_DW15_REGISTER, DATA_BYTES62, 8, 8) 468 FIELD(TB_DW15_REGISTER, DATA_BYTES63, 0, 8) 469 REG32(AFMR_REGISTER, 0xa00) 470 FIELD(AFMR_REGISTER, AMID, 21, 11) 471 FIELD(AFMR_REGISTER, AMSRR, 20, 1) 472 FIELD(AFMR_REGISTER, AMIDE, 19, 1) 473 FIELD(AFMR_REGISTER, AMID_EXT, 1, 18) 474 FIELD(AFMR_REGISTER, AMRTR, 0, 1) 475 REG32(AFIR_REGISTER, 0xa04) 476 FIELD(AFIR_REGISTER, AIID, 21, 11) 477 FIELD(AFIR_REGISTER, AISRR, 20, 1) 478 FIELD(AFIR_REGISTER, AIIDE, 19, 1) 479 FIELD(AFIR_REGISTER, AIID_EXT, 1, 18) 480 FIELD(AFIR_REGISTER, AIRTR, 0, 1) 481 REG32(TXE_FIFO_TB_ID_REGISTER, 0x2000) 482 FIELD(TXE_FIFO_TB_ID_REGISTER, ID, 21, 11) 483 FIELD(TXE_FIFO_TB_ID_REGISTER, SRR_RTR_RRS, 20, 1) 484 FIELD(TXE_FIFO_TB_ID_REGISTER, IDE, 19, 1) 485 FIELD(TXE_FIFO_TB_ID_REGISTER, ID_EXT, 1, 18) 486 FIELD(TXE_FIFO_TB_ID_REGISTER, RTR_RRS, 0, 1) 487 REG32(TXE_FIFO_TB_DLC_REGISTER, 0x2004) 488 FIELD(TXE_FIFO_TB_DLC_REGISTER, DLC, 28, 4) 489 FIELD(TXE_FIFO_TB_DLC_REGISTER, FDF, 27, 1) 490 FIELD(TXE_FIFO_TB_DLC_REGISTER, BRS, 26, 1) 491 FIELD(TXE_FIFO_TB_DLC_REGISTER, ET, 24, 2) 492 FIELD(TXE_FIFO_TB_DLC_REGISTER, MM, 16, 8) 493 FIELD(TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP, 0, 16) 494 REG32(RB_ID_REGISTER, 0x2100) 495 FIELD(RB_ID_REGISTER, ID, 21, 11) 496 FIELD(RB_ID_REGISTER, SRR_RTR_RRS, 20, 1) 497 FIELD(RB_ID_REGISTER, IDE, 19, 1) 498 FIELD(RB_ID_REGISTER, ID_EXT, 1, 18) 499 FIELD(RB_ID_REGISTER, RTR_RRS, 0, 1) 500 REG32(RB_DLC_REGISTER, 0x2104) 501 FIELD(RB_DLC_REGISTER, DLC, 28, 4) 502 FIELD(RB_DLC_REGISTER, FDF, 27, 1) 503 FIELD(RB_DLC_REGISTER, BRS, 26, 1) 504 FIELD(RB_DLC_REGISTER, ESI, 25, 1) 505 FIELD(RB_DLC_REGISTER, MATCHED_FILTER_INDEX, 16, 5) 506 FIELD(RB_DLC_REGISTER, TIMESTAMP, 0, 16) 507 REG32(RB_DW0_REGISTER, 0x2108) 508 FIELD(RB_DW0_REGISTER, DATA_BYTES0, 24, 8) 509 FIELD(RB_DW0_REGISTER, DATA_BYTES1, 16, 8) 510 FIELD(RB_DW0_REGISTER, DATA_BYTES2, 8, 8) 511 FIELD(RB_DW0_REGISTER, DATA_BYTES3, 0, 8) 512 REG32(RB_DW1_REGISTER, 0x210c) 513 FIELD(RB_DW1_REGISTER, DATA_BYTES4, 24, 8) 514 FIELD(RB_DW1_REGISTER, DATA_BYTES5, 16, 8) 515 FIELD(RB_DW1_REGISTER, DATA_BYTES6, 8, 8) 516 FIELD(RB_DW1_REGISTER, DATA_BYTES7, 0, 8) 517 REG32(RB_DW2_REGISTER, 0x2110) 518 FIELD(RB_DW2_REGISTER, DATA_BYTES8, 24, 8) 519 FIELD(RB_DW2_REGISTER, DATA_BYTES9, 16, 8) 520 FIELD(RB_DW2_REGISTER, DATA_BYTES10, 8, 8) 521 FIELD(RB_DW2_REGISTER, DATA_BYTES11, 0, 8) 522 REG32(RB_DW3_REGISTER, 0x2114) 523 FIELD(RB_DW3_REGISTER, DATA_BYTES12, 24, 8) 524 FIELD(RB_DW3_REGISTER, DATA_BYTES13, 16, 8) 525 FIELD(RB_DW3_REGISTER, DATA_BYTES14, 8, 8) 526 FIELD(RB_DW3_REGISTER, DATA_BYTES15, 0, 8) 527 REG32(RB_DW4_REGISTER, 0x2118) 528 FIELD(RB_DW4_REGISTER, DATA_BYTES16, 24, 8) 529 FIELD(RB_DW4_REGISTER, DATA_BYTES17, 16, 8) 530 FIELD(RB_DW4_REGISTER, DATA_BYTES18, 8, 8) 531 FIELD(RB_DW4_REGISTER, DATA_BYTES19, 0, 8) 532 REG32(RB_DW5_REGISTER, 0x211c) 533 FIELD(RB_DW5_REGISTER, DATA_BYTES20, 24, 8) 534 FIELD(RB_DW5_REGISTER, DATA_BYTES21, 16, 8) 535 FIELD(RB_DW5_REGISTER, DATA_BYTES22, 8, 8) 536 FIELD(RB_DW5_REGISTER, DATA_BYTES23, 0, 8) 537 REG32(RB_DW6_REGISTER, 0x2120) 538 FIELD(RB_DW6_REGISTER, DATA_BYTES24, 24, 8) 539 FIELD(RB_DW6_REGISTER, DATA_BYTES25, 16, 8) 540 FIELD(RB_DW6_REGISTER, DATA_BYTES26, 8, 8) 541 FIELD(RB_DW6_REGISTER, DATA_BYTES27, 0, 8) 542 REG32(RB_DW7_REGISTER, 0x2124) 543 FIELD(RB_DW7_REGISTER, DATA_BYTES28, 24, 8) 544 FIELD(RB_DW7_REGISTER, DATA_BYTES29, 16, 8) 545 FIELD(RB_DW7_REGISTER, DATA_BYTES30, 8, 8) 546 FIELD(RB_DW7_REGISTER, DATA_BYTES31, 0, 8) 547 REG32(RB_DW8_REGISTER, 0x2128) 548 FIELD(RB_DW8_REGISTER, DATA_BYTES32, 24, 8) 549 FIELD(RB_DW8_REGISTER, DATA_BYTES33, 16, 8) 550 FIELD(RB_DW8_REGISTER, DATA_BYTES34, 8, 8) 551 FIELD(RB_DW8_REGISTER, DATA_BYTES35, 0, 8) 552 REG32(RB_DW9_REGISTER, 0x212c) 553 FIELD(RB_DW9_REGISTER, DATA_BYTES36, 24, 8) 554 FIELD(RB_DW9_REGISTER, DATA_BYTES37, 16, 8) 555 FIELD(RB_DW9_REGISTER, DATA_BYTES38, 8, 8) 556 FIELD(RB_DW9_REGISTER, DATA_BYTES39, 0, 8) 557 REG32(RB_DW10_REGISTER, 0x2130) 558 FIELD(RB_DW10_REGISTER, DATA_BYTES40, 24, 8) 559 FIELD(RB_DW10_REGISTER, DATA_BYTES41, 16, 8) 560 FIELD(RB_DW10_REGISTER, DATA_BYTES42, 8, 8) 561 FIELD(RB_DW10_REGISTER, DATA_BYTES43, 0, 8) 562 REG32(RB_DW11_REGISTER, 0x2134) 563 FIELD(RB_DW11_REGISTER, DATA_BYTES44, 24, 8) 564 FIELD(RB_DW11_REGISTER, DATA_BYTES45, 16, 8) 565 FIELD(RB_DW11_REGISTER, DATA_BYTES46, 8, 8) 566 FIELD(RB_DW11_REGISTER, DATA_BYTES47, 0, 8) 567 REG32(RB_DW12_REGISTER, 0x2138) 568 FIELD(RB_DW12_REGISTER, DATA_BYTES48, 24, 8) 569 FIELD(RB_DW12_REGISTER, DATA_BYTES49, 16, 8) 570 FIELD(RB_DW12_REGISTER, DATA_BYTES50, 8, 8) 571 FIELD(RB_DW12_REGISTER, DATA_BYTES51, 0, 8) 572 REG32(RB_DW13_REGISTER, 0x213c) 573 FIELD(RB_DW13_REGISTER, DATA_BYTES52, 24, 8) 574 FIELD(RB_DW13_REGISTER, DATA_BYTES53, 16, 8) 575 FIELD(RB_DW13_REGISTER, DATA_BYTES54, 8, 8) 576 FIELD(RB_DW13_REGISTER, DATA_BYTES55, 0, 8) 577 REG32(RB_DW14_REGISTER, 0x2140) 578 FIELD(RB_DW14_REGISTER, DATA_BYTES56, 24, 8) 579 FIELD(RB_DW14_REGISTER, DATA_BYTES57, 16, 8) 580 FIELD(RB_DW14_REGISTER, DATA_BYTES58, 8, 8) 581 FIELD(RB_DW14_REGISTER, DATA_BYTES59, 0, 8) 582 REG32(RB_DW15_REGISTER, 0x2144) 583 FIELD(RB_DW15_REGISTER, DATA_BYTES60, 24, 8) 584 FIELD(RB_DW15_REGISTER, DATA_BYTES61, 16, 8) 585 FIELD(RB_DW15_REGISTER, DATA_BYTES62, 8, 8) 586 FIELD(RB_DW15_REGISTER, DATA_BYTES63, 0, 8) 587 REG32(RB_ID_REGISTER_1, 0x4100) 588 FIELD(RB_ID_REGISTER_1, ID, 21, 11) 589 FIELD(RB_ID_REGISTER_1, SRR_RTR_RRS, 20, 1) 590 FIELD(RB_ID_REGISTER_1, IDE, 19, 1) 591 FIELD(RB_ID_REGISTER_1, ID_EXT, 1, 18) 592 FIELD(RB_ID_REGISTER_1, RTR_RRS, 0, 1) 593 REG32(RB_DLC_REGISTER_1, 0x4104) 594 FIELD(RB_DLC_REGISTER_1, DLC, 28, 4) 595 FIELD(RB_DLC_REGISTER_1, FDF, 27, 1) 596 FIELD(RB_DLC_REGISTER_1, BRS, 26, 1) 597 FIELD(RB_DLC_REGISTER_1, ESI, 25, 1) 598 FIELD(RB_DLC_REGISTER_1, MATCHED_FILTER_INDEX, 16, 5) 599 FIELD(RB_DLC_REGISTER_1, TIMESTAMP, 0, 16) 600 REG32(RB0_DW0_REGISTER_1, 0x4108) 601 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES0, 24, 8) 602 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES1, 16, 8) 603 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES2, 8, 8) 604 FIELD(RB0_DW0_REGISTER_1, DATA_BYTES3, 0, 8) 605 REG32(RB_DW1_REGISTER_1, 0x410c) 606 FIELD(RB_DW1_REGISTER_1, DATA_BYTES4, 24, 8) 607 FIELD(RB_DW1_REGISTER_1, DATA_BYTES5, 16, 8) 608 FIELD(RB_DW1_REGISTER_1, DATA_BYTES6, 8, 8) 609 FIELD(RB_DW1_REGISTER_1, DATA_BYTES7, 0, 8) 610 REG32(RB_DW2_REGISTER_1, 0x4110) 611 FIELD(RB_DW2_REGISTER_1, DATA_BYTES8, 24, 8) 612 FIELD(RB_DW2_REGISTER_1, DATA_BYTES9, 16, 8) 613 FIELD(RB_DW2_REGISTER_1, DATA_BYTES10, 8, 8) 614 FIELD(RB_DW2_REGISTER_1, DATA_BYTES11, 0, 8) 615 REG32(RB_DW3_REGISTER_1, 0x4114) 616 FIELD(RB_DW3_REGISTER_1, DATA_BYTES12, 24, 8) 617 FIELD(RB_DW3_REGISTER_1, DATA_BYTES13, 16, 8) 618 FIELD(RB_DW3_REGISTER_1, DATA_BYTES14, 8, 8) 619 FIELD(RB_DW3_REGISTER_1, DATA_BYTES15, 0, 8) 620 REG32(RB_DW4_REGISTER_1, 0x4118) 621 FIELD(RB_DW4_REGISTER_1, DATA_BYTES16, 24, 8) 622 FIELD(RB_DW4_REGISTER_1, DATA_BYTES17, 16, 8) 623 FIELD(RB_DW4_REGISTER_1, DATA_BYTES18, 8, 8) 624 FIELD(RB_DW4_REGISTER_1, DATA_BYTES19, 0, 8) 625 REG32(RB_DW5_REGISTER_1, 0x411c) 626 FIELD(RB_DW5_REGISTER_1, DATA_BYTES20, 24, 8) 627 FIELD(RB_DW5_REGISTER_1, DATA_BYTES21, 16, 8) 628 FIELD(RB_DW5_REGISTER_1, DATA_BYTES22, 8, 8) 629 FIELD(RB_DW5_REGISTER_1, DATA_BYTES23, 0, 8) 630 REG32(RB_DW6_REGISTER_1, 0x4120) 631 FIELD(RB_DW6_REGISTER_1, DATA_BYTES24, 24, 8) 632 FIELD(RB_DW6_REGISTER_1, DATA_BYTES25, 16, 8) 633 FIELD(RB_DW6_REGISTER_1, DATA_BYTES26, 8, 8) 634 FIELD(RB_DW6_REGISTER_1, DATA_BYTES27, 0, 8) 635 REG32(RB_DW7_REGISTER_1, 0x4124) 636 FIELD(RB_DW7_REGISTER_1, DATA_BYTES28, 24, 8) 637 FIELD(RB_DW7_REGISTER_1, DATA_BYTES29, 16, 8) 638 FIELD(RB_DW7_REGISTER_1, DATA_BYTES30, 8, 8) 639 FIELD(RB_DW7_REGISTER_1, DATA_BYTES31, 0, 8) 640 REG32(RB_DW8_REGISTER_1, 0x4128) 641 FIELD(RB_DW8_REGISTER_1, DATA_BYTES32, 24, 8) 642 FIELD(RB_DW8_REGISTER_1, DATA_BYTES33, 16, 8) 643 FIELD(RB_DW8_REGISTER_1, DATA_BYTES34, 8, 8) 644 FIELD(RB_DW8_REGISTER_1, DATA_BYTES35, 0, 8) 645 REG32(RB_DW9_REGISTER_1, 0x412c) 646 FIELD(RB_DW9_REGISTER_1, DATA_BYTES36, 24, 8) 647 FIELD(RB_DW9_REGISTER_1, DATA_BYTES37, 16, 8) 648 FIELD(RB_DW9_REGISTER_1, DATA_BYTES38, 8, 8) 649 FIELD(RB_DW9_REGISTER_1, DATA_BYTES39, 0, 8) 650 REG32(RB_DW10_REGISTER_1, 0x4130) 651 FIELD(RB_DW10_REGISTER_1, DATA_BYTES40, 24, 8) 652 FIELD(RB_DW10_REGISTER_1, DATA_BYTES41, 16, 8) 653 FIELD(RB_DW10_REGISTER_1, DATA_BYTES42, 8, 8) 654 FIELD(RB_DW10_REGISTER_1, DATA_BYTES43, 0, 8) 655 REG32(RB_DW11_REGISTER_1, 0x4134) 656 FIELD(RB_DW11_REGISTER_1, DATA_BYTES44, 24, 8) 657 FIELD(RB_DW11_REGISTER_1, DATA_BYTES45, 16, 8) 658 FIELD(RB_DW11_REGISTER_1, DATA_BYTES46, 8, 8) 659 FIELD(RB_DW11_REGISTER_1, DATA_BYTES47, 0, 8) 660 REG32(RB_DW12_REGISTER_1, 0x4138) 661 FIELD(RB_DW12_REGISTER_1, DATA_BYTES48, 24, 8) 662 FIELD(RB_DW12_REGISTER_1, DATA_BYTES49, 16, 8) 663 FIELD(RB_DW12_REGISTER_1, DATA_BYTES50, 8, 8) 664 FIELD(RB_DW12_REGISTER_1, DATA_BYTES51, 0, 8) 665 REG32(RB_DW13_REGISTER_1, 0x413c) 666 FIELD(RB_DW13_REGISTER_1, DATA_BYTES52, 24, 8) 667 FIELD(RB_DW13_REGISTER_1, DATA_BYTES53, 16, 8) 668 FIELD(RB_DW13_REGISTER_1, DATA_BYTES54, 8, 8) 669 FIELD(RB_DW13_REGISTER_1, DATA_BYTES55, 0, 8) 670 REG32(RB_DW14_REGISTER_1, 0x4140) 671 FIELD(RB_DW14_REGISTER_1, DATA_BYTES56, 24, 8) 672 FIELD(RB_DW14_REGISTER_1, DATA_BYTES57, 16, 8) 673 FIELD(RB_DW14_REGISTER_1, DATA_BYTES58, 8, 8) 674 FIELD(RB_DW14_REGISTER_1, DATA_BYTES59, 0, 8) 675 REG32(RB_DW15_REGISTER_1, 0x4144) 676 FIELD(RB_DW15_REGISTER_1, DATA_BYTES60, 24, 8) 677 FIELD(RB_DW15_REGISTER_1, DATA_BYTES61, 16, 8) 678 FIELD(RB_DW15_REGISTER_1, DATA_BYTES62, 8, 8) 679 FIELD(RB_DW15_REGISTER_1, DATA_BYTES63, 0, 8) 680 681 static uint8_t canfd_dlc_array[8] = {8, 12, 16, 20, 24, 32, 48, 64}; 682 683 static void canfd_update_irq(XlnxVersalCANFDState *s) 684 { 685 const bool irq = (s->regs[R_INTERRUPT_STATUS_REGISTER] & 686 s->regs[R_INTERRUPT_ENABLE_REGISTER]) != 0; 687 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 688 689 /* RX watermark interrupts. */ 690 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL) > 691 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM)) { 692 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); 693 } 694 695 if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1) > 696 ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM_1)) { 697 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 1); 698 } 699 700 /* TX watermark interrupt. */ 701 if (ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL) > 702 ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM)) { 703 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEWMFLL, 1); 704 } 705 706 trace_xlnx_canfd_update_irq(path, s->regs[R_INTERRUPT_STATUS_REGISTER], 707 s->regs[R_INTERRUPT_ENABLE_REGISTER], irq); 708 709 qemu_set_irq(s->irq_canfd_int, irq); 710 } 711 712 static void canfd_ier_post_write(RegisterInfo *reg, uint64_t val64) 713 { 714 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 715 716 canfd_update_irq(s); 717 } 718 719 static uint64_t canfd_icr_pre_write(RegisterInfo *reg, uint64_t val64) 720 { 721 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 722 uint32_t val = val64; 723 724 s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val; 725 726 /* 727 * RXBOFLW_BI field is automatically cleared to default if RXBOFLW bit is 728 * cleared in ISR. 729 */ 730 if (ARRAY_FIELD_EX32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1)) { 731 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 0); 732 } 733 734 canfd_update_irq(s); 735 736 return 0; 737 } 738 739 static void canfd_config_reset(XlnxVersalCANFDState *s) 740 { 741 742 unsigned int i; 743 744 /* Reset all the configuration registers. */ 745 for (i = 0; i < R_RX_FIFO_WATERMARK_REGISTER; ++i) { 746 register_reset(&s->reg_info[i]); 747 } 748 749 canfd_update_irq(s); 750 } 751 752 static void canfd_config_mode(XlnxVersalCANFDState *s) 753 { 754 register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]); 755 register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]); 756 register_reset(&s->reg_info[R_STATUS_REGISTER]); 757 758 /* Put XlnxVersalCANFDState in configuration mode. */ 759 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); 760 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); 761 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); 762 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); 763 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR_BIT, 0); 764 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 0); 765 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 0); 766 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0); 767 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0); 768 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0); 769 770 /* Clear the time stamp. */ 771 ptimer_transaction_begin(s->canfd_timer); 772 ptimer_set_count(s->canfd_timer, 0); 773 ptimer_transaction_commit(s->canfd_timer); 774 775 canfd_update_irq(s); 776 } 777 778 static void update_status_register_mode_bits(XlnxVersalCANFDState *s) 779 { 780 bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP); 781 bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP); 782 /* Wake up interrupt bit. */ 783 bool wakeup_irq_val = !sleep_mode && sleep_status; 784 /* Sleep interrupt bit. */ 785 bool sleep_irq_val = sleep_mode && !sleep_status; 786 787 /* Clear previous core mode status bits. */ 788 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); 789 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); 790 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); 791 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); 792 793 /* set current mode bit and generate irqs accordingly. */ 794 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { 795 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); 796 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) { 797 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); 798 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 799 sleep_irq_val); 800 } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { 801 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1); 802 } else { 803 /* If all bits are zero, XlnxVersalCANFDState is set in normal mode. */ 804 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1); 805 /* Set wakeup interrupt bit. */ 806 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 807 wakeup_irq_val); 808 } 809 810 /* Put the CANFD in error active state. */ 811 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ESTAT, 1); 812 813 canfd_update_irq(s); 814 } 815 816 static uint64_t canfd_msr_pre_write(RegisterInfo *reg, uint64_t val64) 817 { 818 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 819 uint32_t val = val64; 820 uint8_t multi_mode = 0; 821 822 /* 823 * Multiple mode set check. This is done to make sure user doesn't set 824 * multiple modes. 825 */ 826 multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) + 827 FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) + 828 FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP); 829 830 if (multi_mode > 1) { 831 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to configure several modes" 832 " simultaneously. One mode will be selected according to" 833 " their priority: LBACK > SLEEP > SNOOP.\n"); 834 } 835 836 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { 837 /* In configuration mode, any mode can be selected. */ 838 s->regs[R_MODE_SELECT_REGISTER] = val; 839 } else { 840 bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP); 841 842 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit); 843 844 if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) { 845 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set LBACK mode" 846 " without setting CEN bit as 0\n"); 847 } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) { 848 qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set SNOOP mode" 849 " without setting CEN bit as 0\n"); 850 } 851 852 update_status_register_mode_bits(s); 853 } 854 855 return s->regs[R_MODE_SELECT_REGISTER]; 856 } 857 858 static void canfd_exit_sleep_mode(XlnxVersalCANFDState *s) 859 { 860 ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0); 861 update_status_register_mode_bits(s); 862 } 863 864 static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame, 865 uint32_t reg_num) 866 { 867 uint32_t i = 0; 868 uint32_t j = 0; 869 uint32_t val = 0; 870 uint32_t dlc_reg_val = 0; 871 uint32_t dlc_value = 0; 872 uint32_t id_reg_val = 0; 873 bool is_rtr = false; 874 875 frame->flags = 0; 876 877 /* Check that reg_num should be within TX register space. */ 878 assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * 879 s->cfg.tx_fifo)); 880 881 dlc_reg_val = s->regs[reg_num + 1]; 882 dlc_value = FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, DLC); 883 884 id_reg_val = s->regs[reg_num]; 885 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, IDE)) { 886 frame->can_id = (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID) << 18) | 887 (FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID_EXT)) | 888 QEMU_CAN_EFF_FLAG; 889 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, RTR_RRS)) { 890 is_rtr = true; 891 } 892 } else { 893 frame->can_id = FIELD_EX32(id_reg_val, TB_ID_REGISTER, ID); 894 if (FIELD_EX32(id_reg_val, TB_ID_REGISTER, SRR_RTR_RRS)) { 895 is_rtr = true; 896 } 897 } 898 899 if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) { 900 /* 901 * CANFD frame. 902 * Converting dlc(0 to 15) 4 Byte data to plain length(i.e. 0 to 64) 903 * 1 Byte data. This is done to make it work with SocketCAN. 904 * On actual CANFD frame, this value can't be more than 0xF. 905 * Conversion table for DLC to plain length: 906 * 907 * DLC Plain Length 908 * 0 - 8 0 - 8 909 * 9 9 - 12 910 * 10 13 - 16 911 * 11 17 - 20 912 * 12 21 - 24 913 * 13 25 - 32 914 * 14 33 - 48 915 * 15 49 - 64 916 */ 917 918 frame->flags |= QEMU_CAN_FRMF_TYPE_FD; 919 920 if (dlc_value < 8) { 921 frame->can_dlc = dlc_value; 922 } else { 923 assert((dlc_value - 8) < ARRAY_SIZE(canfd_dlc_array)); 924 frame->can_dlc = canfd_dlc_array[dlc_value - 8]; 925 } 926 927 if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, BRS)) { 928 frame->flags |= QEMU_CAN_FRMF_BRS; 929 } 930 } else { 931 /* 932 * FD Format bit not set that means it is a CAN Frame. 933 * Conversion table for classic CAN: 934 * 935 * DLC Plain Length 936 * 0 - 7 0 - 7 937 * 8 - 15 8 938 */ 939 940 if (dlc_value > 8) { 941 frame->can_dlc = 8; 942 qemu_log_mask(LOG_GUEST_ERROR, "Maximum DLC value for Classic CAN" 943 " frame is 8. Only 8 byte data will be sent.\n"); 944 } else { 945 frame->can_dlc = dlc_value; 946 } 947 948 if (is_rtr) { 949 frame->can_id |= QEMU_CAN_RTR_FLAG; 950 } 951 } 952 953 for (j = 0; j < frame->can_dlc; j++) { 954 val = 8 * (3 - i); 955 956 frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8); 957 i++; 958 959 if (i % 4 == 0) { 960 i = 0; 961 } 962 } 963 } 964 965 static void process_cancellation_requests(XlnxVersalCANFDState *s) 966 { 967 uint32_t clear_mask = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] & 968 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER]; 969 970 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &= ~clear_mask; 971 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] &= ~clear_mask; 972 973 canfd_update_irq(s); 974 } 975 976 static uint32_t frame_to_reg_id(const qemu_can_frame *frame) 977 { 978 uint32_t id_reg_val = 0; 979 const bool is_canfd_frame = frame->flags & QEMU_CAN_FRMF_TYPE_FD; 980 const bool is_rtr = !is_canfd_frame && (frame->can_id & QEMU_CAN_RTR_FLAG); 981 982 if (frame->can_id & QEMU_CAN_EFF_FLAG) { 983 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, 984 (frame->can_id & QEMU_CAN_EFF_MASK) >> 18); 985 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID_EXT, 986 frame->can_id & QEMU_CAN_EFF_MASK); 987 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, IDE, 1); 988 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); 989 if (is_rtr) { 990 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, RTR_RRS, 1); 991 } 992 } else { 993 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, 994 frame->can_id & QEMU_CAN_SFF_MASK); 995 if (is_rtr) { 996 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); 997 } 998 } 999 1000 return id_reg_val; 1001 } 1002 1003 static void store_rx_sequential(XlnxVersalCANFDState *s, 1004 const qemu_can_frame *frame, 1005 uint32_t fill_level, uint32_t read_index, 1006 uint32_t store_location, uint8_t rx_fifo, 1007 bool rx_fifo_id, uint8_t filter_index) 1008 { 1009 int i; 1010 bool is_canfd_frame; 1011 uint8_t dlc = frame->can_dlc; 1012 uint8_t rx_reg_num = 0; 1013 uint32_t dlc_reg_val = 0; 1014 uint32_t data_reg_val = 0; 1015 1016 /* Getting RX0/1 fill level */ 1017 if ((fill_level) > rx_fifo - 1) { 1018 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1019 1020 qemu_log_mask(LOG_GUEST_ERROR, "%s: RX%d Buffer is full. Discarding the" 1021 " message\n", path, rx_fifo_id); 1022 1023 /* Set the corresponding RF buffer overflow interrupt. */ 1024 if (rx_fifo_id == 0) { 1025 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 1); 1026 } else { 1027 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 1); 1028 } 1029 } else { 1030 uint16_t rx_timestamp = CANFD_TIMER_MAX - 1031 ptimer_get_count(s->canfd_timer); 1032 1033 if (rx_timestamp == 0xFFFF) { 1034 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 1); 1035 } else { 1036 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, 1037 rx_timestamp); 1038 } 1039 1040 if (rx_fifo_id == 0) { 1041 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL, 1042 fill_level + 1); 1043 assert(store_location <= 1044 R_RB_ID_REGISTER + (s->cfg.rx0_fifo * 1045 NUM_REGS_PER_MSG_SPACE)); 1046 } else { 1047 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1, 1048 fill_level + 1); 1049 assert(store_location <= 1050 R_RB_ID_REGISTER_1 + (s->cfg.rx1_fifo * 1051 NUM_REGS_PER_MSG_SPACE)); 1052 } 1053 1054 s->regs[store_location] = frame_to_reg_id(frame); 1055 1056 dlc = frame->can_dlc; 1057 1058 if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { 1059 is_canfd_frame = true; 1060 1061 /* Store dlc value in Xilinx specific format. */ 1062 for (i = 0; i < ARRAY_SIZE(canfd_dlc_array); i++) { 1063 if (canfd_dlc_array[i] == frame->can_dlc) { 1064 dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 + i); 1065 } 1066 } 1067 1068 if (frame->flags & QEMU_CAN_FRMF_BRS) { 1069 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1); 1070 } 1071 if (frame->flags & QEMU_CAN_FRMF_ESI) { 1072 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, ESI, 1); 1073 } 1074 } else { 1075 is_canfd_frame = false; 1076 1077 if (frame->can_dlc > 8) { 1078 dlc = 8; 1079 } 1080 1081 dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, dlc); 1082 } 1083 1084 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, is_canfd_frame); 1085 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, TIMESTAMP, rx_timestamp); 1086 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, MATCHED_FILTER_INDEX, 1087 filter_index); 1088 s->regs[store_location + 1] = dlc_reg_val; 1089 1090 for (i = 0; i < dlc; i++) { 1091 /* Register size is 4 byte but frame->data each is 1 byte. */ 1092 switch (i % 4) { 1093 case 0: 1094 rx_reg_num = i / 4; 1095 1096 data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0, 1097 frame->data[i]); 1098 break; 1099 case 1: 1100 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES1, 1101 frame->data[i]); 1102 break; 1103 case 2: 1104 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2, 1105 frame->data[i]); 1106 break; 1107 case 3: 1108 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3, 1109 frame->data[i]); 1110 /* 1111 * Last Bytes data which means we have all 4 bytes ready to 1112 * store in one rx regs. 1113 */ 1114 s->regs[store_location + rx_reg_num + 2] = data_reg_val; 1115 break; 1116 } 1117 } 1118 1119 if (i % 4) { 1120 /* 1121 * In case DLC is not multiplier of 4, data is not saved to RX FIFO 1122 * in above switch case. Store the remaining bytes here. 1123 */ 1124 s->regs[store_location + rx_reg_num + 2] = data_reg_val; 1125 } 1126 1127 /* set the interrupt as RXOK. */ 1128 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); 1129 } 1130 } 1131 1132 static void update_rx_sequential(XlnxVersalCANFDState *s, 1133 const qemu_can_frame *frame) 1134 { 1135 bool filter_pass = false; 1136 uint8_t filter_index = 0; 1137 int i; 1138 int filter_partition = ARRAY_FIELD_EX32(s->regs, 1139 RX_FIFO_WATERMARK_REGISTER, RXFP); 1140 uint32_t store_location; 1141 uint32_t fill_level; 1142 uint32_t read_index; 1143 uint8_t store_index = 0; 1144 g_autofree char *path = NULL; 1145 /* 1146 * If all UAF bits are set to 0, then received messages are not stored 1147 * in the RX buffers. 1148 */ 1149 if (s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]) { 1150 uint32_t acceptance_filter_status = 1151 s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]; 1152 const uint32_t reg_id = frame_to_reg_id(frame); 1153 1154 for (i = 0; i < 32; i++) { 1155 if (acceptance_filter_status & 0x1) { 1156 uint32_t msg_id_masked = s->regs[R_AFMR_REGISTER + 2 * i] & 1157 reg_id; 1158 uint32_t afir_id_masked = s->regs[R_AFIR_REGISTER + 2 * i] & 1159 s->regs[R_AFMR_REGISTER + 2 * i]; 1160 uint16_t std_msg_id_masked = FIELD_EX32(msg_id_masked, 1161 AFIR_REGISTER, AIID); 1162 uint16_t std_afir_id_masked = FIELD_EX32(afir_id_masked, 1163 AFIR_REGISTER, AIID); 1164 uint32_t ext_msg_id_masked = FIELD_EX32(msg_id_masked, 1165 AFIR_REGISTER, 1166 AIID_EXT); 1167 uint32_t ext_afir_id_masked = FIELD_EX32(afir_id_masked, 1168 AFIR_REGISTER, 1169 AIID_EXT); 1170 bool ext_ide = FIELD_EX32(s->regs[R_AFMR_REGISTER + 2 * i], 1171 AFMR_REGISTER, AMIDE); 1172 1173 if (std_msg_id_masked == std_afir_id_masked) { 1174 if (ext_ide) { 1175 /* Extended message ID message. */ 1176 if (ext_msg_id_masked == ext_afir_id_masked) { 1177 filter_pass = true; 1178 filter_index = i; 1179 1180 break; 1181 } 1182 } else { 1183 /* Standard message ID. */ 1184 filter_pass = true; 1185 filter_index = i; 1186 1187 break; 1188 } 1189 } 1190 } 1191 acceptance_filter_status >>= 1; 1192 } 1193 } 1194 1195 if (!filter_pass) { 1196 path = object_get_canonical_path(OBJECT(s)); 1197 1198 trace_xlnx_canfd_rx_fifo_filter_reject(path, frame->can_id, 1199 frame->can_dlc); 1200 } else { 1201 if (filter_index <= filter_partition) { 1202 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL); 1203 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, RI); 1204 store_index = read_index + fill_level; 1205 1206 if (read_index == s->cfg.rx0_fifo - 1) { 1207 /* 1208 * When ri is s->cfg.rx0_fifo - 1 i.e. max, it goes cyclic that 1209 * means we reset the ri to 0x0. 1210 */ 1211 read_index = 0; 1212 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI, 1213 read_index); 1214 } 1215 1216 if (store_index > s->cfg.rx0_fifo - 1) { 1217 store_index -= s->cfg.rx0_fifo - 1; 1218 } 1219 1220 store_location = R_RB_ID_REGISTER + 1221 (store_index * NUM_REGS_PER_MSG_SPACE); 1222 1223 store_rx_sequential(s, frame, fill_level, read_index, 1224 store_location, s->cfg.rx0_fifo, 0, 1225 filter_index); 1226 } else { 1227 /* RX 1 fill level message */ 1228 fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, 1229 FL_1); 1230 read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, 1231 RI_1); 1232 store_index = read_index + fill_level; 1233 1234 if (read_index == s->cfg.rx1_fifo - 1) { 1235 /* 1236 * When ri is s->cfg.rx1_fifo - 1 i.e. max, it goes cyclic that 1237 * means we reset the ri to 0x0. 1238 */ 1239 read_index = 0; 1240 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1, 1241 read_index); 1242 } 1243 1244 if (store_index > s->cfg.rx1_fifo - 1) { 1245 store_index -= s->cfg.rx1_fifo - 1; 1246 } 1247 1248 store_location = R_RB_ID_REGISTER_1 + 1249 (store_index * NUM_REGS_PER_MSG_SPACE); 1250 1251 store_rx_sequential(s, frame, fill_level, read_index, 1252 store_location, s->cfg.rx1_fifo, 1, 1253 filter_index); 1254 } 1255 1256 path = object_get_canonical_path(OBJECT(s)); 1257 1258 trace_xlnx_canfd_rx_data(path, frame->can_id, frame->can_dlc, 1259 frame->flags); 1260 canfd_update_irq(s); 1261 } 1262 } 1263 1264 static bool tx_ready_check(XlnxVersalCANFDState *s) 1265 { 1266 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { 1267 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1268 1269 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while" 1270 " XlnxVersalCANFDState is in reset mode\n", path); 1271 1272 return false; 1273 } 1274 1275 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { 1276 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1277 1278 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while" 1279 " XlnxVersalCANFDState is in configuration mode." 1280 " Reset the core so operations can start fresh\n", 1281 path); 1282 return false; 1283 } 1284 1285 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { 1286 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1287 1288 qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while" 1289 " XlnxVersalCANFDState is in SNOOP MODE\n", 1290 path); 1291 return false; 1292 } 1293 1294 return true; 1295 } 1296 1297 static void tx_fifo_stamp(XlnxVersalCANFDState *s, uint32_t tb0_regid) 1298 { 1299 /* 1300 * If EFC bit in DLC message is set, this means we will store the 1301 * event of this transmitted message with time stamp. 1302 */ 1303 uint32_t dlc_reg_val = 0; 1304 1305 if (FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, EFC)) { 1306 uint8_t dlc_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, 1307 DLC); 1308 bool fdf_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, 1309 FDF); 1310 bool brs_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, 1311 BRS); 1312 uint8_t mm_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, 1313 MM); 1314 uint8_t fill_level = ARRAY_FIELD_EX32(s->regs, 1315 TX_EVENT_FIFO_STATUS_REGISTER, 1316 TXE_FL); 1317 uint8_t read_index = ARRAY_FIELD_EX32(s->regs, 1318 TX_EVENT_FIFO_STATUS_REGISTER, 1319 TXE_RI); 1320 uint8_t store_index = fill_level + read_index; 1321 1322 if ((fill_level) > s->cfg.tx_fifo - 1) { 1323 qemu_log_mask(LOG_GUEST_ERROR, "TX Event Buffer is full." 1324 " Discarding the message\n"); 1325 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEOFLW, 1); 1326 } else { 1327 if (read_index == s->cfg.tx_fifo - 1) { 1328 /* 1329 * When ri is s->cfg.tx_fifo - 1 i.e. max, it goes cyclic that 1330 * means we reset the ri to 0x0. 1331 */ 1332 read_index = 0; 1333 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, 1334 read_index); 1335 } 1336 1337 if (store_index > s->cfg.tx_fifo - 1) { 1338 store_index -= s->cfg.tx_fifo - 1; 1339 } 1340 1341 assert(store_index < s->cfg.tx_fifo); 1342 1343 uint32_t tx_event_reg0_id = R_TXE_FIFO_TB_ID_REGISTER + 1344 (store_index * 2); 1345 1346 /* Store message ID in TX event register. */ 1347 s->regs[tx_event_reg0_id] = s->regs[tb0_regid]; 1348 1349 uint16_t tx_timestamp = CANFD_TIMER_MAX - 1350 ptimer_get_count(s->canfd_timer); 1351 1352 /* Store DLC with time stamp in DLC regs. */ 1353 dlc_reg_val = FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, DLC, dlc_val); 1354 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, FDF, 1355 fdf_val); 1356 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, BRS, 1357 brs_val); 1358 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, ET, 0x3); 1359 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, MM, mm_val); 1360 dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP, 1361 tx_timestamp); 1362 s->regs[tx_event_reg0_id + 1] = dlc_reg_val; 1363 1364 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, 1365 fill_level + 1); 1366 } 1367 } 1368 } 1369 1370 static gint g_cmp_ids(gconstpointer data1, gconstpointer data2) 1371 { 1372 tx_ready_reg_info *tx_reg_1 = (tx_ready_reg_info *) data1; 1373 tx_ready_reg_info *tx_reg_2 = (tx_ready_reg_info *) data2; 1374 1375 if (tx_reg_1->can_id == tx_reg_2->can_id) { 1376 return (tx_reg_1->reg_num < tx_reg_2->reg_num) ? -1 : 1; 1377 } 1378 return (tx_reg_1->can_id < tx_reg_2->can_id) ? -1 : 1; 1379 } 1380 1381 static void free_list(GSList *list) 1382 { 1383 GSList *iterator = NULL; 1384 1385 for (iterator = list; iterator != NULL; iterator = iterator->next) { 1386 g_free((tx_ready_reg_info *)iterator->data); 1387 } 1388 1389 g_slist_free(list); 1390 1391 return; 1392 } 1393 1394 static GSList *prepare_tx_data(XlnxVersalCANFDState *s) 1395 { 1396 uint8_t i = 0; 1397 GSList *list = NULL; 1398 uint32_t reg_num = 0; 1399 uint32_t reg_ready = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER]; 1400 1401 /* First find the messages which are ready for transmission. */ 1402 for (i = 0; i < s->cfg.tx_fifo; i++) { 1403 if (reg_ready & 1) { 1404 reg_num = R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * i); 1405 tx_ready_reg_info *temp = g_new(tx_ready_reg_info, 1); 1406 1407 temp->can_id = s->regs[reg_num]; 1408 temp->reg_num = reg_num; 1409 list = g_slist_prepend(list, temp); 1410 list = g_slist_sort(list, g_cmp_ids); 1411 } 1412 1413 reg_ready >>= 1; 1414 } 1415 1416 s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] = 0; 1417 s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] = 0; 1418 1419 return list; 1420 } 1421 1422 static void transfer_data(XlnxVersalCANFDState *s) 1423 { 1424 bool canfd_tx = tx_ready_check(s); 1425 GSList *list, *iterator = NULL; 1426 qemu_can_frame frame; 1427 1428 if (!canfd_tx) { 1429 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1430 1431 qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller not enabled for data" 1432 " transfer\n", path); 1433 return; 1434 } 1435 1436 list = prepare_tx_data(s); 1437 if (list == NULL) { 1438 return; 1439 } 1440 1441 for (iterator = list; iterator != NULL; iterator = iterator->next) { 1442 regs2frame(s, &frame, 1443 ((tx_ready_reg_info *)iterator->data)->reg_num); 1444 1445 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { 1446 update_rx_sequential(s, &frame); 1447 tx_fifo_stamp(s, ((tx_ready_reg_info *)iterator->data)->reg_num); 1448 1449 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); 1450 } else { 1451 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1452 1453 trace_xlnx_canfd_tx_data(path, frame.can_id, frame.can_dlc, 1454 frame.flags); 1455 can_bus_client_send(&s->bus_client, &frame, 1); 1456 tx_fifo_stamp(s, 1457 ((tx_ready_reg_info *)iterator->data)->reg_num); 1458 1459 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXRRS, 1); 1460 1461 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) { 1462 canfd_exit_sleep_mode(s); 1463 } 1464 } 1465 } 1466 1467 ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1); 1468 free_list(list); 1469 1470 canfd_update_irq(s); 1471 } 1472 1473 static uint64_t canfd_srr_pre_write(RegisterInfo *reg, uint64_t val64) 1474 { 1475 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1476 uint32_t val = val64; 1477 1478 ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN, 1479 FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN)); 1480 1481 if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) { 1482 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1483 1484 trace_xlnx_canfd_reset(path, val64); 1485 1486 /* First, core will do software reset then will enter in config mode. */ 1487 canfd_config_reset(s); 1488 } else if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { 1489 canfd_config_mode(s); 1490 } else { 1491 /* 1492 * Leave config mode. Now XlnxVersalCANFD core will enter Normal, Sleep, 1493 * snoop or Loopback mode depending upon LBACK, SLEEP, SNOOP register 1494 * states. 1495 */ 1496 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0); 1497 1498 ptimer_transaction_begin(s->canfd_timer); 1499 ptimer_set_count(s->canfd_timer, 0); 1500 ptimer_transaction_commit(s->canfd_timer); 1501 update_status_register_mode_bits(s); 1502 transfer_data(s); 1503 } 1504 1505 return s->regs[R_SOFTWARE_RESET_REGISTER]; 1506 } 1507 1508 static uint64_t filter_mask(RegisterInfo *reg, uint64_t val64) 1509 { 1510 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1511 uint32_t reg_idx = (reg->access->addr) / 4; 1512 uint32_t val = val64; 1513 uint32_t filter_offset = (reg_idx - R_AFMR_REGISTER) / 2; 1514 1515 if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & 1516 (1 << filter_offset))) { 1517 s->regs[reg_idx] = val; 1518 } else { 1519 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1520 1521 qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabled\n", 1522 path, filter_offset + 1); 1523 } 1524 1525 return s->regs[reg_idx]; 1526 } 1527 1528 static uint64_t filter_id(RegisterInfo *reg, uint64_t val64) 1529 { 1530 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1531 hwaddr reg_idx = (reg->access->addr) / 4; 1532 uint32_t val = val64; 1533 uint32_t filter_offset = (reg_idx - R_AFIR_REGISTER) / 2; 1534 1535 if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] & 1536 (1 << filter_offset))) { 1537 s->regs[reg_idx] = val; 1538 } else { 1539 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1540 1541 qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabled\n", 1542 path, filter_offset + 1); 1543 } 1544 1545 return s->regs[reg_idx]; 1546 } 1547 1548 static uint64_t canfd_tx_fifo_status_prew(RegisterInfo *reg, uint64_t val64) 1549 { 1550 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1551 uint32_t val = val64; 1552 uint8_t read_ind = 0; 1553 uint8_t fill_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, 1554 TXE_FL); 1555 1556 if (FIELD_EX32(val, TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI) && fill_ind) { 1557 read_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, 1558 TXE_RI) + 1; 1559 1560 if (read_ind > s->cfg.tx_fifo - 1) { 1561 read_ind = 0; 1562 } 1563 1564 /* 1565 * Increase the read index by 1 and decrease the fill level by 1. 1566 */ 1567 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, 1568 read_ind); 1569 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, 1570 fill_ind - 1); 1571 } 1572 1573 return s->regs[R_TX_EVENT_FIFO_STATUS_REGISTER]; 1574 } 1575 1576 static uint64_t canfd_rx_fifo_status_prew(RegisterInfo *reg, uint64_t val64) 1577 { 1578 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1579 uint32_t val = val64; 1580 uint8_t read_ind = 0; 1581 uint8_t fill_ind = 0; 1582 1583 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI)) { 1584 /* FL index is zero, setting IRI bit has no effect. */ 1585 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) != 0) { 1586 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI) + 1; 1587 1588 if (read_ind > s->cfg.rx0_fifo - 1) { 1589 read_ind = 0; 1590 } 1591 1592 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) - 1; 1593 1594 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI, read_ind); 1595 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL, fill_ind); 1596 } 1597 } 1598 1599 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI_1)) { 1600 /* FL_1 index is zero, setting IRI_1 bit has no effect. */ 1601 if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) != 0) { 1602 read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI_1) + 1; 1603 1604 if (read_ind > s->cfg.rx1_fifo - 1) { 1605 read_ind = 0; 1606 } 1607 1608 fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) - 1; 1609 1610 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1, read_ind); 1611 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1, fill_ind); 1612 } 1613 } 1614 1615 return s->regs[R_RX_FIFO_STATUS_REGISTER]; 1616 } 1617 1618 static uint64_t canfd_tsr_pre_write(RegisterInfo *reg, uint64_t val64) 1619 { 1620 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1621 uint32_t val = val64; 1622 1623 if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) { 1624 ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, 0); 1625 ptimer_transaction_begin(s->canfd_timer); 1626 ptimer_set_count(s->canfd_timer, 0); 1627 ptimer_transaction_commit(s->canfd_timer); 1628 } 1629 1630 return 0; 1631 } 1632 1633 static uint64_t canfd_trr_reg_prew(RegisterInfo *reg, uint64_t val64) 1634 { 1635 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1636 1637 if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { 1638 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 1639 1640 qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in SNOOP mode." 1641 " tx_ready_register will stay in reset mode\n", path); 1642 return 0; 1643 } else { 1644 return val64; 1645 } 1646 } 1647 1648 static void canfd_trr_reg_postw(RegisterInfo *reg, uint64_t val64) 1649 { 1650 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1651 1652 transfer_data(s); 1653 } 1654 1655 static void canfd_cancel_reg_postw(RegisterInfo *reg, uint64_t val64) 1656 { 1657 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1658 1659 process_cancellation_requests(s); 1660 } 1661 1662 static uint64_t canfd_write_check_prew(RegisterInfo *reg, uint64_t val64) 1663 { 1664 XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque); 1665 uint32_t val = val64; 1666 1667 if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) { 1668 return val; 1669 } 1670 return 0; 1671 } 1672 1673 static const RegisterAccessInfo canfd_tx_regs[] = { 1674 { .name = "TB_ID_REGISTER", .addr = A_TB_ID_REGISTER, 1675 },{ .name = "TB0_DLC_REGISTER", .addr = A_TB0_DLC_REGISTER, 1676 },{ .name = "TB_DW0_REGISTER", .addr = A_TB_DW0_REGISTER, 1677 },{ .name = "TB_DW1_REGISTER", .addr = A_TB_DW1_REGISTER, 1678 },{ .name = "TB_DW2_REGISTER", .addr = A_TB_DW2_REGISTER, 1679 },{ .name = "TB_DW3_REGISTER", .addr = A_TB_DW3_REGISTER, 1680 },{ .name = "TB_DW4_REGISTER", .addr = A_TB_DW4_REGISTER, 1681 },{ .name = "TB_DW5_REGISTER", .addr = A_TB_DW5_REGISTER, 1682 },{ .name = "TB_DW6_REGISTER", .addr = A_TB_DW6_REGISTER, 1683 },{ .name = "TB_DW7_REGISTER", .addr = A_TB_DW7_REGISTER, 1684 },{ .name = "TB_DW8_REGISTER", .addr = A_TB_DW8_REGISTER, 1685 },{ .name = "TB_DW9_REGISTER", .addr = A_TB_DW9_REGISTER, 1686 },{ .name = "TB_DW10_REGISTER", .addr = A_TB_DW10_REGISTER, 1687 },{ .name = "TB_DW11_REGISTER", .addr = A_TB_DW11_REGISTER, 1688 },{ .name = "TB_DW12_REGISTER", .addr = A_TB_DW12_REGISTER, 1689 },{ .name = "TB_DW13_REGISTER", .addr = A_TB_DW13_REGISTER, 1690 },{ .name = "TB_DW14_REGISTER", .addr = A_TB_DW14_REGISTER, 1691 },{ .name = "TB_DW15_REGISTER", .addr = A_TB_DW15_REGISTER, 1692 } 1693 }; 1694 1695 static const RegisterAccessInfo canfd_rx0_regs[] = { 1696 { .name = "RB_ID_REGISTER", .addr = A_RB_ID_REGISTER, 1697 .ro = 0xffffffff, 1698 },{ .name = "RB_DLC_REGISTER", .addr = A_RB_DLC_REGISTER, 1699 .ro = 0xfe1fffff, 1700 },{ .name = "RB_DW0_REGISTER", .addr = A_RB_DW0_REGISTER, 1701 .ro = 0xffffffff, 1702 },{ .name = "RB_DW1_REGISTER", .addr = A_RB_DW1_REGISTER, 1703 .ro = 0xffffffff, 1704 },{ .name = "RB_DW2_REGISTER", .addr = A_RB_DW2_REGISTER, 1705 .ro = 0xffffffff, 1706 },{ .name = "RB_DW3_REGISTER", .addr = A_RB_DW3_REGISTER, 1707 .ro = 0xffffffff, 1708 },{ .name = "RB_DW4_REGISTER", .addr = A_RB_DW4_REGISTER, 1709 .ro = 0xffffffff, 1710 },{ .name = "RB_DW5_REGISTER", .addr = A_RB_DW5_REGISTER, 1711 .ro = 0xffffffff, 1712 },{ .name = "RB_DW6_REGISTER", .addr = A_RB_DW6_REGISTER, 1713 .ro = 0xffffffff, 1714 },{ .name = "RB_DW7_REGISTER", .addr = A_RB_DW7_REGISTER, 1715 .ro = 0xffffffff, 1716 },{ .name = "RB_DW8_REGISTER", .addr = A_RB_DW8_REGISTER, 1717 .ro = 0xffffffff, 1718 },{ .name = "RB_DW9_REGISTER", .addr = A_RB_DW9_REGISTER, 1719 .ro = 0xffffffff, 1720 },{ .name = "RB_DW10_REGISTER", .addr = A_RB_DW10_REGISTER, 1721 .ro = 0xffffffff, 1722 },{ .name = "RB_DW11_REGISTER", .addr = A_RB_DW11_REGISTER, 1723 .ro = 0xffffffff, 1724 },{ .name = "RB_DW12_REGISTER", .addr = A_RB_DW12_REGISTER, 1725 .ro = 0xffffffff, 1726 },{ .name = "RB_DW13_REGISTER", .addr = A_RB_DW13_REGISTER, 1727 .ro = 0xffffffff, 1728 },{ .name = "RB_DW14_REGISTER", .addr = A_RB_DW14_REGISTER, 1729 .ro = 0xffffffff, 1730 },{ .name = "RB_DW15_REGISTER", .addr = A_RB_DW15_REGISTER, 1731 .ro = 0xffffffff, 1732 } 1733 }; 1734 1735 static const RegisterAccessInfo canfd_rx1_regs[] = { 1736 { .name = "RB_ID_REGISTER_1", .addr = A_RB_ID_REGISTER_1, 1737 .ro = 0xffffffff, 1738 },{ .name = "RB_DLC_REGISTER_1", .addr = A_RB_DLC_REGISTER_1, 1739 .ro = 0xfe1fffff, 1740 },{ .name = "RB0_DW0_REGISTER_1", .addr = A_RB0_DW0_REGISTER_1, 1741 .ro = 0xffffffff, 1742 },{ .name = "RB_DW1_REGISTER_1", .addr = A_RB_DW1_REGISTER_1, 1743 .ro = 0xffffffff, 1744 },{ .name = "RB_DW2_REGISTER_1", .addr = A_RB_DW2_REGISTER_1, 1745 .ro = 0xffffffff, 1746 },{ .name = "RB_DW3_REGISTER_1", .addr = A_RB_DW3_REGISTER_1, 1747 .ro = 0xffffffff, 1748 },{ .name = "RB_DW4_REGISTER_1", .addr = A_RB_DW4_REGISTER_1, 1749 .ro = 0xffffffff, 1750 },{ .name = "RB_DW5_REGISTER_1", .addr = A_RB_DW5_REGISTER_1, 1751 .ro = 0xffffffff, 1752 },{ .name = "RB_DW6_REGISTER_1", .addr = A_RB_DW6_REGISTER_1, 1753 .ro = 0xffffffff, 1754 },{ .name = "RB_DW7_REGISTER_1", .addr = A_RB_DW7_REGISTER_1, 1755 .ro = 0xffffffff, 1756 },{ .name = "RB_DW8_REGISTER_1", .addr = A_RB_DW8_REGISTER_1, 1757 .ro = 0xffffffff, 1758 },{ .name = "RB_DW9_REGISTER_1", .addr = A_RB_DW9_REGISTER_1, 1759 .ro = 0xffffffff, 1760 },{ .name = "RB_DW10_REGISTER_1", .addr = A_RB_DW10_REGISTER_1, 1761 .ro = 0xffffffff, 1762 },{ .name = "RB_DW11_REGISTER_1", .addr = A_RB_DW11_REGISTER_1, 1763 .ro = 0xffffffff, 1764 },{ .name = "RB_DW12_REGISTER_1", .addr = A_RB_DW12_REGISTER_1, 1765 .ro = 0xffffffff, 1766 },{ .name = "RB_DW13_REGISTER_1", .addr = A_RB_DW13_REGISTER_1, 1767 .ro = 0xffffffff, 1768 },{ .name = "RB_DW14_REGISTER_1", .addr = A_RB_DW14_REGISTER_1, 1769 .ro = 0xffffffff, 1770 },{ .name = "RB_DW15_REGISTER_1", .addr = A_RB_DW15_REGISTER_1, 1771 .ro = 0xffffffff, 1772 } 1773 }; 1774 1775 /* Acceptance filter registers. */ 1776 static const RegisterAccessInfo canfd_af_regs[] = { 1777 { .name = "AFMR_REGISTER", .addr = A_AFMR_REGISTER, 1778 .pre_write = filter_mask, 1779 },{ .name = "AFIR_REGISTER", .addr = A_AFIR_REGISTER, 1780 .pre_write = filter_id, 1781 } 1782 }; 1783 1784 static const RegisterAccessInfo canfd_txe_regs[] = { 1785 { .name = "TXE_FIFO_TB_ID_REGISTER", .addr = A_TXE_FIFO_TB_ID_REGISTER, 1786 .ro = 0xffffffff, 1787 },{ .name = "TXE_FIFO_TB_DLC_REGISTER", .addr = A_TXE_FIFO_TB_DLC_REGISTER, 1788 .ro = 0xffffffff, 1789 } 1790 }; 1791 1792 static const RegisterAccessInfo canfd_regs_info[] = { 1793 { .name = "SOFTWARE_RESET_REGISTER", .addr = A_SOFTWARE_RESET_REGISTER, 1794 .pre_write = canfd_srr_pre_write, 1795 },{ .name = "MODE_SELECT_REGISTER", .addr = A_MODE_SELECT_REGISTER, 1796 .pre_write = canfd_msr_pre_write, 1797 },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER", 1798 .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 1799 .pre_write = canfd_write_check_prew, 1800 },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER", 1801 .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER, 1802 .pre_write = canfd_write_check_prew, 1803 },{ .name = "ERROR_COUNTER_REGISTER", .addr = A_ERROR_COUNTER_REGISTER, 1804 .ro = 0xffff, 1805 },{ .name = "ERROR_STATUS_REGISTER", .addr = A_ERROR_STATUS_REGISTER, 1806 .w1c = 0xf1f, 1807 },{ .name = "STATUS_REGISTER", .addr = A_STATUS_REGISTER, 1808 .reset = 0x1, 1809 .ro = 0x7f17ff, 1810 },{ .name = "INTERRUPT_STATUS_REGISTER", 1811 .addr = A_INTERRUPT_STATUS_REGISTER, 1812 .ro = 0xffffff7f, 1813 },{ .name = "INTERRUPT_ENABLE_REGISTER", 1814 .addr = A_INTERRUPT_ENABLE_REGISTER, 1815 .post_write = canfd_ier_post_write, 1816 },{ .name = "INTERRUPT_CLEAR_REGISTER", 1817 .addr = A_INTERRUPT_CLEAR_REGISTER, .pre_write = canfd_icr_pre_write, 1818 },{ .name = "TIMESTAMP_REGISTER", .addr = A_TIMESTAMP_REGISTER, 1819 .ro = 0xffff0000, 1820 .pre_write = canfd_tsr_pre_write, 1821 },{ .name = "DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER", 1822 .addr = A_DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, 1823 .pre_write = canfd_write_check_prew, 1824 },{ .name = "DATA_PHASE_BIT_TIMING_REGISTER", 1825 .addr = A_DATA_PHASE_BIT_TIMING_REGISTER, 1826 .pre_write = canfd_write_check_prew, 1827 },{ .name = "TX_BUFFER_READY_REQUEST_REGISTER", 1828 .addr = A_TX_BUFFER_READY_REQUEST_REGISTER, 1829 .pre_write = canfd_trr_reg_prew, 1830 .post_write = canfd_trr_reg_postw, 1831 },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER", 1832 .addr = A_INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, 1833 },{ .name = "TX_BUFFER_CANCEL_REQUEST_REGISTER", 1834 .addr = A_TX_BUFFER_CANCEL_REQUEST_REGISTER, 1835 .post_write = canfd_cancel_reg_postw, 1836 },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER", 1837 .addr = A_INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, 1838 },{ .name = "TX_EVENT_FIFO_STATUS_REGISTER", 1839 .addr = A_TX_EVENT_FIFO_STATUS_REGISTER, 1840 .ro = 0x3f1f, .pre_write = canfd_tx_fifo_status_prew, 1841 },{ .name = "TX_EVENT_FIFO_WATERMARK_REGISTER", 1842 .addr = A_TX_EVENT_FIFO_WATERMARK_REGISTER, 1843 .reset = 0xf, 1844 .pre_write = canfd_write_check_prew, 1845 },{ .name = "ACCEPTANCE_FILTER_CONTROL_REGISTER", 1846 .addr = A_ACCEPTANCE_FILTER_CONTROL_REGISTER, 1847 },{ .name = "RX_FIFO_STATUS_REGISTER", .addr = A_RX_FIFO_STATUS_REGISTER, 1848 .ro = 0x7f3f7f3f, .pre_write = canfd_rx_fifo_status_prew, 1849 },{ .name = "RX_FIFO_WATERMARK_REGISTER", 1850 .addr = A_RX_FIFO_WATERMARK_REGISTER, 1851 .reset = 0x1f0f0f, 1852 .pre_write = canfd_write_check_prew, 1853 } 1854 }; 1855 1856 static void xlnx_versal_canfd_ptimer_cb(void *opaque) 1857 { 1858 /* No action required on the timer rollover. */ 1859 } 1860 1861 static const MemoryRegionOps canfd_ops = { 1862 .read = register_read_memory, 1863 .write = register_write_memory, 1864 .endianness = DEVICE_LITTLE_ENDIAN, 1865 .valid = { 1866 .min_access_size = 4, 1867 .max_access_size = 4, 1868 }, 1869 }; 1870 1871 static void canfd_reset(DeviceState *dev) 1872 { 1873 XlnxVersalCANFDState *s = XILINX_CANFD(dev); 1874 unsigned int i; 1875 1876 for (i = 0; i < ARRAY_SIZE(s->reg_info); ++i) { 1877 register_reset(&s->reg_info[i]); 1878 } 1879 1880 ptimer_transaction_begin(s->canfd_timer); 1881 ptimer_set_count(s->canfd_timer, 0); 1882 ptimer_transaction_commit(s->canfd_timer); 1883 } 1884 1885 static bool can_xilinx_canfd_receive(CanBusClientState *client) 1886 { 1887 XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState, 1888 bus_client); 1889 1890 bool reset_state = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST); 1891 bool can_enabled = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN); 1892 1893 return !reset_state && can_enabled; 1894 } 1895 1896 static ssize_t canfd_xilinx_receive(CanBusClientState *client, 1897 const qemu_can_frame *buf, 1898 size_t buf_size) 1899 { 1900 XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState, 1901 bus_client); 1902 const qemu_can_frame *frame = buf; 1903 1904 assert(buf_size > 0); 1905 1906 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { 1907 /* 1908 * XlnxVersalCANFDState will not participate in normal bus communication 1909 * and does not receive any messages transmitted by other CAN nodes. 1910 */ 1911 return 1; 1912 } 1913 1914 /* Update the status register that we are receiving message. */ 1915 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 1); 1916 1917 if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { 1918 /* Snoop Mode: Just keep the data. no response back. */ 1919 update_rx_sequential(s, frame); 1920 } else { 1921 if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) { 1922 /* 1923 * XlnxVersalCANFDState is in sleep mode. Any data on bus will bring 1924 * it to the wake up state. 1925 */ 1926 canfd_exit_sleep_mode(s); 1927 } 1928 1929 update_rx_sequential(s, frame); 1930 } 1931 1932 /* Message processing done. Update the status back to !busy */ 1933 ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 0); 1934 return 1; 1935 } 1936 1937 static CanBusClientInfo canfd_xilinx_bus_client_info = { 1938 .can_receive = can_xilinx_canfd_receive, 1939 .receive = canfd_xilinx_receive, 1940 }; 1941 1942 static int xlnx_canfd_connect_to_bus(XlnxVersalCANFDState *s, 1943 CanBusState *bus) 1944 { 1945 s->bus_client.info = &canfd_xilinx_bus_client_info; 1946 1947 return can_bus_insert_client(bus, &s->bus_client); 1948 } 1949 1950 #define NUM_REG_PER_AF ARRAY_SIZE(canfd_af_regs) 1951 #define NUM_AF 32 1952 #define NUM_REG_PER_TXE ARRAY_SIZE(canfd_txe_regs) 1953 #define NUM_TXE 32 1954 1955 static int canfd_populate_regarray(XlnxVersalCANFDState *s, 1956 RegisterInfoArray *r_array, int pos, 1957 const RegisterAccessInfo *rae, 1958 int num_rae) 1959 { 1960 int i; 1961 1962 for (i = 0; i < num_rae; i++) { 1963 int index = rae[i].addr / 4; 1964 RegisterInfo *r = &s->reg_info[index]; 1965 1966 object_initialize(r, sizeof(*r), TYPE_REGISTER); 1967 1968 *r = (RegisterInfo) { 1969 .data = &s->regs[index], 1970 .data_size = sizeof(uint32_t), 1971 .access = &rae[i], 1972 .opaque = OBJECT(s), 1973 }; 1974 1975 r_array->r[i + pos] = r; 1976 } 1977 return i + pos; 1978 } 1979 1980 static void canfd_create_rai(RegisterAccessInfo *rai_array, 1981 const RegisterAccessInfo *canfd_regs, 1982 int template_rai_array_sz, 1983 int num_template_to_copy) 1984 { 1985 int i; 1986 int reg_num; 1987 1988 for (reg_num = 0; reg_num < num_template_to_copy; reg_num++) { 1989 int pos = reg_num * template_rai_array_sz; 1990 1991 memcpy(rai_array + pos, canfd_regs, 1992 template_rai_array_sz * sizeof(RegisterAccessInfo)); 1993 1994 for (i = 0; i < template_rai_array_sz; i++) { 1995 const char *name = canfd_regs[i].name; 1996 uint64_t addr = canfd_regs[i].addr; 1997 rai_array[i + pos].name = g_strdup_printf("%s%d", name, reg_num); 1998 rai_array[i + pos].addr = addr + pos * 4; 1999 } 2000 } 2001 } 2002 2003 static RegisterInfoArray *canfd_create_regarray(XlnxVersalCANFDState *s) 2004 { 2005 const char *device_prefix = object_get_typename(OBJECT(s)); 2006 uint64_t memory_size = XLNX_VERSAL_CANFD_R_MAX * 4; 2007 int num_regs; 2008 int pos = 0; 2009 RegisterInfoArray *r_array; 2010 2011 num_regs = ARRAY_SIZE(canfd_regs_info) + 2012 s->cfg.tx_fifo * NUM_REGS_PER_MSG_SPACE + 2013 s->cfg.rx0_fifo * NUM_REGS_PER_MSG_SPACE + 2014 NUM_AF * NUM_REG_PER_AF + 2015 NUM_TXE * NUM_REG_PER_TXE; 2016 2017 s->tx_regs = g_new0(RegisterAccessInfo, 2018 s->cfg.tx_fifo * ARRAY_SIZE(canfd_tx_regs)); 2019 2020 canfd_create_rai(s->tx_regs, canfd_tx_regs, 2021 ARRAY_SIZE(canfd_tx_regs), s->cfg.tx_fifo); 2022 2023 s->rx0_regs = g_new0(RegisterAccessInfo, 2024 s->cfg.rx0_fifo * ARRAY_SIZE(canfd_rx0_regs)); 2025 2026 canfd_create_rai(s->rx0_regs, canfd_rx0_regs, 2027 ARRAY_SIZE(canfd_rx0_regs), s->cfg.rx0_fifo); 2028 2029 s->af_regs = g_new0(RegisterAccessInfo, 2030 NUM_AF * ARRAY_SIZE(canfd_af_regs)); 2031 2032 canfd_create_rai(s->af_regs, canfd_af_regs, 2033 ARRAY_SIZE(canfd_af_regs), NUM_AF); 2034 2035 s->txe_regs = g_new0(RegisterAccessInfo, 2036 NUM_TXE * ARRAY_SIZE(canfd_txe_regs)); 2037 2038 canfd_create_rai(s->txe_regs, canfd_txe_regs, 2039 ARRAY_SIZE(canfd_txe_regs), NUM_TXE); 2040 2041 if (s->cfg.enable_rx_fifo1) { 2042 num_regs += s->cfg.rx1_fifo * NUM_REGS_PER_MSG_SPACE; 2043 2044 s->rx1_regs = g_new0(RegisterAccessInfo, 2045 s->cfg.rx1_fifo * ARRAY_SIZE(canfd_rx1_regs)); 2046 2047 canfd_create_rai(s->rx1_regs, canfd_rx1_regs, 2048 ARRAY_SIZE(canfd_rx1_regs), s->cfg.rx1_fifo); 2049 } 2050 2051 r_array = g_new0(RegisterInfoArray, 1); 2052 r_array->r = g_new0(RegisterInfo * , num_regs); 2053 r_array->num_elements = num_regs; 2054 r_array->prefix = device_prefix; 2055 2056 pos = canfd_populate_regarray(s, r_array, pos, 2057 canfd_regs_info, 2058 ARRAY_SIZE(canfd_regs_info)); 2059 pos = canfd_populate_regarray(s, r_array, pos, 2060 s->tx_regs, s->cfg.tx_fifo * 2061 NUM_REGS_PER_MSG_SPACE); 2062 pos = canfd_populate_regarray(s, r_array, pos, 2063 s->rx0_regs, s->cfg.rx0_fifo * 2064 NUM_REGS_PER_MSG_SPACE); 2065 if (s->cfg.enable_rx_fifo1) { 2066 pos = canfd_populate_regarray(s, r_array, pos, 2067 s->rx1_regs, s->cfg.rx1_fifo * 2068 NUM_REGS_PER_MSG_SPACE); 2069 } 2070 pos = canfd_populate_regarray(s, r_array, pos, 2071 s->af_regs, NUM_AF * NUM_REG_PER_AF); 2072 pos = canfd_populate_regarray(s, r_array, pos, 2073 s->txe_regs, NUM_TXE * NUM_REG_PER_TXE); 2074 2075 memory_region_init_io(&r_array->mem, OBJECT(s), &canfd_ops, r_array, 2076 device_prefix, memory_size); 2077 return r_array; 2078 } 2079 2080 static void canfd_realize(DeviceState *dev, Error **errp) 2081 { 2082 XlnxVersalCANFDState *s = XILINX_CANFD(dev); 2083 RegisterInfoArray *reg_array; 2084 2085 reg_array = canfd_create_regarray(s); 2086 memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); 2087 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 2088 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_canfd_int); 2089 2090 if (s->canfdbus) { 2091 if (xlnx_canfd_connect_to_bus(s, s->canfdbus) < 0) { 2092 g_autofree char *path = object_get_canonical_path(OBJECT(s)); 2093 2094 error_setg(errp, "%s: xlnx_canfd_connect_to_bus failed", path); 2095 return; 2096 } 2097 2098 } 2099 2100 /* Allocate a new timer. */ 2101 s->canfd_timer = ptimer_init(xlnx_versal_canfd_ptimer_cb, s, 2102 PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | 2103 PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | 2104 PTIMER_POLICY_NO_IMMEDIATE_RELOAD); 2105 2106 ptimer_transaction_begin(s->canfd_timer); 2107 2108 ptimer_set_freq(s->canfd_timer, s->cfg.ext_clk_freq); 2109 ptimer_set_limit(s->canfd_timer, CANFD_TIMER_MAX, 1); 2110 ptimer_run(s->canfd_timer, 0); 2111 ptimer_transaction_commit(s->canfd_timer); 2112 } 2113 2114 static void canfd_init(Object *obj) 2115 { 2116 XlnxVersalCANFDState *s = XILINX_CANFD(obj); 2117 2118 memory_region_init(&s->iomem, obj, TYPE_XILINX_CANFD, 2119 XLNX_VERSAL_CANFD_R_MAX * 4); 2120 } 2121 2122 static const VMStateDescription vmstate_canfd = { 2123 .name = TYPE_XILINX_CANFD, 2124 .version_id = 1, 2125 .minimum_version_id = 1, 2126 .fields = (const VMStateField[]) { 2127 VMSTATE_UINT32_ARRAY(regs, XlnxVersalCANFDState, 2128 XLNX_VERSAL_CANFD_R_MAX), 2129 VMSTATE_PTIMER(canfd_timer, XlnxVersalCANFDState), 2130 VMSTATE_END_OF_LIST(), 2131 } 2132 }; 2133 2134 static Property canfd_core_properties[] = { 2135 DEFINE_PROP_UINT8("rx-fifo0", XlnxVersalCANFDState, cfg.rx0_fifo, 0x40), 2136 DEFINE_PROP_UINT8("rx-fifo1", XlnxVersalCANFDState, cfg.rx1_fifo, 0x40), 2137 DEFINE_PROP_UINT8("tx-fifo", XlnxVersalCANFDState, cfg.tx_fifo, 0x20), 2138 DEFINE_PROP_BOOL("enable-rx-fifo1", XlnxVersalCANFDState, 2139 cfg.enable_rx_fifo1, true), 2140 DEFINE_PROP_UINT32("ext_clk_freq", XlnxVersalCANFDState, cfg.ext_clk_freq, 2141 CANFD_DEFAULT_CLOCK), 2142 DEFINE_PROP_LINK("canfdbus", XlnxVersalCANFDState, canfdbus, TYPE_CAN_BUS, 2143 CanBusState *), 2144 DEFINE_PROP_END_OF_LIST(), 2145 }; 2146 2147 static void canfd_class_init(ObjectClass *klass, void *data) 2148 { 2149 DeviceClass *dc = DEVICE_CLASS(klass); 2150 2151 device_class_set_legacy_reset(dc, canfd_reset); 2152 dc->realize = canfd_realize; 2153 device_class_set_props(dc, canfd_core_properties); 2154 dc->vmsd = &vmstate_canfd; 2155 } 2156 2157 static const TypeInfo canfd_info = { 2158 .name = TYPE_XILINX_CANFD, 2159 .parent = TYPE_SYS_BUS_DEVICE, 2160 .instance_size = sizeof(XlnxVersalCANFDState), 2161 .class_init = canfd_class_init, 2162 .instance_init = canfd_init, 2163 }; 2164 2165 static void canfd_register_types(void) 2166 { 2167 type_register_static(&canfd_info); 2168 } 2169 2170 type_init(canfd_register_types) 2171