xref: /openbmc/qemu/hw/net/can/xlnx-versal-canfd.c (revision 9ea2e69f)
1 /*
2  * QEMU model of the Xilinx Versal CANFD device.
3  *
4  * This implementation is based on the following datasheet:
5  * https://docs.xilinx.com/v/u/2.0-English/pg223-canfd
6  *
7  * Copyright (c) 2023 Advanced Micro Devices, Inc.
8  *
9  * Written-by: Vikram Garhwal <vikram.garhwal@amd.com>
10  *
11  * Based on QEMU CANFD Device emulation implemented by Jin Yang, Deniz Eren and
12  * Pavel Pisa
13  *
14  * Permission is hereby granted, free of charge, to any person obtaining a copy
15  * of this software and associated documentation files (the "Software"), to deal
16  * in the Software without restriction, including without limitation the rights
17  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
18  * copies of the Software, and to permit persons to whom the Software is
19  * furnished to do so, subject to the following conditions:
20  *
21  * The above copyright notice and this permission notice shall be included in
22  * all copies or substantial portions of the Software.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
25  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
26  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
28  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
29  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30  * THE SOFTWARE.
31  */
32 
33 #include "qemu/osdep.h"
34 #include "hw/sysbus.h"
35 #include "hw/irq.h"
36 #include "hw/register.h"
37 #include "qapi/error.h"
38 #include "qemu/bitops.h"
39 #include "qemu/log.h"
40 #include "qemu/cutils.h"
41 #include "qemu/event_notifier.h"
42 #include "hw/qdev-properties.h"
43 #include "qom/object_interfaces.h"
44 #include "migration/vmstate.h"
45 #include "hw/net/xlnx-versal-canfd.h"
46 #include "trace.h"
47 
48 REG32(SOFTWARE_RESET_REGISTER, 0x0)
49     FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
50     FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
51 REG32(MODE_SELECT_REGISTER, 0x4)
52     FIELD(MODE_SELECT_REGISTER, ITO, 8, 8)
53     FIELD(MODE_SELECT_REGISTER, ABR, 7, 1)
54     FIELD(MODE_SELECT_REGISTER, SBR, 6, 1)
55     FIELD(MODE_SELECT_REGISTER, DPEE, 5, 1)
56     FIELD(MODE_SELECT_REGISTER, DAR, 4, 1)
57     FIELD(MODE_SELECT_REGISTER, BRSD, 3, 1)
58     FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
59     FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
60     FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
61 REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
62     FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
63 REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
64     FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 16, 7)
65     FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 8, 7)
66     FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 8)
67 REG32(ERROR_COUNTER_REGISTER, 0x10)
68     FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8)
69     FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
70 REG32(ERROR_STATUS_REGISTER, 0x14)
71     FIELD(ERROR_STATUS_REGISTER, F_BERR, 11, 1)
72     FIELD(ERROR_STATUS_REGISTER, F_STER, 10, 1)
73     FIELD(ERROR_STATUS_REGISTER, F_FMER, 9, 1)
74     FIELD(ERROR_STATUS_REGISTER, F_CRCER, 8, 1)
75     FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
76     FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
77     FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
78     FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
79     FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
80 REG32(STATUS_REGISTER, 0x18)
81     FIELD(STATUS_REGISTER, TDCV, 16, 7)
82     FIELD(STATUS_REGISTER, SNOOP, 12, 1)
83     FIELD(STATUS_REGISTER, BSFR_CONFIG, 10, 1)
84     FIELD(STATUS_REGISTER, PEE_CONFIG, 9, 1)
85     FIELD(STATUS_REGISTER, ESTAT, 7, 2)
86     FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
87     FIELD(STATUS_REGISTER, BBSY, 5, 1)
88     FIELD(STATUS_REGISTER, BIDLE, 4, 1)
89     FIELD(STATUS_REGISTER, NORMAL, 3, 1)
90     FIELD(STATUS_REGISTER, SLEEP, 2, 1)
91     FIELD(STATUS_REGISTER, LBACK, 1, 1)
92     FIELD(STATUS_REGISTER, CONFIG, 0, 1)
93 REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
94     FIELD(INTERRUPT_STATUS_REGISTER, TXEWMFLL, 31, 1)
95     FIELD(INTERRUPT_STATUS_REGISTER, TXEOFLW, 30, 1)
96     FIELD(INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 24, 6)
97     FIELD(INTERRUPT_STATUS_REGISTER, RXLRM_BI, 18, 6)
98     FIELD(INTERRUPT_STATUS_REGISTER, RXMNF, 17, 1)
99     FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 16, 1)
100     FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 15, 1)
101     FIELD(INTERRUPT_STATUS_REGISTER, TXCRS, 14, 1)
102     FIELD(INTERRUPT_STATUS_REGISTER, TXRRS, 13, 1)
103     FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
104     FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
105     FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
106     FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
107     /*
108      * In the original HW description below bit is named as ERROR but an ERROR
109      * field name collides with a macro in Windows build. To avoid Windows build
110      * failures, the bit is renamed to ERROR_BIT.
111      */
112     FIELD(INTERRUPT_STATUS_REGISTER, ERROR_BIT, 8, 1)
113     FIELD(INTERRUPT_STATUS_REGISTER, RXFOFLW, 6, 1)
114     FIELD(INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 5, 1)
115     FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
116     FIELD(INTERRUPT_STATUS_REGISTER, BSFRD, 3, 1)
117     FIELD(INTERRUPT_STATUS_REGISTER, PEE, 2, 1)
118     FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
119     FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
120 REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
121     FIELD(INTERRUPT_ENABLE_REGISTER, ETXEWMFLL, 31, 1)
122     FIELD(INTERRUPT_ENABLE_REGISTER, ETXEOFLW, 30, 1)
123     FIELD(INTERRUPT_ENABLE_REGISTER, ERXMNF, 17, 1)
124     FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL_1, 16, 1)
125     FIELD(INTERRUPT_ENABLE_REGISTER, ERXFOFLW_1, 15, 1)
126     FIELD(INTERRUPT_ENABLE_REGISTER, ETXCRS, 14, 1)
127     FIELD(INTERRUPT_ENABLE_REGISTER, ETXRRS, 13, 1)
128     FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
129     FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
130     FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
131     FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
132     FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
133     FIELD(INTERRUPT_ENABLE_REGISTER, ERFXOFLW, 6, 1)
134     FIELD(INTERRUPT_ENABLE_REGISTER, ETSCNT_OFLW, 5, 1)
135     FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
136     FIELD(INTERRUPT_ENABLE_REGISTER, EBSFRD, 3, 1)
137     FIELD(INTERRUPT_ENABLE_REGISTER, EPEE, 2, 1)
138     FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
139     FIELD(INTERRUPT_ENABLE_REGISTER, EARBLOST, 0, 1)
140 REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
141     FIELD(INTERRUPT_CLEAR_REGISTER, CTXEWMFLL, 31, 1)
142     FIELD(INTERRUPT_CLEAR_REGISTER, CTXEOFLW, 30, 1)
143     FIELD(INTERRUPT_CLEAR_REGISTER, CRXMNF, 17, 1)
144     FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL_1, 16, 1)
145     FIELD(INTERRUPT_CLEAR_REGISTER, CRXFOFLW_1, 15, 1)
146     FIELD(INTERRUPT_CLEAR_REGISTER, CTXCRS, 14, 1)
147     FIELD(INTERRUPT_CLEAR_REGISTER, CTXRRS, 13, 1)
148     FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
149     FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
150     FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
151     FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
152     FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
153     FIELD(INTERRUPT_CLEAR_REGISTER, CRFXOFLW, 6, 1)
154     FIELD(INTERRUPT_CLEAR_REGISTER, CTSCNT_OFLW, 5, 1)
155     FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
156     FIELD(INTERRUPT_CLEAR_REGISTER, CBSFRD, 3, 1)
157     FIELD(INTERRUPT_CLEAR_REGISTER, CPEE, 2, 1)
158     FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
159     FIELD(INTERRUPT_CLEAR_REGISTER, CARBLOST, 0, 1)
160 REG32(TIMESTAMP_REGISTER, 0x28)
161     FIELD(TIMESTAMP_REGISTER, TIMESTAMP_CNT, 16, 16)
162     FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
163 REG32(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x88)
164     FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDC, 16, 1)
165     FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, TDCOFF, 8, 6)
166     FIELD(DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER, DP_BRP, 0, 8)
167 REG32(DATA_PHASE_BIT_TIMING_REGISTER, 0x8c)
168     FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_SJW, 16, 4)
169     FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS2, 8, 4)
170     FIELD(DATA_PHASE_BIT_TIMING_REGISTER, DP_TS1, 0, 5)
171 REG32(TX_BUFFER_READY_REQUEST_REGISTER, 0x90)
172     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR31, 31, 1)
173     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR30, 30, 1)
174     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR29, 29, 1)
175     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR28, 28, 1)
176     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR27, 27, 1)
177     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR26, 26, 1)
178     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR25, 25, 1)
179     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR24, 24, 1)
180     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR23, 23, 1)
181     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR22, 22, 1)
182     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR21, 21, 1)
183     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR20, 20, 1)
184     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR19, 19, 1)
185     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR18, 18, 1)
186     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR17, 17, 1)
187     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR16, 16, 1)
188     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR15, 15, 1)
189     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR14, 14, 1)
190     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR13, 13, 1)
191     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR12, 12, 1)
192     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR11, 11, 1)
193     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR10, 10, 1)
194     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR9, 9, 1)
195     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR8, 8, 1)
196     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR7, 7, 1)
197     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR6, 6, 1)
198     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR5, 5, 1)
199     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR4, 4, 1)
200     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR3, 3, 1)
201     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR2, 2, 1)
202     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR1, 1, 1)
203     FIELD(TX_BUFFER_READY_REQUEST_REGISTER, RR0, 0, 1)
204 REG32(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, 0x94)
205     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS31, 31, 1)
206     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS30, 30, 1)
207     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS29, 29, 1)
208     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS28, 28, 1)
209     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS27, 27, 1)
210     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS26, 26, 1)
211     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS25, 25, 1)
212     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS24, 24, 1)
213     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS23, 23, 1)
214     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS22, 22, 1)
215     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS21, 21, 1)
216     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS20, 20, 1)
217     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS19, 19, 1)
218     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS18, 18, 1)
219     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS17, 17, 1)
220     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS16, 16, 1)
221     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS15, 15, 1)
222     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS14, 14, 1)
223     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS13, 13, 1)
224     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS12, 12, 1)
225     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS11, 11, 1)
226     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS10, 10, 1)
227     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS9, 9, 1)
228     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS8, 8, 1)
229     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS7, 7, 1)
230     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS6, 6, 1)
231     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS5, 5, 1)
232     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS4, 4, 1)
233     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS3, 3, 1)
234     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS2, 2, 1)
235     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS1, 1, 1)
236     FIELD(INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER, ERRS0, 0, 1)
237 REG32(TX_BUFFER_CANCEL_REQUEST_REGISTER, 0x98)
238     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR31, 31, 1)
239     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR30, 30, 1)
240     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR29, 29, 1)
241     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR28, 28, 1)
242     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR27, 27, 1)
243     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR26, 26, 1)
244     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR25, 25, 1)
245     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR24, 24, 1)
246     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR23, 23, 1)
247     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR22, 22, 1)
248     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR21, 21, 1)
249     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR20, 20, 1)
250     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR19, 19, 1)
251     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR18, 18, 1)
252     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR17, 17, 1)
253     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR16, 16, 1)
254     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR15, 15, 1)
255     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR14, 14, 1)
256     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR13, 13, 1)
257     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR12, 12, 1)
258     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR11, 11, 1)
259     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR10, 10, 1)
260     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR9, 9, 1)
261     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR8, 8, 1)
262     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR7, 7, 1)
263     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR6, 6, 1)
264     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR5, 5, 1)
265     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR4, 4, 1)
266     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR3, 3, 1)
267     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR2, 2, 1)
268     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR1, 1, 1)
269     FIELD(TX_BUFFER_CANCEL_REQUEST_REGISTER, CR0, 0, 1)
270 REG32(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, 0x9c)
271     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS31, 31,
272             1)
273     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS30, 30,
274             1)
275     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS29, 29,
276             1)
277     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS28, 28,
278             1)
279     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS27, 27,
280             1)
281     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS26, 26,
282             1)
283     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS25, 25,
284             1)
285     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS24, 24,
286             1)
287     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS23, 23,
288             1)
289     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS22, 22,
290             1)
291     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS21, 21,
292             1)
293     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS20, 20,
294             1)
295     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS19, 19,
296             1)
297     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS18, 18,
298             1)
299     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS17, 17,
300             1)
301     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS16, 16,
302             1)
303     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS15, 15,
304             1)
305     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS14, 14,
306             1)
307     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS13, 13,
308             1)
309     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS12, 12,
310             1)
311     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS11, 11,
312             1)
313     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS10, 10,
314             1)
315     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS9, 9, 1)
316     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS8, 8, 1)
317     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS7, 7, 1)
318     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS6, 6, 1)
319     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS5, 5, 1)
320     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS4, 4, 1)
321     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS3, 3, 1)
322     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS2, 2, 1)
323     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS1, 1, 1)
324     FIELD(INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER, ECRS0, 0, 1)
325 REG32(TX_EVENT_FIFO_STATUS_REGISTER, 0xa0)
326     FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL, 8, 6)
327     FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI, 7, 1)
328     FIELD(TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI, 0, 5)
329 REG32(TX_EVENT_FIFO_WATERMARK_REGISTER, 0xa4)
330     FIELD(TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM, 0, 5)
331 REG32(ACCEPTANCE_FILTER_CONTROL_REGISTER, 0xe0)
332     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF31, 31, 1)
333     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF30, 30, 1)
334     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF29, 29, 1)
335     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF28, 28, 1)
336     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF27, 27, 1)
337     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF26, 26, 1)
338     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF25, 25, 1)
339     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF24, 24, 1)
340     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF23, 23, 1)
341     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF22, 22, 1)
342     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF21, 21, 1)
343     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF20, 20, 1)
344     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF19, 19, 1)
345     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF18, 18, 1)
346     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF17, 17, 1)
347     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF16, 16, 1)
348     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF15, 15, 1)
349     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF14, 14, 1)
350     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF13, 13, 1)
351     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF12, 12, 1)
352     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF11, 11, 1)
353     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF10, 10, 1)
354     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF9, 9, 1)
355     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF8, 8, 1)
356     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF7, 7, 1)
357     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF6, 6, 1)
358     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF5, 5, 1)
359     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF4, 4, 1)
360     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF3, 3, 1)
361     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF2, 2, 1)
362     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF1, 1, 1)
363     FIELD(ACCEPTANCE_FILTER_CONTROL_REGISTER, UAF0, 0, 1)
364 REG32(RX_FIFO_STATUS_REGISTER, 0xe8)
365     FIELD(RX_FIFO_STATUS_REGISTER, FL_1, 24, 7)
366     FIELD(RX_FIFO_STATUS_REGISTER, IRI_1, 23, 1)
367     FIELD(RX_FIFO_STATUS_REGISTER, RI_1, 16, 6)
368     FIELD(RX_FIFO_STATUS_REGISTER, FL, 8, 7)
369     FIELD(RX_FIFO_STATUS_REGISTER, IRI, 7, 1)
370     FIELD(RX_FIFO_STATUS_REGISTER, RI, 0, 6)
371 REG32(RX_FIFO_WATERMARK_REGISTER, 0xec)
372     FIELD(RX_FIFO_WATERMARK_REGISTER, RXFP, 16, 5)
373     FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM_1, 8, 6)
374     FIELD(RX_FIFO_WATERMARK_REGISTER, RXFWM, 0, 6)
375 REG32(TB_ID_REGISTER, 0x100)
376     FIELD(TB_ID_REGISTER, ID, 21, 11)
377     FIELD(TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
378     FIELD(TB_ID_REGISTER, IDE, 19, 1)
379     FIELD(TB_ID_REGISTER, ID_EXT, 1, 18)
380     FIELD(TB_ID_REGISTER, RTR_RRS, 0, 1)
381 REG32(TB0_DLC_REGISTER, 0x104)
382     FIELD(TB0_DLC_REGISTER, DLC, 28, 4)
383     FIELD(TB0_DLC_REGISTER, FDF, 27, 1)
384     FIELD(TB0_DLC_REGISTER, BRS, 26, 1)
385     FIELD(TB0_DLC_REGISTER, RSVD2, 25, 1)
386     FIELD(TB0_DLC_REGISTER, EFC, 24, 1)
387     FIELD(TB0_DLC_REGISTER, MM, 16, 8)
388     FIELD(TB0_DLC_REGISTER, RSVD1, 0, 16)
389 REG32(TB_DW0_REGISTER, 0x108)
390     FIELD(TB_DW0_REGISTER, DATA_BYTES0, 24, 8)
391     FIELD(TB_DW0_REGISTER, DATA_BYTES1, 16, 8)
392     FIELD(TB_DW0_REGISTER, DATA_BYTES2, 8, 8)
393     FIELD(TB_DW0_REGISTER, DATA_BYTES3, 0, 8)
394 REG32(TB_DW1_REGISTER, 0x10c)
395     FIELD(TB_DW1_REGISTER, DATA_BYTES4, 24, 8)
396     FIELD(TB_DW1_REGISTER, DATA_BYTES5, 16, 8)
397     FIELD(TB_DW1_REGISTER, DATA_BYTES6, 8, 8)
398     FIELD(TB_DW1_REGISTER, DATA_BYTES7, 0, 8)
399 REG32(TB_DW2_REGISTER, 0x110)
400     FIELD(TB_DW2_REGISTER, DATA_BYTES8, 24, 8)
401     FIELD(TB_DW2_REGISTER, DATA_BYTES9, 16, 8)
402     FIELD(TB_DW2_REGISTER, DATA_BYTES10, 8, 8)
403     FIELD(TB_DW2_REGISTER, DATA_BYTES11, 0, 8)
404 REG32(TB_DW3_REGISTER, 0x114)
405     FIELD(TB_DW3_REGISTER, DATA_BYTES12, 24, 8)
406     FIELD(TB_DW3_REGISTER, DATA_BYTES13, 16, 8)
407     FIELD(TB_DW3_REGISTER, DATA_BYTES14, 8, 8)
408     FIELD(TB_DW3_REGISTER, DATA_BYTES15, 0, 8)
409 REG32(TB_DW4_REGISTER, 0x118)
410     FIELD(TB_DW4_REGISTER, DATA_BYTES16, 24, 8)
411     FIELD(TB_DW4_REGISTER, DATA_BYTES17, 16, 8)
412     FIELD(TB_DW4_REGISTER, DATA_BYTES18, 8, 8)
413     FIELD(TB_DW4_REGISTER, DATA_BYTES19, 0, 8)
414 REG32(TB_DW5_REGISTER, 0x11c)
415     FIELD(TB_DW5_REGISTER, DATA_BYTES20, 24, 8)
416     FIELD(TB_DW5_REGISTER, DATA_BYTES21, 16, 8)
417     FIELD(TB_DW5_REGISTER, DATA_BYTES22, 8, 8)
418     FIELD(TB_DW5_REGISTER, DATA_BYTES23, 0, 8)
419 REG32(TB_DW6_REGISTER, 0x120)
420     FIELD(TB_DW6_REGISTER, DATA_BYTES24, 24, 8)
421     FIELD(TB_DW6_REGISTER, DATA_BYTES25, 16, 8)
422     FIELD(TB_DW6_REGISTER, DATA_BYTES26, 8, 8)
423     FIELD(TB_DW6_REGISTER, DATA_BYTES27, 0, 8)
424 REG32(TB_DW7_REGISTER, 0x124)
425     FIELD(TB_DW7_REGISTER, DATA_BYTES28, 24, 8)
426     FIELD(TB_DW7_REGISTER, DATA_BYTES29, 16, 8)
427     FIELD(TB_DW7_REGISTER, DATA_BYTES30, 8, 8)
428     FIELD(TB_DW7_REGISTER, DATA_BYTES31, 0, 8)
429 REG32(TB_DW8_REGISTER, 0x128)
430     FIELD(TB_DW8_REGISTER, DATA_BYTES32, 24, 8)
431     FIELD(TB_DW8_REGISTER, DATA_BYTES33, 16, 8)
432     FIELD(TB_DW8_REGISTER, DATA_BYTES34, 8, 8)
433     FIELD(TB_DW8_REGISTER, DATA_BYTES35, 0, 8)
434 REG32(TB_DW9_REGISTER, 0x12c)
435     FIELD(TB_DW9_REGISTER, DATA_BYTES36, 24, 8)
436     FIELD(TB_DW9_REGISTER, DATA_BYTES37, 16, 8)
437     FIELD(TB_DW9_REGISTER, DATA_BYTES38, 8, 8)
438     FIELD(TB_DW9_REGISTER, DATA_BYTES39, 0, 8)
439 REG32(TB_DW10_REGISTER, 0x130)
440     FIELD(TB_DW10_REGISTER, DATA_BYTES40, 24, 8)
441     FIELD(TB_DW10_REGISTER, DATA_BYTES41, 16, 8)
442     FIELD(TB_DW10_REGISTER, DATA_BYTES42, 8, 8)
443     FIELD(TB_DW10_REGISTER, DATA_BYTES43, 0, 8)
444 REG32(TB_DW11_REGISTER, 0x134)
445     FIELD(TB_DW11_REGISTER, DATA_BYTES44, 24, 8)
446     FIELD(TB_DW11_REGISTER, DATA_BYTES45, 16, 8)
447     FIELD(TB_DW11_REGISTER, DATA_BYTES46, 8, 8)
448     FIELD(TB_DW11_REGISTER, DATA_BYTES47, 0, 8)
449 REG32(TB_DW12_REGISTER, 0x138)
450     FIELD(TB_DW12_REGISTER, DATA_BYTES48, 24, 8)
451     FIELD(TB_DW12_REGISTER, DATA_BYTES49, 16, 8)
452     FIELD(TB_DW12_REGISTER, DATA_BYTES50, 8, 8)
453     FIELD(TB_DW12_REGISTER, DATA_BYTES51, 0, 8)
454 REG32(TB_DW13_REGISTER, 0x13c)
455     FIELD(TB_DW13_REGISTER, DATA_BYTES52, 24, 8)
456     FIELD(TB_DW13_REGISTER, DATA_BYTES53, 16, 8)
457     FIELD(TB_DW13_REGISTER, DATA_BYTES54, 8, 8)
458     FIELD(TB_DW13_REGISTER, DATA_BYTES55, 0, 8)
459 REG32(TB_DW14_REGISTER, 0x140)
460     FIELD(TB_DW14_REGISTER, DATA_BYTES56, 24, 8)
461     FIELD(TB_DW14_REGISTER, DATA_BYTES57, 16, 8)
462     FIELD(TB_DW14_REGISTER, DATA_BYTES58, 8, 8)
463     FIELD(TB_DW14_REGISTER, DATA_BYTES59, 0, 8)
464 REG32(TB_DW15_REGISTER, 0x144)
465     FIELD(TB_DW15_REGISTER, DATA_BYTES60, 24, 8)
466     FIELD(TB_DW15_REGISTER, DATA_BYTES61, 16, 8)
467     FIELD(TB_DW15_REGISTER, DATA_BYTES62, 8, 8)
468     FIELD(TB_DW15_REGISTER, DATA_BYTES63, 0, 8)
469 REG32(AFMR_REGISTER, 0xa00)
470     FIELD(AFMR_REGISTER, AMID, 21, 11)
471     FIELD(AFMR_REGISTER, AMSRR, 20, 1)
472     FIELD(AFMR_REGISTER, AMIDE, 19, 1)
473     FIELD(AFMR_REGISTER, AMID_EXT, 1, 18)
474     FIELD(AFMR_REGISTER, AMRTR, 0, 1)
475 REG32(AFIR_REGISTER, 0xa04)
476     FIELD(AFIR_REGISTER, AIID, 21, 11)
477     FIELD(AFIR_REGISTER, AISRR, 20, 1)
478     FIELD(AFIR_REGISTER, AIIDE, 19, 1)
479     FIELD(AFIR_REGISTER, AIID_EXT, 1, 18)
480     FIELD(AFIR_REGISTER, AIRTR, 0, 1)
481 REG32(TXE_FIFO_TB_ID_REGISTER, 0x2000)
482     FIELD(TXE_FIFO_TB_ID_REGISTER, ID, 21, 11)
483     FIELD(TXE_FIFO_TB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
484     FIELD(TXE_FIFO_TB_ID_REGISTER, IDE, 19, 1)
485     FIELD(TXE_FIFO_TB_ID_REGISTER, ID_EXT, 1, 18)
486     FIELD(TXE_FIFO_TB_ID_REGISTER, RTR_RRS, 0, 1)
487 REG32(TXE_FIFO_TB_DLC_REGISTER, 0x2004)
488     FIELD(TXE_FIFO_TB_DLC_REGISTER, DLC, 28, 4)
489     FIELD(TXE_FIFO_TB_DLC_REGISTER, FDF, 27, 1)
490     FIELD(TXE_FIFO_TB_DLC_REGISTER, BRS, 26, 1)
491     FIELD(TXE_FIFO_TB_DLC_REGISTER, ET, 24, 2)
492     FIELD(TXE_FIFO_TB_DLC_REGISTER, MM, 16, 8)
493     FIELD(TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP, 0, 16)
494 REG32(RB_ID_REGISTER, 0x2100)
495     FIELD(RB_ID_REGISTER, ID, 21, 11)
496     FIELD(RB_ID_REGISTER, SRR_RTR_RRS, 20, 1)
497     FIELD(RB_ID_REGISTER, IDE, 19, 1)
498     FIELD(RB_ID_REGISTER, ID_EXT, 1, 18)
499     FIELD(RB_ID_REGISTER, RTR_RRS, 0, 1)
500 REG32(RB_DLC_REGISTER, 0x2104)
501     FIELD(RB_DLC_REGISTER, DLC, 28, 4)
502     FIELD(RB_DLC_REGISTER, FDF, 27, 1)
503     FIELD(RB_DLC_REGISTER, BRS, 26, 1)
504     FIELD(RB_DLC_REGISTER, ESI, 25, 1)
505     FIELD(RB_DLC_REGISTER, MATCHED_FILTER_INDEX, 16, 5)
506     FIELD(RB_DLC_REGISTER, TIMESTAMP, 0, 16)
507 REG32(RB_DW0_REGISTER, 0x2108)
508     FIELD(RB_DW0_REGISTER, DATA_BYTES0, 24, 8)
509     FIELD(RB_DW0_REGISTER, DATA_BYTES1, 16, 8)
510     FIELD(RB_DW0_REGISTER, DATA_BYTES2, 8, 8)
511     FIELD(RB_DW0_REGISTER, DATA_BYTES3, 0, 8)
512 REG32(RB_DW1_REGISTER, 0x210c)
513     FIELD(RB_DW1_REGISTER, DATA_BYTES4, 24, 8)
514     FIELD(RB_DW1_REGISTER, DATA_BYTES5, 16, 8)
515     FIELD(RB_DW1_REGISTER, DATA_BYTES6, 8, 8)
516     FIELD(RB_DW1_REGISTER, DATA_BYTES7, 0, 8)
517 REG32(RB_DW2_REGISTER, 0x2110)
518     FIELD(RB_DW2_REGISTER, DATA_BYTES8, 24, 8)
519     FIELD(RB_DW2_REGISTER, DATA_BYTES9, 16, 8)
520     FIELD(RB_DW2_REGISTER, DATA_BYTES10, 8, 8)
521     FIELD(RB_DW2_REGISTER, DATA_BYTES11, 0, 8)
522 REG32(RB_DW3_REGISTER, 0x2114)
523     FIELD(RB_DW3_REGISTER, DATA_BYTES12, 24, 8)
524     FIELD(RB_DW3_REGISTER, DATA_BYTES13, 16, 8)
525     FIELD(RB_DW3_REGISTER, DATA_BYTES14, 8, 8)
526     FIELD(RB_DW3_REGISTER, DATA_BYTES15, 0, 8)
527 REG32(RB_DW4_REGISTER, 0x2118)
528     FIELD(RB_DW4_REGISTER, DATA_BYTES16, 24, 8)
529     FIELD(RB_DW4_REGISTER, DATA_BYTES17, 16, 8)
530     FIELD(RB_DW4_REGISTER, DATA_BYTES18, 8, 8)
531     FIELD(RB_DW4_REGISTER, DATA_BYTES19, 0, 8)
532 REG32(RB_DW5_REGISTER, 0x211c)
533     FIELD(RB_DW5_REGISTER, DATA_BYTES20, 24, 8)
534     FIELD(RB_DW5_REGISTER, DATA_BYTES21, 16, 8)
535     FIELD(RB_DW5_REGISTER, DATA_BYTES22, 8, 8)
536     FIELD(RB_DW5_REGISTER, DATA_BYTES23, 0, 8)
537 REG32(RB_DW6_REGISTER, 0x2120)
538     FIELD(RB_DW6_REGISTER, DATA_BYTES24, 24, 8)
539     FIELD(RB_DW6_REGISTER, DATA_BYTES25, 16, 8)
540     FIELD(RB_DW6_REGISTER, DATA_BYTES26, 8, 8)
541     FIELD(RB_DW6_REGISTER, DATA_BYTES27, 0, 8)
542 REG32(RB_DW7_REGISTER, 0x2124)
543     FIELD(RB_DW7_REGISTER, DATA_BYTES28, 24, 8)
544     FIELD(RB_DW7_REGISTER, DATA_BYTES29, 16, 8)
545     FIELD(RB_DW7_REGISTER, DATA_BYTES30, 8, 8)
546     FIELD(RB_DW7_REGISTER, DATA_BYTES31, 0, 8)
547 REG32(RB_DW8_REGISTER, 0x2128)
548     FIELD(RB_DW8_REGISTER, DATA_BYTES32, 24, 8)
549     FIELD(RB_DW8_REGISTER, DATA_BYTES33, 16, 8)
550     FIELD(RB_DW8_REGISTER, DATA_BYTES34, 8, 8)
551     FIELD(RB_DW8_REGISTER, DATA_BYTES35, 0, 8)
552 REG32(RB_DW9_REGISTER, 0x212c)
553     FIELD(RB_DW9_REGISTER, DATA_BYTES36, 24, 8)
554     FIELD(RB_DW9_REGISTER, DATA_BYTES37, 16, 8)
555     FIELD(RB_DW9_REGISTER, DATA_BYTES38, 8, 8)
556     FIELD(RB_DW9_REGISTER, DATA_BYTES39, 0, 8)
557 REG32(RB_DW10_REGISTER, 0x2130)
558     FIELD(RB_DW10_REGISTER, DATA_BYTES40, 24, 8)
559     FIELD(RB_DW10_REGISTER, DATA_BYTES41, 16, 8)
560     FIELD(RB_DW10_REGISTER, DATA_BYTES42, 8, 8)
561     FIELD(RB_DW10_REGISTER, DATA_BYTES43, 0, 8)
562 REG32(RB_DW11_REGISTER, 0x2134)
563     FIELD(RB_DW11_REGISTER, DATA_BYTES44, 24, 8)
564     FIELD(RB_DW11_REGISTER, DATA_BYTES45, 16, 8)
565     FIELD(RB_DW11_REGISTER, DATA_BYTES46, 8, 8)
566     FIELD(RB_DW11_REGISTER, DATA_BYTES47, 0, 8)
567 REG32(RB_DW12_REGISTER, 0x2138)
568     FIELD(RB_DW12_REGISTER, DATA_BYTES48, 24, 8)
569     FIELD(RB_DW12_REGISTER, DATA_BYTES49, 16, 8)
570     FIELD(RB_DW12_REGISTER, DATA_BYTES50, 8, 8)
571     FIELD(RB_DW12_REGISTER, DATA_BYTES51, 0, 8)
572 REG32(RB_DW13_REGISTER, 0x213c)
573     FIELD(RB_DW13_REGISTER, DATA_BYTES52, 24, 8)
574     FIELD(RB_DW13_REGISTER, DATA_BYTES53, 16, 8)
575     FIELD(RB_DW13_REGISTER, DATA_BYTES54, 8, 8)
576     FIELD(RB_DW13_REGISTER, DATA_BYTES55, 0, 8)
577 REG32(RB_DW14_REGISTER, 0x2140)
578     FIELD(RB_DW14_REGISTER, DATA_BYTES56, 24, 8)
579     FIELD(RB_DW14_REGISTER, DATA_BYTES57, 16, 8)
580     FIELD(RB_DW14_REGISTER, DATA_BYTES58, 8, 8)
581     FIELD(RB_DW14_REGISTER, DATA_BYTES59, 0, 8)
582 REG32(RB_DW15_REGISTER, 0x2144)
583     FIELD(RB_DW15_REGISTER, DATA_BYTES60, 24, 8)
584     FIELD(RB_DW15_REGISTER, DATA_BYTES61, 16, 8)
585     FIELD(RB_DW15_REGISTER, DATA_BYTES62, 8, 8)
586     FIELD(RB_DW15_REGISTER, DATA_BYTES63, 0, 8)
587 REG32(RB_ID_REGISTER_1, 0x4100)
588     FIELD(RB_ID_REGISTER_1, ID, 21, 11)
589     FIELD(RB_ID_REGISTER_1, SRR_RTR_RRS, 20, 1)
590     FIELD(RB_ID_REGISTER_1, IDE, 19, 1)
591     FIELD(RB_ID_REGISTER_1, ID_EXT, 1, 18)
592     FIELD(RB_ID_REGISTER_1, RTR_RRS, 0, 1)
593 REG32(RB_DLC_REGISTER_1, 0x4104)
594     FIELD(RB_DLC_REGISTER_1, DLC, 28, 4)
595     FIELD(RB_DLC_REGISTER_1, FDF, 27, 1)
596     FIELD(RB_DLC_REGISTER_1, BRS, 26, 1)
597     FIELD(RB_DLC_REGISTER_1, ESI, 25, 1)
598     FIELD(RB_DLC_REGISTER_1, MATCHED_FILTER_INDEX, 16, 5)
599     FIELD(RB_DLC_REGISTER_1, TIMESTAMP, 0, 16)
600 REG32(RB0_DW0_REGISTER_1, 0x4108)
601     FIELD(RB0_DW0_REGISTER_1, DATA_BYTES0, 24, 8)
602     FIELD(RB0_DW0_REGISTER_1, DATA_BYTES1, 16, 8)
603     FIELD(RB0_DW0_REGISTER_1, DATA_BYTES2, 8, 8)
604     FIELD(RB0_DW0_REGISTER_1, DATA_BYTES3, 0, 8)
605 REG32(RB_DW1_REGISTER_1, 0x410c)
606     FIELD(RB_DW1_REGISTER_1, DATA_BYTES4, 24, 8)
607     FIELD(RB_DW1_REGISTER_1, DATA_BYTES5, 16, 8)
608     FIELD(RB_DW1_REGISTER_1, DATA_BYTES6, 8, 8)
609     FIELD(RB_DW1_REGISTER_1, DATA_BYTES7, 0, 8)
610 REG32(RB_DW2_REGISTER_1, 0x4110)
611     FIELD(RB_DW2_REGISTER_1, DATA_BYTES8, 24, 8)
612     FIELD(RB_DW2_REGISTER_1, DATA_BYTES9, 16, 8)
613     FIELD(RB_DW2_REGISTER_1, DATA_BYTES10, 8, 8)
614     FIELD(RB_DW2_REGISTER_1, DATA_BYTES11, 0, 8)
615 REG32(RB_DW3_REGISTER_1, 0x4114)
616     FIELD(RB_DW3_REGISTER_1, DATA_BYTES12, 24, 8)
617     FIELD(RB_DW3_REGISTER_1, DATA_BYTES13, 16, 8)
618     FIELD(RB_DW3_REGISTER_1, DATA_BYTES14, 8, 8)
619     FIELD(RB_DW3_REGISTER_1, DATA_BYTES15, 0, 8)
620 REG32(RB_DW4_REGISTER_1, 0x4118)
621     FIELD(RB_DW4_REGISTER_1, DATA_BYTES16, 24, 8)
622     FIELD(RB_DW4_REGISTER_1, DATA_BYTES17, 16, 8)
623     FIELD(RB_DW4_REGISTER_1, DATA_BYTES18, 8, 8)
624     FIELD(RB_DW4_REGISTER_1, DATA_BYTES19, 0, 8)
625 REG32(RB_DW5_REGISTER_1, 0x411c)
626     FIELD(RB_DW5_REGISTER_1, DATA_BYTES20, 24, 8)
627     FIELD(RB_DW5_REGISTER_1, DATA_BYTES21, 16, 8)
628     FIELD(RB_DW5_REGISTER_1, DATA_BYTES22, 8, 8)
629     FIELD(RB_DW5_REGISTER_1, DATA_BYTES23, 0, 8)
630 REG32(RB_DW6_REGISTER_1, 0x4120)
631     FIELD(RB_DW6_REGISTER_1, DATA_BYTES24, 24, 8)
632     FIELD(RB_DW6_REGISTER_1, DATA_BYTES25, 16, 8)
633     FIELD(RB_DW6_REGISTER_1, DATA_BYTES26, 8, 8)
634     FIELD(RB_DW6_REGISTER_1, DATA_BYTES27, 0, 8)
635 REG32(RB_DW7_REGISTER_1, 0x4124)
636     FIELD(RB_DW7_REGISTER_1, DATA_BYTES28, 24, 8)
637     FIELD(RB_DW7_REGISTER_1, DATA_BYTES29, 16, 8)
638     FIELD(RB_DW7_REGISTER_1, DATA_BYTES30, 8, 8)
639     FIELD(RB_DW7_REGISTER_1, DATA_BYTES31, 0, 8)
640 REG32(RB_DW8_REGISTER_1, 0x4128)
641     FIELD(RB_DW8_REGISTER_1, DATA_BYTES32, 24, 8)
642     FIELD(RB_DW8_REGISTER_1, DATA_BYTES33, 16, 8)
643     FIELD(RB_DW8_REGISTER_1, DATA_BYTES34, 8, 8)
644     FIELD(RB_DW8_REGISTER_1, DATA_BYTES35, 0, 8)
645 REG32(RB_DW9_REGISTER_1, 0x412c)
646     FIELD(RB_DW9_REGISTER_1, DATA_BYTES36, 24, 8)
647     FIELD(RB_DW9_REGISTER_1, DATA_BYTES37, 16, 8)
648     FIELD(RB_DW9_REGISTER_1, DATA_BYTES38, 8, 8)
649     FIELD(RB_DW9_REGISTER_1, DATA_BYTES39, 0, 8)
650 REG32(RB_DW10_REGISTER_1, 0x4130)
651     FIELD(RB_DW10_REGISTER_1, DATA_BYTES40, 24, 8)
652     FIELD(RB_DW10_REGISTER_1, DATA_BYTES41, 16, 8)
653     FIELD(RB_DW10_REGISTER_1, DATA_BYTES42, 8, 8)
654     FIELD(RB_DW10_REGISTER_1, DATA_BYTES43, 0, 8)
655 REG32(RB_DW11_REGISTER_1, 0x4134)
656     FIELD(RB_DW11_REGISTER_1, DATA_BYTES44, 24, 8)
657     FIELD(RB_DW11_REGISTER_1, DATA_BYTES45, 16, 8)
658     FIELD(RB_DW11_REGISTER_1, DATA_BYTES46, 8, 8)
659     FIELD(RB_DW11_REGISTER_1, DATA_BYTES47, 0, 8)
660 REG32(RB_DW12_REGISTER_1, 0x4138)
661     FIELD(RB_DW12_REGISTER_1, DATA_BYTES48, 24, 8)
662     FIELD(RB_DW12_REGISTER_1, DATA_BYTES49, 16, 8)
663     FIELD(RB_DW12_REGISTER_1, DATA_BYTES50, 8, 8)
664     FIELD(RB_DW12_REGISTER_1, DATA_BYTES51, 0, 8)
665 REG32(RB_DW13_REGISTER_1, 0x413c)
666     FIELD(RB_DW13_REGISTER_1, DATA_BYTES52, 24, 8)
667     FIELD(RB_DW13_REGISTER_1, DATA_BYTES53, 16, 8)
668     FIELD(RB_DW13_REGISTER_1, DATA_BYTES54, 8, 8)
669     FIELD(RB_DW13_REGISTER_1, DATA_BYTES55, 0, 8)
670 REG32(RB_DW14_REGISTER_1, 0x4140)
671     FIELD(RB_DW14_REGISTER_1, DATA_BYTES56, 24, 8)
672     FIELD(RB_DW14_REGISTER_1, DATA_BYTES57, 16, 8)
673     FIELD(RB_DW14_REGISTER_1, DATA_BYTES58, 8, 8)
674     FIELD(RB_DW14_REGISTER_1, DATA_BYTES59, 0, 8)
675 REG32(RB_DW15_REGISTER_1, 0x4144)
676     FIELD(RB_DW15_REGISTER_1, DATA_BYTES60, 24, 8)
677     FIELD(RB_DW15_REGISTER_1, DATA_BYTES61, 16, 8)
678     FIELD(RB_DW15_REGISTER_1, DATA_BYTES62, 8, 8)
679     FIELD(RB_DW15_REGISTER_1, DATA_BYTES63, 0, 8)
680 
681 static uint8_t canfd_dlc_array[8] = {8, 12, 16, 20, 24, 32, 48, 64};
682 
683 static void canfd_update_irq(XlnxVersalCANFDState *s)
684 {
685     unsigned int irq = s->regs[R_INTERRUPT_STATUS_REGISTER] &
686                         s->regs[R_INTERRUPT_ENABLE_REGISTER];
687     g_autofree char *path = object_get_canonical_path(OBJECT(s));
688 
689     /* RX watermark interrupts. */
690     if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL) >
691         ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM)) {
692         ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1);
693     }
694 
695     if (ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1) >
696         ARRAY_FIELD_EX32(s->regs, RX_FIFO_WATERMARK_REGISTER, RXFWM_1)) {
697         ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1, 1);
698     }
699 
700     /* TX watermark interrupt. */
701     if (ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL) >
702         ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_WATERMARK_REGISTER, TXE_FWM)) {
703         ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEWMFLL, 1);
704     }
705 
706     trace_xlnx_canfd_update_irq(path, s->regs[R_INTERRUPT_STATUS_REGISTER],
707                                 s->regs[R_INTERRUPT_ENABLE_REGISTER], irq);
708 
709     qemu_set_irq(s->irq_canfd_int, irq);
710 }
711 
712 static void canfd_ier_post_write(RegisterInfo *reg, uint64_t val64)
713 {
714     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
715 
716     canfd_update_irq(s);
717 }
718 
719 static uint64_t canfd_icr_pre_write(RegisterInfo *reg, uint64_t val64)
720 {
721     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
722     uint32_t val = val64;
723 
724     s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
725 
726     /*
727      * RXBOFLW_BI field is automatically cleared to default if RXBOFLW bit is
728      * cleared in ISR.
729      */
730     if (ARRAY_FIELD_EX32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL_1)) {
731         ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXBOFLW_BI, 0);
732     }
733 
734     canfd_update_irq(s);
735 
736     return 0;
737 }
738 
739 static void canfd_config_reset(XlnxVersalCANFDState *s)
740 {
741 
742     unsigned int i;
743 
744     /* Reset all the configuration registers. */
745     for (i = 0; i < R_RX_FIFO_WATERMARK_REGISTER; ++i) {
746         register_reset(&s->reg_info[i]);
747     }
748 
749     canfd_update_irq(s);
750 }
751 
752 static void canfd_config_mode(XlnxVersalCANFDState *s)
753 {
754     register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]);
755     register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]);
756     register_reset(&s->reg_info[R_STATUS_REGISTER]);
757 
758     /* Put XlnxVersalCANFDState in configuration mode. */
759     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1);
760     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0);
761     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0);
762     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0);
763     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR_BIT, 0);
764     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 0);
765     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 0);
766     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0);
767     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0);
768     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0);
769 
770     /* Clear the time stamp. */
771     ptimer_transaction_begin(s->canfd_timer);
772     ptimer_set_count(s->canfd_timer, 0);
773     ptimer_transaction_commit(s->canfd_timer);
774 
775     canfd_update_irq(s);
776 }
777 
778 static void update_status_register_mode_bits(XlnxVersalCANFDState *s)
779 {
780     bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP);
781     bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP);
782     /* Wake up interrupt bit. */
783     bool wakeup_irq_val = !sleep_mode && sleep_status;
784     /* Sleep interrupt bit. */
785     bool sleep_irq_val = sleep_mode && !sleep_status;
786 
787     /* Clear previous core mode status bits. */
788     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0);
789     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0);
790     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0);
791     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0);
792 
793     /* set current mode bit and generate irqs accordingly. */
794     if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) {
795         ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1);
796     } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) {
797         ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1);
798         ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP,
799                          sleep_irq_val);
800     } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
801         ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
802     } else {
803         /* If all bits are zero, XlnxVersalCANFDState is set in normal mode. */
804         ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1);
805         /* Set wakeup interrupt bit. */
806         ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP,
807                          wakeup_irq_val);
808     }
809 
810     /* Put the CANFD in error active state. */
811     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ESTAT, 1);
812 
813     canfd_update_irq(s);
814 }
815 
816 static uint64_t canfd_msr_pre_write(RegisterInfo *reg, uint64_t val64)
817 {
818     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
819     uint32_t val = val64;
820     uint8_t multi_mode = 0;
821 
822     /*
823      * Multiple mode set check. This is done to make sure user doesn't set
824      * multiple modes.
825      */
826     multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) +
827                  FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) +
828                  FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP);
829 
830     if (multi_mode > 1) {
831         qemu_log_mask(LOG_GUEST_ERROR, "Attempting to configure several modes"
832                       " simultaneously. One mode will be selected according to"
833                       " their priority: LBACK > SLEEP > SNOOP.\n");
834     }
835 
836     if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
837         /* In configuration mode, any mode can be selected. */
838         s->regs[R_MODE_SELECT_REGISTER] = val;
839     } else {
840         bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP);
841 
842         ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit);
843 
844         if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) {
845             qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set LBACK mode"
846                           " without setting CEN bit as 0\n");
847         } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) {
848             qemu_log_mask(LOG_GUEST_ERROR, "Attempting to set SNOOP mode"
849                           " without setting CEN bit as 0\n");
850         }
851 
852         update_status_register_mode_bits(s);
853     }
854 
855     return s->regs[R_MODE_SELECT_REGISTER];
856 }
857 
858 static void canfd_exit_sleep_mode(XlnxVersalCANFDState *s)
859 {
860     ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0);
861     update_status_register_mode_bits(s);
862 }
863 
864 static void regs2frame(XlnxVersalCANFDState *s, qemu_can_frame *frame,
865                        uint32_t reg_num)
866 {
867     uint32_t i = 0;
868     uint32_t j = 0;
869     uint32_t val = 0;
870     uint32_t dlc_reg_val = 0;
871     uint32_t dlc_value = 0;
872 
873     /* Check that reg_num should be within TX register space. */
874     assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE *
875                                           s->cfg.tx_fifo));
876 
877     dlc_reg_val = s->regs[reg_num + 1];
878     dlc_value = FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, DLC);
879 
880     frame->can_id = s->regs[reg_num];
881 
882     if (FIELD_EX32(dlc_reg_val, TB0_DLC_REGISTER, FDF)) {
883         /*
884          * CANFD frame.
885          * Converting dlc(0 to 15) 4 Byte data to plain length(i.e. 0 to 64)
886          * 1 Byte data. This is done to make it work with SocketCAN.
887          * On actual CANFD frame, this value can't be more than 0xF.
888          * Conversion table for DLC to plain length:
889          *
890          *  DLC                        Plain Length
891          *  0 - 8                      0 - 8
892          *  9                          9 - 12
893          *  10                         13 - 16
894          *  11                         17 - 20
895          *  12                         21 - 24
896          *  13                         25 - 32
897          *  14                         33 - 48
898          *  15                         49 - 64
899          */
900 
901         frame->flags = QEMU_CAN_FRMF_TYPE_FD;
902 
903         if (dlc_value < 8) {
904             frame->can_dlc = dlc_value;
905         } else {
906             assert((dlc_value - 8) < ARRAY_SIZE(canfd_dlc_array));
907             frame->can_dlc = canfd_dlc_array[dlc_value - 8];
908         }
909     } else {
910         /*
911          * FD Format bit not set that means it is a CAN Frame.
912          * Conversion table for classic CAN:
913          *
914          *  DLC                        Plain Length
915          *  0 - 7                      0 - 7
916          *  8 - 15                     8
917          */
918 
919         if (dlc_value > 8) {
920             frame->can_dlc = 8;
921             qemu_log_mask(LOG_GUEST_ERROR, "Maximum DLC value for Classic CAN"
922                           " frame is 8. Only 8 byte data will be sent.\n");
923         } else {
924             frame->can_dlc = dlc_value;
925         }
926     }
927 
928     for (j = 0; j < frame->can_dlc; j++) {
929         val = 8 * i;
930 
931         frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8);
932         i++;
933 
934         if (i % 4 == 0) {
935             i = 0;
936         }
937     }
938 }
939 
940 static void process_cancellation_requests(XlnxVersalCANFDState *s)
941 {
942     uint32_t clear_mask = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &
943                                  s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER];
944 
945     s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] &= ~clear_mask;
946     s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] &= ~clear_mask;
947 
948     canfd_update_irq(s);
949 }
950 
951 static void store_rx_sequential(XlnxVersalCANFDState *s,
952                                 const qemu_can_frame *frame,
953                                 uint32_t fill_level, uint32_t read_index,
954                                 uint32_t store_location, uint8_t rx_fifo,
955                                 bool rx_fifo_id, uint8_t filter_index)
956 {
957     int i;
958     bool is_canfd_frame;
959     uint8_t dlc = frame->can_dlc;
960     uint8_t rx_reg_num = 0;
961     uint32_t dlc_reg_val = 0;
962     uint32_t data_reg_val = 0;
963 
964     /* Getting RX0/1 fill level */
965     if ((fill_level) > rx_fifo - 1) {
966         g_autofree char *path = object_get_canonical_path(OBJECT(s));
967 
968         qemu_log_mask(LOG_GUEST_ERROR, "%s: RX%d Buffer is full. Discarding the"
969                       " message\n", path, rx_fifo_id);
970 
971         /* Set the corresponding RF buffer overflow interrupt. */
972         if (rx_fifo_id == 0) {
973             ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW, 1);
974         } else {
975             ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFOFLW_1, 1);
976         }
977     } else {
978         uint16_t rx_timestamp = CANFD_TIMER_MAX -
979                                     ptimer_get_count(s->canfd_timer);
980 
981         if (rx_timestamp == 0xFFFF) {
982             ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TSCNT_OFLW, 1);
983         } else {
984             ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT,
985                              rx_timestamp);
986         }
987 
988         if (rx_fifo_id == 0) {
989             ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL,
990                              fill_level + 1);
991             assert(store_location <=
992                               R_RB_ID_REGISTER + (s->cfg.rx0_fifo *
993                                                   NUM_REGS_PER_MSG_SPACE));
994         } else {
995             ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1,
996                              fill_level + 1);
997             assert(store_location <=
998                               R_RB_ID_REGISTER_1 + (s->cfg.rx1_fifo *
999                                                     NUM_REGS_PER_MSG_SPACE));
1000         }
1001 
1002         s->regs[store_location] = frame->can_id;
1003 
1004         dlc = frame->can_dlc;
1005 
1006         if (frame->flags == QEMU_CAN_FRMF_TYPE_FD) {
1007             is_canfd_frame = true;
1008 
1009             /* Store dlc value in Xilinx specific format. */
1010             for (i = 0; i < ARRAY_SIZE(canfd_dlc_array); i++) {
1011                 if (canfd_dlc_array[i] == frame->can_dlc) {
1012                     dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, 8 + i);
1013                 }
1014             }
1015         } else {
1016             is_canfd_frame = false;
1017 
1018             if (frame->can_dlc > 8) {
1019                 dlc = 8;
1020             }
1021 
1022             dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, dlc);
1023         }
1024 
1025         dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, is_canfd_frame);
1026         dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, TIMESTAMP, rx_timestamp);
1027         dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, MATCHED_FILTER_INDEX,
1028                                   filter_index);
1029         s->regs[store_location + 1] = dlc_reg_val;
1030 
1031         for (i = 0; i < dlc; i++) {
1032             /* Register size is 4 byte but frame->data each is 1 byte. */
1033             switch (i % 4) {
1034             case 0:
1035                 rx_reg_num = i / 4;
1036 
1037                 data_reg_val = FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES3,
1038                                           frame->data[i]);
1039                 break;
1040             case 1:
1041                 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES2,
1042                                            frame->data[i]);
1043                 break;
1044             case 2:
1045                 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES1,
1046                                            frame->data[i]);
1047                 break;
1048             case 3:
1049                 data_reg_val |= FIELD_DP32(0, RB_DW0_REGISTER, DATA_BYTES0,
1050                                            frame->data[i]);
1051                 /*
1052                  * Last Bytes data which means we have all 4 bytes ready to
1053                  * store in one rx regs.
1054                  */
1055                 s->regs[store_location + rx_reg_num + 2] = data_reg_val;
1056                 break;
1057             }
1058         }
1059 
1060         if (i % 4) {
1061             /*
1062              * In case DLC is not multiplier of 4, data is not saved to RX FIFO
1063              * in above switch case. Store the remaining bytes here.
1064              */
1065             s->regs[store_location + rx_reg_num + 2] = data_reg_val;
1066         }
1067 
1068         /* set the interrupt as RXOK. */
1069         ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
1070     }
1071 }
1072 
1073 static void update_rx_sequential(XlnxVersalCANFDState *s,
1074                                  const qemu_can_frame *frame)
1075 {
1076     bool filter_pass = false;
1077     uint8_t filter_index = 0;
1078     int i;
1079     int filter_partition = ARRAY_FIELD_EX32(s->regs,
1080                                             RX_FIFO_WATERMARK_REGISTER, RXFP);
1081     uint32_t store_location;
1082     uint32_t fill_level;
1083     uint32_t read_index;
1084     uint8_t store_index = 0;
1085     g_autofree char *path = NULL;
1086     /*
1087      * If all UAF bits are set to 0, then received messages are not stored
1088      * in the RX buffers.
1089      */
1090     if (s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER]) {
1091         uint32_t acceptance_filter_status =
1092                                 s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER];
1093 
1094         for (i = 0; i < 32; i++) {
1095             if (acceptance_filter_status & 0x1) {
1096                 uint32_t msg_id_masked = s->regs[R_AFMR_REGISTER + 2 * i] &
1097                                          frame->can_id;
1098                 uint32_t afir_id_masked = s->regs[R_AFIR_REGISTER + 2 * i] &
1099                                           s->regs[R_AFMR_REGISTER + 2 * i];
1100                 uint16_t std_msg_id_masked = FIELD_EX32(msg_id_masked,
1101                                                         AFIR_REGISTER, AIID);
1102                 uint16_t std_afir_id_masked = FIELD_EX32(afir_id_masked,
1103                                                          AFIR_REGISTER, AIID);
1104                 uint32_t ext_msg_id_masked = FIELD_EX32(msg_id_masked,
1105                                                         AFIR_REGISTER,
1106                                                         AIID_EXT);
1107                 uint32_t ext_afir_id_masked = FIELD_EX32(afir_id_masked,
1108                                                          AFIR_REGISTER,
1109                                                          AIID_EXT);
1110                 bool ext_ide = FIELD_EX32(s->regs[R_AFMR_REGISTER + 2 * i],
1111                                           AFMR_REGISTER, AMIDE);
1112 
1113                 if (std_msg_id_masked == std_afir_id_masked) {
1114                     if (ext_ide) {
1115                         /* Extended message ID message. */
1116                         if (ext_msg_id_masked == ext_afir_id_masked) {
1117                             filter_pass = true;
1118                             filter_index = i;
1119 
1120                             break;
1121                         }
1122                     } else {
1123                         /* Standard message ID. */
1124                         filter_pass = true;
1125                         filter_index = i;
1126 
1127                         break;
1128                     }
1129                 }
1130             }
1131             acceptance_filter_status >>= 1;
1132         }
1133     }
1134 
1135     if (!filter_pass) {
1136         path = object_get_canonical_path(OBJECT(s));
1137 
1138         trace_xlnx_canfd_rx_fifo_filter_reject(path, frame->can_id,
1139                                                frame->can_dlc);
1140     } else {
1141         if (filter_index <= filter_partition) {
1142             fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, FL);
1143             read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER, RI);
1144             store_index = read_index + fill_level;
1145 
1146             if (read_index == s->cfg.rx0_fifo - 1) {
1147                 /*
1148                  * When ri is s->cfg.rx0_fifo - 1 i.e. max, it goes cyclic that
1149                  * means we reset the ri to 0x0.
1150                  */
1151                 read_index = 0;
1152                 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI,
1153                                  read_index);
1154             }
1155 
1156             if (store_index > s->cfg.rx0_fifo - 1) {
1157                 store_index -= s->cfg.rx0_fifo - 1;
1158             }
1159 
1160             store_location = R_RB_ID_REGISTER +
1161                           (store_index * NUM_REGS_PER_MSG_SPACE);
1162 
1163             store_rx_sequential(s, frame, fill_level, read_index,
1164                                 store_location, s->cfg.rx0_fifo, 0,
1165                                 filter_index);
1166         } else {
1167             /* RX 1 fill level message */
1168             fill_level = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER,
1169                                           FL_1);
1170             read_index = ARRAY_FIELD_EX32(s->regs, RX_FIFO_STATUS_REGISTER,
1171                                           RI_1);
1172             store_index = read_index + fill_level;
1173 
1174             if (read_index == s->cfg.rx1_fifo - 1) {
1175                 /*
1176                  * When ri is s->cfg.rx1_fifo - 1 i.e. max, it goes cyclic that
1177                  * means we reset the ri to 0x0.
1178                  */
1179                 read_index = 0;
1180                 ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1,
1181                                  read_index);
1182             }
1183 
1184             if (store_index > s->cfg.rx1_fifo - 1) {
1185                 store_index -= s->cfg.rx1_fifo - 1;
1186             }
1187 
1188             store_location = R_RB_ID_REGISTER_1 +
1189                           (store_index * NUM_REGS_PER_MSG_SPACE);
1190 
1191             store_rx_sequential(s, frame, fill_level, read_index,
1192                                 store_location, s->cfg.rx1_fifo, 1,
1193                                 filter_index);
1194         }
1195 
1196         path = object_get_canonical_path(OBJECT(s));
1197 
1198         trace_xlnx_canfd_rx_data(path, frame->can_id, frame->can_dlc,
1199                                  frame->flags);
1200         canfd_update_irq(s);
1201     }
1202 }
1203 
1204 static bool tx_ready_check(XlnxVersalCANFDState *s)
1205 {
1206     if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
1207         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1208 
1209         qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1210                       " XlnxVersalCANFDState is in reset mode\n", path);
1211 
1212         return false;
1213     }
1214 
1215     if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1216         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1217 
1218         qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1219                       " XlnxVersalCANFDState is in configuration mode."
1220                       " Reset the core so operations can start fresh\n",
1221                       path);
1222         return false;
1223     }
1224 
1225     if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
1226         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1227 
1228         qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
1229                       " XlnxVersalCANFDState is in SNOOP MODE\n",
1230                       path);
1231         return false;
1232     }
1233 
1234     return true;
1235 }
1236 
1237 static void tx_fifo_stamp(XlnxVersalCANFDState *s, uint32_t tb0_regid)
1238 {
1239     /*
1240      * If EFC bit in DLC message is set, this means we will store the
1241      * event of this transmitted message with time stamp.
1242      */
1243     uint32_t dlc_reg_val = 0;
1244 
1245     if (FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER, EFC)) {
1246         uint8_t dlc_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1247                                      DLC);
1248         bool fdf_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1249                                   FDF);
1250         bool brs_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1251                                   BRS);
1252         uint8_t mm_val = FIELD_EX32(s->regs[tb0_regid + 1], TB0_DLC_REGISTER,
1253                                     MM);
1254         uint8_t fill_level = ARRAY_FIELD_EX32(s->regs,
1255                                               TX_EVENT_FIFO_STATUS_REGISTER,
1256                                               TXE_FL);
1257         uint8_t read_index = ARRAY_FIELD_EX32(s->regs,
1258                                               TX_EVENT_FIFO_STATUS_REGISTER,
1259                                               TXE_RI);
1260         uint8_t store_index = fill_level + read_index;
1261 
1262         if ((fill_level) > s->cfg.tx_fifo - 1) {
1263             qemu_log_mask(LOG_GUEST_ERROR, "TX Event Buffer is full."
1264                           " Discarding the message\n");
1265             ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXEOFLW, 1);
1266         } else {
1267             if (read_index == s->cfg.tx_fifo - 1) {
1268                 /*
1269                  * When ri is s->cfg.tx_fifo - 1 i.e. max, it goes cyclic that
1270                  * means we reset the ri to 0x0.
1271                  */
1272                 read_index = 0;
1273                 ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI,
1274                                  read_index);
1275             }
1276 
1277             if (store_index > s->cfg.tx_fifo - 1) {
1278                 store_index -= s->cfg.tx_fifo - 1;
1279             }
1280 
1281             assert(store_index < s->cfg.tx_fifo);
1282 
1283             uint32_t tx_event_reg0_id = R_TXE_FIFO_TB_ID_REGISTER +
1284                                         (store_index * 2);
1285 
1286             /* Store message ID in TX event register. */
1287             s->regs[tx_event_reg0_id] = s->regs[tb0_regid];
1288 
1289             uint16_t tx_timestamp = CANFD_TIMER_MAX -
1290                                             ptimer_get_count(s->canfd_timer);
1291 
1292             /* Store DLC with time stamp in DLC regs. */
1293             dlc_reg_val = FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, DLC, dlc_val);
1294             dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, FDF,
1295                                       fdf_val);
1296             dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, BRS,
1297                                       brs_val);
1298             dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, ET, 0x3);
1299             dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, MM, mm_val);
1300             dlc_reg_val |= FIELD_DP32(0, TXE_FIFO_TB_DLC_REGISTER, TIMESTAMP,
1301                                       tx_timestamp);
1302             s->regs[tx_event_reg0_id + 1] = dlc_reg_val;
1303 
1304             ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL,
1305                              fill_level + 1);
1306         }
1307     }
1308 }
1309 
1310 static gint g_cmp_ids(gconstpointer data1, gconstpointer data2)
1311 {
1312     tx_ready_reg_info *tx_reg_1 = (tx_ready_reg_info *) data1;
1313     tx_ready_reg_info *tx_reg_2 = (tx_ready_reg_info *) data2;
1314 
1315     return tx_reg_1->can_id - tx_reg_2->can_id;
1316 }
1317 
1318 static void free_list(GSList *list)
1319 {
1320     GSList *iterator = NULL;
1321 
1322     for (iterator = list; iterator != NULL; iterator = iterator->next) {
1323         g_free((tx_ready_reg_info *)iterator->data);
1324     }
1325 
1326     g_slist_free(list);
1327 
1328     return;
1329 }
1330 
1331 static GSList *prepare_tx_data(XlnxVersalCANFDState *s)
1332 {
1333     uint8_t i = 0;
1334     GSList *list = NULL;
1335     uint32_t reg_num = 0;
1336     uint32_t reg_ready = s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER];
1337 
1338     /* First find the messages which are ready for transmission. */
1339     for (i = 0; i < s->cfg.tx_fifo; i++) {
1340         if (reg_ready & 1) {
1341             reg_num = R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * i);
1342             tx_ready_reg_info *temp = g_new(tx_ready_reg_info, 1);
1343 
1344             temp->can_id = s->regs[reg_num];
1345             temp->reg_num = reg_num;
1346             list = g_slist_prepend(list, temp);
1347             list = g_slist_sort(list, g_cmp_ids);
1348         }
1349 
1350         reg_ready >>= 1;
1351     }
1352 
1353     s->regs[R_TX_BUFFER_READY_REQUEST_REGISTER] = 0;
1354     s->regs[R_TX_BUFFER_CANCEL_REQUEST_REGISTER] = 0;
1355 
1356     return list;
1357 }
1358 
1359 static void transfer_data(XlnxVersalCANFDState *s)
1360 {
1361     bool canfd_tx = tx_ready_check(s);
1362     GSList *list, *iterator = NULL;
1363     qemu_can_frame frame;
1364 
1365     if (!canfd_tx) {
1366         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1367 
1368         qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller not enabled for data"
1369                       " transfer\n", path);
1370         return;
1371     }
1372 
1373     list = prepare_tx_data(s);
1374     if (list == NULL) {
1375         return;
1376     }
1377 
1378     for (iterator = list; iterator != NULL; iterator = iterator->next) {
1379         regs2frame(s, &frame,
1380                    ((tx_ready_reg_info *)iterator->data)->reg_num);
1381 
1382         if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
1383             update_rx_sequential(s, &frame);
1384             tx_fifo_stamp(s, ((tx_ready_reg_info *)iterator->data)->reg_num);
1385 
1386             ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
1387         } else {
1388             g_autofree char *path = object_get_canonical_path(OBJECT(s));
1389 
1390             trace_xlnx_canfd_tx_data(path, frame.can_id, frame.can_dlc,
1391                                      frame.flags);
1392             can_bus_client_send(&s->bus_client, &frame, 1);
1393             tx_fifo_stamp(s,
1394                           ((tx_ready_reg_info *)iterator->data)->reg_num);
1395 
1396             ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXRRS, 1);
1397 
1398             if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
1399                 canfd_exit_sleep_mode(s);
1400             }
1401         }
1402     }
1403 
1404     ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
1405     free_list(list);
1406 
1407     canfd_update_irq(s);
1408 }
1409 
1410 static uint64_t canfd_srr_pre_write(RegisterInfo *reg, uint64_t val64)
1411 {
1412     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1413     uint32_t val = val64;
1414 
1415     ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
1416                      FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
1417 
1418     if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
1419         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1420 
1421         trace_xlnx_canfd_reset(path, val64);
1422 
1423         /* First, core will do software reset then will enter in config mode. */
1424         canfd_config_reset(s);
1425     } else if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1426         canfd_config_mode(s);
1427     } else {
1428         /*
1429          * Leave config mode. Now XlnxVersalCANFD core will enter Normal, Sleep,
1430          * snoop or Loopback mode depending upon LBACK, SLEEP, SNOOP register
1431          * states.
1432          */
1433         ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0);
1434 
1435         ptimer_transaction_begin(s->canfd_timer);
1436         ptimer_set_count(s->canfd_timer, 0);
1437         ptimer_transaction_commit(s->canfd_timer);
1438         update_status_register_mode_bits(s);
1439         transfer_data(s);
1440     }
1441 
1442     return s->regs[R_SOFTWARE_RESET_REGISTER];
1443 }
1444 
1445 static uint64_t filter_mask(RegisterInfo *reg, uint64_t val64)
1446 {
1447     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1448     uint32_t reg_idx = (reg->access->addr) / 4;
1449     uint32_t val = val64;
1450     uint32_t filter_offset = (reg_idx - R_AFMR_REGISTER) / 2;
1451 
1452     if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] &
1453         (1 << filter_offset))) {
1454         s->regs[reg_idx] = val;
1455     } else {
1456         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1457 
1458         qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabled\n",
1459                       path, filter_offset + 1);
1460     }
1461 
1462     return s->regs[reg_idx];
1463 }
1464 
1465 static uint64_t filter_id(RegisterInfo *reg, uint64_t val64)
1466 {
1467     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1468     hwaddr reg_idx = (reg->access->addr) / 4;
1469     uint32_t val = val64;
1470     uint32_t filter_offset = (reg_idx - R_AFIR_REGISTER) / 2;
1471 
1472     if (!(s->regs[R_ACCEPTANCE_FILTER_CONTROL_REGISTER] &
1473         (1 << filter_offset))) {
1474         s->regs[reg_idx] = val;
1475     } else {
1476         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1477 
1478         qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d not enabled\n",
1479                       path, filter_offset + 1);
1480     }
1481 
1482     return s->regs[reg_idx];
1483 }
1484 
1485 static uint64_t canfd_tx_fifo_status_prew(RegisterInfo *reg, uint64_t val64)
1486 {
1487     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1488     uint32_t val = val64;
1489     uint8_t read_ind = 0;
1490     uint8_t fill_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER,
1491                                         TXE_FL);
1492 
1493     if (FIELD_EX32(val, TX_EVENT_FIFO_STATUS_REGISTER, TXE_IRI) && fill_ind) {
1494         read_ind = ARRAY_FIELD_EX32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER,
1495                                     TXE_RI) + 1;
1496 
1497         if (read_ind > s->cfg.tx_fifo - 1) {
1498             read_ind = 0;
1499         }
1500 
1501         /*
1502          * Increase the read index by 1 and decrease the fill level by 1.
1503          */
1504         ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_RI,
1505                          read_ind);
1506         ARRAY_FIELD_DP32(s->regs, TX_EVENT_FIFO_STATUS_REGISTER, TXE_FL,
1507                          fill_ind - 1);
1508     }
1509 
1510     return s->regs[R_TX_EVENT_FIFO_STATUS_REGISTER];
1511 }
1512 
1513 static uint64_t canfd_rx_fifo_status_prew(RegisterInfo *reg, uint64_t val64)
1514 {
1515     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1516     uint32_t val = val64;
1517     uint8_t read_ind = 0;
1518     uint8_t fill_ind = 0;
1519 
1520     if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI)) {
1521         /* FL index is zero, setting IRI bit has no effect. */
1522         if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) != 0) {
1523             read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI) + 1;
1524 
1525             if (read_ind > s->cfg.rx0_fifo - 1) {
1526                 read_ind = 0;
1527             }
1528 
1529             fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL) - 1;
1530 
1531             ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI, read_ind);
1532             ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL, fill_ind);
1533         }
1534     }
1535 
1536     if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, IRI_1)) {
1537         /* FL_1 index is zero, setting IRI_1 bit has no effect. */
1538         if (FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) != 0) {
1539             read_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, RI_1) + 1;
1540 
1541             if (read_ind > s->cfg.rx1_fifo - 1) {
1542                 read_ind = 0;
1543             }
1544 
1545             fill_ind = FIELD_EX32(val, RX_FIFO_STATUS_REGISTER, FL_1) - 1;
1546 
1547             ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, RI_1, read_ind);
1548             ARRAY_FIELD_DP32(s->regs, RX_FIFO_STATUS_REGISTER, FL_1, fill_ind);
1549         }
1550     }
1551 
1552     return s->regs[R_RX_FIFO_STATUS_REGISTER];
1553 }
1554 
1555 static uint64_t canfd_tsr_pre_write(RegisterInfo *reg, uint64_t val64)
1556 {
1557     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1558     uint32_t val = val64;
1559 
1560     if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
1561         ARRAY_FIELD_DP32(s->regs, TIMESTAMP_REGISTER, TIMESTAMP_CNT, 0);
1562         ptimer_transaction_begin(s->canfd_timer);
1563         ptimer_set_count(s->canfd_timer, 0);
1564         ptimer_transaction_commit(s->canfd_timer);
1565     }
1566 
1567     return 0;
1568 }
1569 
1570 static uint64_t canfd_trr_reg_prew(RegisterInfo *reg, uint64_t val64)
1571 {
1572     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1573 
1574     if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
1575         g_autofree char *path = object_get_canonical_path(OBJECT(s));
1576 
1577         qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in SNOOP mode."
1578                       " tx_ready_register will stay in reset mode\n", path);
1579         return 0;
1580     } else {
1581         return val64;
1582     }
1583 }
1584 
1585 static void canfd_trr_reg_postw(RegisterInfo *reg, uint64_t val64)
1586 {
1587     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1588 
1589     transfer_data(s);
1590 }
1591 
1592 static void canfd_cancel_reg_postw(RegisterInfo *reg, uint64_t val64)
1593 {
1594     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1595 
1596     process_cancellation_requests(s);
1597 }
1598 
1599 static uint64_t canfd_write_check_prew(RegisterInfo *reg, uint64_t val64)
1600 {
1601     XlnxVersalCANFDState *s = XILINX_CANFD(reg->opaque);
1602     uint32_t val = val64;
1603 
1604     if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
1605         return val;
1606     }
1607     return 0;
1608 }
1609 
1610 static const RegisterAccessInfo canfd_tx_regs[] = {
1611     {   .name = "TB_ID_REGISTER",  .addr = A_TB_ID_REGISTER,
1612     },{ .name = "TB0_DLC_REGISTER",  .addr = A_TB0_DLC_REGISTER,
1613     },{ .name = "TB_DW0_REGISTER",  .addr = A_TB_DW0_REGISTER,
1614     },{ .name = "TB_DW1_REGISTER",  .addr = A_TB_DW1_REGISTER,
1615     },{ .name = "TB_DW2_REGISTER",  .addr = A_TB_DW2_REGISTER,
1616     },{ .name = "TB_DW3_REGISTER",  .addr = A_TB_DW3_REGISTER,
1617     },{ .name = "TB_DW4_REGISTER",  .addr = A_TB_DW4_REGISTER,
1618     },{ .name = "TB_DW5_REGISTER",  .addr = A_TB_DW5_REGISTER,
1619     },{ .name = "TB_DW6_REGISTER",  .addr = A_TB_DW6_REGISTER,
1620     },{ .name = "TB_DW7_REGISTER",  .addr = A_TB_DW7_REGISTER,
1621     },{ .name = "TB_DW8_REGISTER",  .addr = A_TB_DW8_REGISTER,
1622     },{ .name = "TB_DW9_REGISTER",  .addr = A_TB_DW9_REGISTER,
1623     },{ .name = "TB_DW10_REGISTER",  .addr = A_TB_DW10_REGISTER,
1624     },{ .name = "TB_DW11_REGISTER",  .addr = A_TB_DW11_REGISTER,
1625     },{ .name = "TB_DW12_REGISTER",  .addr = A_TB_DW12_REGISTER,
1626     },{ .name = "TB_DW13_REGISTER",  .addr = A_TB_DW13_REGISTER,
1627     },{ .name = "TB_DW14_REGISTER",  .addr = A_TB_DW14_REGISTER,
1628     },{ .name = "TB_DW15_REGISTER",  .addr = A_TB_DW15_REGISTER,
1629     }
1630 };
1631 
1632 static const RegisterAccessInfo canfd_rx0_regs[] = {
1633     {   .name = "RB_ID_REGISTER",  .addr = A_RB_ID_REGISTER,
1634         .ro = 0xffffffff,
1635     },{ .name = "RB_DLC_REGISTER",  .addr = A_RB_DLC_REGISTER,
1636         .ro = 0xfe1fffff,
1637     },{ .name = "RB_DW0_REGISTER",  .addr = A_RB_DW0_REGISTER,
1638         .ro = 0xffffffff,
1639     },{ .name = "RB_DW1_REGISTER",  .addr = A_RB_DW1_REGISTER,
1640         .ro = 0xffffffff,
1641     },{ .name = "RB_DW2_REGISTER",  .addr = A_RB_DW2_REGISTER,
1642         .ro = 0xffffffff,
1643     },{ .name = "RB_DW3_REGISTER",  .addr = A_RB_DW3_REGISTER,
1644         .ro = 0xffffffff,
1645     },{ .name = "RB_DW4_REGISTER",  .addr = A_RB_DW4_REGISTER,
1646         .ro = 0xffffffff,
1647     },{ .name = "RB_DW5_REGISTER",  .addr = A_RB_DW5_REGISTER,
1648         .ro = 0xffffffff,
1649     },{ .name = "RB_DW6_REGISTER",  .addr = A_RB_DW6_REGISTER,
1650         .ro = 0xffffffff,
1651     },{ .name = "RB_DW7_REGISTER",  .addr = A_RB_DW7_REGISTER,
1652         .ro = 0xffffffff,
1653     },{ .name = "RB_DW8_REGISTER",  .addr = A_RB_DW8_REGISTER,
1654         .ro = 0xffffffff,
1655     },{ .name = "RB_DW9_REGISTER",  .addr = A_RB_DW9_REGISTER,
1656         .ro = 0xffffffff,
1657     },{ .name = "RB_DW10_REGISTER",  .addr = A_RB_DW10_REGISTER,
1658         .ro = 0xffffffff,
1659     },{ .name = "RB_DW11_REGISTER",  .addr = A_RB_DW11_REGISTER,
1660         .ro = 0xffffffff,
1661     },{ .name = "RB_DW12_REGISTER",  .addr = A_RB_DW12_REGISTER,
1662         .ro = 0xffffffff,
1663     },{ .name = "RB_DW13_REGISTER",  .addr = A_RB_DW13_REGISTER,
1664         .ro = 0xffffffff,
1665     },{ .name = "RB_DW14_REGISTER",  .addr = A_RB_DW14_REGISTER,
1666         .ro = 0xffffffff,
1667     },{ .name = "RB_DW15_REGISTER",  .addr = A_RB_DW15_REGISTER,
1668         .ro = 0xffffffff,
1669     }
1670 };
1671 
1672 static const RegisterAccessInfo canfd_rx1_regs[] = {
1673     {   .name = "RB_ID_REGISTER_1",  .addr = A_RB_ID_REGISTER_1,
1674         .ro = 0xffffffff,
1675     },{ .name = "RB_DLC_REGISTER_1",  .addr = A_RB_DLC_REGISTER_1,
1676         .ro = 0xfe1fffff,
1677     },{ .name = "RB0_DW0_REGISTER_1",  .addr = A_RB0_DW0_REGISTER_1,
1678         .ro = 0xffffffff,
1679     },{ .name = "RB_DW1_REGISTER_1",  .addr = A_RB_DW1_REGISTER_1,
1680         .ro = 0xffffffff,
1681     },{ .name = "RB_DW2_REGISTER_1",  .addr = A_RB_DW2_REGISTER_1,
1682         .ro = 0xffffffff,
1683     },{ .name = "RB_DW3_REGISTER_1",  .addr = A_RB_DW3_REGISTER_1,
1684         .ro = 0xffffffff,
1685     },{ .name = "RB_DW4_REGISTER_1",  .addr = A_RB_DW4_REGISTER_1,
1686         .ro = 0xffffffff,
1687     },{ .name = "RB_DW5_REGISTER_1",  .addr = A_RB_DW5_REGISTER_1,
1688         .ro = 0xffffffff,
1689     },{ .name = "RB_DW6_REGISTER_1",  .addr = A_RB_DW6_REGISTER_1,
1690         .ro = 0xffffffff,
1691     },{ .name = "RB_DW7_REGISTER_1",  .addr = A_RB_DW7_REGISTER_1,
1692         .ro = 0xffffffff,
1693     },{ .name = "RB_DW8_REGISTER_1",  .addr = A_RB_DW8_REGISTER_1,
1694         .ro = 0xffffffff,
1695     },{ .name = "RB_DW9_REGISTER_1",  .addr = A_RB_DW9_REGISTER_1,
1696         .ro = 0xffffffff,
1697     },{ .name = "RB_DW10_REGISTER_1",  .addr = A_RB_DW10_REGISTER_1,
1698         .ro = 0xffffffff,
1699     },{ .name = "RB_DW11_REGISTER_1",  .addr = A_RB_DW11_REGISTER_1,
1700         .ro = 0xffffffff,
1701     },{ .name = "RB_DW12_REGISTER_1",  .addr = A_RB_DW12_REGISTER_1,
1702         .ro = 0xffffffff,
1703     },{ .name = "RB_DW13_REGISTER_1",  .addr = A_RB_DW13_REGISTER_1,
1704         .ro = 0xffffffff,
1705     },{ .name = "RB_DW14_REGISTER_1",  .addr = A_RB_DW14_REGISTER_1,
1706         .ro = 0xffffffff,
1707     },{ .name = "RB_DW15_REGISTER_1",  .addr = A_RB_DW15_REGISTER_1,
1708         .ro = 0xffffffff,
1709     }
1710 };
1711 
1712 /* Acceptance filter registers. */
1713 static const RegisterAccessInfo canfd_af_regs[] = {
1714     {   .name = "AFMR_REGISTER",  .addr = A_AFMR_REGISTER,
1715         .pre_write = filter_mask,
1716     },{ .name = "AFIR_REGISTER",  .addr = A_AFIR_REGISTER,
1717         .pre_write = filter_id,
1718     }
1719 };
1720 
1721 static const RegisterAccessInfo canfd_txe_regs[] = {
1722     {   .name = "TXE_FIFO_TB_ID_REGISTER",  .addr = A_TXE_FIFO_TB_ID_REGISTER,
1723         .ro = 0xffffffff,
1724     },{ .name = "TXE_FIFO_TB_DLC_REGISTER",  .addr = A_TXE_FIFO_TB_DLC_REGISTER,
1725         .ro = 0xffffffff,
1726     }
1727 };
1728 
1729 static const RegisterAccessInfo canfd_regs_info[] = {
1730     {   .name = "SOFTWARE_RESET_REGISTER",  .addr = A_SOFTWARE_RESET_REGISTER,
1731         .pre_write = canfd_srr_pre_write,
1732     },{ .name = "MODE_SELECT_REGISTER",  .addr = A_MODE_SELECT_REGISTER,
1733         .pre_write = canfd_msr_pre_write,
1734     },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER",
1735         .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER,
1736         .pre_write = canfd_write_check_prew,
1737     },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER",
1738         .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER,
1739         .pre_write = canfd_write_check_prew,
1740     },{ .name = "ERROR_COUNTER_REGISTER",  .addr = A_ERROR_COUNTER_REGISTER,
1741         .ro = 0xffff,
1742     },{ .name = "ERROR_STATUS_REGISTER",  .addr = A_ERROR_STATUS_REGISTER,
1743         .w1c = 0xf1f,
1744     },{ .name = "STATUS_REGISTER",  .addr = A_STATUS_REGISTER,
1745         .reset = 0x1,
1746         .ro = 0x7f17ff,
1747     },{ .name = "INTERRUPT_STATUS_REGISTER",
1748         .addr = A_INTERRUPT_STATUS_REGISTER,
1749         .ro = 0xffffff7f,
1750     },{ .name = "INTERRUPT_ENABLE_REGISTER",
1751         .addr = A_INTERRUPT_ENABLE_REGISTER,
1752         .post_write = canfd_ier_post_write,
1753     },{ .name = "INTERRUPT_CLEAR_REGISTER",
1754         .addr = A_INTERRUPT_CLEAR_REGISTER, .pre_write = canfd_icr_pre_write,
1755     },{ .name = "TIMESTAMP_REGISTER",  .addr = A_TIMESTAMP_REGISTER,
1756         .ro = 0xffff0000,
1757         .pre_write = canfd_tsr_pre_write,
1758     },{ .name = "DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER",
1759         .addr = A_DATA_PHASE_BAUD_RATE_PRESCALER_REGISTER,
1760         .pre_write = canfd_write_check_prew,
1761     },{ .name = "DATA_PHASE_BIT_TIMING_REGISTER",
1762         .addr = A_DATA_PHASE_BIT_TIMING_REGISTER,
1763         .pre_write = canfd_write_check_prew,
1764     },{ .name = "TX_BUFFER_READY_REQUEST_REGISTER",
1765         .addr = A_TX_BUFFER_READY_REQUEST_REGISTER,
1766         .pre_write = canfd_trr_reg_prew,
1767         .post_write = canfd_trr_reg_postw,
1768     },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER",
1769         .addr = A_INTERRUPT_ENABLE_TX_BUFFER_READY_REQUEST_REGISTER,
1770     },{ .name = "TX_BUFFER_CANCEL_REQUEST_REGISTER",
1771         .addr = A_TX_BUFFER_CANCEL_REQUEST_REGISTER,
1772         .post_write = canfd_cancel_reg_postw,
1773     },{ .name = "INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER",
1774         .addr = A_INTERRUPT_ENABLE_TX_BUFFER_CANCELLATION_REQUEST_REGISTER,
1775     },{ .name = "TX_EVENT_FIFO_STATUS_REGISTER",
1776         .addr = A_TX_EVENT_FIFO_STATUS_REGISTER,
1777         .ro = 0x3f1f, .pre_write = canfd_tx_fifo_status_prew,
1778     },{ .name = "TX_EVENT_FIFO_WATERMARK_REGISTER",
1779         .addr = A_TX_EVENT_FIFO_WATERMARK_REGISTER,
1780         .reset = 0xf,
1781         .pre_write = canfd_write_check_prew,
1782     },{ .name = "ACCEPTANCE_FILTER_CONTROL_REGISTER",
1783         .addr = A_ACCEPTANCE_FILTER_CONTROL_REGISTER,
1784     },{ .name = "RX_FIFO_STATUS_REGISTER",  .addr = A_RX_FIFO_STATUS_REGISTER,
1785         .ro = 0x7f3f7f3f, .pre_write = canfd_rx_fifo_status_prew,
1786     },{ .name = "RX_FIFO_WATERMARK_REGISTER",
1787         .addr = A_RX_FIFO_WATERMARK_REGISTER,
1788         .reset = 0x1f0f0f,
1789         .pre_write = canfd_write_check_prew,
1790     }
1791 };
1792 
1793 static void xlnx_versal_canfd_ptimer_cb(void *opaque)
1794 {
1795     /* No action required on the timer rollover. */
1796 }
1797 
1798 static const MemoryRegionOps canfd_ops = {
1799     .read = register_read_memory,
1800     .write = register_write_memory,
1801     .endianness = DEVICE_LITTLE_ENDIAN,
1802     .valid = {
1803         .min_access_size = 4,
1804         .max_access_size = 4,
1805     },
1806 };
1807 
1808 static void canfd_reset(DeviceState *dev)
1809 {
1810     XlnxVersalCANFDState *s = XILINX_CANFD(dev);
1811     unsigned int i;
1812 
1813     for (i = 0; i < ARRAY_SIZE(s->reg_info); ++i) {
1814         register_reset(&s->reg_info[i]);
1815     }
1816 
1817     ptimer_transaction_begin(s->canfd_timer);
1818     ptimer_set_count(s->canfd_timer, 0);
1819     ptimer_transaction_commit(s->canfd_timer);
1820 }
1821 
1822 static bool can_xilinx_canfd_receive(CanBusClientState *client)
1823 {
1824     XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState,
1825                                            bus_client);
1826 
1827     bool reset_state = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST);
1828     bool can_enabled = ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN);
1829 
1830     return !reset_state && can_enabled;
1831 }
1832 
1833 static ssize_t canfd_xilinx_receive(CanBusClientState *client,
1834                                     const qemu_can_frame *buf,
1835                                     size_t buf_size)
1836 {
1837     XlnxVersalCANFDState *s = container_of(client, XlnxVersalCANFDState,
1838                                            bus_client);
1839     const qemu_can_frame *frame = buf;
1840 
1841     assert(buf_size > 0);
1842 
1843     if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
1844         /*
1845          * XlnxVersalCANFDState will not participate in normal bus communication
1846          * and does not receive any messages transmitted by other CAN nodes.
1847          */
1848         return 1;
1849     }
1850 
1851     /* Update the status register that we are receiving message. */
1852     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 1);
1853 
1854     if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
1855         /* Snoop Mode: Just keep the data. no response back. */
1856         update_rx_sequential(s, frame);
1857     } else {
1858         if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
1859             /*
1860              * XlnxVersalCANFDState is in sleep mode. Any data on bus will bring
1861              * it to the wake up state.
1862              */
1863             canfd_exit_sleep_mode(s);
1864         }
1865 
1866         update_rx_sequential(s, frame);
1867     }
1868 
1869     /* Message processing done. Update the status back to !busy */
1870     ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, BBSY, 0);
1871     return 1;
1872 }
1873 
1874 static CanBusClientInfo canfd_xilinx_bus_client_info = {
1875     .can_receive = can_xilinx_canfd_receive,
1876     .receive = canfd_xilinx_receive,
1877 };
1878 
1879 static int xlnx_canfd_connect_to_bus(XlnxVersalCANFDState *s,
1880                                      CanBusState *bus)
1881 {
1882     s->bus_client.info = &canfd_xilinx_bus_client_info;
1883 
1884     return can_bus_insert_client(bus, &s->bus_client);
1885 }
1886 
1887 #define NUM_REG_PER_AF      ARRAY_SIZE(canfd_af_regs)
1888 #define NUM_AF              32
1889 #define NUM_REG_PER_TXE     ARRAY_SIZE(canfd_txe_regs)
1890 #define NUM_TXE             32
1891 
1892 static int canfd_populate_regarray(XlnxVersalCANFDState *s,
1893                                   RegisterInfoArray *r_array, int pos,
1894                                   const RegisterAccessInfo *rae,
1895                                   int num_rae)
1896 {
1897     int i;
1898 
1899     for (i = 0; i < num_rae; i++) {
1900         int index = rae[i].addr / 4;
1901         RegisterInfo *r = &s->reg_info[index];
1902 
1903         object_initialize(r, sizeof(*r), TYPE_REGISTER);
1904 
1905         *r = (RegisterInfo) {
1906             .data = &s->regs[index],
1907             .data_size = sizeof(uint32_t),
1908             .access = &rae[i],
1909             .opaque = OBJECT(s),
1910         };
1911 
1912         r_array->r[i + pos] = r;
1913     }
1914     return i + pos;
1915 }
1916 
1917 static void canfd_create_rai(RegisterAccessInfo *rai_array,
1918                                 const RegisterAccessInfo *canfd_regs,
1919                                 int template_rai_array_sz,
1920                                 int num_template_to_copy)
1921 {
1922     int i;
1923     int reg_num;
1924 
1925     for (reg_num = 0; reg_num < num_template_to_copy; reg_num++) {
1926         int pos = reg_num * template_rai_array_sz;
1927 
1928         memcpy(rai_array + pos, canfd_regs,
1929                template_rai_array_sz * sizeof(RegisterAccessInfo));
1930 
1931         for (i = 0; i < template_rai_array_sz; i++) {
1932             const char *name = canfd_regs[i].name;
1933             uint64_t addr = canfd_regs[i].addr;
1934             rai_array[i + pos].name = g_strdup_printf("%s%d", name, reg_num);
1935             rai_array[i + pos].addr = addr + pos * 4;
1936         }
1937     }
1938 }
1939 
1940 static RegisterInfoArray *canfd_create_regarray(XlnxVersalCANFDState *s)
1941 {
1942     const char *device_prefix = object_get_typename(OBJECT(s));
1943     uint64_t memory_size = XLNX_VERSAL_CANFD_R_MAX * 4;
1944     int num_regs;
1945     int pos = 0;
1946     RegisterInfoArray *r_array;
1947 
1948     num_regs = ARRAY_SIZE(canfd_regs_info) +
1949                 s->cfg.tx_fifo * NUM_REGS_PER_MSG_SPACE +
1950                 s->cfg.rx0_fifo * NUM_REGS_PER_MSG_SPACE +
1951                 NUM_AF * NUM_REG_PER_AF +
1952                 NUM_TXE * NUM_REG_PER_TXE;
1953 
1954     s->tx_regs = g_new0(RegisterAccessInfo,
1955                         s->cfg.tx_fifo * ARRAY_SIZE(canfd_tx_regs));
1956 
1957     canfd_create_rai(s->tx_regs, canfd_tx_regs,
1958                      ARRAY_SIZE(canfd_tx_regs), s->cfg.tx_fifo);
1959 
1960     s->rx0_regs = g_new0(RegisterAccessInfo,
1961                          s->cfg.rx0_fifo * ARRAY_SIZE(canfd_rx0_regs));
1962 
1963     canfd_create_rai(s->rx0_regs, canfd_rx0_regs,
1964                      ARRAY_SIZE(canfd_rx0_regs), s->cfg.rx0_fifo);
1965 
1966     s->af_regs = g_new0(RegisterAccessInfo,
1967                         NUM_AF * ARRAY_SIZE(canfd_af_regs));
1968 
1969     canfd_create_rai(s->af_regs, canfd_af_regs,
1970                      ARRAY_SIZE(canfd_af_regs), NUM_AF);
1971 
1972     s->txe_regs = g_new0(RegisterAccessInfo,
1973                          NUM_TXE * ARRAY_SIZE(canfd_txe_regs));
1974 
1975     canfd_create_rai(s->txe_regs, canfd_txe_regs,
1976                      ARRAY_SIZE(canfd_txe_regs), NUM_TXE);
1977 
1978     if (s->cfg.enable_rx_fifo1) {
1979         num_regs += s->cfg.rx1_fifo * NUM_REGS_PER_MSG_SPACE;
1980 
1981         s->rx1_regs = g_new0(RegisterAccessInfo,
1982                              s->cfg.rx1_fifo * ARRAY_SIZE(canfd_rx1_regs));
1983 
1984         canfd_create_rai(s->rx1_regs, canfd_rx1_regs,
1985                          ARRAY_SIZE(canfd_rx1_regs), s->cfg.rx1_fifo);
1986     }
1987 
1988     r_array = g_new0(RegisterInfoArray, 1);
1989     r_array->r = g_new0(RegisterInfo * , num_regs);
1990     r_array->num_elements = num_regs;
1991     r_array->prefix = device_prefix;
1992 
1993     pos = canfd_populate_regarray(s, r_array, pos,
1994                                   canfd_regs_info,
1995                                   ARRAY_SIZE(canfd_regs_info));
1996     pos = canfd_populate_regarray(s, r_array, pos,
1997                                   s->tx_regs, s->cfg.tx_fifo *
1998                                   NUM_REGS_PER_MSG_SPACE);
1999     pos = canfd_populate_regarray(s, r_array, pos,
2000                                   s->rx0_regs, s->cfg.rx0_fifo *
2001                                   NUM_REGS_PER_MSG_SPACE);
2002     if (s->cfg.enable_rx_fifo1) {
2003         pos = canfd_populate_regarray(s, r_array, pos,
2004                                       s->rx1_regs, s->cfg.rx1_fifo *
2005                                       NUM_REGS_PER_MSG_SPACE);
2006     }
2007     pos = canfd_populate_regarray(s, r_array, pos,
2008                                   s->af_regs, NUM_AF * NUM_REG_PER_AF);
2009     pos = canfd_populate_regarray(s, r_array, pos,
2010                                   s->txe_regs, NUM_TXE * NUM_REG_PER_TXE);
2011 
2012     memory_region_init_io(&r_array->mem, OBJECT(s), &canfd_ops, r_array,
2013                           device_prefix, memory_size);
2014     return r_array;
2015 }
2016 
2017 static void canfd_realize(DeviceState *dev, Error **errp)
2018 {
2019     XlnxVersalCANFDState *s = XILINX_CANFD(dev);
2020     RegisterInfoArray *reg_array;
2021 
2022     reg_array = canfd_create_regarray(s);
2023     memory_region_add_subregion(&s->iomem, 0x00, &reg_array->mem);
2024     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
2025     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq_canfd_int);
2026 
2027     if (s->canfdbus) {
2028         if (xlnx_canfd_connect_to_bus(s, s->canfdbus) < 0) {
2029             g_autofree char *path = object_get_canonical_path(OBJECT(s));
2030 
2031             error_setg(errp, "%s: xlnx_canfd_connect_to_bus failed", path);
2032             return;
2033         }
2034 
2035     }
2036 
2037     /* Allocate a new timer. */
2038     s->canfd_timer = ptimer_init(xlnx_versal_canfd_ptimer_cb, s,
2039                                  PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
2040                                  PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
2041                                  PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
2042 
2043     ptimer_transaction_begin(s->canfd_timer);
2044 
2045     ptimer_set_freq(s->canfd_timer, s->cfg.ext_clk_freq);
2046     ptimer_set_limit(s->canfd_timer, CANFD_TIMER_MAX, 1);
2047     ptimer_run(s->canfd_timer, 0);
2048     ptimer_transaction_commit(s->canfd_timer);
2049 }
2050 
2051 static void canfd_init(Object *obj)
2052 {
2053     XlnxVersalCANFDState *s = XILINX_CANFD(obj);
2054 
2055     memory_region_init(&s->iomem, obj, TYPE_XILINX_CANFD,
2056                        XLNX_VERSAL_CANFD_R_MAX * 4);
2057 }
2058 
2059 static const VMStateDescription vmstate_canfd = {
2060     .name = TYPE_XILINX_CANFD,
2061     .version_id = 1,
2062     .minimum_version_id = 1,
2063     .fields = (VMStateField[]) {
2064         VMSTATE_UINT32_ARRAY(regs, XlnxVersalCANFDState,
2065                              XLNX_VERSAL_CANFD_R_MAX),
2066         VMSTATE_PTIMER(canfd_timer, XlnxVersalCANFDState),
2067         VMSTATE_END_OF_LIST(),
2068     }
2069 };
2070 
2071 static Property canfd_core_properties[] = {
2072     DEFINE_PROP_UINT8("rx-fifo0", XlnxVersalCANFDState, cfg.rx0_fifo, 0x40),
2073     DEFINE_PROP_UINT8("rx-fifo1", XlnxVersalCANFDState, cfg.rx1_fifo, 0x40),
2074     DEFINE_PROP_UINT8("tx-fifo", XlnxVersalCANFDState, cfg.tx_fifo, 0x20),
2075     DEFINE_PROP_BOOL("enable-rx-fifo1", XlnxVersalCANFDState,
2076                      cfg.enable_rx_fifo1, true),
2077     DEFINE_PROP_UINT32("ext_clk_freq", XlnxVersalCANFDState, cfg.ext_clk_freq,
2078                        CANFD_DEFAULT_CLOCK),
2079     DEFINE_PROP_LINK("canfdbus", XlnxVersalCANFDState, canfdbus, TYPE_CAN_BUS,
2080                      CanBusState *),
2081     DEFINE_PROP_END_OF_LIST(),
2082 };
2083 
2084 static void canfd_class_init(ObjectClass *klass, void *data)
2085 {
2086     DeviceClass *dc = DEVICE_CLASS(klass);
2087 
2088     dc->reset = canfd_reset;
2089     dc->realize = canfd_realize;
2090     device_class_set_props(dc, canfd_core_properties);
2091     dc->vmsd = &vmstate_canfd;
2092 }
2093 
2094 static const TypeInfo canfd_info = {
2095     .name          = TYPE_XILINX_CANFD,
2096     .parent        = TYPE_SYS_BUS_DEVICE,
2097     .instance_size = sizeof(XlnxVersalCANFDState),
2098     .class_init    = canfd_class_init,
2099     .instance_init = canfd_init,
2100 };
2101 
2102 static void canfd_register_types(void)
2103 {
2104     type_register_static(&canfd_info);
2105 }
2106 
2107 type_init(canfd_register_types)
2108