1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /******************************************************************************* 3 * 4 * CTU CAN FD IP Core 5 * 6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU 7 * Copyright (C) 2018-2020 Ondrej Ille <ondrej.ille@gmail.com> self-funded 8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU 9 * Copyright (C) 2018-2020 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded 10 * 11 * Project advisors: 12 * Jiri Novak <jnovak@fel.cvut.cz> 13 * Pavel Pisa <pisa@cmp.felk.cvut.cz> 14 * 15 * Department of Measurement (http://meas.fel.cvut.cz/) 16 * Faculty of Electrical Engineering (http://www.fel.cvut.cz) 17 * Czech Technical University (http://www.cvut.cz/) 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 2 22 * of the License, or (at your option) any later version. 23 * 24 * This program is distributed in the hope that it will be useful, 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27 * GNU General Public License for more details. 28 ******************************************************************************/ 29 30 /* This file is autogenerated, DO NOT EDIT! */ 31 32 #ifndef HW_CAN_CTU_CAN_FD_REGS_H 33 #define HW_CAN_CTU_CAN_FD_REGS_H 34 35 /* CAN_Registers memory map */ 36 enum ctu_can_fd_can_registers { 37 CTU_CAN_FD_DEVICE_ID = 0x0, 38 CTU_CAN_FD_VERSION = 0x2, 39 CTU_CAN_FD_MODE = 0x4, 40 CTU_CAN_FD_SETTINGS = 0x6, 41 CTU_CAN_FD_STATUS = 0x8, 42 CTU_CAN_FD_COMMAND = 0xc, 43 CTU_CAN_FD_INT_STAT = 0x10, 44 CTU_CAN_FD_INT_ENA_SET = 0x14, 45 CTU_CAN_FD_INT_ENA_CLR = 0x18, 46 CTU_CAN_FD_INT_MASK_SET = 0x1c, 47 CTU_CAN_FD_INT_MASK_CLR = 0x20, 48 CTU_CAN_FD_BTR = 0x24, 49 CTU_CAN_FD_BTR_FD = 0x28, 50 CTU_CAN_FD_EWL = 0x2c, 51 CTU_CAN_FD_ERP = 0x2d, 52 CTU_CAN_FD_FAULT_STATE = 0x2e, 53 CTU_CAN_FD_REC = 0x30, 54 CTU_CAN_FD_TEC = 0x32, 55 CTU_CAN_FD_ERR_NORM = 0x34, 56 CTU_CAN_FD_ERR_FD = 0x36, 57 CTU_CAN_FD_CTR_PRES = 0x38, 58 CTU_CAN_FD_FILTER_A_MASK = 0x3c, 59 CTU_CAN_FD_FILTER_A_VAL = 0x40, 60 CTU_CAN_FD_FILTER_B_MASK = 0x44, 61 CTU_CAN_FD_FILTER_B_VAL = 0x48, 62 CTU_CAN_FD_FILTER_C_MASK = 0x4c, 63 CTU_CAN_FD_FILTER_C_VAL = 0x50, 64 CTU_CAN_FD_FILTER_RAN_LOW = 0x54, 65 CTU_CAN_FD_FILTER_RAN_HIGH = 0x58, 66 CTU_CAN_FD_FILTER_CONTROL = 0x5c, 67 CTU_CAN_FD_FILTER_STATUS = 0x5e, 68 CTU_CAN_FD_RX_MEM_INFO = 0x60, 69 CTU_CAN_FD_RX_POINTERS = 0x64, 70 CTU_CAN_FD_RX_STATUS = 0x68, 71 CTU_CAN_FD_RX_SETTINGS = 0x6a, 72 CTU_CAN_FD_RX_DATA = 0x6c, 73 CTU_CAN_FD_TX_STATUS = 0x70, 74 CTU_CAN_FD_TX_COMMAND = 0x74, 75 CTU_CAN_FD_TX_PRIORITY = 0x78, 76 CTU_CAN_FD_ERR_CAPT = 0x7c, 77 CTU_CAN_FD_ALC = 0x7e, 78 CTU_CAN_FD_TRV_DELAY = 0x80, 79 CTU_CAN_FD_SSP_CFG = 0x82, 80 CTU_CAN_FD_RX_FR_CTR = 0x84, 81 CTU_CAN_FD_TX_FR_CTR = 0x88, 82 CTU_CAN_FD_DEBUG_REGISTER = 0x8c, 83 CTU_CAN_FD_YOLO_REG = 0x90, 84 CTU_CAN_FD_TIMESTAMP_LOW = 0x94, 85 CTU_CAN_FD_TIMESTAMP_HIGH = 0x98, 86 CTU_CAN_FD_TXTB1_DATA_1 = 0x100, 87 CTU_CAN_FD_TXTB1_DATA_2 = 0x104, 88 CTU_CAN_FD_TXTB1_DATA_20 = 0x14c, 89 CTU_CAN_FD_TXTB2_DATA_1 = 0x200, 90 CTU_CAN_FD_TXTB2_DATA_2 = 0x204, 91 CTU_CAN_FD_TXTB2_DATA_20 = 0x24c, 92 CTU_CAN_FD_TXTB3_DATA_1 = 0x300, 93 CTU_CAN_FD_TXTB3_DATA_2 = 0x304, 94 CTU_CAN_FD_TXTB3_DATA_20 = 0x34c, 95 CTU_CAN_FD_TXTB4_DATA_1 = 0x400, 96 CTU_CAN_FD_TXTB4_DATA_2 = 0x404, 97 CTU_CAN_FD_TXTB4_DATA_20 = 0x44c, 98 }; 99 100 101 /* Register descriptions: */ 102 union ctu_can_fd_device_id_version { 103 uint32_t u32; 104 struct ctu_can_fd_device_id_version_s { 105 #ifdef __LITTLE_ENDIAN_BITFIELD 106 /* DEVICE_ID */ 107 uint32_t device_id : 16; 108 /* VERSION */ 109 uint32_t ver_minor : 8; 110 uint32_t ver_major : 8; 111 #else 112 uint32_t ver_major : 8; 113 uint32_t ver_minor : 8; 114 uint32_t device_id : 16; 115 #endif 116 } s; 117 }; 118 119 enum ctu_can_fd_device_id_device_id { 120 CTU_CAN_FD_ID = 0xcafd, 121 }; 122 123 union ctu_can_fd_mode_settings { 124 uint32_t u32; 125 struct ctu_can_fd_mode_settings_s { 126 #ifdef __LITTLE_ENDIAN_BITFIELD 127 /* MODE */ 128 uint32_t rst : 1; 129 uint32_t lom : 1; 130 uint32_t stm : 1; 131 uint32_t afm : 1; 132 uint32_t fde : 1; 133 uint32_t reserved_6_5 : 2; 134 uint32_t acf : 1; 135 uint32_t tstm : 1; 136 uint32_t reserved_15_9 : 7; 137 /* SETTINGS */ 138 uint32_t rtrle : 1; 139 uint32_t rtrth : 4; 140 uint32_t ilbp : 1; 141 uint32_t ena : 1; 142 uint32_t nisofd : 1; 143 uint32_t pex : 1; 144 uint32_t reserved_31_25 : 7; 145 #else 146 uint32_t reserved_31_25 : 7; 147 uint32_t pex : 1; 148 uint32_t nisofd : 1; 149 uint32_t ena : 1; 150 uint32_t ilbp : 1; 151 uint32_t rtrth : 4; 152 uint32_t rtrle : 1; 153 uint32_t reserved_15_9 : 7; 154 uint32_t tstm : 1; 155 uint32_t acf : 1; 156 uint32_t reserved_6_5 : 2; 157 uint32_t fde : 1; 158 uint32_t afm : 1; 159 uint32_t stm : 1; 160 uint32_t lom : 1; 161 uint32_t rst : 1; 162 #endif 163 } s; 164 }; 165 166 enum ctu_can_fd_mode_lom { 167 LOM_DISABLED = 0x0, 168 LOM_ENABLED = 0x1, 169 }; 170 171 enum ctu_can_fd_mode_stm { 172 STM_DISABLED = 0x0, 173 STM_ENABLED = 0x1, 174 }; 175 176 enum ctu_can_fd_mode_afm { 177 AFM_DISABLED = 0x0, 178 AFM_ENABLED = 0x1, 179 }; 180 181 enum ctu_can_fd_mode_fde { 182 FDE_DISABLE = 0x0, 183 FDE_ENABLE = 0x1, 184 }; 185 186 enum ctu_can_fd_mode_acf { 187 ACF_DISABLED = 0x0, 188 ACF_ENABLED = 0x1, 189 }; 190 191 enum ctu_can_fd_settings_rtrle { 192 RTRLE_DISABLED = 0x0, 193 RTRLE_ENABLED = 0x1, 194 }; 195 196 enum ctu_can_fd_settings_ilbp { 197 INT_LOOP_DISABLED = 0x0, 198 INT_LOOP_ENABLED = 0x1, 199 }; 200 201 enum ctu_can_fd_settings_ena { 202 CTU_CAN_DISABLED = 0x0, 203 CTU_CAN_ENABLED = 0x1, 204 }; 205 206 enum ctu_can_fd_settings_nisofd { 207 ISO_FD = 0x0, 208 NON_ISO_FD = 0x1, 209 }; 210 211 enum ctu_can_fd_settings_pex { 212 PROTOCOL_EXCEPTION_DISABLED = 0x0, 213 PROTOCOL_EXCEPTION_ENABLED = 0x1, 214 }; 215 216 union ctu_can_fd_status { 217 uint32_t u32; 218 struct ctu_can_fd_status_s { 219 #ifdef __LITTLE_ENDIAN_BITFIELD 220 /* STATUS */ 221 uint32_t rxne : 1; 222 uint32_t dor : 1; 223 uint32_t txnf : 1; 224 uint32_t eft : 1; 225 uint32_t rxs : 1; 226 uint32_t txs : 1; 227 uint32_t ewl : 1; 228 uint32_t idle : 1; 229 uint32_t reserved_31_8 : 24; 230 #else 231 uint32_t reserved_31_8 : 24; 232 uint32_t idle : 1; 233 uint32_t ewl : 1; 234 uint32_t txs : 1; 235 uint32_t rxs : 1; 236 uint32_t eft : 1; 237 uint32_t txnf : 1; 238 uint32_t dor : 1; 239 uint32_t rxne : 1; 240 #endif 241 } s; 242 }; 243 244 union ctu_can_fd_command { 245 uint32_t u32; 246 struct ctu_can_fd_command_s { 247 #ifdef __LITTLE_ENDIAN_BITFIELD 248 uint32_t reserved_1_0 : 2; 249 /* COMMAND */ 250 uint32_t rrb : 1; 251 uint32_t cdo : 1; 252 uint32_t ercrst : 1; 253 uint32_t rxfcrst : 1; 254 uint32_t txfcrst : 1; 255 uint32_t reserved_31_7 : 25; 256 #else 257 uint32_t reserved_31_7 : 25; 258 uint32_t txfcrst : 1; 259 uint32_t rxfcrst : 1; 260 uint32_t ercrst : 1; 261 uint32_t cdo : 1; 262 uint32_t rrb : 1; 263 uint32_t reserved_1_0 : 2; 264 #endif 265 } s; 266 }; 267 268 union ctu_can_fd_int_stat { 269 uint32_t u32; 270 struct ctu_can_fd_int_stat_s { 271 #ifdef __LITTLE_ENDIAN_BITFIELD 272 /* INT_STAT */ 273 uint32_t rxi : 1; 274 uint32_t txi : 1; 275 uint32_t ewli : 1; 276 uint32_t doi : 1; 277 uint32_t fcsi : 1; 278 uint32_t ali : 1; 279 uint32_t bei : 1; 280 uint32_t ofi : 1; 281 uint32_t rxfi : 1; 282 uint32_t bsi : 1; 283 uint32_t rbnei : 1; 284 uint32_t txbhci : 1; 285 uint32_t reserved_31_12 : 20; 286 #else 287 uint32_t reserved_31_12 : 20; 288 uint32_t txbhci : 1; 289 uint32_t rbnei : 1; 290 uint32_t bsi : 1; 291 uint32_t rxfi : 1; 292 uint32_t ofi : 1; 293 uint32_t bei : 1; 294 uint32_t ali : 1; 295 uint32_t fcsi : 1; 296 uint32_t doi : 1; 297 uint32_t ewli : 1; 298 uint32_t txi : 1; 299 uint32_t rxi : 1; 300 #endif 301 } s; 302 }; 303 304 union ctu_can_fd_int_ena_set { 305 uint32_t u32; 306 struct ctu_can_fd_int_ena_set_s { 307 #ifdef __LITTLE_ENDIAN_BITFIELD 308 /* INT_ENA_SET */ 309 uint32_t int_ena_set : 12; 310 uint32_t reserved_31_12 : 20; 311 #else 312 uint32_t reserved_31_12 : 20; 313 uint32_t int_ena_set : 12; 314 #endif 315 } s; 316 }; 317 318 union ctu_can_fd_int_ena_clr { 319 uint32_t u32; 320 struct ctu_can_fd_int_ena_clr_s { 321 #ifdef __LITTLE_ENDIAN_BITFIELD 322 /* INT_ENA_CLR */ 323 uint32_t int_ena_clr : 12; 324 uint32_t reserved_31_12 : 20; 325 #else 326 uint32_t reserved_31_12 : 20; 327 uint32_t int_ena_clr : 12; 328 #endif 329 } s; 330 }; 331 332 union ctu_can_fd_int_mask_set { 333 uint32_t u32; 334 struct ctu_can_fd_int_mask_set_s { 335 #ifdef __LITTLE_ENDIAN_BITFIELD 336 /* INT_MASK_SET */ 337 uint32_t int_mask_set : 12; 338 uint32_t reserved_31_12 : 20; 339 #else 340 uint32_t reserved_31_12 : 20; 341 uint32_t int_mask_set : 12; 342 #endif 343 } s; 344 }; 345 346 union ctu_can_fd_int_mask_clr { 347 uint32_t u32; 348 struct ctu_can_fd_int_mask_clr_s { 349 #ifdef __LITTLE_ENDIAN_BITFIELD 350 /* INT_MASK_CLR */ 351 uint32_t int_mask_clr : 12; 352 uint32_t reserved_31_12 : 20; 353 #else 354 uint32_t reserved_31_12 : 20; 355 uint32_t int_mask_clr : 12; 356 #endif 357 } s; 358 }; 359 360 union ctu_can_fd_btr { 361 uint32_t u32; 362 struct ctu_can_fd_btr_s { 363 #ifdef __LITTLE_ENDIAN_BITFIELD 364 /* BTR */ 365 uint32_t prop : 7; 366 uint32_t ph1 : 6; 367 uint32_t ph2 : 6; 368 uint32_t brp : 8; 369 uint32_t sjw : 5; 370 #else 371 uint32_t sjw : 5; 372 uint32_t brp : 8; 373 uint32_t ph2 : 6; 374 uint32_t ph1 : 6; 375 uint32_t prop : 7; 376 #endif 377 } s; 378 }; 379 380 union ctu_can_fd_btr_fd { 381 uint32_t u32; 382 struct ctu_can_fd_btr_fd_s { 383 #ifdef __LITTLE_ENDIAN_BITFIELD 384 /* BTR_FD */ 385 uint32_t prop_fd : 6; 386 uint32_t reserved_6 : 1; 387 uint32_t ph1_fd : 5; 388 uint32_t reserved_12 : 1; 389 uint32_t ph2_fd : 5; 390 uint32_t reserved_18 : 1; 391 uint32_t brp_fd : 8; 392 uint32_t sjw_fd : 5; 393 #else 394 uint32_t sjw_fd : 5; 395 uint32_t brp_fd : 8; 396 uint32_t reserved_18 : 1; 397 uint32_t ph2_fd : 5; 398 uint32_t reserved_12 : 1; 399 uint32_t ph1_fd : 5; 400 uint32_t reserved_6 : 1; 401 uint32_t prop_fd : 6; 402 #endif 403 } s; 404 }; 405 406 union ctu_can_fd_ewl_erp_fault_state { 407 uint32_t u32; 408 struct ctu_can_fd_ewl_erp_fault_state_s { 409 #ifdef __LITTLE_ENDIAN_BITFIELD 410 /* EWL */ 411 uint32_t ew_limit : 8; 412 /* ERP */ 413 uint32_t erp_limit : 8; 414 /* FAULT_STATE */ 415 uint32_t era : 1; 416 uint32_t erp : 1; 417 uint32_t bof : 1; 418 uint32_t reserved_31_19 : 13; 419 #else 420 uint32_t reserved_31_19 : 13; 421 uint32_t bof : 1; 422 uint32_t erp : 1; 423 uint32_t era : 1; 424 uint32_t erp_limit : 8; 425 uint32_t ew_limit : 8; 426 #endif 427 } s; 428 }; 429 430 union ctu_can_fd_rec_tec { 431 uint32_t u32; 432 struct ctu_can_fd_rec_tec_s { 433 #ifdef __LITTLE_ENDIAN_BITFIELD 434 /* REC */ 435 uint32_t rec_val : 9; 436 uint32_t reserved_15_9 : 7; 437 /* TEC */ 438 uint32_t tec_val : 9; 439 uint32_t reserved_31_25 : 7; 440 #else 441 uint32_t reserved_31_25 : 7; 442 uint32_t tec_val : 9; 443 uint32_t reserved_15_9 : 7; 444 uint32_t rec_val : 9; 445 #endif 446 } s; 447 }; 448 449 union ctu_can_fd_err_norm_err_fd { 450 uint32_t u32; 451 struct ctu_can_fd_err_norm_err_fd_s { 452 #ifdef __LITTLE_ENDIAN_BITFIELD 453 /* ERR_NORM */ 454 uint32_t err_norm_val : 16; 455 /* ERR_FD */ 456 uint32_t err_fd_val : 16; 457 #else 458 uint32_t err_fd_val : 16; 459 uint32_t err_norm_val : 16; 460 #endif 461 } s; 462 }; 463 464 union ctu_can_fd_ctr_pres { 465 uint32_t u32; 466 struct ctu_can_fd_ctr_pres_s { 467 #ifdef __LITTLE_ENDIAN_BITFIELD 468 /* CTR_PRES */ 469 uint32_t ctpv : 9; 470 uint32_t ptx : 1; 471 uint32_t prx : 1; 472 uint32_t enorm : 1; 473 uint32_t efd : 1; 474 uint32_t reserved_31_13 : 19; 475 #else 476 uint32_t reserved_31_13 : 19; 477 uint32_t efd : 1; 478 uint32_t enorm : 1; 479 uint32_t prx : 1; 480 uint32_t ptx : 1; 481 uint32_t ctpv : 9; 482 #endif 483 } s; 484 }; 485 486 union ctu_can_fd_filter_a_mask { 487 uint32_t u32; 488 struct ctu_can_fd_filter_a_mask_s { 489 #ifdef __LITTLE_ENDIAN_BITFIELD 490 /* FILTER_A_MASK */ 491 uint32_t bit_mask_a_val : 29; 492 uint32_t reserved_31_29 : 3; 493 #else 494 uint32_t reserved_31_29 : 3; 495 uint32_t bit_mask_a_val : 29; 496 #endif 497 } s; 498 }; 499 500 union ctu_can_fd_filter_a_val { 501 uint32_t u32; 502 struct ctu_can_fd_filter_a_val_s { 503 #ifdef __LITTLE_ENDIAN_BITFIELD 504 /* FILTER_A_VAL */ 505 uint32_t bit_val_a_val : 29; 506 uint32_t reserved_31_29 : 3; 507 #else 508 uint32_t reserved_31_29 : 3; 509 uint32_t bit_val_a_val : 29; 510 #endif 511 } s; 512 }; 513 514 union ctu_can_fd_filter_b_mask { 515 uint32_t u32; 516 struct ctu_can_fd_filter_b_mask_s { 517 #ifdef __LITTLE_ENDIAN_BITFIELD 518 /* FILTER_B_MASK */ 519 uint32_t bit_mask_b_val : 29; 520 uint32_t reserved_31_29 : 3; 521 #else 522 uint32_t reserved_31_29 : 3; 523 uint32_t bit_mask_b_val : 29; 524 #endif 525 } s; 526 }; 527 528 union ctu_can_fd_filter_b_val { 529 uint32_t u32; 530 struct ctu_can_fd_filter_b_val_s { 531 #ifdef __LITTLE_ENDIAN_BITFIELD 532 /* FILTER_B_VAL */ 533 uint32_t bit_val_b_val : 29; 534 uint32_t reserved_31_29 : 3; 535 #else 536 uint32_t reserved_31_29 : 3; 537 uint32_t bit_val_b_val : 29; 538 #endif 539 } s; 540 }; 541 542 union ctu_can_fd_filter_c_mask { 543 uint32_t u32; 544 struct ctu_can_fd_filter_c_mask_s { 545 #ifdef __LITTLE_ENDIAN_BITFIELD 546 /* FILTER_C_MASK */ 547 uint32_t bit_mask_c_val : 29; 548 uint32_t reserved_31_29 : 3; 549 #else 550 uint32_t reserved_31_29 : 3; 551 uint32_t bit_mask_c_val : 29; 552 #endif 553 } s; 554 }; 555 556 union ctu_can_fd_filter_c_val { 557 uint32_t u32; 558 struct ctu_can_fd_filter_c_val_s { 559 #ifdef __LITTLE_ENDIAN_BITFIELD 560 /* FILTER_C_VAL */ 561 uint32_t bit_val_c_val : 29; 562 uint32_t reserved_31_29 : 3; 563 #else 564 uint32_t reserved_31_29 : 3; 565 uint32_t bit_val_c_val : 29; 566 #endif 567 } s; 568 }; 569 570 union ctu_can_fd_filter_ran_low { 571 uint32_t u32; 572 struct ctu_can_fd_filter_ran_low_s { 573 #ifdef __LITTLE_ENDIAN_BITFIELD 574 /* FILTER_RAN_LOW */ 575 uint32_t bit_ran_low_val : 29; 576 uint32_t reserved_31_29 : 3; 577 #else 578 uint32_t reserved_31_29 : 3; 579 uint32_t bit_ran_low_val : 29; 580 #endif 581 } s; 582 }; 583 584 union ctu_can_fd_filter_ran_high { 585 uint32_t u32; 586 struct ctu_can_fd_filter_ran_high_s { 587 #ifdef __LITTLE_ENDIAN_BITFIELD 588 /* FILTER_RAN_HIGH */ 589 uint32_t bit_ran_high_val : 29; 590 uint32_t reserved_31_29 : 3; 591 #else 592 uint32_t reserved_31_29 : 3; 593 uint32_t bit_ran_high_val : 29; 594 #endif 595 } s; 596 }; 597 598 union ctu_can_fd_filter_control_filter_status { 599 uint32_t u32; 600 struct ctu_can_fd_filter_control_filter_status_s { 601 #ifdef __LITTLE_ENDIAN_BITFIELD 602 /* FILTER_CONTROL */ 603 uint32_t fanb : 1; 604 uint32_t fane : 1; 605 uint32_t fafb : 1; 606 uint32_t fafe : 1; 607 uint32_t fbnb : 1; 608 uint32_t fbne : 1; 609 uint32_t fbfb : 1; 610 uint32_t fbfe : 1; 611 uint32_t fcnb : 1; 612 uint32_t fcne : 1; 613 uint32_t fcfb : 1; 614 uint32_t fcfe : 1; 615 uint32_t frnb : 1; 616 uint32_t frne : 1; 617 uint32_t frfb : 1; 618 uint32_t frfe : 1; 619 /* FILTER_STATUS */ 620 uint32_t sfa : 1; 621 uint32_t sfb : 1; 622 uint32_t sfc : 1; 623 uint32_t sfr : 1; 624 uint32_t reserved_31_20 : 12; 625 #else 626 uint32_t reserved_31_20 : 12; 627 uint32_t sfr : 1; 628 uint32_t sfc : 1; 629 uint32_t sfb : 1; 630 uint32_t sfa : 1; 631 uint32_t frfe : 1; 632 uint32_t frfb : 1; 633 uint32_t frne : 1; 634 uint32_t frnb : 1; 635 uint32_t fcfe : 1; 636 uint32_t fcfb : 1; 637 uint32_t fcne : 1; 638 uint32_t fcnb : 1; 639 uint32_t fbfe : 1; 640 uint32_t fbfb : 1; 641 uint32_t fbne : 1; 642 uint32_t fbnb : 1; 643 uint32_t fafe : 1; 644 uint32_t fafb : 1; 645 uint32_t fane : 1; 646 uint32_t fanb : 1; 647 #endif 648 } s; 649 }; 650 651 union ctu_can_fd_rx_mem_info { 652 uint32_t u32; 653 struct ctu_can_fd_rx_mem_info_s { 654 #ifdef __LITTLE_ENDIAN_BITFIELD 655 /* RX_MEM_INFO */ 656 uint32_t rx_buff_size : 13; 657 uint32_t reserved_15_13 : 3; 658 uint32_t rx_mem_free : 13; 659 uint32_t reserved_31_29 : 3; 660 #else 661 uint32_t reserved_31_29 : 3; 662 uint32_t rx_mem_free : 13; 663 uint32_t reserved_15_13 : 3; 664 uint32_t rx_buff_size : 13; 665 #endif 666 } s; 667 }; 668 669 union ctu_can_fd_rx_pointers { 670 uint32_t u32; 671 struct ctu_can_fd_rx_pointers_s { 672 #ifdef __LITTLE_ENDIAN_BITFIELD 673 /* RX_POINTERS */ 674 uint32_t rx_wpp : 12; 675 uint32_t reserved_15_12 : 4; 676 uint32_t rx_rpp : 12; 677 uint32_t reserved_31_28 : 4; 678 #else 679 uint32_t reserved_31_28 : 4; 680 uint32_t rx_rpp : 12; 681 uint32_t reserved_15_12 : 4; 682 uint32_t rx_wpp : 12; 683 #endif 684 } s; 685 }; 686 687 union ctu_can_fd_rx_status_rx_settings { 688 uint32_t u32; 689 struct ctu_can_fd_rx_status_rx_settings_s { 690 #ifdef __LITTLE_ENDIAN_BITFIELD 691 /* RX_STATUS */ 692 uint32_t rxe : 1; 693 uint32_t rxf : 1; 694 uint32_t reserved_3_2 : 2; 695 uint32_t rxfrc : 11; 696 uint32_t reserved_15 : 1; 697 /* RX_SETTINGS */ 698 uint32_t rtsop : 1; 699 uint32_t reserved_31_17 : 15; 700 #else 701 uint32_t reserved_31_17 : 15; 702 uint32_t rtsop : 1; 703 uint32_t reserved_15 : 1; 704 uint32_t rxfrc : 11; 705 uint32_t reserved_3_2 : 2; 706 uint32_t rxf : 1; 707 uint32_t rxe : 1; 708 #endif 709 } s; 710 }; 711 712 enum ctu_can_fd_rx_settings_rtsop { 713 RTS_END = 0x0, 714 RTS_BEG = 0x1, 715 }; 716 717 union ctu_can_fd_rx_data { 718 uint32_t u32; 719 struct ctu_can_fd_rx_data_s { 720 /* RX_DATA */ 721 uint32_t rx_data : 32; 722 } s; 723 }; 724 725 union ctu_can_fd_tx_status { 726 uint32_t u32; 727 struct ctu_can_fd_tx_status_s { 728 #ifdef __LITTLE_ENDIAN_BITFIELD 729 /* TX_STATUS */ 730 uint32_t tx1s : 4; 731 uint32_t tx2s : 4; 732 uint32_t tx3s : 4; 733 uint32_t tx4s : 4; 734 uint32_t reserved_31_16 : 16; 735 #else 736 uint32_t reserved_31_16 : 16; 737 uint32_t tx4s : 4; 738 uint32_t tx3s : 4; 739 uint32_t tx2s : 4; 740 uint32_t tx1s : 4; 741 #endif 742 } s; 743 }; 744 745 enum ctu_can_fd_tx_status_tx1s { 746 TXT_RDY = 0x1, 747 TXT_TRAN = 0x2, 748 TXT_ABTP = 0x3, 749 TXT_TOK = 0x4, 750 TXT_ERR = 0x6, 751 TXT_ABT = 0x7, 752 TXT_ETY = 0x8, 753 }; 754 755 union ctu_can_fd_tx_command { 756 uint32_t u32; 757 struct ctu_can_fd_tx_command_s { 758 #ifdef __LITTLE_ENDIAN_BITFIELD 759 /* TX_COMMAND */ 760 uint32_t txce : 1; 761 uint32_t txcr : 1; 762 uint32_t txca : 1; 763 uint32_t reserved_7_3 : 5; 764 uint32_t txb1 : 1; 765 uint32_t txb2 : 1; 766 uint32_t txb3 : 1; 767 uint32_t txb4 : 1; 768 uint32_t reserved_31_12 : 20; 769 #else 770 uint32_t reserved_31_12 : 20; 771 uint32_t txb4 : 1; 772 uint32_t txb3 : 1; 773 uint32_t txb2 : 1; 774 uint32_t txb1 : 1; 775 uint32_t reserved_7_3 : 5; 776 uint32_t txca : 1; 777 uint32_t txcr : 1; 778 uint32_t txce : 1; 779 #endif 780 } s; 781 }; 782 783 union ctu_can_fd_tx_priority { 784 uint32_t u32; 785 struct ctu_can_fd_tx_priority_s { 786 #ifdef __LITTLE_ENDIAN_BITFIELD 787 /* TX_PRIORITY */ 788 uint32_t txt1p : 3; 789 uint32_t reserved_3 : 1; 790 uint32_t txt2p : 3; 791 uint32_t reserved_7 : 1; 792 uint32_t txt3p : 3; 793 uint32_t reserved_11 : 1; 794 uint32_t txt4p : 3; 795 uint32_t reserved_31_15 : 17; 796 #else 797 uint32_t reserved_31_15 : 17; 798 uint32_t txt4p : 3; 799 uint32_t reserved_11 : 1; 800 uint32_t txt3p : 3; 801 uint32_t reserved_7 : 1; 802 uint32_t txt2p : 3; 803 uint32_t reserved_3 : 1; 804 uint32_t txt1p : 3; 805 #endif 806 } s; 807 }; 808 809 union ctu_can_fd_err_capt_alc { 810 uint32_t u32; 811 struct ctu_can_fd_err_capt_alc_s { 812 #ifdef __LITTLE_ENDIAN_BITFIELD 813 /* ERR_CAPT */ 814 uint32_t err_pos : 5; 815 uint32_t err_type : 3; 816 uint32_t reserved_15_8 : 8; 817 /* ALC */ 818 uint32_t alc_bit : 5; 819 uint32_t alc_id_field : 3; 820 uint32_t reserved_31_24 : 8; 821 #else 822 uint32_t reserved_31_24 : 8; 823 uint32_t alc_id_field : 3; 824 uint32_t alc_bit : 5; 825 uint32_t reserved_15_8 : 8; 826 uint32_t err_type : 3; 827 uint32_t err_pos : 5; 828 #endif 829 } s; 830 }; 831 832 enum ctu_can_fd_err_capt_err_pos { 833 ERC_POS_SOF = 0x0, 834 ERC_POS_ARB = 0x1, 835 ERC_POS_CTRL = 0x2, 836 ERC_POS_DATA = 0x3, 837 ERC_POS_CRC = 0x4, 838 ERC_POS_ACK = 0x5, 839 ERC_POS_EOF = 0x6, 840 ERC_POS_ERR = 0x7, 841 ERC_POS_OVRL = 0x8, 842 ERC_POS_OTHER = 0x1f, 843 }; 844 845 enum ctu_can_fd_err_capt_err_type { 846 ERC_BIT_ERR = 0x0, 847 ERC_CRC_ERR = 0x1, 848 ERC_FRM_ERR = 0x2, 849 ERC_ACK_ERR = 0x3, 850 ERC_STUF_ERR = 0x4, 851 }; 852 853 enum ctu_can_fd_alc_alc_id_field { 854 ALC_RSVD = 0x0, 855 ALC_BASE_ID = 0x1, 856 ALC_SRR_RTR = 0x2, 857 ALC_IDE = 0x3, 858 ALC_EXTENSION = 0x4, 859 ALC_RTR = 0x5, 860 }; 861 862 union ctu_can_fd_trv_delay_ssp_cfg { 863 uint32_t u32; 864 struct ctu_can_fd_trv_delay_ssp_cfg_s { 865 #ifdef __LITTLE_ENDIAN_BITFIELD 866 /* TRV_DELAY */ 867 uint32_t trv_delay_value : 7; 868 uint32_t reserved_15_7 : 9; 869 /* SSP_CFG */ 870 uint32_t ssp_offset : 8; 871 uint32_t ssp_src : 2; 872 uint32_t reserved_31_26 : 6; 873 #else 874 uint32_t reserved_31_26 : 6; 875 uint32_t ssp_src : 2; 876 uint32_t ssp_offset : 8; 877 uint32_t reserved_15_7 : 9; 878 uint32_t trv_delay_value : 7; 879 #endif 880 } s; 881 }; 882 883 enum ctu_can_fd_ssp_cfg_ssp_src { 884 SSP_SRC_MEAS_N_OFFSET = 0x0, 885 SSP_SRC_NO_SSP = 0x1, 886 SSP_SRC_OFFSET = 0x2, 887 }; 888 889 union ctu_can_fd_rx_fr_ctr { 890 uint32_t u32; 891 struct ctu_can_fd_rx_fr_ctr_s { 892 /* RX_FR_CTR */ 893 uint32_t rx_fr_ctr_val : 32; 894 } s; 895 }; 896 897 union ctu_can_fd_tx_fr_ctr { 898 uint32_t u32; 899 struct ctu_can_fd_tx_fr_ctr_s { 900 /* TX_FR_CTR */ 901 uint32_t tx_fr_ctr_val : 32; 902 } s; 903 }; 904 905 union ctu_can_fd_debug_register { 906 uint32_t u32; 907 struct ctu_can_fd_debug_register_s { 908 #ifdef __LITTLE_ENDIAN_BITFIELD 909 /* DEBUG_REGISTER */ 910 uint32_t stuff_count : 3; 911 uint32_t destuff_count : 3; 912 uint32_t pc_arb : 1; 913 uint32_t pc_con : 1; 914 uint32_t pc_dat : 1; 915 uint32_t pc_stc : 1; 916 uint32_t pc_crc : 1; 917 uint32_t pc_crcd : 1; 918 uint32_t pc_ack : 1; 919 uint32_t pc_ackd : 1; 920 uint32_t pc_eof : 1; 921 uint32_t pc_int : 1; 922 uint32_t pc_susp : 1; 923 uint32_t pc_ovr : 1; 924 uint32_t pc_sof : 1; 925 uint32_t reserved_31_19 : 13; 926 #else 927 uint32_t reserved_31_19 : 13; 928 uint32_t pc_sof : 1; 929 uint32_t pc_ovr : 1; 930 uint32_t pc_susp : 1; 931 uint32_t pc_int : 1; 932 uint32_t pc_eof : 1; 933 uint32_t pc_ackd : 1; 934 uint32_t pc_ack : 1; 935 uint32_t pc_crcd : 1; 936 uint32_t pc_crc : 1; 937 uint32_t pc_stc : 1; 938 uint32_t pc_dat : 1; 939 uint32_t pc_con : 1; 940 uint32_t pc_arb : 1; 941 uint32_t destuff_count : 3; 942 uint32_t stuff_count : 3; 943 #endif 944 } s; 945 }; 946 947 union ctu_can_fd_yolo_reg { 948 uint32_t u32; 949 struct ctu_can_fd_yolo_reg_s { 950 /* YOLO_REG */ 951 uint32_t yolo_val : 32; 952 } s; 953 }; 954 955 union ctu_can_fd_timestamp_low { 956 uint32_t u32; 957 struct ctu_can_fd_timestamp_low_s { 958 /* TIMESTAMP_LOW */ 959 uint32_t timestamp_low : 32; 960 } s; 961 }; 962 963 union ctu_can_fd_timestamp_high { 964 uint32_t u32; 965 struct ctu_can_fd_timestamp_high_s { 966 /* TIMESTAMP_HIGH */ 967 uint32_t timestamp_high : 32; 968 } s; 969 }; 970 971 #endif 972