1 /* 2 * CAN device - SJA1000 chip emulation for QEMU 3 * 4 * Copyright (c) 2013-2014 Jin Yang 5 * Copyright (c) 2014-2018 Pavel Pisa 6 * 7 * Initial development supported by Google GSoC 2013 from RTEMS project slot 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "chardev/char.h" 31 #include "hw/irq.h" 32 #include "migration/vmstate.h" 33 #include "net/can_emu.h" 34 35 #include "can_sja1000.h" 36 37 #ifndef DEBUG_FILTER 38 #define DEBUG_FILTER 0 39 #endif /*DEBUG_FILTER*/ 40 41 #ifndef DEBUG_CAN 42 #define DEBUG_CAN 0 43 #endif /*DEBUG_CAN*/ 44 45 #define DPRINTF(fmt, ...) \ 46 do { \ 47 if (DEBUG_CAN) { \ 48 qemu_log("[cansja]: " fmt , ## __VA_ARGS__); \ 49 } \ 50 } while (0) 51 52 static void can_sja_software_reset(CanSJA1000State *s) 53 { 54 s->mode &= ~0x31; 55 s->mode |= 0x01; 56 s->status_pel &= ~0x37; 57 s->status_pel |= 0x34; 58 59 s->rxbuf_start = 0x00; 60 s->rxmsg_cnt = 0x00; 61 s->rx_cnt = 0x00; 62 } 63 64 void can_sja_hardware_reset(CanSJA1000State *s) 65 { 66 /* Reset by hardware, p10 */ 67 s->mode = 0x01; 68 s->status_pel = 0x3c; 69 s->interrupt_pel = 0x00; 70 s->clock = 0x00; 71 s->rxbuf_start = 0x00; 72 s->rxmsg_cnt = 0x00; 73 s->rx_cnt = 0x00; 74 75 s->control = 0x01; 76 s->status_bas = 0x0c; 77 s->interrupt_bas = 0x00; 78 79 qemu_irq_lower(s->irq); 80 } 81 82 static 83 void can_sja_single_filter(struct qemu_can_filter *filter, 84 const uint8_t *acr, const uint8_t *amr, int extended) 85 { 86 if (extended) { 87 filter->can_id = (uint32_t)acr[0] << 21; 88 filter->can_id |= (uint32_t)acr[1] << 13; 89 filter->can_id |= (uint32_t)acr[2] << 5; 90 filter->can_id |= (uint32_t)acr[3] >> 3; 91 if (acr[3] & 4) { 92 filter->can_id |= QEMU_CAN_RTR_FLAG; 93 } 94 95 filter->can_mask = (uint32_t)amr[0] << 21; 96 filter->can_mask |= (uint32_t)amr[1] << 13; 97 filter->can_mask |= (uint32_t)amr[2] << 5; 98 filter->can_mask |= (uint32_t)amr[3] >> 3; 99 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK; 100 if (!(amr[3] & 4)) { 101 filter->can_mask |= QEMU_CAN_RTR_FLAG; 102 } 103 } else { 104 filter->can_id = (uint32_t)acr[0] << 3; 105 filter->can_id |= (uint32_t)acr[1] >> 5; 106 if (acr[1] & 0x10) { 107 filter->can_id |= QEMU_CAN_RTR_FLAG; 108 } 109 110 filter->can_mask = (uint32_t)amr[0] << 3; 111 filter->can_mask |= (uint32_t)amr[1] << 5; 112 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK; 113 if (!(amr[1] & 0x10)) { 114 filter->can_mask |= QEMU_CAN_RTR_FLAG; 115 } 116 } 117 } 118 119 static 120 void can_sja_dual_filter(struct qemu_can_filter *filter, 121 const uint8_t *acr, const uint8_t *amr, int extended) 122 { 123 if (extended) { 124 filter->can_id = (uint32_t)acr[0] << 21; 125 filter->can_id |= (uint32_t)acr[1] << 13; 126 127 filter->can_mask = (uint32_t)amr[0] << 21; 128 filter->can_mask |= (uint32_t)amr[1] << 13; 129 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK & ~0x1fff; 130 } else { 131 filter->can_id = (uint32_t)acr[0] << 3; 132 filter->can_id |= (uint32_t)acr[1] >> 5; 133 if (acr[1] & 0x10) { 134 filter->can_id |= QEMU_CAN_RTR_FLAG; 135 } 136 137 filter->can_mask = (uint32_t)amr[0] << 3; 138 filter->can_mask |= (uint32_t)amr[1] >> 5; 139 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK; 140 if (!(amr[1] & 0x10)) { 141 filter->can_mask |= QEMU_CAN_RTR_FLAG; 142 } 143 } 144 } 145 146 /* Details in DS-p22, what we need to do here is to test the data. */ 147 static 148 int can_sja_accept_filter(CanSJA1000State *s, 149 const qemu_can_frame *frame) 150 { 151 152 struct qemu_can_filter filter; 153 154 if (s->clock & 0x80) { /* PeliCAN Mode */ 155 if (s->mode & (1 << 3)) { /* Single mode. */ 156 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 157 can_sja_single_filter(&filter, 158 s->code_mask + 0, s->code_mask + 4, 1); 159 160 if (!can_bus_filter_match(&filter, frame->can_id)) { 161 return 0; 162 } 163 } else { /* SFF */ 164 can_sja_single_filter(&filter, 165 s->code_mask + 0, s->code_mask + 4, 0); 166 167 if (!can_bus_filter_match(&filter, frame->can_id)) { 168 return 0; 169 } 170 171 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 172 return 1; 173 } 174 175 if (frame->can_dlc == 0) { 176 return 1; 177 } 178 179 if ((frame->data[0] & ~(s->code_mask[6])) != 180 (s->code_mask[2] & ~(s->code_mask[6]))) { 181 return 0; 182 } 183 184 if (frame->can_dlc < 2) { 185 return 1; 186 } 187 188 if ((frame->data[1] & ~(s->code_mask[7])) == 189 (s->code_mask[3] & ~(s->code_mask[7]))) { 190 return 1; 191 } 192 193 return 0; 194 } 195 } else { /* Dual mode */ 196 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 197 can_sja_dual_filter(&filter, 198 s->code_mask + 0, s->code_mask + 4, 1); 199 200 if (can_bus_filter_match(&filter, frame->can_id)) { 201 return 1; 202 } 203 204 can_sja_dual_filter(&filter, 205 s->code_mask + 2, s->code_mask + 6, 1); 206 207 if (can_bus_filter_match(&filter, frame->can_id)) { 208 return 1; 209 } 210 211 return 0; 212 } else { 213 can_sja_dual_filter(&filter, 214 s->code_mask + 0, s->code_mask + 4, 0); 215 216 if (can_bus_filter_match(&filter, frame->can_id)) { 217 uint8_t expect; 218 uint8_t mask; 219 expect = s->code_mask[1] << 4; 220 expect |= s->code_mask[3] & 0x0f; 221 222 mask = s->code_mask[5] << 4; 223 mask |= s->code_mask[7] & 0x0f; 224 mask = ~mask & 0xff; 225 226 if ((frame->data[0] & mask) == 227 (expect & mask)) { 228 return 1; 229 } 230 } 231 232 can_sja_dual_filter(&filter, 233 s->code_mask + 2, s->code_mask + 6, 0); 234 235 if (can_bus_filter_match(&filter, frame->can_id)) { 236 return 1; 237 } 238 239 return 0; 240 } 241 } 242 } 243 244 return 1; 245 } 246 247 static void can_display_msg(const char *prefix, const qemu_can_frame *msg) 248 { 249 int i; 250 FILE *logfile = qemu_log_trylock(); 251 252 if (logfile) { 253 fprintf(logfile, "%s%03X [%01d] %s %s", 254 prefix, 255 msg->can_id & QEMU_CAN_EFF_MASK, 256 msg->can_dlc, 257 msg->can_id & QEMU_CAN_EFF_FLAG ? "EFF" : "SFF", 258 msg->can_id & QEMU_CAN_RTR_FLAG ? "RTR" : "DAT"); 259 260 for (i = 0; i < msg->can_dlc; i++) { 261 fprintf(logfile, " %02X", msg->data[i]); 262 } 263 fprintf(logfile, "\n"); 264 qemu_log_flush(); 265 qemu_log_unlock(logfile); 266 } 267 } 268 269 static void buff2frame_pel(const uint8_t *buff, qemu_can_frame *frame) 270 { 271 uint8_t i; 272 273 frame->flags = 0; 274 frame->can_id = 0; 275 if (buff[0] & 0x40) { /* RTR */ 276 frame->can_id = QEMU_CAN_RTR_FLAG; 277 } 278 frame->can_dlc = buff[0] & 0x0f; 279 280 if (frame->can_dlc > 8) { 281 frame->can_dlc = 8; 282 } 283 284 if (buff[0] & 0x80) { /* Extended */ 285 frame->can_id |= QEMU_CAN_EFF_FLAG; 286 frame->can_id |= buff[1] << 21; /* ID.28~ID.21 */ 287 frame->can_id |= buff[2] << 13; /* ID.20~ID.13 */ 288 frame->can_id |= buff[3] << 5; 289 frame->can_id |= buff[4] >> 3; 290 for (i = 0; i < frame->can_dlc; i++) { 291 frame->data[i] = buff[5 + i]; 292 } 293 for (; i < 8; i++) { 294 frame->data[i] = 0; 295 } 296 } else { 297 frame->can_id |= buff[1] << 3; 298 frame->can_id |= buff[2] >> 5; 299 for (i = 0; i < frame->can_dlc; i++) { 300 frame->data[i] = buff[3 + i]; 301 } 302 for (; i < 8; i++) { 303 frame->data[i] = 0; 304 } 305 } 306 } 307 308 309 static void buff2frame_bas(const uint8_t *buff, qemu_can_frame *frame) 310 { 311 uint8_t i; 312 313 frame->flags = 0; 314 frame->can_id = ((buff[0] << 3) & (0xff << 3)) + ((buff[1] >> 5) & 0x07); 315 if (buff[1] & 0x10) { /* RTR */ 316 frame->can_id = QEMU_CAN_RTR_FLAG; 317 } 318 frame->can_dlc = buff[1] & 0x0f; 319 320 if (frame->can_dlc > 8) { 321 frame->can_dlc = 8; 322 } 323 324 for (i = 0; i < frame->can_dlc; i++) { 325 frame->data[i] = buff[2 + i]; 326 } 327 for (; i < 8; i++) { 328 frame->data[i] = 0; 329 } 330 } 331 332 333 static int frame2buff_pel(const qemu_can_frame *frame, uint8_t *buff) 334 { 335 int i; 336 int dlen = frame->can_dlc; 337 338 if (frame->can_id & QEMU_CAN_ERR_FLAG) { /* error frame, NOT support now. */ 339 return -1; 340 } 341 342 if (dlen > 8) { 343 return -1; 344 } 345 346 buff[0] = 0x0f & frame->can_dlc; /* DLC */ 347 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 348 buff[0] |= (1 << 6); 349 } 350 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 351 buff[0] |= (1 << 7); 352 buff[1] = extract32(frame->can_id, 21, 8); /* ID.28~ID.21 */ 353 buff[2] = extract32(frame->can_id, 13, 8); /* ID.20~ID.13 */ 354 buff[3] = extract32(frame->can_id, 5, 8); /* ID.12~ID.05 */ 355 buff[4] = extract32(frame->can_id, 0, 5) << 3; /* ID.04~ID.00,xxx */ 356 for (i = 0; i < dlen; i++) { 357 buff[5 + i] = frame->data[i]; 358 } 359 return dlen + 5; 360 } else { /* SFF */ 361 buff[1] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ 362 buff[2] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */ 363 for (i = 0; i < dlen; i++) { 364 buff[3 + i] = frame->data[i]; 365 } 366 367 return dlen + 3; 368 } 369 370 return -1; 371 } 372 373 static int frame2buff_bas(const qemu_can_frame *frame, uint8_t *buff) 374 { 375 int i; 376 int dlen = frame->can_dlc; 377 378 /* 379 * EFF, no support for BasicMode 380 * No use for Error frames now, 381 * they could be used in future to update SJA1000 error state 382 */ 383 if ((frame->can_id & QEMU_CAN_EFF_FLAG) || 384 (frame->can_id & QEMU_CAN_ERR_FLAG)) { 385 return -1; 386 } 387 388 if (dlen > 8) { 389 return -1; 390 } 391 392 buff[0] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ 393 buff[1] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */ 394 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 395 buff[1] |= (1 << 4); 396 } 397 buff[1] |= frame->can_dlc & 0x0f; 398 for (i = 0; i < dlen; i++) { 399 buff[2 + i] = frame->data[i]; 400 } 401 402 return dlen + 2; 403 } 404 405 static void can_sja_update_pel_irq(CanSJA1000State *s) 406 { 407 if (s->interrupt_en & s->interrupt_pel) { 408 qemu_irq_raise(s->irq); 409 } else { 410 qemu_irq_lower(s->irq); 411 } 412 } 413 414 static void can_sja_update_bas_irq(CanSJA1000State *s) 415 { 416 if ((s->control >> 1) & s->interrupt_bas) { 417 qemu_irq_raise(s->irq); 418 } else { 419 qemu_irq_lower(s->irq); 420 } 421 } 422 423 void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val, 424 unsigned size) 425 { 426 qemu_can_frame frame; 427 uint32_t tmp; 428 uint8_t tmp8, count; 429 430 431 DPRINTF("write 0x%02llx addr 0x%02x\n", 432 (unsigned long long)val, (unsigned int)addr); 433 434 if (addr > CAN_SJA_MEM_SIZE) { 435 return ; 436 } 437 438 if (s->clock & 0x80) { /* PeliCAN Mode */ 439 switch (addr) { 440 case SJA_MOD: /* Mode register */ 441 s->mode = 0x1f & val; 442 if ((s->mode & 0x01) && ((val & 0x01) == 0)) { 443 /* Go to operation mode from reset mode. */ 444 if (s->mode & (1 << 3)) { /* Single mode. */ 445 /* For EFF */ 446 can_sja_single_filter(&s->filter[0], 447 s->code_mask + 0, s->code_mask + 4, 1); 448 449 /* For SFF */ 450 can_sja_single_filter(&s->filter[1], 451 s->code_mask + 0, s->code_mask + 4, 0); 452 453 can_bus_client_set_filters(&s->bus_client, s->filter, 2); 454 } else { /* Dual mode */ 455 /* For EFF */ 456 can_sja_dual_filter(&s->filter[0], 457 s->code_mask + 0, s->code_mask + 4, 1); 458 459 can_sja_dual_filter(&s->filter[1], 460 s->code_mask + 2, s->code_mask + 6, 1); 461 462 /* For SFF */ 463 can_sja_dual_filter(&s->filter[2], 464 s->code_mask + 0, s->code_mask + 4, 0); 465 466 can_sja_dual_filter(&s->filter[3], 467 s->code_mask + 2, s->code_mask + 6, 0); 468 469 can_bus_client_set_filters(&s->bus_client, s->filter, 4); 470 } 471 472 s->rxmsg_cnt = 0; 473 s->rx_cnt = 0; 474 } 475 break; 476 477 case SJA_CMR: /* Command register. */ 478 if (0x01 & val) { /* Send transmission request. */ 479 buff2frame_pel(s->tx_buff, &frame); 480 if (DEBUG_FILTER) { 481 can_display_msg("[cansja]: Tx request " , &frame); 482 } 483 484 /* 485 * Clear transmission complete status, 486 * and Transmit Buffer Status. 487 * write to the backends. 488 */ 489 s->status_pel &= ~(3 << 2); 490 491 can_bus_client_send(&s->bus_client, &frame, 1); 492 493 /* 494 * Set transmission complete status 495 * and Transmit Buffer Status. 496 */ 497 s->status_pel |= (3 << 2); 498 499 /* Clear transmit status. */ 500 s->status_pel &= ~(1 << 5); 501 s->interrupt_pel |= 0x02; 502 can_sja_update_pel_irq(s); 503 } 504 if (0x04 & val) { /* Release Receive Buffer */ 505 if (s->rxmsg_cnt <= 0) { 506 break; 507 } 508 509 tmp8 = s->rx_buff[s->rxbuf_start]; count = 0; 510 if (tmp8 & (1 << 7)) { /* EFF */ 511 count += 2; 512 } 513 count += 3; 514 if (!(tmp8 & (1 << 6))) { /* DATA */ 515 count += (tmp8 & 0x0f); 516 } 517 518 if (DEBUG_FILTER) { 519 qemu_log("[cansja]: message released from " 520 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count); 521 } 522 523 s->rxbuf_start += count; 524 s->rxbuf_start %= SJA_RCV_BUF_LEN; 525 526 s->rx_cnt -= count; 527 s->rxmsg_cnt--; 528 if (s->rxmsg_cnt == 0) { 529 s->status_pel &= ~(1 << 0); 530 s->interrupt_pel &= ~(1 << 0); 531 can_sja_update_pel_irq(s); 532 } 533 } 534 if (0x08 & val) { /* Clear data overrun */ 535 s->status_pel &= ~(1 << 1); 536 s->interrupt_pel &= ~(1 << 3); 537 can_sja_update_pel_irq(s); 538 } 539 break; 540 case SJA_SR: /* Status register */ 541 case SJA_IR: /* Interrupt register */ 542 break; /* Do nothing */ 543 case SJA_IER: /* Interrupt enable register */ 544 s->interrupt_en = val; 545 break; 546 case 16: /* RX frame information addr16-28. */ 547 s->status_pel |= (1 << 5); /* Set transmit status. */ 548 /* fallthrough */ 549 case 17 ... 28: 550 if (s->mode & 0x01) { /* Reset mode */ 551 if (addr < 24) { 552 s->code_mask[addr - 16] = val; 553 } 554 } else { /* Operation mode */ 555 s->tx_buff[addr - 16] = val; /* Store to TX buffer directly. */ 556 } 557 break; 558 case SJA_CDR: 559 s->clock = val; 560 break; 561 } 562 } else { /* Basic Mode */ 563 switch (addr) { 564 case SJA_BCAN_CTR: /* Control register, addr 0 */ 565 if ((s->control & 0x01) && ((val & 0x01) == 0)) { 566 /* Go to operation mode from reset mode. */ 567 s->filter[0].can_id = (s->code << 3) & (0xff << 3); 568 tmp = (~(s->mask << 3)) & (0xff << 3); 569 tmp |= QEMU_CAN_EFF_FLAG; /* Only Basic CAN Frame. */ 570 s->filter[0].can_mask = tmp; 571 can_bus_client_set_filters(&s->bus_client, s->filter, 1); 572 573 s->rxmsg_cnt = 0; 574 s->rx_cnt = 0; 575 } else if (!(s->control & 0x01) && !(val & 0x01)) { 576 can_sja_software_reset(s); 577 } 578 579 s->control = 0x1f & val; 580 break; 581 case SJA_BCAN_CMR: /* Command register, addr 1 */ 582 if (0x01 & val) { /* Send transmission request. */ 583 buff2frame_bas(s->tx_buff, &frame); 584 if (DEBUG_FILTER) { 585 can_display_msg("[cansja]: Tx request " , &frame); 586 } 587 588 /* 589 * Clear transmission complete status, 590 * and Transmit Buffer Status. 591 */ 592 s->status_bas &= ~(3 << 2); 593 594 /* write to the backends. */ 595 can_bus_client_send(&s->bus_client, &frame, 1); 596 597 /* 598 * Set transmission complete status, 599 * and Transmit Buffer Status. 600 */ 601 s->status_bas |= (3 << 2); 602 603 /* Clear transmit status. */ 604 s->status_bas &= ~(1 << 5); 605 s->interrupt_bas |= 0x02; 606 can_sja_update_bas_irq(s); 607 } 608 if (0x04 & val) { /* Release Receive Buffer */ 609 if (s->rxmsg_cnt <= 0) { 610 break; 611 } 612 613 tmp8 = s->rx_buff[(s->rxbuf_start + 1) % SJA_RCV_BUF_LEN]; 614 count = 2 + (tmp8 & 0x0f); 615 616 if (DEBUG_FILTER) { 617 qemu_log("[cansja]: message released from " 618 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count); 619 } 620 621 s->rxbuf_start += count; 622 s->rxbuf_start %= SJA_RCV_BUF_LEN; 623 s->rx_cnt -= count; 624 s->rxmsg_cnt--; 625 626 if (s->rxmsg_cnt == 0) { 627 s->status_bas &= ~(1 << 0); 628 s->interrupt_bas &= ~(1 << 0); 629 can_sja_update_bas_irq(s); 630 } 631 } 632 if (0x08 & val) { /* Clear data overrun */ 633 s->status_bas &= ~(1 << 1); 634 s->interrupt_bas &= ~(1 << 3); 635 can_sja_update_bas_irq(s); 636 } 637 break; 638 case 4: 639 s->code = val; 640 break; 641 case 5: 642 s->mask = val; 643 break; 644 case 10: 645 s->status_bas |= (1 << 5); /* Set transmit status. */ 646 /* fallthrough */ 647 case 11 ... 19: 648 if ((s->control & 0x01) == 0) { /* Operation mode */ 649 s->tx_buff[addr - 10] = val; /* Store to TX buffer directly. */ 650 } 651 break; 652 case SJA_CDR: 653 s->clock = val; 654 break; 655 } 656 } 657 } 658 659 uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size) 660 { 661 uint64_t temp = 0; 662 663 DPRINTF("read addr 0x%02x ...\n", (unsigned int)addr); 664 665 if (addr > CAN_SJA_MEM_SIZE) { 666 return 0; 667 } 668 669 if (s->clock & 0x80) { /* PeliCAN Mode */ 670 switch (addr) { 671 case SJA_MOD: /* Mode register, addr 0 */ 672 temp = s->mode; 673 break; 674 case SJA_CMR: /* Command register, addr 1 */ 675 temp = 0x00; /* Command register, cannot be read. */ 676 break; 677 case SJA_SR: /* Status register, addr 2 */ 678 temp = s->status_pel; 679 break; 680 case SJA_IR: /* Interrupt register, addr 3 */ 681 temp = s->interrupt_pel; 682 s->interrupt_pel = 0; 683 if (s->rxmsg_cnt) { 684 s->interrupt_pel |= (1 << 0); /* Receive interrupt. */ 685 } 686 can_sja_update_pel_irq(s); 687 break; 688 case SJA_IER: /* Interrupt enable register, addr 4 */ 689 temp = s->interrupt_en; 690 break; 691 case 5: /* Reserved */ 692 case 6: /* Bus timing 0, hardware related, not support now. */ 693 case 7: /* Bus timing 1, hardware related, not support now. */ 694 case 8: /* 695 * Output control register, hardware related, 696 * not supported for now. 697 */ 698 case 9: /* Test. */ 699 case 10 ... 15: /* Reserved */ 700 temp = 0x00; 701 break; 702 703 case 16 ... 28: 704 if (s->mode & 0x01) { /* Reset mode */ 705 if (addr < 24) { 706 temp = s->code_mask[addr - 16]; 707 } else { 708 temp = 0x00; 709 } 710 } else { /* Operation mode */ 711 temp = s->rx_buff[(s->rxbuf_start + addr - 16) % 712 SJA_RCV_BUF_LEN]; 713 } 714 break; 715 case SJA_CDR: 716 temp = s->clock; 717 break; 718 default: 719 temp = 0xff; 720 } 721 } else { /* Basic Mode */ 722 switch (addr) { 723 case SJA_BCAN_CTR: /* Control register, addr 0 */ 724 temp = s->control; 725 break; 726 case SJA_BCAN_SR: /* Status register, addr 2 */ 727 temp = s->status_bas; 728 break; 729 case SJA_BCAN_IR: /* Interrupt register, addr 3 */ 730 temp = s->interrupt_bas; 731 s->interrupt_bas = 0; 732 if (s->rxmsg_cnt) { 733 s->interrupt_bas |= (1 << 0); /* Receive interrupt. */ 734 } 735 can_sja_update_bas_irq(s); 736 break; 737 case 4: 738 temp = s->code; 739 break; 740 case 5: 741 temp = s->mask; 742 break; 743 case 20 ... 29: 744 temp = s->rx_buff[(s->rxbuf_start + addr - 20) % SJA_RCV_BUF_LEN]; 745 break; 746 case 31: 747 temp = s->clock; 748 break; 749 default: 750 temp = 0xff; 751 break; 752 } 753 } 754 DPRINTF("read addr 0x%02x, %d bytes, content 0x%02lx\n", 755 (int)addr, size, (long unsigned int)temp); 756 757 return temp; 758 } 759 760 bool can_sja_can_receive(CanBusClientState *client) 761 { 762 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client); 763 764 if (s->clock & 0x80) { /* PeliCAN Mode */ 765 if (s->mode & 0x01) { /* reset mode. */ 766 return false; 767 } 768 } else { /* BasicCAN mode */ 769 if (s->control & 0x01) { 770 return false; 771 } 772 } 773 774 return true; /* always return true, when operation mode */ 775 } 776 777 ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames, 778 size_t frames_cnt) 779 { 780 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client); 781 static uint8_t rcv[SJA_MSG_MAX_LEN]; 782 int i; 783 int ret = -1; 784 const qemu_can_frame *frame = frames; 785 786 if (frames_cnt <= 0) { 787 return 0; 788 } 789 if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { 790 if (DEBUG_FILTER) { 791 can_display_msg("[cansja]: ignor fd frame ", frame); 792 } 793 return 1; 794 } 795 796 if (DEBUG_FILTER) { 797 can_display_msg("[cansja]: receive ", frame); 798 } 799 800 if (s->clock & 0x80) { /* PeliCAN Mode */ 801 802 /* the CAN controller is receiving a message */ 803 s->status_pel |= (1 << 4); 804 805 if (can_sja_accept_filter(s, frame) == 0) { 806 s->status_pel &= ~(1 << 4); 807 if (DEBUG_FILTER) { 808 qemu_log("[cansja]: filter rejects message\n"); 809 } 810 return ret; 811 } 812 813 ret = frame2buff_pel(frame, rcv); 814 if (ret < 0) { 815 s->status_pel &= ~(1 << 4); 816 if (DEBUG_FILTER) { 817 qemu_log("[cansja]: message store failed\n"); 818 } 819 return ret; /* maybe not support now. */ 820 } 821 822 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ 823 s->status_pel |= (1 << 1); /* Overrun status */ 824 s->interrupt_pel |= (1 << 3); 825 s->status_pel &= ~(1 << 4); 826 if (DEBUG_FILTER) { 827 qemu_log("[cansja]: receive FIFO overrun\n"); 828 } 829 can_sja_update_pel_irq(s); 830 return ret; 831 } 832 s->rx_cnt += ret; 833 s->rxmsg_cnt++; 834 if (DEBUG_FILTER) { 835 qemu_log("[cansja]: message stored in receive FIFO\n"); 836 } 837 838 for (i = 0; i < ret; i++) { 839 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i]; 840 } 841 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */ 842 843 s->status_pel |= 0x01; /* Set the Receive Buffer Status. DS-p23 */ 844 s->interrupt_pel |= 0x01; 845 s->status_pel &= ~(1 << 4); 846 s->status_pel |= (1 << 0); 847 can_sja_update_pel_irq(s); 848 } else { /* BasicCAN mode */ 849 850 /* the CAN controller is receiving a message */ 851 s->status_bas |= (1 << 4); 852 853 ret = frame2buff_bas(frame, rcv); 854 if (ret < 0) { 855 s->status_bas &= ~(1 << 4); 856 if (DEBUG_FILTER) { 857 qemu_log("[cansja]: message store failed\n"); 858 } 859 return ret; /* maybe not support now. */ 860 } 861 862 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ 863 s->status_bas |= (1 << 1); /* Overrun status */ 864 s->status_bas &= ~(1 << 4); 865 s->interrupt_bas |= (1 << 3); 866 can_sja_update_bas_irq(s); 867 if (DEBUG_FILTER) { 868 qemu_log("[cansja]: receive FIFO overrun\n"); 869 } 870 return ret; 871 } 872 s->rx_cnt += ret; 873 s->rxmsg_cnt++; 874 875 if (DEBUG_FILTER) { 876 qemu_log("[cansja]: message stored\n"); 877 } 878 879 for (i = 0; i < ret; i++) { 880 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i]; 881 } 882 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */ 883 884 s->status_bas |= 0x01; /* Set the Receive Buffer Status. DS-p15 */ 885 s->status_bas &= ~(1 << 4); 886 s->interrupt_bas |= (1 << 0); 887 can_sja_update_bas_irq(s); 888 } 889 return 1; 890 } 891 892 static CanBusClientInfo can_sja_bus_client_info = { 893 .can_receive = can_sja_can_receive, 894 .receive = can_sja_receive, 895 }; 896 897 898 int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus) 899 { 900 s->bus_client.info = &can_sja_bus_client_info; 901 902 if (!bus) { 903 return -EINVAL; 904 } 905 906 if (can_bus_insert_client(bus, &s->bus_client) < 0) { 907 return -1; 908 } 909 910 return 0; 911 } 912 913 void can_sja_disconnect(CanSJA1000State *s) 914 { 915 can_bus_remove_client(&s->bus_client); 916 } 917 918 int can_sja_init(CanSJA1000State *s, qemu_irq irq) 919 { 920 s->irq = irq; 921 922 qemu_irq_lower(s->irq); 923 924 can_sja_hardware_reset(s); 925 926 return 0; 927 } 928 929 const VMStateDescription vmstate_qemu_can_filter = { 930 .name = "qemu_can_filter", 931 .version_id = 1, 932 .minimum_version_id = 1, 933 .fields = (VMStateField[]) { 934 VMSTATE_UINT32(can_id, qemu_can_filter), 935 VMSTATE_UINT32(can_mask, qemu_can_filter), 936 VMSTATE_END_OF_LIST() 937 } 938 }; 939 940 static int can_sja_post_load(void *opaque, int version_id) 941 { 942 CanSJA1000State *s = opaque; 943 if (s->clock & 0x80) { /* PeliCAN Mode */ 944 can_sja_update_pel_irq(s); 945 } else { 946 can_sja_update_bas_irq(s); 947 } 948 return 0; 949 } 950 951 /* VMState is needed for live migration of QEMU images */ 952 const VMStateDescription vmstate_can_sja = { 953 .name = "can_sja", 954 .version_id = 1, 955 .minimum_version_id = 1, 956 .post_load = can_sja_post_load, 957 .fields = (VMStateField[]) { 958 VMSTATE_UINT8(mode, CanSJA1000State), 959 960 VMSTATE_UINT8(status_pel, CanSJA1000State), 961 VMSTATE_UINT8(interrupt_pel, CanSJA1000State), 962 VMSTATE_UINT8(interrupt_en, CanSJA1000State), 963 VMSTATE_UINT8(rxmsg_cnt, CanSJA1000State), 964 VMSTATE_UINT8(rxbuf_start, CanSJA1000State), 965 VMSTATE_UINT8(clock, CanSJA1000State), 966 967 VMSTATE_BUFFER(code_mask, CanSJA1000State), 968 VMSTATE_BUFFER(tx_buff, CanSJA1000State), 969 970 VMSTATE_BUFFER(rx_buff, CanSJA1000State), 971 972 VMSTATE_UINT32(rx_ptr, CanSJA1000State), 973 VMSTATE_UINT32(rx_cnt, CanSJA1000State), 974 975 VMSTATE_UINT8(control, CanSJA1000State), 976 977 VMSTATE_UINT8(status_bas, CanSJA1000State), 978 VMSTATE_UINT8(interrupt_bas, CanSJA1000State), 979 VMSTATE_UINT8(code, CanSJA1000State), 980 VMSTATE_UINT8(mask, CanSJA1000State), 981 982 VMSTATE_STRUCT_ARRAY(filter, CanSJA1000State, 4, 0, 983 vmstate_qemu_can_filter, qemu_can_filter), 984 985 986 VMSTATE_END_OF_LIST() 987 } 988 }; 989