1 /* 2 * PCM-3680i PCI CAN device (SJA1000 based) emulation 3 * 4 * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com) 5 * 6 * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by 7 * Jin Yang and Pavel Pisa 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/event_notifier.h" 30 #include "qemu/module.h" 31 #include "qemu/thread.h" 32 #include "qemu/sockets.h" 33 #include "qapi/error.h" 34 #include "chardev/char.h" 35 #include "hw/hw.h" 36 #include "hw/irq.h" 37 #include "hw/pci/pci.h" 38 #include "net/can_emu.h" 39 40 #include "can_sja1000.h" 41 42 #define TYPE_CAN_PCI_DEV "pcm3680_pci" 43 44 #define PCM3680i_PCI_DEV(obj) \ 45 OBJECT_CHECK(Pcm3680iPCIState, (obj), TYPE_CAN_PCI_DEV) 46 47 /* the PCI device and vendor IDs */ 48 #ifndef PCM3680i_PCI_VENDOR_ID1 49 #define PCM3680i_PCI_VENDOR_ID1 0x13fe 50 #endif 51 52 #ifndef PCM3680i_PCI_DEVICE_ID1 53 #define PCM3680i_PCI_DEVICE_ID1 0xc002 54 #endif 55 56 #define PCM3680i_PCI_SJA_COUNT 2 57 #define PCM3680i_PCI_SJA_RANGE 0x100 58 59 #define PCM3680i_PCI_BYTES_PER_SJA 0x20 60 61 typedef struct Pcm3680iPCIState { 62 /*< private >*/ 63 PCIDevice dev; 64 /*< public >*/ 65 MemoryRegion sja_io[PCM3680i_PCI_SJA_COUNT]; 66 67 CanSJA1000State sja_state[PCM3680i_PCI_SJA_COUNT]; 68 qemu_irq irq; 69 70 char *model; /* The model that support, only SJA1000 now. */ 71 CanBusState *canbus[PCM3680i_PCI_SJA_COUNT]; 72 } Pcm3680iPCIState; 73 74 static void pcm3680i_pci_reset(DeviceState *dev) 75 { 76 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(dev); 77 int i; 78 79 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) { 80 can_sja_hardware_reset(&d->sja_state[i]); 81 } 82 } 83 84 static uint64_t pcm3680i_pci_sja1_io_read(void *opaque, hwaddr addr, 85 unsigned size) 86 { 87 Pcm3680iPCIState *d = opaque; 88 CanSJA1000State *s = &d->sja_state[0]; 89 90 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) { 91 return 0; 92 } 93 94 return can_sja_mem_read(s, addr, size); 95 } 96 97 static void pcm3680i_pci_sja1_io_write(void *opaque, hwaddr addr, 98 uint64_t data, unsigned size) 99 { 100 Pcm3680iPCIState *d = opaque; 101 CanSJA1000State *s = &d->sja_state[0]; 102 103 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) { 104 return; 105 } 106 107 can_sja_mem_write(s, addr, data, size); 108 } 109 110 static uint64_t pcm3680i_pci_sja2_io_read(void *opaque, hwaddr addr, 111 unsigned size) 112 { 113 Pcm3680iPCIState *d = opaque; 114 CanSJA1000State *s = &d->sja_state[1]; 115 116 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) { 117 return 0; 118 } 119 120 return can_sja_mem_read(s, addr, size); 121 } 122 123 static void pcm3680i_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data, 124 unsigned size) 125 { 126 Pcm3680iPCIState *d = opaque; 127 CanSJA1000State *s = &d->sja_state[1]; 128 129 if (addr >= PCM3680i_PCI_BYTES_PER_SJA) { 130 return; 131 } 132 133 can_sja_mem_write(s, addr, data, size); 134 } 135 136 static const MemoryRegionOps pcm3680i_pci_sja1_io_ops = { 137 .read = pcm3680i_pci_sja1_io_read, 138 .write = pcm3680i_pci_sja1_io_write, 139 .endianness = DEVICE_LITTLE_ENDIAN, 140 .impl = { 141 .max_access_size = 1, 142 }, 143 }; 144 145 static const MemoryRegionOps pcm3680i_pci_sja2_io_ops = { 146 .read = pcm3680i_pci_sja2_io_read, 147 .write = pcm3680i_pci_sja2_io_write, 148 .endianness = DEVICE_LITTLE_ENDIAN, 149 .impl = { 150 .max_access_size = 1, 151 }, 152 }; 153 154 static void pcm3680i_pci_realize(PCIDevice *pci_dev, Error **errp) 155 { 156 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(pci_dev); 157 uint8_t *pci_conf; 158 int i; 159 160 pci_conf = pci_dev->config; 161 pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 162 163 d->irq = pci_allocate_irq(&d->dev); 164 165 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) { 166 can_sja_init(&d->sja_state[i], d->irq); 167 } 168 169 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) { 170 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { 171 error_setg(errp, "can_sja_connect_to_bus failed"); 172 return; 173 } 174 } 175 176 memory_region_init_io(&d->sja_io[0], OBJECT(d), &pcm3680i_pci_sja1_io_ops, 177 d, "pcm3680i_pci-sja1", PCM3680i_PCI_SJA_RANGE); 178 179 memory_region_init_io(&d->sja_io[1], OBJECT(d), &pcm3680i_pci_sja2_io_ops, 180 d, "pcm3680i_pci-sja2", PCM3680i_PCI_SJA_RANGE); 181 182 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) { 183 pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO, 184 &d->sja_io[i]); 185 } 186 } 187 188 static void pcm3680i_pci_exit(PCIDevice *pci_dev) 189 { 190 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(pci_dev); 191 int i; 192 193 for (i = 0; i < PCM3680i_PCI_SJA_COUNT; i++) { 194 can_sja_disconnect(&d->sja_state[i]); 195 } 196 197 qemu_free_irq(d->irq); 198 } 199 200 static const VMStateDescription vmstate_pcm3680i_pci = { 201 .name = "pcm3680i_pci", 202 .version_id = 1, 203 .minimum_version_id = 1, 204 .minimum_version_id_old = 1, 205 .fields = (VMStateField[]) { 206 VMSTATE_PCI_DEVICE(dev, Pcm3680iPCIState), 207 VMSTATE_STRUCT(sja_state[0], Pcm3680iPCIState, 0, 208 vmstate_can_sja, CanSJA1000State), 209 VMSTATE_STRUCT(sja_state[1], Pcm3680iPCIState, 0, 210 vmstate_can_sja, CanSJA1000State), 211 VMSTATE_END_OF_LIST() 212 } 213 }; 214 215 static void pcm3680i_pci_instance_init(Object *obj) 216 { 217 Pcm3680iPCIState *d = PCM3680i_PCI_DEV(obj); 218 219 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 220 (Object **)&d->canbus[0], 221 qdev_prop_allow_set_link_before_realize, 222 0, &error_abort); 223 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 224 (Object **)&d->canbus[1], 225 qdev_prop_allow_set_link_before_realize, 226 0, &error_abort); 227 } 228 229 static void pcm3680i_pci_class_init(ObjectClass *klass, void *data) 230 { 231 DeviceClass *dc = DEVICE_CLASS(klass); 232 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 233 234 k->realize = pcm3680i_pci_realize; 235 k->exit = pcm3680i_pci_exit; 236 k->vendor_id = PCM3680i_PCI_VENDOR_ID1; 237 k->device_id = PCM3680i_PCI_DEVICE_ID1; 238 k->revision = 0x00; 239 k->class_id = 0x000c09; 240 k->subsystem_vendor_id = PCM3680i_PCI_VENDOR_ID1; 241 k->subsystem_id = PCM3680i_PCI_DEVICE_ID1; 242 dc->desc = "Pcm3680i PCICANx"; 243 dc->vmsd = &vmstate_pcm3680i_pci; 244 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 245 dc->reset = pcm3680i_pci_reset; 246 } 247 248 static const TypeInfo pcm3680i_pci_info = { 249 .name = TYPE_CAN_PCI_DEV, 250 .parent = TYPE_PCI_DEVICE, 251 .instance_size = sizeof(Pcm3680iPCIState), 252 .class_init = pcm3680i_pci_class_init, 253 .instance_init = pcm3680i_pci_instance_init, 254 .interfaces = (InterfaceInfo[]) { 255 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 256 { }, 257 }, 258 }; 259 260 static void pcm3680i_pci_register_types(void) 261 { 262 type_register_static(&pcm3680i_pci_info); 263 } 264 265 type_init(pcm3680i_pci_register_types) 266