1 /* 2 * MIOe-3680 PCI CAN device (SJA1000 based) emulation 3 * 4 * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com) 5 * 6 * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by 7 * Jin Yang and Pavel Pisa 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/event_notifier.h" 30 #include "qemu/module.h" 31 #include "qemu/thread.h" 32 #include "qemu/sockets.h" 33 #include "qapi/error.h" 34 #include "chardev/char.h" 35 #include "hw/irq.h" 36 #include "hw/pci/pci.h" 37 #include "hw/qdev-properties.h" 38 #include "migration/vmstate.h" 39 #include "net/can_emu.h" 40 41 #include "can_sja1000.h" 42 43 #define TYPE_CAN_PCI_DEV "mioe3680_pci" 44 45 #define MIOe3680_PCI_DEV(obj) \ 46 OBJECT_CHECK(Mioe3680PCIState, (obj), TYPE_CAN_PCI_DEV) 47 48 /* the PCI device and vendor IDs */ 49 #ifndef MIOe3680_PCI_VENDOR_ID1 50 #define MIOe3680_PCI_VENDOR_ID1 0x13fe 51 #endif 52 53 #ifndef MIOe3680_PCI_DEVICE_ID1 54 #define MIOe3680_PCI_DEVICE_ID1 0xc302 55 #endif 56 57 #define MIOe3680_PCI_SJA_COUNT 2 58 #define MIOe3680_PCI_SJA_RANGE 0x400 59 60 #define MIOe3680_PCI_BYTES_PER_SJA 0x80 61 62 typedef struct Mioe3680PCIState { 63 /*< private >*/ 64 PCIDevice dev; 65 /*< public >*/ 66 MemoryRegion sja_io[MIOe3680_PCI_SJA_COUNT]; 67 68 CanSJA1000State sja_state[MIOe3680_PCI_SJA_COUNT]; 69 qemu_irq irq; 70 71 char *model; /* The model that support, only SJA1000 now. */ 72 CanBusState *canbus[MIOe3680_PCI_SJA_COUNT]; 73 } Mioe3680PCIState; 74 75 static void mioe3680_pci_reset(DeviceState *dev) 76 { 77 Mioe3680PCIState *d = MIOe3680_PCI_DEV(dev); 78 int i; 79 80 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 81 can_sja_hardware_reset(&d->sja_state[i]); 82 } 83 } 84 85 static uint64_t mioe3680_pci_sja1_io_read(void *opaque, hwaddr addr, 86 unsigned size) 87 { 88 Mioe3680PCIState *d = opaque; 89 CanSJA1000State *s = &d->sja_state[0]; 90 91 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 92 return 0; 93 } 94 95 return can_sja_mem_read(s, addr >> 2, size); 96 } 97 98 static void mioe3680_pci_sja1_io_write(void *opaque, hwaddr addr, uint64_t data, 99 unsigned size) 100 { 101 Mioe3680PCIState *d = opaque; 102 CanSJA1000State *s = &d->sja_state[0]; 103 104 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 105 return; 106 } 107 108 can_sja_mem_write(s, addr >> 2, data, size); 109 } 110 111 static uint64_t mioe3680_pci_sja2_io_read(void *opaque, hwaddr addr, 112 unsigned size) 113 { 114 Mioe3680PCIState *d = opaque; 115 CanSJA1000State *s = &d->sja_state[1]; 116 117 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 118 return 0; 119 } 120 121 return can_sja_mem_read(s, addr >> 2, size); 122 } 123 124 static void mioe3680_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data, 125 unsigned size) 126 { 127 Mioe3680PCIState *d = opaque; 128 CanSJA1000State *s = &d->sja_state[1]; 129 130 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 131 return; 132 } 133 134 can_sja_mem_write(s, addr >> 2, data, size); 135 } 136 137 static const MemoryRegionOps mioe3680_pci_sja1_io_ops = { 138 .read = mioe3680_pci_sja1_io_read, 139 .write = mioe3680_pci_sja1_io_write, 140 .endianness = DEVICE_LITTLE_ENDIAN, 141 .impl = { 142 .max_access_size = 1, 143 }, 144 }; 145 146 static const MemoryRegionOps mioe3680_pci_sja2_io_ops = { 147 .read = mioe3680_pci_sja2_io_read, 148 .write = mioe3680_pci_sja2_io_write, 149 .endianness = DEVICE_LITTLE_ENDIAN, 150 .impl = { 151 .max_access_size = 1, 152 }, 153 }; 154 155 static void mioe3680_pci_realize(PCIDevice *pci_dev, Error **errp) 156 { 157 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 158 uint8_t *pci_conf; 159 int i; 160 161 pci_conf = pci_dev->config; 162 pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 163 164 d->irq = pci_allocate_irq(&d->dev); 165 166 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 167 can_sja_init(&d->sja_state[i], d->irq); 168 } 169 170 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 171 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { 172 error_setg(errp, "can_sja_connect_to_bus failed"); 173 return; 174 } 175 } 176 177 memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops, 178 d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE); 179 memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops, 180 d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE); 181 182 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 183 pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO, 184 &d->sja_io[i]); 185 } 186 } 187 188 static void mioe3680_pci_exit(PCIDevice *pci_dev) 189 { 190 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 191 int i; 192 193 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 194 can_sja_disconnect(&d->sja_state[i]); 195 } 196 197 qemu_free_irq(d->irq); 198 } 199 200 static const VMStateDescription vmstate_mioe3680_pci = { 201 .name = "mioe3680_pci", 202 .version_id = 1, 203 .minimum_version_id = 1, 204 .minimum_version_id_old = 1, 205 .fields = (VMStateField[]) { 206 VMSTATE_PCI_DEVICE(dev, Mioe3680PCIState), 207 VMSTATE_STRUCT(sja_state[0], Mioe3680PCIState, 0, vmstate_can_sja, 208 CanSJA1000State), 209 VMSTATE_STRUCT(sja_state[1], Mioe3680PCIState, 0, vmstate_can_sja, 210 CanSJA1000State), 211 VMSTATE_END_OF_LIST() 212 } 213 }; 214 215 static void mioe3680_pci_instance_init(Object *obj) 216 { 217 Mioe3680PCIState *d = MIOe3680_PCI_DEV(obj); 218 219 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 220 (Object **)&d->canbus[0], 221 qdev_prop_allow_set_link_before_realize, 222 0); 223 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 224 (Object **)&d->canbus[1], 225 qdev_prop_allow_set_link_before_realize, 226 0); 227 } 228 229 static void mioe3680_pci_class_init(ObjectClass *klass, void *data) 230 { 231 DeviceClass *dc = DEVICE_CLASS(klass); 232 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 233 234 k->realize = mioe3680_pci_realize; 235 k->exit = mioe3680_pci_exit; 236 k->vendor_id = MIOe3680_PCI_VENDOR_ID1; 237 k->device_id = MIOe3680_PCI_DEVICE_ID1; 238 k->revision = 0x00; 239 k->class_id = 0x000c09; 240 k->subsystem_vendor_id = MIOe3680_PCI_VENDOR_ID1; 241 k->subsystem_id = MIOe3680_PCI_DEVICE_ID1; 242 dc->desc = "Mioe3680 PCICANx"; 243 dc->vmsd = &vmstate_mioe3680_pci; 244 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 245 dc->reset = mioe3680_pci_reset; 246 } 247 248 static const TypeInfo mioe3680_pci_info = { 249 .name = TYPE_CAN_PCI_DEV, 250 .parent = TYPE_PCI_DEVICE, 251 .instance_size = sizeof(Mioe3680PCIState), 252 .class_init = mioe3680_pci_class_init, 253 .instance_init = mioe3680_pci_instance_init, 254 .interfaces = (InterfaceInfo[]) { 255 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 256 { }, 257 }, 258 }; 259 260 static void mioe3680_pci_register_types(void) 261 { 262 type_register_static(&mioe3680_pci_info); 263 } 264 265 type_init(mioe3680_pci_register_types) 266