1 /* 2 * MIOe-3680 PCI CAN device (SJA1000 based) emulation 3 * 4 * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com) 5 * 6 * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by 7 * Jin Yang and Pavel Pisa 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/event_notifier.h" 30 #include "qemu/thread.h" 31 #include "qemu/sockets.h" 32 #include "qapi/error.h" 33 #include "chardev/char.h" 34 #include "hw/hw.h" 35 #include "hw/pci/pci.h" 36 #include "net/can_emu.h" 37 38 #include "can_sja1000.h" 39 40 #define TYPE_CAN_PCI_DEV "mioe3680_pci" 41 42 #define MIOe3680_PCI_DEV(obj) \ 43 OBJECT_CHECK(Mioe3680PCIState, (obj), TYPE_CAN_PCI_DEV) 44 45 /* the PCI device and vendor IDs */ 46 #ifndef MIOe3680_PCI_VENDOR_ID1 47 #define MIOe3680_PCI_VENDOR_ID1 0x13fe 48 #endif 49 50 #ifndef MIOe3680_PCI_DEVICE_ID1 51 #define MIOe3680_PCI_DEVICE_ID1 0xc302 52 #endif 53 54 #define MIOe3680_PCI_SJA_COUNT 2 55 #define MIOe3680_PCI_SJA_RANGE 0x400 56 57 #define MIOe3680_PCI_BYTES_PER_SJA 0x80 58 59 typedef struct Mioe3680PCIState { 60 /*< private >*/ 61 PCIDevice dev; 62 /*< public >*/ 63 MemoryRegion sja_io[MIOe3680_PCI_SJA_COUNT]; 64 65 CanSJA1000State sja_state[MIOe3680_PCI_SJA_COUNT]; 66 qemu_irq irq; 67 68 char *model; /* The model that support, only SJA1000 now. */ 69 CanBusState *canbus[MIOe3680_PCI_SJA_COUNT]; 70 } Mioe3680PCIState; 71 72 static void mioe3680_pci_reset(DeviceState *dev) 73 { 74 Mioe3680PCIState *d = MIOe3680_PCI_DEV(dev); 75 int i; 76 77 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 78 can_sja_hardware_reset(&d->sja_state[i]); 79 } 80 } 81 82 static uint64_t mioe3680_pci_sja1_io_read(void *opaque, hwaddr addr, 83 unsigned size) 84 { 85 Mioe3680PCIState *d = opaque; 86 CanSJA1000State *s = &d->sja_state[0]; 87 88 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 89 return 0; 90 } 91 92 return can_sja_mem_read(s, addr >> 2, size); 93 } 94 95 static void mioe3680_pci_sja1_io_write(void *opaque, hwaddr addr, uint64_t data, 96 unsigned size) 97 { 98 Mioe3680PCIState *d = opaque; 99 CanSJA1000State *s = &d->sja_state[0]; 100 101 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 102 return; 103 } 104 105 can_sja_mem_write(s, addr >> 2, data, size); 106 } 107 108 static uint64_t mioe3680_pci_sja2_io_read(void *opaque, hwaddr addr, 109 unsigned size) 110 { 111 Mioe3680PCIState *d = opaque; 112 CanSJA1000State *s = &d->sja_state[1]; 113 114 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 115 return 0; 116 } 117 118 return can_sja_mem_read(s, addr >> 2, size); 119 } 120 121 static void mioe3680_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data, 122 unsigned size) 123 { 124 Mioe3680PCIState *d = opaque; 125 CanSJA1000State *s = &d->sja_state[1]; 126 127 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 128 return; 129 } 130 131 can_sja_mem_write(s, addr >> 2, data, size); 132 } 133 134 static const MemoryRegionOps mioe3680_pci_sja1_io_ops = { 135 .read = mioe3680_pci_sja1_io_read, 136 .write = mioe3680_pci_sja1_io_write, 137 .endianness = DEVICE_LITTLE_ENDIAN, 138 .impl = { 139 .max_access_size = 1, 140 }, 141 }; 142 143 static const MemoryRegionOps mioe3680_pci_sja2_io_ops = { 144 .read = mioe3680_pci_sja2_io_read, 145 .write = mioe3680_pci_sja2_io_write, 146 .endianness = DEVICE_LITTLE_ENDIAN, 147 .impl = { 148 .max_access_size = 1, 149 }, 150 }; 151 152 static void mioe3680_pci_realize(PCIDevice *pci_dev, Error **errp) 153 { 154 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 155 uint8_t *pci_conf; 156 int i; 157 158 pci_conf = pci_dev->config; 159 pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 160 161 d->irq = pci_allocate_irq(&d->dev); 162 163 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 164 can_sja_init(&d->sja_state[i], d->irq); 165 } 166 167 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 168 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { 169 error_setg(errp, "can_sja_connect_to_bus failed"); 170 return; 171 } 172 } 173 174 memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops, 175 d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE); 176 memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops, 177 d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE); 178 179 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 180 pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO, 181 &d->sja_io[i]); 182 } 183 } 184 185 static void mioe3680_pci_exit(PCIDevice *pci_dev) 186 { 187 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 188 int i; 189 190 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 191 can_sja_disconnect(&d->sja_state[i]); 192 } 193 194 qemu_free_irq(d->irq); 195 } 196 197 static const VMStateDescription vmstate_mioe3680_pci = { 198 .name = "mioe3680_pci", 199 .version_id = 1, 200 .minimum_version_id = 1, 201 .minimum_version_id_old = 1, 202 .fields = (VMStateField[]) { 203 VMSTATE_PCI_DEVICE(dev, Mioe3680PCIState), 204 VMSTATE_STRUCT(sja_state[0], Mioe3680PCIState, 0, vmstate_can_sja, 205 CanSJA1000State), 206 VMSTATE_STRUCT(sja_state[1], Mioe3680PCIState, 0, vmstate_can_sja, 207 CanSJA1000State), 208 VMSTATE_END_OF_LIST() 209 } 210 }; 211 212 static void mioe3680_pci_instance_init(Object *obj) 213 { 214 Mioe3680PCIState *d = MIOe3680_PCI_DEV(obj); 215 216 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 217 (Object **)&d->canbus[0], 218 qdev_prop_allow_set_link_before_realize, 219 0, &error_abort); 220 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 221 (Object **)&d->canbus[1], 222 qdev_prop_allow_set_link_before_realize, 223 0, &error_abort); 224 } 225 226 static void mioe3680_pci_class_init(ObjectClass *klass, void *data) 227 { 228 DeviceClass *dc = DEVICE_CLASS(klass); 229 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 230 231 k->realize = mioe3680_pci_realize; 232 k->exit = mioe3680_pci_exit; 233 k->vendor_id = MIOe3680_PCI_VENDOR_ID1; 234 k->device_id = MIOe3680_PCI_DEVICE_ID1; 235 k->revision = 0x00; 236 k->class_id = 0x000c09; 237 k->subsystem_vendor_id = MIOe3680_PCI_VENDOR_ID1; 238 k->subsystem_id = MIOe3680_PCI_DEVICE_ID1; 239 dc->desc = "Mioe3680 PCICANx"; 240 dc->vmsd = &vmstate_mioe3680_pci; 241 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 242 dc->reset = mioe3680_pci_reset; 243 } 244 245 static const TypeInfo mioe3680_pci_info = { 246 .name = TYPE_CAN_PCI_DEV, 247 .parent = TYPE_PCI_DEVICE, 248 .instance_size = sizeof(Mioe3680PCIState), 249 .class_init = mioe3680_pci_class_init, 250 .instance_init = mioe3680_pci_instance_init, 251 .interfaces = (InterfaceInfo[]) { 252 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 253 { }, 254 }, 255 }; 256 257 static void mioe3680_pci_register_types(void) 258 { 259 type_register_static(&mioe3680_pci_info); 260 } 261 262 type_init(mioe3680_pci_register_types) 263