xref: /openbmc/qemu/hw/net/cadence_gem.c (revision db725815985654007ade0fd53590d613fd657208)
1 /*
2  * QEMU Cadence GEM emulation
3  *
4  * Copyright (c) 2011 Xilinx, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include <zlib.h> /* For crc32 */
27 
28 #include "hw/irq.h"
29 #include "hw/net/cadence_gem.h"
30 #include "migration/vmstate.h"
31 #include "qapi/error.h"
32 #include "qemu/log.h"
33 #include "qemu/module.h"
34 #include "sysemu/dma.h"
35 #include "net/checksum.h"
36 
37 #ifdef CADENCE_GEM_ERR_DEBUG
38 #define DB_PRINT(...) do { \
39     fprintf(stderr,  ": %s: ", __func__); \
40     fprintf(stderr, ## __VA_ARGS__); \
41     } while (0)
42 #else
43     #define DB_PRINT(...)
44 #endif
45 
46 #define GEM_NWCTRL        (0x00000000/4) /* Network Control reg */
47 #define GEM_NWCFG         (0x00000004/4) /* Network Config reg */
48 #define GEM_NWSTATUS      (0x00000008/4) /* Network Status reg */
49 #define GEM_USERIO        (0x0000000C/4) /* User IO reg */
50 #define GEM_DMACFG        (0x00000010/4) /* DMA Control reg */
51 #define GEM_TXSTATUS      (0x00000014/4) /* TX Status reg */
52 #define GEM_RXQBASE       (0x00000018/4) /* RX Q Base address reg */
53 #define GEM_TXQBASE       (0x0000001C/4) /* TX Q Base address reg */
54 #define GEM_RXSTATUS      (0x00000020/4) /* RX Status reg */
55 #define GEM_ISR           (0x00000024/4) /* Interrupt Status reg */
56 #define GEM_IER           (0x00000028/4) /* Interrupt Enable reg */
57 #define GEM_IDR           (0x0000002C/4) /* Interrupt Disable reg */
58 #define GEM_IMR           (0x00000030/4) /* Interrupt Mask reg */
59 #define GEM_PHYMNTNC      (0x00000034/4) /* Phy Maintenance reg */
60 #define GEM_RXPAUSE       (0x00000038/4) /* RX Pause Time reg */
61 #define GEM_TXPAUSE       (0x0000003C/4) /* TX Pause Time reg */
62 #define GEM_TXPARTIALSF   (0x00000040/4) /* TX Partial Store and Forward */
63 #define GEM_RXPARTIALSF   (0x00000044/4) /* RX Partial Store and Forward */
64 #define GEM_HASHLO        (0x00000080/4) /* Hash Low address reg */
65 #define GEM_HASHHI        (0x00000084/4) /* Hash High address reg */
66 #define GEM_SPADDR1LO     (0x00000088/4) /* Specific addr 1 low reg */
67 #define GEM_SPADDR1HI     (0x0000008C/4) /* Specific addr 1 high reg */
68 #define GEM_SPADDR2LO     (0x00000090/4) /* Specific addr 2 low reg */
69 #define GEM_SPADDR2HI     (0x00000094/4) /* Specific addr 2 high reg */
70 #define GEM_SPADDR3LO     (0x00000098/4) /* Specific addr 3 low reg */
71 #define GEM_SPADDR3HI     (0x0000009C/4) /* Specific addr 3 high reg */
72 #define GEM_SPADDR4LO     (0x000000A0/4) /* Specific addr 4 low reg */
73 #define GEM_SPADDR4HI     (0x000000A4/4) /* Specific addr 4 high reg */
74 #define GEM_TIDMATCH1     (0x000000A8/4) /* Type ID1 Match reg */
75 #define GEM_TIDMATCH2     (0x000000AC/4) /* Type ID2 Match reg */
76 #define GEM_TIDMATCH3     (0x000000B0/4) /* Type ID3 Match reg */
77 #define GEM_TIDMATCH4     (0x000000B4/4) /* Type ID4 Match reg */
78 #define GEM_WOLAN         (0x000000B8/4) /* Wake on LAN reg */
79 #define GEM_IPGSTRETCH    (0x000000BC/4) /* IPG Stretch reg */
80 #define GEM_SVLAN         (0x000000C0/4) /* Stacked VLAN reg */
81 #define GEM_MODID         (0x000000FC/4) /* Module ID reg */
82 #define GEM_OCTTXLO       (0x00000100/4) /* Octects transmitted Low reg */
83 #define GEM_OCTTXHI       (0x00000104/4) /* Octects transmitted High reg */
84 #define GEM_TXCNT         (0x00000108/4) /* Error-free Frames transmitted */
85 #define GEM_TXBCNT        (0x0000010C/4) /* Error-free Broadcast Frames */
86 #define GEM_TXMCNT        (0x00000110/4) /* Error-free Multicast Frame */
87 #define GEM_TXPAUSECNT    (0x00000114/4) /* Pause Frames Transmitted */
88 #define GEM_TX64CNT       (0x00000118/4) /* Error-free 64 TX */
89 #define GEM_TX65CNT       (0x0000011C/4) /* Error-free 65-127 TX */
90 #define GEM_TX128CNT      (0x00000120/4) /* Error-free 128-255 TX */
91 #define GEM_TX256CNT      (0x00000124/4) /* Error-free 256-511 */
92 #define GEM_TX512CNT      (0x00000128/4) /* Error-free 512-1023 TX */
93 #define GEM_TX1024CNT     (0x0000012C/4) /* Error-free 1024-1518 TX */
94 #define GEM_TX1519CNT     (0x00000130/4) /* Error-free larger than 1519 TX */
95 #define GEM_TXURUNCNT     (0x00000134/4) /* TX under run error counter */
96 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
97 #define GEM_MULTCOLLCNT   (0x0000013C/4) /* Multiple Collision Frames */
98 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
99 #define GEM_LATECOLLCNT   (0x00000144/4) /* Late Collision Frames */
100 #define GEM_DEFERTXCNT    (0x00000148/4) /* Deferred Transmission Frames */
101 #define GEM_CSENSECNT     (0x0000014C/4) /* Carrier Sense Error Counter */
102 #define GEM_OCTRXLO       (0x00000150/4) /* Octects Received register Low */
103 #define GEM_OCTRXHI       (0x00000154/4) /* Octects Received register High */
104 #define GEM_RXCNT         (0x00000158/4) /* Error-free Frames Received */
105 #define GEM_RXBROADCNT    (0x0000015C/4) /* Error-free Broadcast Frames RX */
106 #define GEM_RXMULTICNT    (0x00000160/4) /* Error-free Multicast Frames RX */
107 #define GEM_RXPAUSECNT    (0x00000164/4) /* Pause Frames Received Counter */
108 #define GEM_RX64CNT       (0x00000168/4) /* Error-free 64 byte Frames RX */
109 #define GEM_RX65CNT       (0x0000016C/4) /* Error-free 65-127B Frames RX */
110 #define GEM_RX128CNT      (0x00000170/4) /* Error-free 128-255B Frames RX */
111 #define GEM_RX256CNT      (0x00000174/4) /* Error-free 256-512B Frames RX */
112 #define GEM_RX512CNT      (0x00000178/4) /* Error-free 512-1023B Frames RX */
113 #define GEM_RX1024CNT     (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
114 #define GEM_RX1519CNT     (0x00000180/4) /* Error-free 1519-max Frames RX */
115 #define GEM_RXUNDERCNT    (0x00000184/4) /* Undersize Frames Received */
116 #define GEM_RXOVERCNT     (0x00000188/4) /* Oversize Frames Received */
117 #define GEM_RXJABCNT      (0x0000018C/4) /* Jabbers Received Counter */
118 #define GEM_RXFCSCNT      (0x00000190/4) /* Frame Check seq. Error Counter */
119 #define GEM_RXLENERRCNT   (0x00000194/4) /* Length Field Error Counter */
120 #define GEM_RXSYMERRCNT   (0x00000198/4) /* Symbol Error Counter */
121 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
122 #define GEM_RXRSCERRCNT   (0x000001A0/4) /* Receive Resource Error Counter */
123 #define GEM_RXORUNCNT     (0x000001A4/4) /* Receive Overrun Counter */
124 #define GEM_RXIPCSERRCNT  (0x000001A8/4) /* IP header Checksum Error Counter */
125 #define GEM_RXTCPCCNT     (0x000001AC/4) /* TCP Checksum Error Counter */
126 #define GEM_RXUDPCCNT     (0x000001B0/4) /* UDP Checksum Error Counter */
127 
128 #define GEM_1588S         (0x000001D0/4) /* 1588 Timer Seconds */
129 #define GEM_1588NS        (0x000001D4/4) /* 1588 Timer Nanoseconds */
130 #define GEM_1588ADJ       (0x000001D8/4) /* 1588 Timer Adjust */
131 #define GEM_1588INC       (0x000001DC/4) /* 1588 Timer Increment */
132 #define GEM_PTPETXS       (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
133 #define GEM_PTPETXNS      (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
134 #define GEM_PTPERXS       (0x000001E8/4) /* PTP Event Frame Received (s) */
135 #define GEM_PTPERXNS      (0x000001EC/4) /* PTP Event Frame Received (ns) */
136 #define GEM_PTPPTXS       (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
137 #define GEM_PTPPTXNS      (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
138 #define GEM_PTPPRXS       (0x000001E8/4) /* PTP Peer Frame Received (s) */
139 #define GEM_PTPPRXNS      (0x000001EC/4) /* PTP Peer Frame Received (ns) */
140 
141 /* Design Configuration Registers */
142 #define GEM_DESCONF       (0x00000280/4)
143 #define GEM_DESCONF2      (0x00000284/4)
144 #define GEM_DESCONF3      (0x00000288/4)
145 #define GEM_DESCONF4      (0x0000028C/4)
146 #define GEM_DESCONF5      (0x00000290/4)
147 #define GEM_DESCONF6      (0x00000294/4)
148 #define GEM_DESCONF6_64B_MASK (1U << 23)
149 #define GEM_DESCONF7      (0x00000298/4)
150 
151 #define GEM_INT_Q1_STATUS               (0x00000400 / 4)
152 #define GEM_INT_Q1_MASK                 (0x00000640 / 4)
153 
154 #define GEM_TRANSMIT_Q1_PTR             (0x00000440 / 4)
155 #define GEM_TRANSMIT_Q7_PTR             (GEM_TRANSMIT_Q1_PTR + 6)
156 
157 #define GEM_RECEIVE_Q1_PTR              (0x00000480 / 4)
158 #define GEM_RECEIVE_Q7_PTR              (GEM_RECEIVE_Q1_PTR + 6)
159 
160 #define GEM_TBQPH                       (0x000004C8 / 4)
161 #define GEM_RBQPH                       (0x000004D4 / 4)
162 
163 #define GEM_INT_Q1_ENABLE               (0x00000600 / 4)
164 #define GEM_INT_Q7_ENABLE               (GEM_INT_Q1_ENABLE + 6)
165 
166 #define GEM_INT_Q1_DISABLE              (0x00000620 / 4)
167 #define GEM_INT_Q7_DISABLE              (GEM_INT_Q1_DISABLE + 6)
168 
169 #define GEM_INT_Q1_MASK                 (0x00000640 / 4)
170 #define GEM_INT_Q7_MASK                 (GEM_INT_Q1_MASK + 6)
171 
172 #define GEM_SCREENING_TYPE1_REGISTER_0  (0x00000500 / 4)
173 
174 #define GEM_ST1R_UDP_PORT_MATCH_ENABLE  (1 << 29)
175 #define GEM_ST1R_DSTC_ENABLE            (1 << 28)
176 #define GEM_ST1R_UDP_PORT_MATCH_SHIFT   (12)
177 #define GEM_ST1R_UDP_PORT_MATCH_WIDTH   (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
178 #define GEM_ST1R_DSTC_MATCH_SHIFT       (4)
179 #define GEM_ST1R_DSTC_MATCH_WIDTH       (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
180 #define GEM_ST1R_QUEUE_SHIFT            (0)
181 #define GEM_ST1R_QUEUE_WIDTH            (3 - GEM_ST1R_QUEUE_SHIFT + 1)
182 
183 #define GEM_SCREENING_TYPE2_REGISTER_0  (0x00000540 / 4)
184 
185 #define GEM_ST2R_COMPARE_A_ENABLE       (1 << 18)
186 #define GEM_ST2R_COMPARE_A_SHIFT        (13)
187 #define GEM_ST2R_COMPARE_WIDTH          (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
188 #define GEM_ST2R_ETHERTYPE_ENABLE       (1 << 12)
189 #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT  (9)
190 #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH  (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
191                                             + 1)
192 #define GEM_ST2R_QUEUE_SHIFT            (0)
193 #define GEM_ST2R_QUEUE_WIDTH            (3 - GEM_ST2R_QUEUE_SHIFT + 1)
194 
195 #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0     (0x000006e0 / 4)
196 #define GEM_TYPE2_COMPARE_0_WORD_0              (0x00000700 / 4)
197 
198 #define GEM_T2CW1_COMPARE_OFFSET_SHIFT  (7)
199 #define GEM_T2CW1_COMPARE_OFFSET_WIDTH  (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
200 #define GEM_T2CW1_OFFSET_VALUE_SHIFT    (0)
201 #define GEM_T2CW1_OFFSET_VALUE_WIDTH    (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
202 
203 /*****************************************/
204 #define GEM_NWCTRL_TXSTART     0x00000200 /* Transmit Enable */
205 #define GEM_NWCTRL_TXENA       0x00000008 /* Transmit Enable */
206 #define GEM_NWCTRL_RXENA       0x00000004 /* Receive Enable */
207 #define GEM_NWCTRL_LOCALLOOP   0x00000002 /* Local Loopback */
208 
209 #define GEM_NWCFG_STRIP_FCS    0x00020000 /* Strip FCS field */
210 #define GEM_NWCFG_LERR_DISC    0x00010000 /* Discard RX frames with len err */
211 #define GEM_NWCFG_BUFF_OFST_M  0x0000C000 /* Receive buffer offset mask */
212 #define GEM_NWCFG_BUFF_OFST_S  14         /* Receive buffer offset shift */
213 #define GEM_NWCFG_UCAST_HASH   0x00000080 /* accept unicast if hash match */
214 #define GEM_NWCFG_MCAST_HASH   0x00000040 /* accept multicast if hash match */
215 #define GEM_NWCFG_BCAST_REJ    0x00000020 /* Reject broadcast packets */
216 #define GEM_NWCFG_PROMISC      0x00000010 /* Accept all packets */
217 
218 #define GEM_DMACFG_ADDR_64B    (1U << 30)
219 #define GEM_DMACFG_TX_BD_EXT   (1U << 29)
220 #define GEM_DMACFG_RX_BD_EXT   (1U << 28)
221 #define GEM_DMACFG_RBUFSZ_M    0x00FF0000 /* DMA RX Buffer Size mask */
222 #define GEM_DMACFG_RBUFSZ_S    16         /* DMA RX Buffer Size shift */
223 #define GEM_DMACFG_RBUFSZ_MUL  64         /* DMA RX Buffer Size multiplier */
224 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
225 
226 #define GEM_TXSTATUS_TXCMPL    0x00000020 /* Transmit Complete */
227 #define GEM_TXSTATUS_USED      0x00000001 /* sw owned descriptor encountered */
228 
229 #define GEM_RXSTATUS_FRMRCVD   0x00000002 /* Frame received */
230 #define GEM_RXSTATUS_NOBUF     0x00000001 /* Buffer unavailable */
231 
232 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
233 #define GEM_INT_TXCMPL        0x00000080 /* Transmit Complete */
234 #define GEM_INT_TXUSED         0x00000008
235 #define GEM_INT_RXUSED         0x00000004
236 #define GEM_INT_RXCMPL        0x00000002
237 
238 #define GEM_PHYMNTNC_OP_R      0x20000000 /* read operation */
239 #define GEM_PHYMNTNC_OP_W      0x10000000 /* write operation */
240 #define GEM_PHYMNTNC_ADDR      0x0F800000 /* Address bits */
241 #define GEM_PHYMNTNC_ADDR_SHFT 23
242 #define GEM_PHYMNTNC_REG       0x007C0000 /* register bits */
243 #define GEM_PHYMNTNC_REG_SHIFT 18
244 
245 /* Marvell PHY definitions */
246 #define BOARD_PHY_ADDRESS    23 /* PHY address we will emulate a device at */
247 
248 #define PHY_REG_CONTROL      0
249 #define PHY_REG_STATUS       1
250 #define PHY_REG_PHYID1       2
251 #define PHY_REG_PHYID2       3
252 #define PHY_REG_ANEGADV      4
253 #define PHY_REG_LINKPABIL    5
254 #define PHY_REG_ANEGEXP      6
255 #define PHY_REG_NEXTP        7
256 #define PHY_REG_LINKPNEXTP   8
257 #define PHY_REG_100BTCTRL    9
258 #define PHY_REG_1000BTSTAT   10
259 #define PHY_REG_EXTSTAT      15
260 #define PHY_REG_PHYSPCFC_CTL 16
261 #define PHY_REG_PHYSPCFC_ST  17
262 #define PHY_REG_INT_EN       18
263 #define PHY_REG_INT_ST       19
264 #define PHY_REG_EXT_PHYSPCFC_CTL  20
265 #define PHY_REG_RXERR        21
266 #define PHY_REG_EACD         22
267 #define PHY_REG_LED          24
268 #define PHY_REG_LED_OVRD     25
269 #define PHY_REG_EXT_PHYSPCFC_CTL2 26
270 #define PHY_REG_EXT_PHYSPCFC_ST   27
271 #define PHY_REG_CABLE_DIAG   28
272 
273 #define PHY_REG_CONTROL_RST  0x8000
274 #define PHY_REG_CONTROL_LOOP 0x4000
275 #define PHY_REG_CONTROL_ANEG 0x1000
276 
277 #define PHY_REG_STATUS_LINK     0x0004
278 #define PHY_REG_STATUS_ANEGCMPL 0x0020
279 
280 #define PHY_REG_INT_ST_ANEGCMPL 0x0800
281 #define PHY_REG_INT_ST_LINKC    0x0400
282 #define PHY_REG_INT_ST_ENERGY   0x0010
283 
284 /***********************************************************************/
285 #define GEM_RX_REJECT                   (-1)
286 #define GEM_RX_PROMISCUOUS_ACCEPT       (-2)
287 #define GEM_RX_BROADCAST_ACCEPT         (-3)
288 #define GEM_RX_MULTICAST_HASH_ACCEPT    (-4)
289 #define GEM_RX_UNICAST_HASH_ACCEPT      (-5)
290 
291 #define GEM_RX_SAR_ACCEPT               0
292 
293 /***********************************************************************/
294 
295 #define DESC_1_USED 0x80000000
296 #define DESC_1_LENGTH 0x00001FFF
297 
298 #define DESC_1_TX_WRAP 0x40000000
299 #define DESC_1_TX_LAST 0x00008000
300 
301 #define DESC_0_RX_WRAP 0x00000002
302 #define DESC_0_RX_OWNERSHIP 0x00000001
303 
304 #define R_DESC_1_RX_SAR_SHIFT           25
305 #define R_DESC_1_RX_SAR_LENGTH          2
306 #define R_DESC_1_RX_SAR_MATCH           (1 << 27)
307 #define R_DESC_1_RX_UNICAST_HASH        (1 << 29)
308 #define R_DESC_1_RX_MULTICAST_HASH      (1 << 30)
309 #define R_DESC_1_RX_BROADCAST           (1 << 31)
310 
311 #define DESC_1_RX_SOF 0x00004000
312 #define DESC_1_RX_EOF 0x00008000
313 
314 #define GEM_MODID_VALUE 0x00020118
315 
316 static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
317 {
318     uint64_t ret = desc[0];
319 
320     if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
321         ret |= (uint64_t)desc[2] << 32;
322     }
323     return ret;
324 }
325 
326 static inline unsigned tx_desc_get_used(uint32_t *desc)
327 {
328     return (desc[1] & DESC_1_USED) ? 1 : 0;
329 }
330 
331 static inline void tx_desc_set_used(uint32_t *desc)
332 {
333     desc[1] |= DESC_1_USED;
334 }
335 
336 static inline unsigned tx_desc_get_wrap(uint32_t *desc)
337 {
338     return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
339 }
340 
341 static inline unsigned tx_desc_get_last(uint32_t *desc)
342 {
343     return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
344 }
345 
346 static inline void tx_desc_set_last(uint32_t *desc)
347 {
348     desc[1] |= DESC_1_TX_LAST;
349 }
350 
351 static inline unsigned tx_desc_get_length(uint32_t *desc)
352 {
353     return desc[1] & DESC_1_LENGTH;
354 }
355 
356 static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
357 {
358     DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
359     DB_PRINT("bufaddr: 0x%08x\n", *desc);
360     DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
361     DB_PRINT("wrap:    %d\n", tx_desc_get_wrap(desc));
362     DB_PRINT("last:    %d\n", tx_desc_get_last(desc));
363     DB_PRINT("length:  %d\n", tx_desc_get_length(desc));
364 }
365 
366 static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
367 {
368     uint64_t ret = desc[0] & ~0x3UL;
369 
370     if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
371         ret |= (uint64_t)desc[2] << 32;
372     }
373     return ret;
374 }
375 
376 static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
377 {
378     int ret = 2;
379 
380     if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
381         ret += 2;
382     }
383     if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
384                                        : GEM_DMACFG_TX_BD_EXT)) {
385         ret += 2;
386     }
387 
388     assert(ret <= DESC_MAX_NUM_WORDS);
389     return ret;
390 }
391 
392 static inline unsigned rx_desc_get_wrap(uint32_t *desc)
393 {
394     return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
395 }
396 
397 static inline unsigned rx_desc_get_ownership(uint32_t *desc)
398 {
399     return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
400 }
401 
402 static inline void rx_desc_set_ownership(uint32_t *desc)
403 {
404     desc[0] |= DESC_0_RX_OWNERSHIP;
405 }
406 
407 static inline void rx_desc_set_sof(uint32_t *desc)
408 {
409     desc[1] |= DESC_1_RX_SOF;
410 }
411 
412 static inline void rx_desc_set_eof(uint32_t *desc)
413 {
414     desc[1] |= DESC_1_RX_EOF;
415 }
416 
417 static inline void rx_desc_set_length(uint32_t *desc, unsigned len)
418 {
419     desc[1] &= ~DESC_1_LENGTH;
420     desc[1] |= len;
421 }
422 
423 static inline void rx_desc_set_broadcast(uint32_t *desc)
424 {
425     desc[1] |= R_DESC_1_RX_BROADCAST;
426 }
427 
428 static inline void rx_desc_set_unicast_hash(uint32_t *desc)
429 {
430     desc[1] |= R_DESC_1_RX_UNICAST_HASH;
431 }
432 
433 static inline void rx_desc_set_multicast_hash(uint32_t *desc)
434 {
435     desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
436 }
437 
438 static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
439 {
440     desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
441                         sar_idx);
442     desc[1] |= R_DESC_1_RX_SAR_MATCH;
443 }
444 
445 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
446 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
447 
448 /*
449  * gem_init_register_masks:
450  * One time initialization.
451  * Set masks to identify which register bits have magical clear properties
452  */
453 static void gem_init_register_masks(CadenceGEMState *s)
454 {
455     /* Mask of register bits which are read only */
456     memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
457     s->regs_ro[GEM_NWCTRL]   = 0xFFF80000;
458     s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
459     s->regs_ro[GEM_DMACFG]   = 0x8E00F000;
460     s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
461     s->regs_ro[GEM_RXQBASE]  = 0x00000003;
462     s->regs_ro[GEM_TXQBASE]  = 0x00000003;
463     s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
464     s->regs_ro[GEM_ISR]      = 0xFFFFFFFF;
465     s->regs_ro[GEM_IMR]      = 0xFFFFFFFF;
466     s->regs_ro[GEM_MODID]    = 0xFFFFFFFF;
467 
468     /* Mask of register bits which are clear on read */
469     memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
470     s->regs_rtc[GEM_ISR]      = 0xFFFFFFFF;
471 
472     /* Mask of register bits which are write 1 to clear */
473     memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
474     s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
475     s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
476 
477     /* Mask of register bits which are write only */
478     memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
479     s->regs_wo[GEM_NWCTRL]   = 0x00073E60;
480     s->regs_wo[GEM_IER]      = 0x07FFFFFF;
481     s->regs_wo[GEM_IDR]      = 0x07FFFFFF;
482 }
483 
484 /*
485  * phy_update_link:
486  * Make the emulated PHY link state match the QEMU "interface" state.
487  */
488 static void phy_update_link(CadenceGEMState *s)
489 {
490     DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
491 
492     /* Autonegotiation status mirrors link status.  */
493     if (qemu_get_queue(s->nic)->link_down) {
494         s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
495                                          PHY_REG_STATUS_LINK);
496         s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
497     } else {
498         s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
499                                          PHY_REG_STATUS_LINK);
500         s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
501                                         PHY_REG_INT_ST_ANEGCMPL |
502                                         PHY_REG_INT_ST_ENERGY);
503     }
504 }
505 
506 static int gem_can_receive(NetClientState *nc)
507 {
508     CadenceGEMState *s;
509     int i;
510 
511     s = qemu_get_nic_opaque(nc);
512 
513     /* Do nothing if receive is not enabled. */
514     if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
515         if (s->can_rx_state != 1) {
516             s->can_rx_state = 1;
517             DB_PRINT("can't receive - no enable\n");
518         }
519         return 0;
520     }
521 
522     for (i = 0; i < s->num_priority_queues; i++) {
523         if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
524             break;
525         }
526     };
527 
528     if (i == s->num_priority_queues) {
529         if (s->can_rx_state != 2) {
530             s->can_rx_state = 2;
531             DB_PRINT("can't receive - all the buffer descriptors are busy\n");
532         }
533         return 0;
534     }
535 
536     if (s->can_rx_state != 0) {
537         s->can_rx_state = 0;
538         DB_PRINT("can receive\n");
539     }
540     return 1;
541 }
542 
543 /*
544  * gem_update_int_status:
545  * Raise or lower interrupt based on current status.
546  */
547 static void gem_update_int_status(CadenceGEMState *s)
548 {
549     int i;
550 
551     if (!s->regs[GEM_ISR]) {
552         /* ISR isn't set, clear all the interrupts */
553         for (i = 0; i < s->num_priority_queues; ++i) {
554             qemu_set_irq(s->irq[i], 0);
555         }
556         return;
557     }
558 
559     /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
560      * check it again.
561      */
562     if (s->num_priority_queues == 1) {
563         /* No priority queues, just trigger the interrupt */
564         DB_PRINT("asserting int.\n");
565         qemu_set_irq(s->irq[0], 1);
566         return;
567     }
568 
569     for (i = 0; i < s->num_priority_queues; ++i) {
570         if (s->regs[GEM_INT_Q1_STATUS + i]) {
571             DB_PRINT("asserting int. (q=%d)\n", i);
572             qemu_set_irq(s->irq[i], 1);
573         }
574     }
575 }
576 
577 /*
578  * gem_receive_updatestats:
579  * Increment receive statistics.
580  */
581 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
582                                     unsigned bytes)
583 {
584     uint64_t octets;
585 
586     /* Total octets (bytes) received */
587     octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
588              s->regs[GEM_OCTRXHI];
589     octets += bytes;
590     s->regs[GEM_OCTRXLO] = octets >> 32;
591     s->regs[GEM_OCTRXHI] = octets;
592 
593     /* Error-free Frames received */
594     s->regs[GEM_RXCNT]++;
595 
596     /* Error-free Broadcast Frames counter */
597     if (!memcmp(packet, broadcast_addr, 6)) {
598         s->regs[GEM_RXBROADCNT]++;
599     }
600 
601     /* Error-free Multicast Frames counter */
602     if (packet[0] == 0x01) {
603         s->regs[GEM_RXMULTICNT]++;
604     }
605 
606     if (bytes <= 64) {
607         s->regs[GEM_RX64CNT]++;
608     } else if (bytes <= 127) {
609         s->regs[GEM_RX65CNT]++;
610     } else if (bytes <= 255) {
611         s->regs[GEM_RX128CNT]++;
612     } else if (bytes <= 511) {
613         s->regs[GEM_RX256CNT]++;
614     } else if (bytes <= 1023) {
615         s->regs[GEM_RX512CNT]++;
616     } else if (bytes <= 1518) {
617         s->regs[GEM_RX1024CNT]++;
618     } else {
619         s->regs[GEM_RX1519CNT]++;
620     }
621 }
622 
623 /*
624  * Get the MAC Address bit from the specified position
625  */
626 static unsigned get_bit(const uint8_t *mac, unsigned bit)
627 {
628     unsigned byte;
629 
630     byte = mac[bit / 8];
631     byte >>= (bit & 0x7);
632     byte &= 1;
633 
634     return byte;
635 }
636 
637 /*
638  * Calculate a GEM MAC Address hash index
639  */
640 static unsigned calc_mac_hash(const uint8_t *mac)
641 {
642     int index_bit, mac_bit;
643     unsigned hash_index;
644 
645     hash_index = 0;
646     mac_bit = 5;
647     for (index_bit = 5; index_bit >= 0; index_bit--) {
648         hash_index |= (get_bit(mac,  mac_bit) ^
649                                get_bit(mac, mac_bit + 6) ^
650                                get_bit(mac, mac_bit + 12) ^
651                                get_bit(mac, mac_bit + 18) ^
652                                get_bit(mac, mac_bit + 24) ^
653                                get_bit(mac, mac_bit + 30) ^
654                                get_bit(mac, mac_bit + 36) ^
655                                get_bit(mac, mac_bit + 42)) << index_bit;
656         mac_bit--;
657     }
658 
659     return hash_index;
660 }
661 
662 /*
663  * gem_mac_address_filter:
664  * Accept or reject this destination address?
665  * Returns:
666  * GEM_RX_REJECT: reject
667  * >= 0: Specific address accept (which matched SAR is returned)
668  * others for various other modes of accept:
669  * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
670  * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
671  */
672 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
673 {
674     uint8_t *gem_spaddr;
675     int i;
676 
677     /* Promiscuous mode? */
678     if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
679         return GEM_RX_PROMISCUOUS_ACCEPT;
680     }
681 
682     if (!memcmp(packet, broadcast_addr, 6)) {
683         /* Reject broadcast packets? */
684         if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
685             return GEM_RX_REJECT;
686         }
687         return GEM_RX_BROADCAST_ACCEPT;
688     }
689 
690     /* Accept packets -w- hash match? */
691     if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
692         (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
693         unsigned hash_index;
694 
695         hash_index = calc_mac_hash(packet);
696         if (hash_index < 32) {
697             if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
698                 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
699                                            GEM_RX_UNICAST_HASH_ACCEPT;
700             }
701         } else {
702             hash_index -= 32;
703             if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
704                 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
705                                            GEM_RX_UNICAST_HASH_ACCEPT;
706             }
707         }
708     }
709 
710     /* Check all 4 specific addresses */
711     gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
712     for (i = 3; i >= 0; i--) {
713         if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
714             return GEM_RX_SAR_ACCEPT + i;
715         }
716     }
717 
718     /* No address match; reject the packet */
719     return GEM_RX_REJECT;
720 }
721 
722 /* Figure out which queue the received data should be sent to */
723 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
724                                  unsigned rxbufsize)
725 {
726     uint32_t reg;
727     bool matched, mismatched;
728     int i, j;
729 
730     for (i = 0; i < s->num_type1_screeners; i++) {
731         reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
732         matched = false;
733         mismatched = false;
734 
735         /* Screening is based on UDP Port */
736         if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
737             uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
738             if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
739                                            GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
740                 matched = true;
741             } else {
742                 mismatched = true;
743             }
744         }
745 
746         /* Screening is based on DS/TC */
747         if (reg & GEM_ST1R_DSTC_ENABLE) {
748             uint8_t dscp = rxbuf_ptr[14 + 1];
749             if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
750                                        GEM_ST1R_DSTC_MATCH_WIDTH)) {
751                 matched = true;
752             } else {
753                 mismatched = true;
754             }
755         }
756 
757         if (matched && !mismatched) {
758             return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
759         }
760     }
761 
762     for (i = 0; i < s->num_type2_screeners; i++) {
763         reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
764         matched = false;
765         mismatched = false;
766 
767         if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
768             uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
769             int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
770                                         GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
771 
772             if (et_idx > s->num_type2_screeners) {
773                 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
774                               "register index: %d\n", et_idx);
775             }
776             if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
777                                 et_idx]) {
778                 matched = true;
779             } else {
780                 mismatched = true;
781             }
782         }
783 
784         /* Compare A, B, C */
785         for (j = 0; j < 3; j++) {
786             uint32_t cr0, cr1, mask;
787             uint16_t rx_cmp;
788             int offset;
789             int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
790                                         GEM_ST2R_COMPARE_WIDTH);
791 
792             if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
793                 continue;
794             }
795             if (cr_idx > s->num_type2_screeners) {
796                 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
797                               "register index: %d\n", cr_idx);
798             }
799 
800             cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
801             cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
802             offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
803                                     GEM_T2CW1_OFFSET_VALUE_WIDTH);
804 
805             switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
806                                    GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
807             case 3: /* Skip UDP header */
808                 qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
809                               "unimplemented - assuming UDP\n");
810                 offset += 8;
811                 /* Fallthrough */
812             case 2: /* skip the IP header */
813                 offset += 20;
814                 /* Fallthrough */
815             case 1: /* Count from after the ethertype */
816                 offset += 14;
817                 break;
818             case 0:
819                 /* Offset from start of frame */
820                 break;
821             }
822 
823             rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
824             mask = extract32(cr0, 0, 16);
825 
826             if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
827                 matched = true;
828             } else {
829                 mismatched = true;
830             }
831         }
832 
833         if (matched && !mismatched) {
834             return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
835         }
836     }
837 
838     /* We made it here, assume it's queue 0 */
839     return 0;
840 }
841 
842 static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
843 {
844     hwaddr desc_addr = 0;
845 
846     if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
847         desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
848     }
849     desc_addr <<= 32;
850     desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
851     return desc_addr;
852 }
853 
854 static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q)
855 {
856     return gem_get_desc_addr(s, true, q);
857 }
858 
859 static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q)
860 {
861     return gem_get_desc_addr(s, false, q);
862 }
863 
864 static void gem_get_rx_desc(CadenceGEMState *s, int q)
865 {
866     hwaddr desc_addr = gem_get_rx_desc_addr(s, q);
867 
868     DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr);
869 
870     /* read current descriptor */
871     address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
872                        (uint8_t *)s->rx_desc[q],
873                        sizeof(uint32_t) * gem_get_desc_len(s, true));
874 
875     /* Descriptor owned by software ? */
876     if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
877         DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
878         s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
879         s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
880         /* Handle interrupt consequences */
881         gem_update_int_status(s);
882     }
883 }
884 
885 /*
886  * gem_receive:
887  * Fit a packet handed to us by QEMU into the receive descriptor ring.
888  */
889 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
890 {
891     CadenceGEMState *s;
892     unsigned   rxbufsize, bytes_to_copy;
893     unsigned   rxbuf_offset;
894     uint8_t    rxbuf[2048];
895     uint8_t   *rxbuf_ptr;
896     bool first_desc = true;
897     int maf;
898     int q = 0;
899 
900     s = qemu_get_nic_opaque(nc);
901 
902     /* Is this destination MAC address "for us" ? */
903     maf = gem_mac_address_filter(s, buf);
904     if (maf == GEM_RX_REJECT) {
905         return -1;
906     }
907 
908     /* Discard packets with receive length error enabled ? */
909     if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
910         unsigned type_len;
911 
912         /* Fish the ethertype / length field out of the RX packet */
913         type_len = buf[12] << 8 | buf[13];
914         /* It is a length field, not an ethertype */
915         if (type_len < 0x600) {
916             if (size < type_len) {
917                 /* discard */
918                 return -1;
919             }
920         }
921     }
922 
923     /*
924      * Determine configured receive buffer offset (probably 0)
925      */
926     rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
927                    GEM_NWCFG_BUFF_OFST_S;
928 
929     /* The configure size of each receive buffer.  Determines how many
930      * buffers needed to hold this packet.
931      */
932     rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
933                  GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
934     bytes_to_copy = size;
935 
936     /* Hardware allows a zero value here but warns against it. To avoid QEMU
937      * indefinite loops we enforce a minimum value here
938      */
939     if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
940         rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
941     }
942 
943     /* Pad to minimum length. Assume FCS field is stripped, logic
944      * below will increment it to the real minimum of 64 when
945      * not FCS stripping
946      */
947     if (size < 60) {
948         size = 60;
949     }
950 
951     /* Strip of FCS field ? (usually yes) */
952     if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
953         rxbuf_ptr = (void *)buf;
954     } else {
955         unsigned crc_val;
956 
957         if (size > sizeof(rxbuf) - sizeof(crc_val)) {
958             size = sizeof(rxbuf) - sizeof(crc_val);
959         }
960         bytes_to_copy = size;
961         /* The application wants the FCS field, which QEMU does not provide.
962          * We must try and calculate one.
963          */
964 
965         memcpy(rxbuf, buf, size);
966         memset(rxbuf + size, 0, sizeof(rxbuf) - size);
967         rxbuf_ptr = rxbuf;
968         crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
969         memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
970 
971         bytes_to_copy += 4;
972         size += 4;
973     }
974 
975     DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
976 
977     /* Find which queue we are targeting */
978     q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
979 
980     while (bytes_to_copy) {
981         hwaddr desc_addr;
982 
983         /* Do nothing if receive is not enabled. */
984         if (!gem_can_receive(nc)) {
985             return -1;
986         }
987 
988         DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
989                 rx_desc_get_buffer(s->rx_desc[q]));
990 
991         /* Copy packet data to emulated DMA buffer */
992         address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
993                                                                   rxbuf_offset,
994                             MEMTXATTRS_UNSPECIFIED, rxbuf_ptr,
995                             MIN(bytes_to_copy, rxbufsize));
996         rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
997         bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
998 
999         /* Update the descriptor.  */
1000         if (first_desc) {
1001             rx_desc_set_sof(s->rx_desc[q]);
1002             first_desc = false;
1003         }
1004         if (bytes_to_copy == 0) {
1005             rx_desc_set_eof(s->rx_desc[q]);
1006             rx_desc_set_length(s->rx_desc[q], size);
1007         }
1008         rx_desc_set_ownership(s->rx_desc[q]);
1009 
1010         switch (maf) {
1011         case GEM_RX_PROMISCUOUS_ACCEPT:
1012             break;
1013         case GEM_RX_BROADCAST_ACCEPT:
1014             rx_desc_set_broadcast(s->rx_desc[q]);
1015             break;
1016         case GEM_RX_UNICAST_HASH_ACCEPT:
1017             rx_desc_set_unicast_hash(s->rx_desc[q]);
1018             break;
1019         case GEM_RX_MULTICAST_HASH_ACCEPT:
1020             rx_desc_set_multicast_hash(s->rx_desc[q]);
1021             break;
1022         case GEM_RX_REJECT:
1023             abort();
1024         default: /* SAR */
1025             rx_desc_set_sar(s->rx_desc[q], maf);
1026         }
1027 
1028         /* Descriptor write-back.  */
1029         desc_addr = gem_get_rx_desc_addr(s, q);
1030         address_space_write(&s->dma_as, desc_addr,
1031                             MEMTXATTRS_UNSPECIFIED,
1032                             (uint8_t *)s->rx_desc[q],
1033                             sizeof(uint32_t) * gem_get_desc_len(s, true));
1034 
1035         /* Next descriptor */
1036         if (rx_desc_get_wrap(s->rx_desc[q])) {
1037             DB_PRINT("wrapping RX descriptor list\n");
1038             s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
1039         } else {
1040             DB_PRINT("incrementing RX descriptor list\n");
1041             s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
1042         }
1043 
1044         gem_get_rx_desc(s, q);
1045     }
1046 
1047     /* Count it */
1048     gem_receive_updatestats(s, buf, size);
1049 
1050     s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
1051     s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
1052 
1053     /* Handle interrupt consequences */
1054     gem_update_int_status(s);
1055 
1056     return size;
1057 }
1058 
1059 /*
1060  * gem_transmit_updatestats:
1061  * Increment transmit statistics.
1062  */
1063 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
1064                                      unsigned bytes)
1065 {
1066     uint64_t octets;
1067 
1068     /* Total octets (bytes) transmitted */
1069     octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
1070              s->regs[GEM_OCTTXHI];
1071     octets += bytes;
1072     s->regs[GEM_OCTTXLO] = octets >> 32;
1073     s->regs[GEM_OCTTXHI] = octets;
1074 
1075     /* Error-free Frames transmitted */
1076     s->regs[GEM_TXCNT]++;
1077 
1078     /* Error-free Broadcast Frames counter */
1079     if (!memcmp(packet, broadcast_addr, 6)) {
1080         s->regs[GEM_TXBCNT]++;
1081     }
1082 
1083     /* Error-free Multicast Frames counter */
1084     if (packet[0] == 0x01) {
1085         s->regs[GEM_TXMCNT]++;
1086     }
1087 
1088     if (bytes <= 64) {
1089         s->regs[GEM_TX64CNT]++;
1090     } else if (bytes <= 127) {
1091         s->regs[GEM_TX65CNT]++;
1092     } else if (bytes <= 255) {
1093         s->regs[GEM_TX128CNT]++;
1094     } else if (bytes <= 511) {
1095         s->regs[GEM_TX256CNT]++;
1096     } else if (bytes <= 1023) {
1097         s->regs[GEM_TX512CNT]++;
1098     } else if (bytes <= 1518) {
1099         s->regs[GEM_TX1024CNT]++;
1100     } else {
1101         s->regs[GEM_TX1519CNT]++;
1102     }
1103 }
1104 
1105 /*
1106  * gem_transmit:
1107  * Fish packets out of the descriptor ring and feed them to QEMU
1108  */
1109 static void gem_transmit(CadenceGEMState *s)
1110 {
1111     uint32_t desc[DESC_MAX_NUM_WORDS];
1112     hwaddr packet_desc_addr;
1113     uint8_t     tx_packet[2048];
1114     uint8_t     *p;
1115     unsigned    total_bytes;
1116     int q = 0;
1117 
1118     /* Do nothing if transmit is not enabled. */
1119     if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1120         return;
1121     }
1122 
1123     DB_PRINT("\n");
1124 
1125     /* The packet we will hand off to QEMU.
1126      * Packets scattered across multiple descriptors are gathered to this
1127      * one contiguous buffer first.
1128      */
1129     p = tx_packet;
1130     total_bytes = 0;
1131 
1132     for (q = s->num_priority_queues - 1; q >= 0; q--) {
1133         /* read current descriptor */
1134         packet_desc_addr = gem_get_tx_desc_addr(s, q);
1135 
1136         DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1137         address_space_read(&s->dma_as, packet_desc_addr,
1138                            MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
1139                            sizeof(uint32_t) * gem_get_desc_len(s, false));
1140         /* Handle all descriptors owned by hardware */
1141         while (tx_desc_get_used(desc) == 0) {
1142 
1143             /* Do nothing if transmit is not enabled. */
1144             if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1145                 return;
1146             }
1147             print_gem_tx_desc(desc, q);
1148 
1149             /* The real hardware would eat this (and possibly crash).
1150              * For QEMU let's lend a helping hand.
1151              */
1152             if ((tx_desc_get_buffer(s, desc) == 0) ||
1153                 (tx_desc_get_length(desc) == 0)) {
1154                 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
1155                          (unsigned)packet_desc_addr);
1156                 break;
1157             }
1158 
1159             if (tx_desc_get_length(desc) > sizeof(tx_packet) -
1160                                                (p - tx_packet)) {
1161                 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
1162                          "0x%x\n", (unsigned)packet_desc_addr,
1163                          (unsigned)tx_desc_get_length(desc),
1164                          sizeof(tx_packet) - (p - tx_packet));
1165                 break;
1166             }
1167 
1168             /* Gather this fragment of the packet from "dma memory" to our
1169              * contig buffer.
1170              */
1171             address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc),
1172                                MEMTXATTRS_UNSPECIFIED,
1173                                p, tx_desc_get_length(desc));
1174             p += tx_desc_get_length(desc);
1175             total_bytes += tx_desc_get_length(desc);
1176 
1177             /* Last descriptor for this packet; hand the whole thing off */
1178             if (tx_desc_get_last(desc)) {
1179                 uint32_t desc_first[DESC_MAX_NUM_WORDS];
1180                 hwaddr desc_addr = gem_get_tx_desc_addr(s, q);
1181 
1182                 /* Modify the 1st descriptor of this packet to be owned by
1183                  * the processor.
1184                  */
1185                 address_space_read(&s->dma_as, desc_addr,
1186                                    MEMTXATTRS_UNSPECIFIED,
1187                                    (uint8_t *)desc_first,
1188                                    sizeof(desc_first));
1189                 tx_desc_set_used(desc_first);
1190                 address_space_write(&s->dma_as, desc_addr,
1191                                   MEMTXATTRS_UNSPECIFIED,
1192                                   (uint8_t *)desc_first,
1193                                    sizeof(desc_first));
1194                 /* Advance the hardware current descriptor past this packet */
1195                 if (tx_desc_get_wrap(desc)) {
1196                     s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
1197                 } else {
1198                     s->tx_desc_addr[q] = packet_desc_addr +
1199                                          4 * gem_get_desc_len(s, false);
1200                 }
1201                 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
1202 
1203                 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
1204                 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
1205 
1206                 /* Update queue interrupt status */
1207                 if (s->num_priority_queues > 1) {
1208                     s->regs[GEM_INT_Q1_STATUS + q] |=
1209                             GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
1210                 }
1211 
1212                 /* Handle interrupt consequences */
1213                 gem_update_int_status(s);
1214 
1215                 /* Is checksum offload enabled? */
1216                 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
1217                     net_checksum_calculate(tx_packet, total_bytes);
1218                 }
1219 
1220                 /* Update MAC statistics */
1221                 gem_transmit_updatestats(s, tx_packet, total_bytes);
1222 
1223                 /* Send the packet somewhere */
1224                 if (s->phy_loop || (s->regs[GEM_NWCTRL] &
1225                                     GEM_NWCTRL_LOCALLOOP)) {
1226                     gem_receive(qemu_get_queue(s->nic), tx_packet,
1227                                 total_bytes);
1228                 } else {
1229                     qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
1230                                      total_bytes);
1231                 }
1232 
1233                 /* Prepare for next packet */
1234                 p = tx_packet;
1235                 total_bytes = 0;
1236             }
1237 
1238             /* read next descriptor */
1239             if (tx_desc_get_wrap(desc)) {
1240                 tx_desc_set_last(desc);
1241                 packet_desc_addr = s->regs[GEM_TXQBASE];
1242             } else {
1243                 packet_desc_addr += 4 * gem_get_desc_len(s, false);
1244             }
1245             DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1246             address_space_read(&s->dma_as, packet_desc_addr,
1247                               MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
1248                               sizeof(uint32_t) * gem_get_desc_len(s, false));
1249         }
1250 
1251         if (tx_desc_get_used(desc)) {
1252             s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
1253             s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
1254             gem_update_int_status(s);
1255         }
1256     }
1257 }
1258 
1259 static void gem_phy_reset(CadenceGEMState *s)
1260 {
1261     memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
1262     s->phy_regs[PHY_REG_CONTROL] = 0x1140;
1263     s->phy_regs[PHY_REG_STATUS] = 0x7969;
1264     s->phy_regs[PHY_REG_PHYID1] = 0x0141;
1265     s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
1266     s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
1267     s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
1268     s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
1269     s->phy_regs[PHY_REG_NEXTP] = 0x2001;
1270     s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
1271     s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
1272     s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
1273     s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
1274     s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
1275     s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
1276     s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
1277     s->phy_regs[PHY_REG_LED] = 0x4100;
1278     s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
1279     s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
1280 
1281     phy_update_link(s);
1282 }
1283 
1284 static void gem_reset(DeviceState *d)
1285 {
1286     int i;
1287     CadenceGEMState *s = CADENCE_GEM(d);
1288     const uint8_t *a;
1289     uint32_t queues_mask = 0;
1290 
1291     DB_PRINT("\n");
1292 
1293     /* Set post reset register values */
1294     memset(&s->regs[0], 0, sizeof(s->regs));
1295     s->regs[GEM_NWCFG] = 0x00080000;
1296     s->regs[GEM_NWSTATUS] = 0x00000006;
1297     s->regs[GEM_DMACFG] = 0x00020784;
1298     s->regs[GEM_IMR] = 0x07ffffff;
1299     s->regs[GEM_TXPAUSE] = 0x0000ffff;
1300     s->regs[GEM_TXPARTIALSF] = 0x000003ff;
1301     s->regs[GEM_RXPARTIALSF] = 0x000003ff;
1302     s->regs[GEM_MODID] = s->revision;
1303     s->regs[GEM_DESCONF] = 0x02500111;
1304     s->regs[GEM_DESCONF2] = 0x2ab13fff;
1305     s->regs[GEM_DESCONF5] = 0x002f2045;
1306     s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
1307 
1308     if (s->num_priority_queues > 1) {
1309         queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
1310         s->regs[GEM_DESCONF6] |= queues_mask;
1311     }
1312 
1313     /* Set MAC address */
1314     a = &s->conf.macaddr.a[0];
1315     s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1316     s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1317 
1318     for (i = 0; i < 4; i++) {
1319         s->sar_active[i] = false;
1320     }
1321 
1322     gem_phy_reset(s);
1323 
1324     gem_update_int_status(s);
1325 }
1326 
1327 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
1328 {
1329     DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
1330     return s->phy_regs[reg_num];
1331 }
1332 
1333 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
1334 {
1335     DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
1336 
1337     switch (reg_num) {
1338     case PHY_REG_CONTROL:
1339         if (val & PHY_REG_CONTROL_RST) {
1340             /* Phy reset */
1341             gem_phy_reset(s);
1342             val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
1343             s->phy_loop = 0;
1344         }
1345         if (val & PHY_REG_CONTROL_ANEG) {
1346             /* Complete autonegotiation immediately */
1347             val &= ~PHY_REG_CONTROL_ANEG;
1348             s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
1349         }
1350         if (val & PHY_REG_CONTROL_LOOP) {
1351             DB_PRINT("PHY placed in loopback\n");
1352             s->phy_loop = 1;
1353         } else {
1354             s->phy_loop = 0;
1355         }
1356         break;
1357     }
1358     s->phy_regs[reg_num] = val;
1359 }
1360 
1361 /*
1362  * gem_read32:
1363  * Read a GEM register.
1364  */
1365 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1366 {
1367     CadenceGEMState *s;
1368     uint32_t retval;
1369     s = (CadenceGEMState *)opaque;
1370 
1371     offset >>= 2;
1372     retval = s->regs[offset];
1373 
1374     DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1375 
1376     switch (offset) {
1377     case GEM_ISR:
1378         DB_PRINT("lowering irqs on ISR read\n");
1379         /* The interrupts get updated at the end of the function. */
1380         break;
1381     case GEM_PHYMNTNC:
1382         if (retval & GEM_PHYMNTNC_OP_R) {
1383             uint32_t phy_addr, reg_num;
1384 
1385             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1386             if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1387                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1388                 retval &= 0xFFFF0000;
1389                 retval |= gem_phy_read(s, reg_num);
1390             } else {
1391                 retval |= 0xFFFF; /* No device at this address */
1392             }
1393         }
1394         break;
1395     }
1396 
1397     /* Squash read to clear bits */
1398     s->regs[offset] &= ~(s->regs_rtc[offset]);
1399 
1400     /* Do not provide write only bits */
1401     retval &= ~(s->regs_wo[offset]);
1402 
1403     DB_PRINT("0x%08x\n", retval);
1404     gem_update_int_status(s);
1405     return retval;
1406 }
1407 
1408 /*
1409  * gem_write32:
1410  * Write a GEM register.
1411  */
1412 static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1413         unsigned size)
1414 {
1415     CadenceGEMState *s = (CadenceGEMState *)opaque;
1416     uint32_t readonly;
1417     int i;
1418 
1419     DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1420     offset >>= 2;
1421 
1422     /* Squash bits which are read only in write value */
1423     val &= ~(s->regs_ro[offset]);
1424     /* Preserve (only) bits which are read only and wtc in register */
1425     readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1426 
1427     /* Copy register write to backing store */
1428     s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1429 
1430     /* do w1c */
1431     s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1432 
1433     /* Handle register write side effects */
1434     switch (offset) {
1435     case GEM_NWCTRL:
1436         if (val & GEM_NWCTRL_RXENA) {
1437             for (i = 0; i < s->num_priority_queues; ++i) {
1438                 gem_get_rx_desc(s, i);
1439             }
1440         }
1441         if (val & GEM_NWCTRL_TXSTART) {
1442             gem_transmit(s);
1443         }
1444         if (!(val & GEM_NWCTRL_TXENA)) {
1445             /* Reset to start of Q when transmit disabled. */
1446             for (i = 0; i < s->num_priority_queues; i++) {
1447                 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
1448             }
1449         }
1450         if (gem_can_receive(qemu_get_queue(s->nic))) {
1451             qemu_flush_queued_packets(qemu_get_queue(s->nic));
1452         }
1453         break;
1454 
1455     case GEM_TXSTATUS:
1456         gem_update_int_status(s);
1457         break;
1458     case GEM_RXQBASE:
1459         s->rx_desc_addr[0] = val;
1460         break;
1461     case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
1462         s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
1463         break;
1464     case GEM_TXQBASE:
1465         s->tx_desc_addr[0] = val;
1466         break;
1467     case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
1468         s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
1469         break;
1470     case GEM_RXSTATUS:
1471         gem_update_int_status(s);
1472         break;
1473     case GEM_IER:
1474         s->regs[GEM_IMR] &= ~val;
1475         gem_update_int_status(s);
1476         break;
1477     case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
1478         s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
1479         gem_update_int_status(s);
1480         break;
1481     case GEM_IDR:
1482         s->regs[GEM_IMR] |= val;
1483         gem_update_int_status(s);
1484         break;
1485     case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
1486         s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
1487         gem_update_int_status(s);
1488         break;
1489     case GEM_SPADDR1LO:
1490     case GEM_SPADDR2LO:
1491     case GEM_SPADDR3LO:
1492     case GEM_SPADDR4LO:
1493         s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1494         break;
1495     case GEM_SPADDR1HI:
1496     case GEM_SPADDR2HI:
1497     case GEM_SPADDR3HI:
1498     case GEM_SPADDR4HI:
1499         s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1500         break;
1501     case GEM_PHYMNTNC:
1502         if (val & GEM_PHYMNTNC_OP_W) {
1503             uint32_t phy_addr, reg_num;
1504 
1505             phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1506             if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1507                 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1508                 gem_phy_write(s, reg_num, val);
1509             }
1510         }
1511         break;
1512     }
1513 
1514     DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1515 }
1516 
1517 static const MemoryRegionOps gem_ops = {
1518     .read = gem_read,
1519     .write = gem_write,
1520     .endianness = DEVICE_LITTLE_ENDIAN,
1521 };
1522 
1523 static void gem_set_link(NetClientState *nc)
1524 {
1525     CadenceGEMState *s = qemu_get_nic_opaque(nc);
1526 
1527     DB_PRINT("\n");
1528     phy_update_link(s);
1529     gem_update_int_status(s);
1530 }
1531 
1532 static NetClientInfo net_gem_info = {
1533     .type = NET_CLIENT_DRIVER_NIC,
1534     .size = sizeof(NICState),
1535     .can_receive = gem_can_receive,
1536     .receive = gem_receive,
1537     .link_status_changed = gem_set_link,
1538 };
1539 
1540 static void gem_realize(DeviceState *dev, Error **errp)
1541 {
1542     CadenceGEMState *s = CADENCE_GEM(dev);
1543     int i;
1544 
1545     address_space_init(&s->dma_as,
1546                        s->dma_mr ? s->dma_mr : get_system_memory(), "dma");
1547 
1548     if (s->num_priority_queues == 0 ||
1549         s->num_priority_queues > MAX_PRIORITY_QUEUES) {
1550         error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
1551                    s->num_priority_queues);
1552         return;
1553     } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
1554         error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8,
1555                    s->num_type1_screeners);
1556         return;
1557     } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
1558         error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8,
1559                    s->num_type2_screeners);
1560         return;
1561     }
1562 
1563     for (i = 0; i < s->num_priority_queues; ++i) {
1564         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1565     }
1566 
1567     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1568 
1569     s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1570                           object_get_typename(OBJECT(dev)), dev->id, s);
1571 }
1572 
1573 static void gem_init(Object *obj)
1574 {
1575     CadenceGEMState *s = CADENCE_GEM(obj);
1576     DeviceState *dev = DEVICE(obj);
1577 
1578     DB_PRINT("\n");
1579 
1580     gem_init_register_masks(s);
1581     memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1582                           "enet", sizeof(s->regs));
1583 
1584     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1585 
1586     object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
1587                              (Object **)&s->dma_mr,
1588                              qdev_prop_allow_set_link_before_realize,
1589                              OBJ_PROP_LINK_STRONG,
1590                              &error_abort);
1591 }
1592 
1593 static const VMStateDescription vmstate_cadence_gem = {
1594     .name = "cadence_gem",
1595     .version_id = 4,
1596     .minimum_version_id = 4,
1597     .fields = (VMStateField[]) {
1598         VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1599         VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
1600         VMSTATE_UINT8(phy_loop, CadenceGEMState),
1601         VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
1602                              MAX_PRIORITY_QUEUES),
1603         VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
1604                              MAX_PRIORITY_QUEUES),
1605         VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1606         VMSTATE_END_OF_LIST(),
1607     }
1608 };
1609 
1610 static Property gem_properties[] = {
1611     DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1612     DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
1613                        GEM_MODID_VALUE),
1614     DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1615                       num_priority_queues, 1),
1616     DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
1617                       num_type1_screeners, 4),
1618     DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
1619                       num_type2_screeners, 4),
1620     DEFINE_PROP_END_OF_LIST(),
1621 };
1622 
1623 static void gem_class_init(ObjectClass *klass, void *data)
1624 {
1625     DeviceClass *dc = DEVICE_CLASS(klass);
1626 
1627     dc->realize = gem_realize;
1628     dc->props = gem_properties;
1629     dc->vmsd = &vmstate_cadence_gem;
1630     dc->reset = gem_reset;
1631 }
1632 
1633 static const TypeInfo gem_info = {
1634     .name  = TYPE_CADENCE_GEM,
1635     .parent = TYPE_SYS_BUS_DEVICE,
1636     .instance_size  = sizeof(CadenceGEMState),
1637     .instance_init = gem_init,
1638     .class_init = gem_class_init,
1639 };
1640 
1641 static void gem_register_types(void)
1642 {
1643     type_register_static(&gem_info);
1644 }
1645 
1646 type_init(gem_register_types)
1647