1 /* 2 * QEMU Xilinx GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include <zlib.h> /* For crc32 */ 26 27 #include "hw/sysbus.h" 28 #include "net/net.h" 29 #include "net/checksum.h" 30 31 #ifdef CADENCE_GEM_ERR_DEBUG 32 #define DB_PRINT(...) do { \ 33 fprintf(stderr, ": %s: ", __func__); \ 34 fprintf(stderr, ## __VA_ARGS__); \ 35 } while (0); 36 #else 37 #define DB_PRINT(...) 38 #endif 39 40 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 41 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 42 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 43 #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 44 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 45 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 46 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 47 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 48 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 49 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 50 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 51 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 52 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 53 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintaince reg */ 54 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 55 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 56 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 57 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 58 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 59 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 60 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 61 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 62 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 63 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 64 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 65 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 66 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 67 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 68 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 69 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 70 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 71 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 72 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 73 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 74 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 75 #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 76 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 77 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 78 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 79 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 80 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 81 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 82 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 83 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 84 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 85 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 86 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 87 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 88 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 89 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 90 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 91 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 92 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 93 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 94 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 95 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 96 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 97 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 98 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 99 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 100 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 101 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 102 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 103 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 104 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 105 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 106 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 107 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 108 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 109 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 110 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 111 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 112 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 113 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 114 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 115 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 116 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 117 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 118 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 119 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 120 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 121 122 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 123 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 124 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 125 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 126 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 127 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 128 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 129 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 130 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 131 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 132 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 133 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 134 135 /* Design Configuration Registers */ 136 #define GEM_DESCONF (0x00000280/4) 137 #define GEM_DESCONF2 (0x00000284/4) 138 #define GEM_DESCONF3 (0x00000288/4) 139 #define GEM_DESCONF4 (0x0000028C/4) 140 #define GEM_DESCONF5 (0x00000290/4) 141 #define GEM_DESCONF6 (0x00000294/4) 142 #define GEM_DESCONF7 (0x00000298/4) 143 144 #define GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ 145 146 /*****************************************/ 147 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 148 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 149 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 150 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 151 152 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 153 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with lenth err */ 154 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 155 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 156 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 157 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 158 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 159 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 160 161 #define GEM_DMACFG_RBUFSZ_M 0x007F0000 /* DMA RX Buffer Size mask */ 162 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 163 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 164 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 165 166 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 167 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 168 169 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 170 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 171 172 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 173 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 174 #define GEM_INT_TXUSED 0x00000008 175 #define GEM_INT_RXUSED 0x00000004 176 #define GEM_INT_RXCMPL 0x00000002 177 178 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 179 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 180 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 181 #define GEM_PHYMNTNC_ADDR_SHFT 23 182 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 183 #define GEM_PHYMNTNC_REG_SHIFT 18 184 185 /* Marvell PHY definitions */ 186 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 187 188 #define PHY_REG_CONTROL 0 189 #define PHY_REG_STATUS 1 190 #define PHY_REG_PHYID1 2 191 #define PHY_REG_PHYID2 3 192 #define PHY_REG_ANEGADV 4 193 #define PHY_REG_LINKPABIL 5 194 #define PHY_REG_ANEGEXP 6 195 #define PHY_REG_NEXTP 7 196 #define PHY_REG_LINKPNEXTP 8 197 #define PHY_REG_100BTCTRL 9 198 #define PHY_REG_1000BTSTAT 10 199 #define PHY_REG_EXTSTAT 15 200 #define PHY_REG_PHYSPCFC_CTL 16 201 #define PHY_REG_PHYSPCFC_ST 17 202 #define PHY_REG_INT_EN 18 203 #define PHY_REG_INT_ST 19 204 #define PHY_REG_EXT_PHYSPCFC_CTL 20 205 #define PHY_REG_RXERR 21 206 #define PHY_REG_EACD 22 207 #define PHY_REG_LED 24 208 #define PHY_REG_LED_OVRD 25 209 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 210 #define PHY_REG_EXT_PHYSPCFC_ST 27 211 #define PHY_REG_CABLE_DIAG 28 212 213 #define PHY_REG_CONTROL_RST 0x8000 214 #define PHY_REG_CONTROL_LOOP 0x4000 215 #define PHY_REG_CONTROL_ANEG 0x1000 216 217 #define PHY_REG_STATUS_LINK 0x0004 218 #define PHY_REG_STATUS_ANEGCMPL 0x0020 219 220 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 221 #define PHY_REG_INT_ST_LINKC 0x0400 222 #define PHY_REG_INT_ST_ENERGY 0x0010 223 224 /***********************************************************************/ 225 #define GEM_RX_REJECT 1 226 #define GEM_RX_ACCEPT 0 227 228 /***********************************************************************/ 229 230 #define DESC_1_USED 0x80000000 231 #define DESC_1_LENGTH 0x00001FFF 232 233 #define DESC_1_TX_WRAP 0x40000000 234 #define DESC_1_TX_LAST 0x00008000 235 236 #define DESC_0_RX_WRAP 0x00000002 237 #define DESC_0_RX_OWNERSHIP 0x00000001 238 239 #define DESC_1_RX_SOF 0x00004000 240 #define DESC_1_RX_EOF 0x00008000 241 242 static inline unsigned tx_desc_get_buffer(unsigned *desc) 243 { 244 return desc[0]; 245 } 246 247 static inline unsigned tx_desc_get_used(unsigned *desc) 248 { 249 return (desc[1] & DESC_1_USED) ? 1 : 0; 250 } 251 252 static inline void tx_desc_set_used(unsigned *desc) 253 { 254 desc[1] |= DESC_1_USED; 255 } 256 257 static inline unsigned tx_desc_get_wrap(unsigned *desc) 258 { 259 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 260 } 261 262 static inline unsigned tx_desc_get_last(unsigned *desc) 263 { 264 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 265 } 266 267 static inline unsigned tx_desc_get_length(unsigned *desc) 268 { 269 return desc[1] & DESC_1_LENGTH; 270 } 271 272 static inline void print_gem_tx_desc(unsigned *desc) 273 { 274 DB_PRINT("TXDESC:\n"); 275 DB_PRINT("bufaddr: 0x%08x\n", *desc); 276 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 277 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 278 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 279 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 280 } 281 282 static inline unsigned rx_desc_get_buffer(unsigned *desc) 283 { 284 return desc[0] & ~0x3UL; 285 } 286 287 static inline unsigned rx_desc_get_wrap(unsigned *desc) 288 { 289 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 290 } 291 292 static inline unsigned rx_desc_get_ownership(unsigned *desc) 293 { 294 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 295 } 296 297 static inline void rx_desc_set_ownership(unsigned *desc) 298 { 299 desc[0] |= DESC_0_RX_OWNERSHIP; 300 } 301 302 static inline void rx_desc_set_sof(unsigned *desc) 303 { 304 desc[1] |= DESC_1_RX_SOF; 305 } 306 307 static inline void rx_desc_set_eof(unsigned *desc) 308 { 309 desc[1] |= DESC_1_RX_EOF; 310 } 311 312 static inline void rx_desc_set_length(unsigned *desc, unsigned len) 313 { 314 desc[1] &= ~DESC_1_LENGTH; 315 desc[1] |= len; 316 } 317 318 #define TYPE_CADENCE_GEM "cadence_gem" 319 #define GEM(obj) OBJECT_CHECK(GemState, (obj), TYPE_CADENCE_GEM) 320 321 typedef struct GemState { 322 SysBusDevice parent_obj; 323 324 MemoryRegion iomem; 325 NICState *nic; 326 NICConf conf; 327 qemu_irq irq; 328 329 /* GEM registers backing store */ 330 uint32_t regs[GEM_MAXREG]; 331 /* Mask of register bits which are write only */ 332 uint32_t regs_wo[GEM_MAXREG]; 333 /* Mask of register bits which are read only */ 334 uint32_t regs_ro[GEM_MAXREG]; 335 /* Mask of register bits which are clear on read */ 336 uint32_t regs_rtc[GEM_MAXREG]; 337 /* Mask of register bits which are write 1 to clear */ 338 uint32_t regs_w1c[GEM_MAXREG]; 339 340 /* PHY registers backing store */ 341 uint16_t phy_regs[32]; 342 343 uint8_t phy_loop; /* Are we in phy loopback? */ 344 345 /* The current DMA descriptor pointers */ 346 uint32_t rx_desc_addr; 347 uint32_t tx_desc_addr; 348 349 } GemState; 350 351 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 352 const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 353 354 /* 355 * gem_init_register_masks: 356 * One time initialization. 357 * Set masks to identify which register bits have magical clear properties 358 */ 359 static void gem_init_register_masks(GemState *s) 360 { 361 /* Mask of register bits which are read only*/ 362 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 363 s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 364 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 365 s->regs_ro[GEM_DMACFG] = 0xFE00F000; 366 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 367 s->regs_ro[GEM_RXQBASE] = 0x00000003; 368 s->regs_ro[GEM_TXQBASE] = 0x00000003; 369 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 370 s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 371 s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 372 s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 373 374 /* Mask of register bits which are clear on read */ 375 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 376 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 377 378 /* Mask of register bits which are write 1 to clear */ 379 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 380 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 381 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 382 383 /* Mask of register bits which are write only */ 384 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 385 s->regs_wo[GEM_NWCTRL] = 0x00073E60; 386 s->regs_wo[GEM_IER] = 0x07FFFFFF; 387 s->regs_wo[GEM_IDR] = 0x07FFFFFF; 388 } 389 390 /* 391 * phy_update_link: 392 * Make the emulated PHY link state match the QEMU "interface" state. 393 */ 394 static void phy_update_link(GemState *s) 395 { 396 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 397 398 /* Autonegotiation status mirrors link status. */ 399 if (qemu_get_queue(s->nic)->link_down) { 400 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 401 PHY_REG_STATUS_LINK); 402 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 403 } else { 404 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 405 PHY_REG_STATUS_LINK); 406 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 407 PHY_REG_INT_ST_ANEGCMPL | 408 PHY_REG_INT_ST_ENERGY); 409 } 410 } 411 412 static int gem_can_receive(NetClientState *nc) 413 { 414 GemState *s; 415 416 s = qemu_get_nic_opaque(nc); 417 418 DB_PRINT("\n"); 419 420 /* Do nothing if receive is not enabled. */ 421 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 422 return 0; 423 } 424 425 return 1; 426 } 427 428 /* 429 * gem_update_int_status: 430 * Raise or lower interrupt based on current status. 431 */ 432 static void gem_update_int_status(GemState *s) 433 { 434 if (s->regs[GEM_ISR]) { 435 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]); 436 qemu_set_irq(s->irq, 1); 437 } 438 } 439 440 /* 441 * gem_receive_updatestats: 442 * Increment receive statistics. 443 */ 444 static void gem_receive_updatestats(GemState *s, const uint8_t *packet, 445 unsigned bytes) 446 { 447 uint64_t octets; 448 449 /* Total octets (bytes) received */ 450 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 451 s->regs[GEM_OCTRXHI]; 452 octets += bytes; 453 s->regs[GEM_OCTRXLO] = octets >> 32; 454 s->regs[GEM_OCTRXHI] = octets; 455 456 /* Error-free Frames received */ 457 s->regs[GEM_RXCNT]++; 458 459 /* Error-free Broadcast Frames counter */ 460 if (!memcmp(packet, broadcast_addr, 6)) { 461 s->regs[GEM_RXBROADCNT]++; 462 } 463 464 /* Error-free Multicast Frames counter */ 465 if (packet[0] == 0x01) { 466 s->regs[GEM_RXMULTICNT]++; 467 } 468 469 if (bytes <= 64) { 470 s->regs[GEM_RX64CNT]++; 471 } else if (bytes <= 127) { 472 s->regs[GEM_RX65CNT]++; 473 } else if (bytes <= 255) { 474 s->regs[GEM_RX128CNT]++; 475 } else if (bytes <= 511) { 476 s->regs[GEM_RX256CNT]++; 477 } else if (bytes <= 1023) { 478 s->regs[GEM_RX512CNT]++; 479 } else if (bytes <= 1518) { 480 s->regs[GEM_RX1024CNT]++; 481 } else { 482 s->regs[GEM_RX1519CNT]++; 483 } 484 } 485 486 /* 487 * Get the MAC Address bit from the specified position 488 */ 489 static unsigned get_bit(const uint8_t *mac, unsigned bit) 490 { 491 unsigned byte; 492 493 byte = mac[bit / 8]; 494 byte >>= (bit & 0x7); 495 byte &= 1; 496 497 return byte; 498 } 499 500 /* 501 * Calculate a GEM MAC Address hash index 502 */ 503 static unsigned calc_mac_hash(const uint8_t *mac) 504 { 505 int index_bit, mac_bit; 506 unsigned hash_index; 507 508 hash_index = 0; 509 mac_bit = 5; 510 for (index_bit = 5; index_bit >= 0; index_bit--) { 511 hash_index |= (get_bit(mac, mac_bit) ^ 512 get_bit(mac, mac_bit + 6) ^ 513 get_bit(mac, mac_bit + 12) ^ 514 get_bit(mac, mac_bit + 18) ^ 515 get_bit(mac, mac_bit + 24) ^ 516 get_bit(mac, mac_bit + 30) ^ 517 get_bit(mac, mac_bit + 36) ^ 518 get_bit(mac, mac_bit + 42)) << index_bit; 519 mac_bit--; 520 } 521 522 return hash_index; 523 } 524 525 /* 526 * gem_mac_address_filter: 527 * Accept or reject this destination address? 528 * Returns: 529 * GEM_RX_REJECT: reject 530 * GEM_RX_ACCEPT: accept 531 */ 532 static int gem_mac_address_filter(GemState *s, const uint8_t *packet) 533 { 534 uint8_t *gem_spaddr; 535 int i; 536 537 /* Promiscuous mode? */ 538 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 539 return GEM_RX_ACCEPT; 540 } 541 542 if (!memcmp(packet, broadcast_addr, 6)) { 543 /* Reject broadcast packets? */ 544 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 545 return GEM_RX_REJECT; 546 } 547 return GEM_RX_ACCEPT; 548 } 549 550 /* Accept packets -w- hash match? */ 551 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 552 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 553 unsigned hash_index; 554 555 hash_index = calc_mac_hash(packet); 556 if (hash_index < 32) { 557 if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 558 return GEM_RX_ACCEPT; 559 } 560 } else { 561 hash_index -= 32; 562 if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 563 return GEM_RX_ACCEPT; 564 } 565 } 566 } 567 568 /* Check all 4 specific addresses */ 569 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 570 for (i = 0; i < 4; i++) { 571 if (!memcmp(packet, gem_spaddr, 6)) { 572 return GEM_RX_ACCEPT; 573 } 574 575 gem_spaddr += 8; 576 } 577 578 /* No address match; reject the packet */ 579 return GEM_RX_REJECT; 580 } 581 582 /* 583 * gem_receive: 584 * Fit a packet handed to us by QEMU into the receive descriptor ring. 585 */ 586 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 587 { 588 unsigned desc[2]; 589 hwaddr packet_desc_addr, last_desc_addr; 590 GemState *s; 591 unsigned rxbufsize, bytes_to_copy; 592 unsigned rxbuf_offset; 593 uint8_t rxbuf[2048]; 594 uint8_t *rxbuf_ptr; 595 596 s = qemu_get_nic_opaque(nc); 597 598 /* Do nothing if receive is not enabled. */ 599 if (!gem_can_receive(nc)) { 600 return -1; 601 } 602 603 /* Is this destination MAC address "for us" ? */ 604 if (gem_mac_address_filter(s, buf) == GEM_RX_REJECT) { 605 return -1; 606 } 607 608 /* Discard packets with receive length error enabled ? */ 609 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 610 unsigned type_len; 611 612 /* Fish the ethertype / length field out of the RX packet */ 613 type_len = buf[12] << 8 | buf[13]; 614 /* It is a length field, not an ethertype */ 615 if (type_len < 0x600) { 616 if (size < type_len) { 617 /* discard */ 618 return -1; 619 } 620 } 621 } 622 623 /* 624 * Determine configured receive buffer offset (probably 0) 625 */ 626 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 627 GEM_NWCFG_BUFF_OFST_S; 628 629 /* The configure size of each receive buffer. Determines how many 630 * buffers needed to hold this packet. 631 */ 632 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 633 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 634 bytes_to_copy = size; 635 636 /* Strip of FCS field ? (usually yes) */ 637 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 638 rxbuf_ptr = (void *)buf; 639 } else { 640 unsigned crc_val; 641 int crc_offset; 642 643 /* The application wants the FCS field, which QEMU does not provide. 644 * We must try and caclculate one. 645 */ 646 647 memcpy(rxbuf, buf, size); 648 memset(rxbuf + size, 0, sizeof(rxbuf) - size); 649 rxbuf_ptr = rxbuf; 650 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 651 if (size < 60) { 652 crc_offset = 60; 653 } else { 654 crc_offset = size; 655 } 656 memcpy(rxbuf + crc_offset, &crc_val, sizeof(crc_val)); 657 658 bytes_to_copy += 4; 659 size += 4; 660 } 661 662 /* Pad to minimum length */ 663 if (size < 64) { 664 size = 64; 665 } 666 667 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 668 669 packet_desc_addr = s->rx_desc_addr; 670 while (1) { 671 DB_PRINT("read descriptor 0x%x\n", (unsigned)packet_desc_addr); 672 /* read current descriptor */ 673 cpu_physical_memory_read(packet_desc_addr, 674 (uint8_t *)&desc[0], sizeof(desc)); 675 676 /* Descriptor owned by software ? */ 677 if (rx_desc_get_ownership(desc) == 1) { 678 DB_PRINT("descriptor 0x%x owned by sw.\n", 679 (unsigned)packet_desc_addr); 680 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 681 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 682 /* Handle interrupt consequences */ 683 gem_update_int_status(s); 684 return -1; 685 } 686 687 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 688 rx_desc_get_buffer(desc)); 689 690 /* 691 * Let's have QEMU lend a helping hand. 692 */ 693 if (rx_desc_get_buffer(desc) == 0) { 694 DB_PRINT("Invalid RX buffer (NULL) for descriptor 0x%x\n", 695 (unsigned)packet_desc_addr); 696 break; 697 } 698 699 /* Copy packet data to emulated DMA buffer */ 700 cpu_physical_memory_write(rx_desc_get_buffer(desc) + rxbuf_offset, 701 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 702 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 703 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 704 if (bytes_to_copy == 0) { 705 break; 706 } 707 708 /* Next descriptor */ 709 if (rx_desc_get_wrap(desc)) { 710 packet_desc_addr = s->regs[GEM_RXQBASE]; 711 } else { 712 packet_desc_addr += 8; 713 } 714 } 715 716 DB_PRINT("set length: %ld, EOF on descriptor 0x%x\n", size, 717 (unsigned)packet_desc_addr); 718 719 /* Update last descriptor with EOF and total length */ 720 rx_desc_set_eof(desc); 721 rx_desc_set_length(desc, size); 722 cpu_physical_memory_write(packet_desc_addr, 723 (uint8_t *)&desc[0], sizeof(desc)); 724 725 /* Advance RX packet descriptor Q */ 726 last_desc_addr = packet_desc_addr; 727 packet_desc_addr = s->rx_desc_addr; 728 s->rx_desc_addr = last_desc_addr; 729 if (rx_desc_get_wrap(desc)) { 730 s->rx_desc_addr = s->regs[GEM_RXQBASE]; 731 DB_PRINT("wrapping RX descriptor list\n"); 732 } else { 733 DB_PRINT("incrementing RX descriptor list\n"); 734 s->rx_desc_addr += 8; 735 } 736 737 DB_PRINT("set SOF, OWN on descriptor 0x%08x\n", (unsigned)packet_desc_addr); 738 739 /* Count it */ 740 gem_receive_updatestats(s, buf, size); 741 742 /* Update first descriptor (which could also be the last) */ 743 /* read descriptor */ 744 cpu_physical_memory_read(packet_desc_addr, 745 (uint8_t *)&desc[0], sizeof(desc)); 746 rx_desc_set_sof(desc); 747 rx_desc_set_ownership(desc); 748 cpu_physical_memory_write(packet_desc_addr, 749 (uint8_t *)&desc[0], sizeof(desc)); 750 751 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 752 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 753 754 /* Handle interrupt consequences */ 755 gem_update_int_status(s); 756 757 return size; 758 } 759 760 /* 761 * gem_transmit_updatestats: 762 * Increment transmit statistics. 763 */ 764 static void gem_transmit_updatestats(GemState *s, const uint8_t *packet, 765 unsigned bytes) 766 { 767 uint64_t octets; 768 769 /* Total octets (bytes) transmitted */ 770 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 771 s->regs[GEM_OCTTXHI]; 772 octets += bytes; 773 s->regs[GEM_OCTTXLO] = octets >> 32; 774 s->regs[GEM_OCTTXHI] = octets; 775 776 /* Error-free Frames transmitted */ 777 s->regs[GEM_TXCNT]++; 778 779 /* Error-free Broadcast Frames counter */ 780 if (!memcmp(packet, broadcast_addr, 6)) { 781 s->regs[GEM_TXBCNT]++; 782 } 783 784 /* Error-free Multicast Frames counter */ 785 if (packet[0] == 0x01) { 786 s->regs[GEM_TXMCNT]++; 787 } 788 789 if (bytes <= 64) { 790 s->regs[GEM_TX64CNT]++; 791 } else if (bytes <= 127) { 792 s->regs[GEM_TX65CNT]++; 793 } else if (bytes <= 255) { 794 s->regs[GEM_TX128CNT]++; 795 } else if (bytes <= 511) { 796 s->regs[GEM_TX256CNT]++; 797 } else if (bytes <= 1023) { 798 s->regs[GEM_TX512CNT]++; 799 } else if (bytes <= 1518) { 800 s->regs[GEM_TX1024CNT]++; 801 } else { 802 s->regs[GEM_TX1519CNT]++; 803 } 804 } 805 806 /* 807 * gem_transmit: 808 * Fish packets out of the descriptor ring and feed them to QEMU 809 */ 810 static void gem_transmit(GemState *s) 811 { 812 unsigned desc[2]; 813 hwaddr packet_desc_addr; 814 uint8_t tx_packet[2048]; 815 uint8_t *p; 816 unsigned total_bytes; 817 818 /* Do nothing if transmit is not enabled. */ 819 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 820 return; 821 } 822 823 DB_PRINT("\n"); 824 825 /* The packet we will hand off to qemu. 826 * Packets scattered across multiple descriptors are gathered to this 827 * one contiguous buffer first. 828 */ 829 p = tx_packet; 830 total_bytes = 0; 831 832 /* read current descriptor */ 833 packet_desc_addr = s->tx_desc_addr; 834 cpu_physical_memory_read(packet_desc_addr, 835 (uint8_t *)&desc[0], sizeof(desc)); 836 /* Handle all descriptors owned by hardware */ 837 while (tx_desc_get_used(desc) == 0) { 838 839 /* Do nothing if transmit is not enabled. */ 840 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 841 return; 842 } 843 print_gem_tx_desc(desc); 844 845 /* The real hardware would eat this (and possibly crash). 846 * For QEMU let's lend a helping hand. 847 */ 848 if ((tx_desc_get_buffer(desc) == 0) || 849 (tx_desc_get_length(desc) == 0)) { 850 DB_PRINT("Invalid TX descriptor @ 0x%x\n", 851 (unsigned)packet_desc_addr); 852 break; 853 } 854 855 /* Gather this fragment of the packet from "dma memory" to our contig. 856 * buffer. 857 */ 858 cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 859 tx_desc_get_length(desc)); 860 p += tx_desc_get_length(desc); 861 total_bytes += tx_desc_get_length(desc); 862 863 /* Last descriptor for this packet; hand the whole thing off */ 864 if (tx_desc_get_last(desc)) { 865 /* Modify the 1st descriptor of this packet to be owned by 866 * the processor. 867 */ 868 cpu_physical_memory_read(s->tx_desc_addr, 869 (uint8_t *)&desc[0], sizeof(desc)); 870 tx_desc_set_used(desc); 871 cpu_physical_memory_write(s->tx_desc_addr, 872 (uint8_t *)&desc[0], sizeof(desc)); 873 /* Advance the hardare current descriptor past this packet */ 874 if (tx_desc_get_wrap(desc)) { 875 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 876 } else { 877 s->tx_desc_addr = packet_desc_addr + 8; 878 } 879 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr); 880 881 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 882 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 883 884 /* Handle interrupt consequences */ 885 gem_update_int_status(s); 886 887 /* Is checksum offload enabled? */ 888 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 889 net_checksum_calculate(tx_packet, total_bytes); 890 } 891 892 /* Update MAC statistics */ 893 gem_transmit_updatestats(s, tx_packet, total_bytes); 894 895 /* Send the packet somewhere */ 896 if (s->phy_loop) { 897 gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes); 898 } else { 899 qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 900 total_bytes); 901 } 902 903 /* Prepare for next packet */ 904 p = tx_packet; 905 total_bytes = 0; 906 } 907 908 /* read next descriptor */ 909 if (tx_desc_get_wrap(desc)) { 910 packet_desc_addr = s->regs[GEM_TXQBASE]; 911 } else { 912 packet_desc_addr += 8; 913 } 914 cpu_physical_memory_read(packet_desc_addr, 915 (uint8_t *)&desc[0], sizeof(desc)); 916 } 917 918 if (tx_desc_get_used(desc)) { 919 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 920 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 921 gem_update_int_status(s); 922 } 923 } 924 925 static void gem_phy_reset(GemState *s) 926 { 927 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 928 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 929 s->phy_regs[PHY_REG_STATUS] = 0x7969; 930 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 931 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 932 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 933 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 934 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 935 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 936 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 937 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 938 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 939 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 940 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 941 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00; 942 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 943 s->phy_regs[PHY_REG_LED] = 0x4100; 944 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 945 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 946 947 phy_update_link(s); 948 } 949 950 static void gem_reset(DeviceState *d) 951 { 952 GemState *s = GEM(d); 953 954 DB_PRINT("\n"); 955 956 /* Set post reset register values */ 957 memset(&s->regs[0], 0, sizeof(s->regs)); 958 s->regs[GEM_NWCFG] = 0x00080000; 959 s->regs[GEM_NWSTATUS] = 0x00000006; 960 s->regs[GEM_DMACFG] = 0x00020784; 961 s->regs[GEM_IMR] = 0x07ffffff; 962 s->regs[GEM_TXPAUSE] = 0x0000ffff; 963 s->regs[GEM_TXPARTIALSF] = 0x000003ff; 964 s->regs[GEM_RXPARTIALSF] = 0x000003ff; 965 s->regs[GEM_MODID] = 0x00020118; 966 s->regs[GEM_DESCONF] = 0x02500111; 967 s->regs[GEM_DESCONF2] = 0x2ab13fff; 968 s->regs[GEM_DESCONF5] = 0x002f2145; 969 s->regs[GEM_DESCONF6] = 0x00000200; 970 971 gem_phy_reset(s); 972 973 gem_update_int_status(s); 974 } 975 976 static uint16_t gem_phy_read(GemState *s, unsigned reg_num) 977 { 978 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 979 return s->phy_regs[reg_num]; 980 } 981 982 static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val) 983 { 984 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 985 986 switch (reg_num) { 987 case PHY_REG_CONTROL: 988 if (val & PHY_REG_CONTROL_RST) { 989 /* Phy reset */ 990 gem_phy_reset(s); 991 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 992 s->phy_loop = 0; 993 } 994 if (val & PHY_REG_CONTROL_ANEG) { 995 /* Complete autonegotiation immediately */ 996 val &= ~PHY_REG_CONTROL_ANEG; 997 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 998 } 999 if (val & PHY_REG_CONTROL_LOOP) { 1000 DB_PRINT("PHY placed in loopback\n"); 1001 s->phy_loop = 1; 1002 } else { 1003 s->phy_loop = 0; 1004 } 1005 break; 1006 } 1007 s->phy_regs[reg_num] = val; 1008 } 1009 1010 /* 1011 * gem_read32: 1012 * Read a GEM register. 1013 */ 1014 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1015 { 1016 GemState *s; 1017 uint32_t retval; 1018 1019 s = (GemState *)opaque; 1020 1021 offset >>= 2; 1022 retval = s->regs[offset]; 1023 1024 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1025 1026 switch (offset) { 1027 case GEM_ISR: 1028 DB_PRINT("lowering irq on ISR read\n"); 1029 qemu_set_irq(s->irq, 0); 1030 break; 1031 case GEM_PHYMNTNC: 1032 if (retval & GEM_PHYMNTNC_OP_R) { 1033 uint32_t phy_addr, reg_num; 1034 1035 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1036 if (phy_addr == BOARD_PHY_ADDRESS) { 1037 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1038 retval &= 0xFFFF0000; 1039 retval |= gem_phy_read(s, reg_num); 1040 } else { 1041 retval |= 0xFFFF; /* No device at this address */ 1042 } 1043 } 1044 break; 1045 } 1046 1047 /* Squash read to clear bits */ 1048 s->regs[offset] &= ~(s->regs_rtc[offset]); 1049 1050 /* Do not provide write only bits */ 1051 retval &= ~(s->regs_wo[offset]); 1052 1053 DB_PRINT("0x%08x\n", retval); 1054 return retval; 1055 } 1056 1057 /* 1058 * gem_write32: 1059 * Write a GEM register. 1060 */ 1061 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1062 unsigned size) 1063 { 1064 GemState *s = (GemState *)opaque; 1065 uint32_t readonly; 1066 1067 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1068 offset >>= 2; 1069 1070 /* Squash bits which are read only in write value */ 1071 val &= ~(s->regs_ro[offset]); 1072 /* Preserve (only) bits which are read only in register */ 1073 readonly = s->regs[offset]; 1074 readonly &= s->regs_ro[offset]; 1075 1076 /* Squash bits which are write 1 to clear */ 1077 val &= ~(s->regs_w1c[offset] & val); 1078 1079 /* Copy register write to backing store */ 1080 s->regs[offset] = val | readonly; 1081 1082 /* Handle register write side effects */ 1083 switch (offset) { 1084 case GEM_NWCTRL: 1085 if (val & GEM_NWCTRL_TXSTART) { 1086 gem_transmit(s); 1087 } 1088 if (!(val & GEM_NWCTRL_TXENA)) { 1089 /* Reset to start of Q when transmit disabled. */ 1090 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 1091 } 1092 if (val & GEM_NWCTRL_RXENA) { 1093 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1094 } 1095 break; 1096 1097 case GEM_TXSTATUS: 1098 gem_update_int_status(s); 1099 break; 1100 case GEM_RXQBASE: 1101 s->rx_desc_addr = val; 1102 break; 1103 case GEM_TXQBASE: 1104 s->tx_desc_addr = val; 1105 break; 1106 case GEM_RXSTATUS: 1107 gem_update_int_status(s); 1108 break; 1109 case GEM_IER: 1110 s->regs[GEM_IMR] &= ~val; 1111 gem_update_int_status(s); 1112 break; 1113 case GEM_IDR: 1114 s->regs[GEM_IMR] |= val; 1115 gem_update_int_status(s); 1116 break; 1117 case GEM_PHYMNTNC: 1118 if (val & GEM_PHYMNTNC_OP_W) { 1119 uint32_t phy_addr, reg_num; 1120 1121 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1122 if (phy_addr == BOARD_PHY_ADDRESS) { 1123 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1124 gem_phy_write(s, reg_num, val); 1125 } 1126 } 1127 break; 1128 } 1129 1130 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1131 } 1132 1133 static const MemoryRegionOps gem_ops = { 1134 .read = gem_read, 1135 .write = gem_write, 1136 .endianness = DEVICE_LITTLE_ENDIAN, 1137 }; 1138 1139 static void gem_cleanup(NetClientState *nc) 1140 { 1141 GemState *s = qemu_get_nic_opaque(nc); 1142 1143 DB_PRINT("\n"); 1144 s->nic = NULL; 1145 } 1146 1147 static void gem_set_link(NetClientState *nc) 1148 { 1149 DB_PRINT("\n"); 1150 phy_update_link(qemu_get_nic_opaque(nc)); 1151 } 1152 1153 static NetClientInfo net_gem_info = { 1154 .type = NET_CLIENT_OPTIONS_KIND_NIC, 1155 .size = sizeof(NICState), 1156 .can_receive = gem_can_receive, 1157 .receive = gem_receive, 1158 .cleanup = gem_cleanup, 1159 .link_status_changed = gem_set_link, 1160 }; 1161 1162 static int gem_init(SysBusDevice *sbd) 1163 { 1164 DeviceState *dev = DEVICE(sbd); 1165 GemState *s = GEM(dev); 1166 1167 DB_PRINT("\n"); 1168 1169 gem_init_register_masks(s); 1170 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1171 "enet", sizeof(s->regs)); 1172 sysbus_init_mmio(sbd, &s->iomem); 1173 sysbus_init_irq(sbd, &s->irq); 1174 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1175 1176 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1177 object_get_typename(OBJECT(dev)), dev->id, s); 1178 1179 return 0; 1180 } 1181 1182 static const VMStateDescription vmstate_cadence_gem = { 1183 .name = "cadence_gem", 1184 .version_id = 1, 1185 .minimum_version_id = 1, 1186 .minimum_version_id_old = 1, 1187 .fields = (VMStateField[]) { 1188 VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG), 1189 VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32), 1190 VMSTATE_UINT8(phy_loop, GemState), 1191 VMSTATE_UINT32(rx_desc_addr, GemState), 1192 VMSTATE_UINT32(tx_desc_addr, GemState), 1193 } 1194 }; 1195 1196 static Property gem_properties[] = { 1197 DEFINE_NIC_PROPERTIES(GemState, conf), 1198 DEFINE_PROP_END_OF_LIST(), 1199 }; 1200 1201 static void gem_class_init(ObjectClass *klass, void *data) 1202 { 1203 DeviceClass *dc = DEVICE_CLASS(klass); 1204 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1205 1206 sdc->init = gem_init; 1207 dc->props = gem_properties; 1208 dc->vmsd = &vmstate_cadence_gem; 1209 dc->reset = gem_reset; 1210 } 1211 1212 static const TypeInfo gem_info = { 1213 .name = TYPE_CADENCE_GEM, 1214 .parent = TYPE_SYS_BUS_DEVICE, 1215 .instance_size = sizeof(GemState), 1216 .class_init = gem_class_init, 1217 }; 1218 1219 static void gem_register_types(void) 1220 { 1221 type_register_static(&gem_info); 1222 } 1223 1224 type_init(gem_register_types) 1225