1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/net/cadence_gem.h" 29 #include "net/checksum.h" 30 31 #ifdef CADENCE_GEM_ERR_DEBUG 32 #define DB_PRINT(...) do { \ 33 fprintf(stderr, ": %s: ", __func__); \ 34 fprintf(stderr, ## __VA_ARGS__); \ 35 } while (0); 36 #else 37 #define DB_PRINT(...) 38 #endif 39 40 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 41 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 42 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 43 #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 44 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 45 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 46 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 47 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 48 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 49 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 50 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 51 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 52 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 53 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 54 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 55 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 56 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 57 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 58 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 59 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 60 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 61 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 62 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 63 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 64 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 65 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 66 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 67 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 68 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 69 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 70 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 71 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 72 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 73 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 74 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 75 #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 76 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 77 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 78 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 79 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 80 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 81 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 82 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 83 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 84 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 85 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 86 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 87 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 88 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 89 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 90 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 91 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 92 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 93 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 94 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 95 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 96 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 97 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 98 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 99 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 100 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 101 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 102 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 103 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 104 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 105 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 106 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 107 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 108 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 109 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 110 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 111 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 112 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 113 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 114 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 115 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 116 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 117 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 118 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 119 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 120 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 121 122 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 123 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 124 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 125 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 126 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 127 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 128 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 129 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 130 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 131 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 132 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 133 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 134 135 /* Design Configuration Registers */ 136 #define GEM_DESCONF (0x00000280/4) 137 #define GEM_DESCONF2 (0x00000284/4) 138 #define GEM_DESCONF3 (0x00000288/4) 139 #define GEM_DESCONF4 (0x0000028C/4) 140 #define GEM_DESCONF5 (0x00000290/4) 141 #define GEM_DESCONF6 (0x00000294/4) 142 #define GEM_DESCONF7 (0x00000298/4) 143 144 /*****************************************/ 145 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 146 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 147 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 148 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 149 150 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 151 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 152 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 153 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 154 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 155 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 156 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 157 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 158 159 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 160 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 161 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 162 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 163 164 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 165 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 166 167 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 168 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 169 170 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 171 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 172 #define GEM_INT_TXUSED 0x00000008 173 #define GEM_INT_RXUSED 0x00000004 174 #define GEM_INT_RXCMPL 0x00000002 175 176 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 177 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 178 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 179 #define GEM_PHYMNTNC_ADDR_SHFT 23 180 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 181 #define GEM_PHYMNTNC_REG_SHIFT 18 182 183 /* Marvell PHY definitions */ 184 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 185 186 #define PHY_REG_CONTROL 0 187 #define PHY_REG_STATUS 1 188 #define PHY_REG_PHYID1 2 189 #define PHY_REG_PHYID2 3 190 #define PHY_REG_ANEGADV 4 191 #define PHY_REG_LINKPABIL 5 192 #define PHY_REG_ANEGEXP 6 193 #define PHY_REG_NEXTP 7 194 #define PHY_REG_LINKPNEXTP 8 195 #define PHY_REG_100BTCTRL 9 196 #define PHY_REG_1000BTSTAT 10 197 #define PHY_REG_EXTSTAT 15 198 #define PHY_REG_PHYSPCFC_CTL 16 199 #define PHY_REG_PHYSPCFC_ST 17 200 #define PHY_REG_INT_EN 18 201 #define PHY_REG_INT_ST 19 202 #define PHY_REG_EXT_PHYSPCFC_CTL 20 203 #define PHY_REG_RXERR 21 204 #define PHY_REG_EACD 22 205 #define PHY_REG_LED 24 206 #define PHY_REG_LED_OVRD 25 207 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 208 #define PHY_REG_EXT_PHYSPCFC_ST 27 209 #define PHY_REG_CABLE_DIAG 28 210 211 #define PHY_REG_CONTROL_RST 0x8000 212 #define PHY_REG_CONTROL_LOOP 0x4000 213 #define PHY_REG_CONTROL_ANEG 0x1000 214 215 #define PHY_REG_STATUS_LINK 0x0004 216 #define PHY_REG_STATUS_ANEGCMPL 0x0020 217 218 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 219 #define PHY_REG_INT_ST_LINKC 0x0400 220 #define PHY_REG_INT_ST_ENERGY 0x0010 221 222 /***********************************************************************/ 223 #define GEM_RX_REJECT (-1) 224 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 225 #define GEM_RX_BROADCAST_ACCEPT (-3) 226 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 227 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 228 229 #define GEM_RX_SAR_ACCEPT 0 230 231 /***********************************************************************/ 232 233 #define DESC_1_USED 0x80000000 234 #define DESC_1_LENGTH 0x00001FFF 235 236 #define DESC_1_TX_WRAP 0x40000000 237 #define DESC_1_TX_LAST 0x00008000 238 239 #define DESC_0_RX_WRAP 0x00000002 240 #define DESC_0_RX_OWNERSHIP 0x00000001 241 242 #define R_DESC_1_RX_SAR_SHIFT 25 243 #define R_DESC_1_RX_SAR_LENGTH 2 244 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 245 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 246 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 247 #define R_DESC_1_RX_BROADCAST (1 << 31) 248 249 #define DESC_1_RX_SOF 0x00004000 250 #define DESC_1_RX_EOF 0x00008000 251 252 static inline unsigned tx_desc_get_buffer(unsigned *desc) 253 { 254 return desc[0]; 255 } 256 257 static inline unsigned tx_desc_get_used(unsigned *desc) 258 { 259 return (desc[1] & DESC_1_USED) ? 1 : 0; 260 } 261 262 static inline void tx_desc_set_used(unsigned *desc) 263 { 264 desc[1] |= DESC_1_USED; 265 } 266 267 static inline unsigned tx_desc_get_wrap(unsigned *desc) 268 { 269 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 270 } 271 272 static inline unsigned tx_desc_get_last(unsigned *desc) 273 { 274 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 275 } 276 277 static inline unsigned tx_desc_get_length(unsigned *desc) 278 { 279 return desc[1] & DESC_1_LENGTH; 280 } 281 282 static inline void print_gem_tx_desc(unsigned *desc) 283 { 284 DB_PRINT("TXDESC:\n"); 285 DB_PRINT("bufaddr: 0x%08x\n", *desc); 286 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 287 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 288 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 289 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 290 } 291 292 static inline unsigned rx_desc_get_buffer(unsigned *desc) 293 { 294 return desc[0] & ~0x3UL; 295 } 296 297 static inline unsigned rx_desc_get_wrap(unsigned *desc) 298 { 299 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 300 } 301 302 static inline unsigned rx_desc_get_ownership(unsigned *desc) 303 { 304 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 305 } 306 307 static inline void rx_desc_set_ownership(unsigned *desc) 308 { 309 desc[0] |= DESC_0_RX_OWNERSHIP; 310 } 311 312 static inline void rx_desc_set_sof(unsigned *desc) 313 { 314 desc[1] |= DESC_1_RX_SOF; 315 } 316 317 static inline void rx_desc_set_eof(unsigned *desc) 318 { 319 desc[1] |= DESC_1_RX_EOF; 320 } 321 322 static inline void rx_desc_set_length(unsigned *desc, unsigned len) 323 { 324 desc[1] &= ~DESC_1_LENGTH; 325 desc[1] |= len; 326 } 327 328 static inline void rx_desc_set_broadcast(unsigned *desc) 329 { 330 desc[1] |= R_DESC_1_RX_BROADCAST; 331 } 332 333 static inline void rx_desc_set_unicast_hash(unsigned *desc) 334 { 335 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 336 } 337 338 static inline void rx_desc_set_multicast_hash(unsigned *desc) 339 { 340 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 341 } 342 343 static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) 344 { 345 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 346 sar_idx); 347 desc[1] |= R_DESC_1_RX_SAR_MATCH; 348 } 349 350 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 351 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 352 353 /* 354 * gem_init_register_masks: 355 * One time initialization. 356 * Set masks to identify which register bits have magical clear properties 357 */ 358 static void gem_init_register_masks(CadenceGEMState *s) 359 { 360 /* Mask of register bits which are read only */ 361 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 362 s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 363 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 364 s->regs_ro[GEM_DMACFG] = 0xFE00F000; 365 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 366 s->regs_ro[GEM_RXQBASE] = 0x00000003; 367 s->regs_ro[GEM_TXQBASE] = 0x00000003; 368 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 369 s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 370 s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 371 s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 372 373 /* Mask of register bits which are clear on read */ 374 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 375 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 376 377 /* Mask of register bits which are write 1 to clear */ 378 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 379 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 380 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 381 382 /* Mask of register bits which are write only */ 383 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 384 s->regs_wo[GEM_NWCTRL] = 0x00073E60; 385 s->regs_wo[GEM_IER] = 0x07FFFFFF; 386 s->regs_wo[GEM_IDR] = 0x07FFFFFF; 387 } 388 389 /* 390 * phy_update_link: 391 * Make the emulated PHY link state match the QEMU "interface" state. 392 */ 393 static void phy_update_link(CadenceGEMState *s) 394 { 395 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 396 397 /* Autonegotiation status mirrors link status. */ 398 if (qemu_get_queue(s->nic)->link_down) { 399 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 400 PHY_REG_STATUS_LINK); 401 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 402 } else { 403 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 404 PHY_REG_STATUS_LINK); 405 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 406 PHY_REG_INT_ST_ANEGCMPL | 407 PHY_REG_INT_ST_ENERGY); 408 } 409 } 410 411 static int gem_can_receive(NetClientState *nc) 412 { 413 CadenceGEMState *s; 414 415 s = qemu_get_nic_opaque(nc); 416 417 /* Do nothing if receive is not enabled. */ 418 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 419 if (s->can_rx_state != 1) { 420 s->can_rx_state = 1; 421 DB_PRINT("can't receive - no enable\n"); 422 } 423 return 0; 424 } 425 426 if (rx_desc_get_ownership(s->rx_desc) == 1) { 427 if (s->can_rx_state != 2) { 428 s->can_rx_state = 2; 429 DB_PRINT("can't receive - busy buffer descriptor 0x%x\n", 430 s->rx_desc_addr); 431 } 432 return 0; 433 } 434 435 if (s->can_rx_state != 0) { 436 s->can_rx_state = 0; 437 DB_PRINT("can receive 0x%x\n", s->rx_desc_addr); 438 } 439 return 1; 440 } 441 442 /* 443 * gem_update_int_status: 444 * Raise or lower interrupt based on current status. 445 */ 446 static void gem_update_int_status(CadenceGEMState *s) 447 { 448 if (s->regs[GEM_ISR]) { 449 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]); 450 qemu_set_irq(s->irq, 1); 451 } 452 } 453 454 /* 455 * gem_receive_updatestats: 456 * Increment receive statistics. 457 */ 458 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 459 unsigned bytes) 460 { 461 uint64_t octets; 462 463 /* Total octets (bytes) received */ 464 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 465 s->regs[GEM_OCTRXHI]; 466 octets += bytes; 467 s->regs[GEM_OCTRXLO] = octets >> 32; 468 s->regs[GEM_OCTRXHI] = octets; 469 470 /* Error-free Frames received */ 471 s->regs[GEM_RXCNT]++; 472 473 /* Error-free Broadcast Frames counter */ 474 if (!memcmp(packet, broadcast_addr, 6)) { 475 s->regs[GEM_RXBROADCNT]++; 476 } 477 478 /* Error-free Multicast Frames counter */ 479 if (packet[0] == 0x01) { 480 s->regs[GEM_RXMULTICNT]++; 481 } 482 483 if (bytes <= 64) { 484 s->regs[GEM_RX64CNT]++; 485 } else if (bytes <= 127) { 486 s->regs[GEM_RX65CNT]++; 487 } else if (bytes <= 255) { 488 s->regs[GEM_RX128CNT]++; 489 } else if (bytes <= 511) { 490 s->regs[GEM_RX256CNT]++; 491 } else if (bytes <= 1023) { 492 s->regs[GEM_RX512CNT]++; 493 } else if (bytes <= 1518) { 494 s->regs[GEM_RX1024CNT]++; 495 } else { 496 s->regs[GEM_RX1519CNT]++; 497 } 498 } 499 500 /* 501 * Get the MAC Address bit from the specified position 502 */ 503 static unsigned get_bit(const uint8_t *mac, unsigned bit) 504 { 505 unsigned byte; 506 507 byte = mac[bit / 8]; 508 byte >>= (bit & 0x7); 509 byte &= 1; 510 511 return byte; 512 } 513 514 /* 515 * Calculate a GEM MAC Address hash index 516 */ 517 static unsigned calc_mac_hash(const uint8_t *mac) 518 { 519 int index_bit, mac_bit; 520 unsigned hash_index; 521 522 hash_index = 0; 523 mac_bit = 5; 524 for (index_bit = 5; index_bit >= 0; index_bit--) { 525 hash_index |= (get_bit(mac, mac_bit) ^ 526 get_bit(mac, mac_bit + 6) ^ 527 get_bit(mac, mac_bit + 12) ^ 528 get_bit(mac, mac_bit + 18) ^ 529 get_bit(mac, mac_bit + 24) ^ 530 get_bit(mac, mac_bit + 30) ^ 531 get_bit(mac, mac_bit + 36) ^ 532 get_bit(mac, mac_bit + 42)) << index_bit; 533 mac_bit--; 534 } 535 536 return hash_index; 537 } 538 539 /* 540 * gem_mac_address_filter: 541 * Accept or reject this destination address? 542 * Returns: 543 * GEM_RX_REJECT: reject 544 * >= 0: Specific address accept (which matched SAR is returned) 545 * others for various other modes of accept: 546 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 547 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 548 */ 549 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 550 { 551 uint8_t *gem_spaddr; 552 int i; 553 554 /* Promiscuous mode? */ 555 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 556 return GEM_RX_PROMISCUOUS_ACCEPT; 557 } 558 559 if (!memcmp(packet, broadcast_addr, 6)) { 560 /* Reject broadcast packets? */ 561 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 562 return GEM_RX_REJECT; 563 } 564 return GEM_RX_BROADCAST_ACCEPT; 565 } 566 567 /* Accept packets -w- hash match? */ 568 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 569 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 570 unsigned hash_index; 571 572 hash_index = calc_mac_hash(packet); 573 if (hash_index < 32) { 574 if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 575 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 576 GEM_RX_UNICAST_HASH_ACCEPT; 577 } 578 } else { 579 hash_index -= 32; 580 if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 581 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 582 GEM_RX_UNICAST_HASH_ACCEPT; 583 } 584 } 585 } 586 587 /* Check all 4 specific addresses */ 588 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 589 for (i = 3; i >= 0; i--) { 590 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 591 return GEM_RX_SAR_ACCEPT + i; 592 } 593 } 594 595 /* No address match; reject the packet */ 596 return GEM_RX_REJECT; 597 } 598 599 static void gem_get_rx_desc(CadenceGEMState *s) 600 { 601 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr); 602 /* read current descriptor */ 603 cpu_physical_memory_read(s->rx_desc_addr, 604 (uint8_t *)s->rx_desc, sizeof(s->rx_desc)); 605 606 /* Descriptor owned by software ? */ 607 if (rx_desc_get_ownership(s->rx_desc) == 1) { 608 DB_PRINT("descriptor 0x%x owned by sw.\n", 609 (unsigned)s->rx_desc_addr); 610 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 611 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 612 /* Handle interrupt consequences */ 613 gem_update_int_status(s); 614 } 615 } 616 617 /* 618 * gem_receive: 619 * Fit a packet handed to us by QEMU into the receive descriptor ring. 620 */ 621 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 622 { 623 CadenceGEMState *s; 624 unsigned rxbufsize, bytes_to_copy; 625 unsigned rxbuf_offset; 626 uint8_t rxbuf[2048]; 627 uint8_t *rxbuf_ptr; 628 bool first_desc = true; 629 int maf; 630 631 s = qemu_get_nic_opaque(nc); 632 633 /* Is this destination MAC address "for us" ? */ 634 maf = gem_mac_address_filter(s, buf); 635 if (maf == GEM_RX_REJECT) { 636 return -1; 637 } 638 639 /* Discard packets with receive length error enabled ? */ 640 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 641 unsigned type_len; 642 643 /* Fish the ethertype / length field out of the RX packet */ 644 type_len = buf[12] << 8 | buf[13]; 645 /* It is a length field, not an ethertype */ 646 if (type_len < 0x600) { 647 if (size < type_len) { 648 /* discard */ 649 return -1; 650 } 651 } 652 } 653 654 /* 655 * Determine configured receive buffer offset (probably 0) 656 */ 657 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 658 GEM_NWCFG_BUFF_OFST_S; 659 660 /* The configure size of each receive buffer. Determines how many 661 * buffers needed to hold this packet. 662 */ 663 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 664 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 665 bytes_to_copy = size; 666 667 /* Pad to minimum length. Assume FCS field is stripped, logic 668 * below will increment it to the real minimum of 64 when 669 * not FCS stripping 670 */ 671 if (size < 60) { 672 size = 60; 673 } 674 675 /* Strip of FCS field ? (usually yes) */ 676 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 677 rxbuf_ptr = (void *)buf; 678 } else { 679 unsigned crc_val; 680 681 /* The application wants the FCS field, which QEMU does not provide. 682 * We must try and calculate one. 683 */ 684 685 memcpy(rxbuf, buf, size); 686 memset(rxbuf + size, 0, sizeof(rxbuf) - size); 687 rxbuf_ptr = rxbuf; 688 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 689 memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 690 691 bytes_to_copy += 4; 692 size += 4; 693 } 694 695 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 696 697 while (bytes_to_copy) { 698 /* Do nothing if receive is not enabled. */ 699 if (!gem_can_receive(nc)) { 700 assert(!first_desc); 701 return -1; 702 } 703 704 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 705 rx_desc_get_buffer(s->rx_desc)); 706 707 /* Copy packet data to emulated DMA buffer */ 708 cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc) + rxbuf_offset, 709 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 710 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 711 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 712 713 /* Update the descriptor. */ 714 if (first_desc) { 715 rx_desc_set_sof(s->rx_desc); 716 first_desc = false; 717 } 718 if (bytes_to_copy == 0) { 719 rx_desc_set_eof(s->rx_desc); 720 rx_desc_set_length(s->rx_desc, size); 721 } 722 rx_desc_set_ownership(s->rx_desc); 723 724 switch (maf) { 725 case GEM_RX_PROMISCUOUS_ACCEPT: 726 break; 727 case GEM_RX_BROADCAST_ACCEPT: 728 rx_desc_set_broadcast(s->rx_desc); 729 break; 730 case GEM_RX_UNICAST_HASH_ACCEPT: 731 rx_desc_set_unicast_hash(s->rx_desc); 732 break; 733 case GEM_RX_MULTICAST_HASH_ACCEPT: 734 rx_desc_set_multicast_hash(s->rx_desc); 735 break; 736 case GEM_RX_REJECT: 737 abort(); 738 default: /* SAR */ 739 rx_desc_set_sar(s->rx_desc, maf); 740 } 741 742 /* Descriptor write-back. */ 743 cpu_physical_memory_write(s->rx_desc_addr, 744 (uint8_t *)s->rx_desc, sizeof(s->rx_desc)); 745 746 /* Next descriptor */ 747 if (rx_desc_get_wrap(s->rx_desc)) { 748 DB_PRINT("wrapping RX descriptor list\n"); 749 s->rx_desc_addr = s->regs[GEM_RXQBASE]; 750 } else { 751 DB_PRINT("incrementing RX descriptor list\n"); 752 s->rx_desc_addr += 8; 753 } 754 gem_get_rx_desc(s); 755 } 756 757 /* Count it */ 758 gem_receive_updatestats(s, buf, size); 759 760 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 761 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 762 763 /* Handle interrupt consequences */ 764 gem_update_int_status(s); 765 766 return size; 767 } 768 769 /* 770 * gem_transmit_updatestats: 771 * Increment transmit statistics. 772 */ 773 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 774 unsigned bytes) 775 { 776 uint64_t octets; 777 778 /* Total octets (bytes) transmitted */ 779 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 780 s->regs[GEM_OCTTXHI]; 781 octets += bytes; 782 s->regs[GEM_OCTTXLO] = octets >> 32; 783 s->regs[GEM_OCTTXHI] = octets; 784 785 /* Error-free Frames transmitted */ 786 s->regs[GEM_TXCNT]++; 787 788 /* Error-free Broadcast Frames counter */ 789 if (!memcmp(packet, broadcast_addr, 6)) { 790 s->regs[GEM_TXBCNT]++; 791 } 792 793 /* Error-free Multicast Frames counter */ 794 if (packet[0] == 0x01) { 795 s->regs[GEM_TXMCNT]++; 796 } 797 798 if (bytes <= 64) { 799 s->regs[GEM_TX64CNT]++; 800 } else if (bytes <= 127) { 801 s->regs[GEM_TX65CNT]++; 802 } else if (bytes <= 255) { 803 s->regs[GEM_TX128CNT]++; 804 } else if (bytes <= 511) { 805 s->regs[GEM_TX256CNT]++; 806 } else if (bytes <= 1023) { 807 s->regs[GEM_TX512CNT]++; 808 } else if (bytes <= 1518) { 809 s->regs[GEM_TX1024CNT]++; 810 } else { 811 s->regs[GEM_TX1519CNT]++; 812 } 813 } 814 815 /* 816 * gem_transmit: 817 * Fish packets out of the descriptor ring and feed them to QEMU 818 */ 819 static void gem_transmit(CadenceGEMState *s) 820 { 821 unsigned desc[2]; 822 hwaddr packet_desc_addr; 823 uint8_t tx_packet[2048]; 824 uint8_t *p; 825 unsigned total_bytes; 826 827 /* Do nothing if transmit is not enabled. */ 828 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 829 return; 830 } 831 832 DB_PRINT("\n"); 833 834 /* The packet we will hand off to QEMU. 835 * Packets scattered across multiple descriptors are gathered to this 836 * one contiguous buffer first. 837 */ 838 p = tx_packet; 839 total_bytes = 0; 840 841 /* read current descriptor */ 842 packet_desc_addr = s->tx_desc_addr; 843 844 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 845 cpu_physical_memory_read(packet_desc_addr, 846 (uint8_t *)desc, sizeof(desc)); 847 /* Handle all descriptors owned by hardware */ 848 while (tx_desc_get_used(desc) == 0) { 849 850 /* Do nothing if transmit is not enabled. */ 851 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 852 return; 853 } 854 print_gem_tx_desc(desc); 855 856 /* The real hardware would eat this (and possibly crash). 857 * For QEMU let's lend a helping hand. 858 */ 859 if ((tx_desc_get_buffer(desc) == 0) || 860 (tx_desc_get_length(desc) == 0)) { 861 DB_PRINT("Invalid TX descriptor @ 0x%x\n", 862 (unsigned)packet_desc_addr); 863 break; 864 } 865 866 /* Gather this fragment of the packet from "dma memory" to our contig. 867 * buffer. 868 */ 869 cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 870 tx_desc_get_length(desc)); 871 p += tx_desc_get_length(desc); 872 total_bytes += tx_desc_get_length(desc); 873 874 /* Last descriptor for this packet; hand the whole thing off */ 875 if (tx_desc_get_last(desc)) { 876 unsigned desc_first[2]; 877 878 /* Modify the 1st descriptor of this packet to be owned by 879 * the processor. 880 */ 881 cpu_physical_memory_read(s->tx_desc_addr, (uint8_t *)desc_first, 882 sizeof(desc_first)); 883 tx_desc_set_used(desc_first); 884 cpu_physical_memory_write(s->tx_desc_addr, (uint8_t *)desc_first, 885 sizeof(desc_first)); 886 /* Advance the hardware current descriptor past this packet */ 887 if (tx_desc_get_wrap(desc)) { 888 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 889 } else { 890 s->tx_desc_addr = packet_desc_addr + 8; 891 } 892 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr); 893 894 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 895 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 896 897 /* Handle interrupt consequences */ 898 gem_update_int_status(s); 899 900 /* Is checksum offload enabled? */ 901 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 902 net_checksum_calculate(tx_packet, total_bytes); 903 } 904 905 /* Update MAC statistics */ 906 gem_transmit_updatestats(s, tx_packet, total_bytes); 907 908 /* Send the packet somewhere */ 909 if (s->phy_loop || (s->regs[GEM_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) { 910 gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes); 911 } else { 912 qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 913 total_bytes); 914 } 915 916 /* Prepare for next packet */ 917 p = tx_packet; 918 total_bytes = 0; 919 } 920 921 /* read next descriptor */ 922 if (tx_desc_get_wrap(desc)) { 923 packet_desc_addr = s->regs[GEM_TXQBASE]; 924 } else { 925 packet_desc_addr += 8; 926 } 927 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 928 cpu_physical_memory_read(packet_desc_addr, 929 (uint8_t *)desc, sizeof(desc)); 930 } 931 932 if (tx_desc_get_used(desc)) { 933 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 934 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 935 gem_update_int_status(s); 936 } 937 } 938 939 static void gem_phy_reset(CadenceGEMState *s) 940 { 941 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 942 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 943 s->phy_regs[PHY_REG_STATUS] = 0x7969; 944 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 945 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 946 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 947 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 948 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 949 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 950 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 951 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 952 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 953 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 954 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 955 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 956 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 957 s->phy_regs[PHY_REG_LED] = 0x4100; 958 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 959 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 960 961 phy_update_link(s); 962 } 963 964 static void gem_reset(DeviceState *d) 965 { 966 int i; 967 CadenceGEMState *s = CADENCE_GEM(d); 968 const uint8_t *a; 969 970 DB_PRINT("\n"); 971 972 /* Set post reset register values */ 973 memset(&s->regs[0], 0, sizeof(s->regs)); 974 s->regs[GEM_NWCFG] = 0x00080000; 975 s->regs[GEM_NWSTATUS] = 0x00000006; 976 s->regs[GEM_DMACFG] = 0x00020784; 977 s->regs[GEM_IMR] = 0x07ffffff; 978 s->regs[GEM_TXPAUSE] = 0x0000ffff; 979 s->regs[GEM_TXPARTIALSF] = 0x000003ff; 980 s->regs[GEM_RXPARTIALSF] = 0x000003ff; 981 s->regs[GEM_MODID] = 0x00020118; 982 s->regs[GEM_DESCONF] = 0x02500111; 983 s->regs[GEM_DESCONF2] = 0x2ab13fff; 984 s->regs[GEM_DESCONF5] = 0x002f2145; 985 s->regs[GEM_DESCONF6] = 0x00000200; 986 987 /* Set MAC address */ 988 a = &s->conf.macaddr.a[0]; 989 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 990 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 991 992 for (i = 0; i < 4; i++) { 993 s->sar_active[i] = false; 994 } 995 996 gem_phy_reset(s); 997 998 gem_update_int_status(s); 999 } 1000 1001 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1002 { 1003 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1004 return s->phy_regs[reg_num]; 1005 } 1006 1007 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1008 { 1009 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1010 1011 switch (reg_num) { 1012 case PHY_REG_CONTROL: 1013 if (val & PHY_REG_CONTROL_RST) { 1014 /* Phy reset */ 1015 gem_phy_reset(s); 1016 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1017 s->phy_loop = 0; 1018 } 1019 if (val & PHY_REG_CONTROL_ANEG) { 1020 /* Complete autonegotiation immediately */ 1021 val &= ~PHY_REG_CONTROL_ANEG; 1022 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1023 } 1024 if (val & PHY_REG_CONTROL_LOOP) { 1025 DB_PRINT("PHY placed in loopback\n"); 1026 s->phy_loop = 1; 1027 } else { 1028 s->phy_loop = 0; 1029 } 1030 break; 1031 } 1032 s->phy_regs[reg_num] = val; 1033 } 1034 1035 /* 1036 * gem_read32: 1037 * Read a GEM register. 1038 */ 1039 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1040 { 1041 CadenceGEMState *s; 1042 uint32_t retval; 1043 1044 s = (CadenceGEMState *)opaque; 1045 1046 offset >>= 2; 1047 retval = s->regs[offset]; 1048 1049 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1050 1051 switch (offset) { 1052 case GEM_ISR: 1053 DB_PRINT("lowering irq on ISR read\n"); 1054 qemu_set_irq(s->irq, 0); 1055 break; 1056 case GEM_PHYMNTNC: 1057 if (retval & GEM_PHYMNTNC_OP_R) { 1058 uint32_t phy_addr, reg_num; 1059 1060 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1061 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1062 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1063 retval &= 0xFFFF0000; 1064 retval |= gem_phy_read(s, reg_num); 1065 } else { 1066 retval |= 0xFFFF; /* No device at this address */ 1067 } 1068 } 1069 break; 1070 } 1071 1072 /* Squash read to clear bits */ 1073 s->regs[offset] &= ~(s->regs_rtc[offset]); 1074 1075 /* Do not provide write only bits */ 1076 retval &= ~(s->regs_wo[offset]); 1077 1078 DB_PRINT("0x%08x\n", retval); 1079 return retval; 1080 } 1081 1082 /* 1083 * gem_write32: 1084 * Write a GEM register. 1085 */ 1086 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1087 unsigned size) 1088 { 1089 CadenceGEMState *s = (CadenceGEMState *)opaque; 1090 uint32_t readonly; 1091 1092 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1093 offset >>= 2; 1094 1095 /* Squash bits which are read only in write value */ 1096 val &= ~(s->regs_ro[offset]); 1097 /* Preserve (only) bits which are read only and wtc in register */ 1098 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1099 1100 /* Copy register write to backing store */ 1101 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1102 1103 /* do w1c */ 1104 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1105 1106 /* Handle register write side effects */ 1107 switch (offset) { 1108 case GEM_NWCTRL: 1109 if (val & GEM_NWCTRL_RXENA) { 1110 gem_get_rx_desc(s); 1111 } 1112 if (val & GEM_NWCTRL_TXSTART) { 1113 gem_transmit(s); 1114 } 1115 if (!(val & GEM_NWCTRL_TXENA)) { 1116 /* Reset to start of Q when transmit disabled. */ 1117 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 1118 } 1119 if (gem_can_receive(qemu_get_queue(s->nic))) { 1120 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1121 } 1122 break; 1123 1124 case GEM_TXSTATUS: 1125 gem_update_int_status(s); 1126 break; 1127 case GEM_RXQBASE: 1128 s->rx_desc_addr = val; 1129 break; 1130 case GEM_TXQBASE: 1131 s->tx_desc_addr = val; 1132 break; 1133 case GEM_RXSTATUS: 1134 gem_update_int_status(s); 1135 break; 1136 case GEM_IER: 1137 s->regs[GEM_IMR] &= ~val; 1138 gem_update_int_status(s); 1139 break; 1140 case GEM_IDR: 1141 s->regs[GEM_IMR] |= val; 1142 gem_update_int_status(s); 1143 break; 1144 case GEM_SPADDR1LO: 1145 case GEM_SPADDR2LO: 1146 case GEM_SPADDR3LO: 1147 case GEM_SPADDR4LO: 1148 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 1149 break; 1150 case GEM_SPADDR1HI: 1151 case GEM_SPADDR2HI: 1152 case GEM_SPADDR3HI: 1153 case GEM_SPADDR4HI: 1154 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 1155 break; 1156 case GEM_PHYMNTNC: 1157 if (val & GEM_PHYMNTNC_OP_W) { 1158 uint32_t phy_addr, reg_num; 1159 1160 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1161 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1162 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1163 gem_phy_write(s, reg_num, val); 1164 } 1165 } 1166 break; 1167 } 1168 1169 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1170 } 1171 1172 static const MemoryRegionOps gem_ops = { 1173 .read = gem_read, 1174 .write = gem_write, 1175 .endianness = DEVICE_LITTLE_ENDIAN, 1176 }; 1177 1178 static void gem_set_link(NetClientState *nc) 1179 { 1180 DB_PRINT("\n"); 1181 phy_update_link(qemu_get_nic_opaque(nc)); 1182 } 1183 1184 static NetClientInfo net_gem_info = { 1185 .type = NET_CLIENT_OPTIONS_KIND_NIC, 1186 .size = sizeof(NICState), 1187 .can_receive = gem_can_receive, 1188 .receive = gem_receive, 1189 .link_status_changed = gem_set_link, 1190 }; 1191 1192 static int gem_init(SysBusDevice *sbd) 1193 { 1194 DeviceState *dev = DEVICE(sbd); 1195 CadenceGEMState *s = CADENCE_GEM(dev); 1196 1197 DB_PRINT("\n"); 1198 1199 gem_init_register_masks(s); 1200 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1201 "enet", sizeof(s->regs)); 1202 sysbus_init_mmio(sbd, &s->iomem); 1203 sysbus_init_irq(sbd, &s->irq); 1204 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1205 1206 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1207 object_get_typename(OBJECT(dev)), dev->id, s); 1208 1209 return 0; 1210 } 1211 1212 static const VMStateDescription vmstate_cadence_gem = { 1213 .name = "cadence_gem", 1214 .version_id = 2, 1215 .minimum_version_id = 2, 1216 .fields = (VMStateField[]) { 1217 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1218 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1219 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1220 VMSTATE_UINT32(rx_desc_addr, CadenceGEMState), 1221 VMSTATE_UINT32(tx_desc_addr, CadenceGEMState), 1222 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1223 VMSTATE_END_OF_LIST(), 1224 } 1225 }; 1226 1227 static Property gem_properties[] = { 1228 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1229 DEFINE_PROP_END_OF_LIST(), 1230 }; 1231 1232 static void gem_class_init(ObjectClass *klass, void *data) 1233 { 1234 DeviceClass *dc = DEVICE_CLASS(klass); 1235 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1236 1237 sdc->init = gem_init; 1238 dc->props = gem_properties; 1239 dc->vmsd = &vmstate_cadence_gem; 1240 dc->reset = gem_reset; 1241 } 1242 1243 static const TypeInfo gem_info = { 1244 .name = TYPE_CADENCE_GEM, 1245 .parent = TYPE_SYS_BUS_DEVICE, 1246 .instance_size = sizeof(CadenceGEMState), 1247 .class_init = gem_class_init, 1248 }; 1249 1250 static void gem_register_types(void) 1251 { 1252 type_register_static(&gem_info); 1253 } 1254 1255 type_init(gem_register_types) 1256