xref: /openbmc/qemu/hw/net/cadence_gem.c (revision 84d0984dfe336f24109a6792d06aad0e9ae5e0a6)
1 /*
2  * QEMU Cadence GEM emulation
3  *
4  * Copyright (c) 2011 Xilinx, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include <zlib.h> /* For crc32 */
27 
28 #include "hw/net/cadence_gem.h"
29 #include "qapi/error.h"
30 #include "qemu/log.h"
31 #include "net/checksum.h"
32 
33 #ifdef CADENCE_GEM_ERR_DEBUG
34 #define DB_PRINT(...) do { \
35     fprintf(stderr,  ": %s: ", __func__); \
36     fprintf(stderr, ## __VA_ARGS__); \
37     } while (0);
38 #else
39     #define DB_PRINT(...)
40 #endif
41 
42 #define GEM_NWCTRL        (0x00000000/4) /* Network Control reg */
43 #define GEM_NWCFG         (0x00000004/4) /* Network Config reg */
44 #define GEM_NWSTATUS      (0x00000008/4) /* Network Status reg */
45 #define GEM_USERIO        (0x0000000C/4) /* User IO reg */
46 #define GEM_DMACFG        (0x00000010/4) /* DMA Control reg */
47 #define GEM_TXSTATUS      (0x00000014/4) /* TX Status reg */
48 #define GEM_RXQBASE       (0x00000018/4) /* RX Q Base address reg */
49 #define GEM_TXQBASE       (0x0000001C/4) /* TX Q Base address reg */
50 #define GEM_RXSTATUS      (0x00000020/4) /* RX Status reg */
51 #define GEM_ISR           (0x00000024/4) /* Interrupt Status reg */
52 #define GEM_IER           (0x00000028/4) /* Interrupt Enable reg */
53 #define GEM_IDR           (0x0000002C/4) /* Interrupt Disable reg */
54 #define GEM_IMR           (0x00000030/4) /* Interrupt Mask reg */
55 #define GEM_PHYMNTNC      (0x00000034/4) /* Phy Maintenance reg */
56 #define GEM_RXPAUSE       (0x00000038/4) /* RX Pause Time reg */
57 #define GEM_TXPAUSE       (0x0000003C/4) /* TX Pause Time reg */
58 #define GEM_TXPARTIALSF   (0x00000040/4) /* TX Partial Store and Forward */
59 #define GEM_RXPARTIALSF   (0x00000044/4) /* RX Partial Store and Forward */
60 #define GEM_HASHLO        (0x00000080/4) /* Hash Low address reg */
61 #define GEM_HASHHI        (0x00000084/4) /* Hash High address reg */
62 #define GEM_SPADDR1LO     (0x00000088/4) /* Specific addr 1 low reg */
63 #define GEM_SPADDR1HI     (0x0000008C/4) /* Specific addr 1 high reg */
64 #define GEM_SPADDR2LO     (0x00000090/4) /* Specific addr 2 low reg */
65 #define GEM_SPADDR2HI     (0x00000094/4) /* Specific addr 2 high reg */
66 #define GEM_SPADDR3LO     (0x00000098/4) /* Specific addr 3 low reg */
67 #define GEM_SPADDR3HI     (0x0000009C/4) /* Specific addr 3 high reg */
68 #define GEM_SPADDR4LO     (0x000000A0/4) /* Specific addr 4 low reg */
69 #define GEM_SPADDR4HI     (0x000000A4/4) /* Specific addr 4 high reg */
70 #define GEM_TIDMATCH1     (0x000000A8/4) /* Type ID1 Match reg */
71 #define GEM_TIDMATCH2     (0x000000AC/4) /* Type ID2 Match reg */
72 #define GEM_TIDMATCH3     (0x000000B0/4) /* Type ID3 Match reg */
73 #define GEM_TIDMATCH4     (0x000000B4/4) /* Type ID4 Match reg */
74 #define GEM_WOLAN         (0x000000B8/4) /* Wake on LAN reg */
75 #define GEM_IPGSTRETCH    (0x000000BC/4) /* IPG Stretch reg */
76 #define GEM_SVLAN         (0x000000C0/4) /* Stacked VLAN reg */
77 #define GEM_MODID         (0x000000FC/4) /* Module ID reg */
78 #define GEM_OCTTXLO       (0x00000100/4) /* Octects transmitted Low reg */
79 #define GEM_OCTTXHI       (0x00000104/4) /* Octects transmitted High reg */
80 #define GEM_TXCNT         (0x00000108/4) /* Error-free Frames transmitted */
81 #define GEM_TXBCNT        (0x0000010C/4) /* Error-free Broadcast Frames */
82 #define GEM_TXMCNT        (0x00000110/4) /* Error-free Multicast Frame */
83 #define GEM_TXPAUSECNT    (0x00000114/4) /* Pause Frames Transmitted */
84 #define GEM_TX64CNT       (0x00000118/4) /* Error-free 64 TX */
85 #define GEM_TX65CNT       (0x0000011C/4) /* Error-free 65-127 TX */
86 #define GEM_TX128CNT      (0x00000120/4) /* Error-free 128-255 TX */
87 #define GEM_TX256CNT      (0x00000124/4) /* Error-free 256-511 */
88 #define GEM_TX512CNT      (0x00000128/4) /* Error-free 512-1023 TX */
89 #define GEM_TX1024CNT     (0x0000012C/4) /* Error-free 1024-1518 TX */
90 #define GEM_TX1519CNT     (0x00000130/4) /* Error-free larger than 1519 TX */
91 #define GEM_TXURUNCNT     (0x00000134/4) /* TX under run error counter */
92 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
93 #define GEM_MULTCOLLCNT   (0x0000013C/4) /* Multiple Collision Frames */
94 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
95 #define GEM_LATECOLLCNT   (0x00000144/4) /* Late Collision Frames */
96 #define GEM_DEFERTXCNT    (0x00000148/4) /* Deferred Transmission Frames */
97 #define GEM_CSENSECNT     (0x0000014C/4) /* Carrier Sense Error Counter */
98 #define GEM_OCTRXLO       (0x00000150/4) /* Octects Received register Low */
99 #define GEM_OCTRXHI       (0x00000154/4) /* Octects Received register High */
100 #define GEM_RXCNT         (0x00000158/4) /* Error-free Frames Received */
101 #define GEM_RXBROADCNT    (0x0000015C/4) /* Error-free Broadcast Frames RX */
102 #define GEM_RXMULTICNT    (0x00000160/4) /* Error-free Multicast Frames RX */
103 #define GEM_RXPAUSECNT    (0x00000164/4) /* Pause Frames Received Counter */
104 #define GEM_RX64CNT       (0x00000168/4) /* Error-free 64 byte Frames RX */
105 #define GEM_RX65CNT       (0x0000016C/4) /* Error-free 65-127B Frames RX */
106 #define GEM_RX128CNT      (0x00000170/4) /* Error-free 128-255B Frames RX */
107 #define GEM_RX256CNT      (0x00000174/4) /* Error-free 256-512B Frames RX */
108 #define GEM_RX512CNT      (0x00000178/4) /* Error-free 512-1023B Frames RX */
109 #define GEM_RX1024CNT     (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
110 #define GEM_RX1519CNT     (0x00000180/4) /* Error-free 1519-max Frames RX */
111 #define GEM_RXUNDERCNT    (0x00000184/4) /* Undersize Frames Received */
112 #define GEM_RXOVERCNT     (0x00000188/4) /* Oversize Frames Received */
113 #define GEM_RXJABCNT      (0x0000018C/4) /* Jabbers Received Counter */
114 #define GEM_RXFCSCNT      (0x00000190/4) /* Frame Check seq. Error Counter */
115 #define GEM_RXLENERRCNT   (0x00000194/4) /* Length Field Error Counter */
116 #define GEM_RXSYMERRCNT   (0x00000198/4) /* Symbol Error Counter */
117 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
118 #define GEM_RXRSCERRCNT   (0x000001A0/4) /* Receive Resource Error Counter */
119 #define GEM_RXORUNCNT     (0x000001A4/4) /* Receive Overrun Counter */
120 #define GEM_RXIPCSERRCNT  (0x000001A8/4) /* IP header Checksum Error Counter */
121 #define GEM_RXTCPCCNT     (0x000001AC/4) /* TCP Checksum Error Counter */
122 #define GEM_RXUDPCCNT     (0x000001B0/4) /* UDP Checksum Error Counter */
123 
124 #define GEM_1588S         (0x000001D0/4) /* 1588 Timer Seconds */
125 #define GEM_1588NS        (0x000001D4/4) /* 1588 Timer Nanoseconds */
126 #define GEM_1588ADJ       (0x000001D8/4) /* 1588 Timer Adjust */
127 #define GEM_1588INC       (0x000001DC/4) /* 1588 Timer Increment */
128 #define GEM_PTPETXS       (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
129 #define GEM_PTPETXNS      (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
130 #define GEM_PTPERXS       (0x000001E8/4) /* PTP Event Frame Received (s) */
131 #define GEM_PTPERXNS      (0x000001EC/4) /* PTP Event Frame Received (ns) */
132 #define GEM_PTPPTXS       (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
133 #define GEM_PTPPTXNS      (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
134 #define GEM_PTPPRXS       (0x000001E8/4) /* PTP Peer Frame Received (s) */
135 #define GEM_PTPPRXNS      (0x000001EC/4) /* PTP Peer Frame Received (ns) */
136 
137 /* Design Configuration Registers */
138 #define GEM_DESCONF       (0x00000280/4)
139 #define GEM_DESCONF2      (0x00000284/4)
140 #define GEM_DESCONF3      (0x00000288/4)
141 #define GEM_DESCONF4      (0x0000028C/4)
142 #define GEM_DESCONF5      (0x00000290/4)
143 #define GEM_DESCONF6      (0x00000294/4)
144 #define GEM_DESCONF7      (0x00000298/4)
145 
146 #define GEM_INT_Q1_STATUS               (0x00000400 / 4)
147 #define GEM_INT_Q1_MASK                 (0x00000640 / 4)
148 
149 #define GEM_TRANSMIT_Q1_PTR             (0x00000440 / 4)
150 #define GEM_TRANSMIT_Q15_PTR            (GEM_TRANSMIT_Q1_PTR + 14)
151 
152 #define GEM_RECEIVE_Q1_PTR              (0x00000480 / 4)
153 #define GEM_RECEIVE_Q15_PTR             (GEM_RECEIVE_Q1_PTR + 14)
154 
155 #define GEM_INT_Q1_ENABLE               (0x00000600 / 4)
156 #define GEM_INT_Q7_ENABLE               (GEM_INT_Q1_ENABLE + 6)
157 #define GEM_INT_Q8_ENABLE               (0x00000660 / 4)
158 #define GEM_INT_Q15_ENABLE              (GEM_INT_Q8_ENABLE + 7)
159 
160 #define GEM_INT_Q1_DISABLE              (0x00000620 / 4)
161 #define GEM_INT_Q7_DISABLE              (GEM_INT_Q1_DISABLE + 6)
162 #define GEM_INT_Q8_DISABLE              (0x00000680 / 4)
163 #define GEM_INT_Q15_DISABLE             (GEM_INT_Q8_DISABLE + 7)
164 
165 #define GEM_INT_Q1_MASK                 (0x00000640 / 4)
166 #define GEM_INT_Q7_MASK                 (GEM_INT_Q1_MASK + 6)
167 #define GEM_INT_Q8_MASK                 (0x000006A0 / 4)
168 #define GEM_INT_Q15_MASK                (GEM_INT_Q8_MASK + 7)
169 
170 #define GEM_SCREENING_TYPE1_REGISTER_0  (0x00000500 / 4)
171 
172 #define GEM_ST1R_UDP_PORT_MATCH_ENABLE  (1 << 29)
173 #define GEM_ST1R_DSTC_ENABLE            (1 << 28)
174 #define GEM_ST1R_UDP_PORT_MATCH_SHIFT   (12)
175 #define GEM_ST1R_UDP_PORT_MATCH_WIDTH   (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
176 #define GEM_ST1R_DSTC_MATCH_SHIFT       (4)
177 #define GEM_ST1R_DSTC_MATCH_WIDTH       (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
178 #define GEM_ST1R_QUEUE_SHIFT            (0)
179 #define GEM_ST1R_QUEUE_WIDTH            (3 - GEM_ST1R_QUEUE_SHIFT + 1)
180 
181 #define GEM_SCREENING_TYPE2_REGISTER_0  (0x00000540 / 4)
182 
183 #define GEM_ST2R_COMPARE_A_ENABLE       (1 << 18)
184 #define GEM_ST2R_COMPARE_A_SHIFT        (13)
185 #define GEM_ST2R_COMPARE_WIDTH          (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
186 #define GEM_ST2R_ETHERTYPE_ENABLE       (1 << 12)
187 #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT  (9)
188 #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH  (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
189                                             + 1)
190 #define GEM_ST2R_QUEUE_SHIFT            (0)
191 #define GEM_ST2R_QUEUE_WIDTH            (3 - GEM_ST2R_QUEUE_SHIFT + 1)
192 
193 #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0     (0x000006e0 / 4)
194 #define GEM_TYPE2_COMPARE_0_WORD_0              (0x00000700 / 4)
195 
196 #define GEM_T2CW1_COMPARE_OFFSET_SHIFT  (7)
197 #define GEM_T2CW1_COMPARE_OFFSET_WIDTH  (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
198 #define GEM_T2CW1_OFFSET_VALUE_SHIFT    (0)
199 #define GEM_T2CW1_OFFSET_VALUE_WIDTH    (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
200 
201 /*****************************************/
202 #define GEM_NWCTRL_TXSTART     0x00000200 /* Transmit Enable */
203 #define GEM_NWCTRL_TXENA       0x00000008 /* Transmit Enable */
204 #define GEM_NWCTRL_RXENA       0x00000004 /* Receive Enable */
205 #define GEM_NWCTRL_LOCALLOOP   0x00000002 /* Local Loopback */
206 
207 #define GEM_NWCFG_STRIP_FCS    0x00020000 /* Strip FCS field */
208 #define GEM_NWCFG_LERR_DISC    0x00010000 /* Discard RX frames with len err */
209 #define GEM_NWCFG_BUFF_OFST_M  0x0000C000 /* Receive buffer offset mask */
210 #define GEM_NWCFG_BUFF_OFST_S  14         /* Receive buffer offset shift */
211 #define GEM_NWCFG_UCAST_HASH   0x00000080 /* accept unicast if hash match */
212 #define GEM_NWCFG_MCAST_HASH   0x00000040 /* accept multicast if hash match */
213 #define GEM_NWCFG_BCAST_REJ    0x00000020 /* Reject broadcast packets */
214 #define GEM_NWCFG_PROMISC      0x00000010 /* Accept all packets */
215 
216 #define GEM_DMACFG_RBUFSZ_M    0x00FF0000 /* DMA RX Buffer Size mask */
217 #define GEM_DMACFG_RBUFSZ_S    16         /* DMA RX Buffer Size shift */
218 #define GEM_DMACFG_RBUFSZ_MUL  64         /* DMA RX Buffer Size multiplier */
219 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
220 
221 #define GEM_TXSTATUS_TXCMPL    0x00000020 /* Transmit Complete */
222 #define GEM_TXSTATUS_USED      0x00000001 /* sw owned descriptor encountered */
223 
224 #define GEM_RXSTATUS_FRMRCVD   0x00000002 /* Frame received */
225 #define GEM_RXSTATUS_NOBUF     0x00000001 /* Buffer unavailable */
226 
227 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
228 #define GEM_INT_TXCMPL        0x00000080 /* Transmit Complete */
229 #define GEM_INT_TXUSED         0x00000008
230 #define GEM_INT_RXUSED         0x00000004
231 #define GEM_INT_RXCMPL        0x00000002
232 
233 #define GEM_PHYMNTNC_OP_R      0x20000000 /* read operation */
234 #define GEM_PHYMNTNC_OP_W      0x10000000 /* write operation */
235 #define GEM_PHYMNTNC_ADDR      0x0F800000 /* Address bits */
236 #define GEM_PHYMNTNC_ADDR_SHFT 23
237 #define GEM_PHYMNTNC_REG       0x007C0000 /* register bits */
238 #define GEM_PHYMNTNC_REG_SHIFT 18
239 
240 /* Marvell PHY definitions */
241 #define BOARD_PHY_ADDRESS    23 /* PHY address we will emulate a device at */
242 
243 #define PHY_REG_CONTROL      0
244 #define PHY_REG_STATUS       1
245 #define PHY_REG_PHYID1       2
246 #define PHY_REG_PHYID2       3
247 #define PHY_REG_ANEGADV      4
248 #define PHY_REG_LINKPABIL    5
249 #define PHY_REG_ANEGEXP      6
250 #define PHY_REG_NEXTP        7
251 #define PHY_REG_LINKPNEXTP   8
252 #define PHY_REG_100BTCTRL    9
253 #define PHY_REG_1000BTSTAT   10
254 #define PHY_REG_EXTSTAT      15
255 #define PHY_REG_PHYSPCFC_CTL 16
256 #define PHY_REG_PHYSPCFC_ST  17
257 #define PHY_REG_INT_EN       18
258 #define PHY_REG_INT_ST       19
259 #define PHY_REG_EXT_PHYSPCFC_CTL  20
260 #define PHY_REG_RXERR        21
261 #define PHY_REG_EACD         22
262 #define PHY_REG_LED          24
263 #define PHY_REG_LED_OVRD     25
264 #define PHY_REG_EXT_PHYSPCFC_CTL2 26
265 #define PHY_REG_EXT_PHYSPCFC_ST   27
266 #define PHY_REG_CABLE_DIAG   28
267 
268 #define PHY_REG_CONTROL_RST  0x8000
269 #define PHY_REG_CONTROL_LOOP 0x4000
270 #define PHY_REG_CONTROL_ANEG 0x1000
271 
272 #define PHY_REG_STATUS_LINK     0x0004
273 #define PHY_REG_STATUS_ANEGCMPL 0x0020
274 
275 #define PHY_REG_INT_ST_ANEGCMPL 0x0800
276 #define PHY_REG_INT_ST_LINKC    0x0400
277 #define PHY_REG_INT_ST_ENERGY   0x0010
278 
279 /***********************************************************************/
280 #define GEM_RX_REJECT                   (-1)
281 #define GEM_RX_PROMISCUOUS_ACCEPT       (-2)
282 #define GEM_RX_BROADCAST_ACCEPT         (-3)
283 #define GEM_RX_MULTICAST_HASH_ACCEPT    (-4)
284 #define GEM_RX_UNICAST_HASH_ACCEPT      (-5)
285 
286 #define GEM_RX_SAR_ACCEPT               0
287 
288 /***********************************************************************/
289 
290 #define DESC_1_USED 0x80000000
291 #define DESC_1_LENGTH 0x00001FFF
292 
293 #define DESC_1_TX_WRAP 0x40000000
294 #define DESC_1_TX_LAST 0x00008000
295 
296 #define DESC_0_RX_WRAP 0x00000002
297 #define DESC_0_RX_OWNERSHIP 0x00000001
298 
299 #define R_DESC_1_RX_SAR_SHIFT           25
300 #define R_DESC_1_RX_SAR_LENGTH          2
301 #define R_DESC_1_RX_SAR_MATCH           (1 << 27)
302 #define R_DESC_1_RX_UNICAST_HASH        (1 << 29)
303 #define R_DESC_1_RX_MULTICAST_HASH      (1 << 30)
304 #define R_DESC_1_RX_BROADCAST           (1 << 31)
305 
306 #define DESC_1_RX_SOF 0x00004000
307 #define DESC_1_RX_EOF 0x00008000
308 
309 static inline unsigned tx_desc_get_buffer(unsigned *desc)
310 {
311     return desc[0];
312 }
313 
314 static inline unsigned tx_desc_get_used(unsigned *desc)
315 {
316     return (desc[1] & DESC_1_USED) ? 1 : 0;
317 }
318 
319 static inline void tx_desc_set_used(unsigned *desc)
320 {
321     desc[1] |= DESC_1_USED;
322 }
323 
324 static inline unsigned tx_desc_get_wrap(unsigned *desc)
325 {
326     return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
327 }
328 
329 static inline unsigned tx_desc_get_last(unsigned *desc)
330 {
331     return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
332 }
333 
334 static inline void tx_desc_set_last(unsigned *desc)
335 {
336     desc[1] |= DESC_1_TX_LAST;
337 }
338 
339 static inline unsigned tx_desc_get_length(unsigned *desc)
340 {
341     return desc[1] & DESC_1_LENGTH;
342 }
343 
344 static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue)
345 {
346     DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
347     DB_PRINT("bufaddr: 0x%08x\n", *desc);
348     DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
349     DB_PRINT("wrap:    %d\n", tx_desc_get_wrap(desc));
350     DB_PRINT("last:    %d\n", tx_desc_get_last(desc));
351     DB_PRINT("length:  %d\n", tx_desc_get_length(desc));
352 }
353 
354 static inline unsigned rx_desc_get_buffer(unsigned *desc)
355 {
356     return desc[0] & ~0x3UL;
357 }
358 
359 static inline unsigned rx_desc_get_wrap(unsigned *desc)
360 {
361     return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
362 }
363 
364 static inline unsigned rx_desc_get_ownership(unsigned *desc)
365 {
366     return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
367 }
368 
369 static inline void rx_desc_set_ownership(unsigned *desc)
370 {
371     desc[0] |= DESC_0_RX_OWNERSHIP;
372 }
373 
374 static inline void rx_desc_set_sof(unsigned *desc)
375 {
376     desc[1] |= DESC_1_RX_SOF;
377 }
378 
379 static inline void rx_desc_set_eof(unsigned *desc)
380 {
381     desc[1] |= DESC_1_RX_EOF;
382 }
383 
384 static inline void rx_desc_set_length(unsigned *desc, unsigned len)
385 {
386     desc[1] &= ~DESC_1_LENGTH;
387     desc[1] |= len;
388 }
389 
390 static inline void rx_desc_set_broadcast(unsigned *desc)
391 {
392     desc[1] |= R_DESC_1_RX_BROADCAST;
393 }
394 
395 static inline void rx_desc_set_unicast_hash(unsigned *desc)
396 {
397     desc[1] |= R_DESC_1_RX_UNICAST_HASH;
398 }
399 
400 static inline void rx_desc_set_multicast_hash(unsigned *desc)
401 {
402     desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
403 }
404 
405 static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
406 {
407     desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
408                         sar_idx);
409     desc[1] |= R_DESC_1_RX_SAR_MATCH;
410 }
411 
412 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
413 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
414 
415 /*
416  * gem_init_register_masks:
417  * One time initialization.
418  * Set masks to identify which register bits have magical clear properties
419  */
420 static void gem_init_register_masks(CadenceGEMState *s)
421 {
422     /* Mask of register bits which are read only */
423     memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
424     s->regs_ro[GEM_NWCTRL]   = 0xFFF80000;
425     s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
426     s->regs_ro[GEM_DMACFG]   = 0xFE00F000;
427     s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
428     s->regs_ro[GEM_RXQBASE]  = 0x00000003;
429     s->regs_ro[GEM_TXQBASE]  = 0x00000003;
430     s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
431     s->regs_ro[GEM_ISR]      = 0xFFFFFFFF;
432     s->regs_ro[GEM_IMR]      = 0xFFFFFFFF;
433     s->regs_ro[GEM_MODID]    = 0xFFFFFFFF;
434 
435     /* Mask of register bits which are clear on read */
436     memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
437     s->regs_rtc[GEM_ISR]      = 0xFFFFFFFF;
438 
439     /* Mask of register bits which are write 1 to clear */
440     memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
441     s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
442     s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
443 
444     /* Mask of register bits which are write only */
445     memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
446     s->regs_wo[GEM_NWCTRL]   = 0x00073E60;
447     s->regs_wo[GEM_IER]      = 0x07FFFFFF;
448     s->regs_wo[GEM_IDR]      = 0x07FFFFFF;
449 }
450 
451 /*
452  * phy_update_link:
453  * Make the emulated PHY link state match the QEMU "interface" state.
454  */
455 static void phy_update_link(CadenceGEMState *s)
456 {
457     DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
458 
459     /* Autonegotiation status mirrors link status.  */
460     if (qemu_get_queue(s->nic)->link_down) {
461         s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
462                                          PHY_REG_STATUS_LINK);
463         s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
464     } else {
465         s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
466                                          PHY_REG_STATUS_LINK);
467         s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
468                                         PHY_REG_INT_ST_ANEGCMPL |
469                                         PHY_REG_INT_ST_ENERGY);
470     }
471 }
472 
473 static int gem_can_receive(NetClientState *nc)
474 {
475     CadenceGEMState *s;
476     int i;
477 
478     s = qemu_get_nic_opaque(nc);
479 
480     /* Do nothing if receive is not enabled. */
481     if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
482         if (s->can_rx_state != 1) {
483             s->can_rx_state = 1;
484             DB_PRINT("can't receive - no enable\n");
485         }
486         return 0;
487     }
488 
489     for (i = 0; i < s->num_priority_queues; i++) {
490         if (rx_desc_get_ownership(s->rx_desc[i]) == 1) {
491             if (s->can_rx_state != 2) {
492                 s->can_rx_state = 2;
493                 DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n",
494                          i, s->rx_desc_addr[i]);
495              }
496             return 0;
497         }
498     }
499 
500     if (s->can_rx_state != 0) {
501         s->can_rx_state = 0;
502         DB_PRINT("can receive\n");
503     }
504     return 1;
505 }
506 
507 /*
508  * gem_update_int_status:
509  * Raise or lower interrupt based on current status.
510  */
511 static void gem_update_int_status(CadenceGEMState *s)
512 {
513     int i;
514 
515     if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) {
516         /* No priority queues, just trigger the interrupt */
517         DB_PRINT("asserting int.\n", i);
518         qemu_set_irq(s->irq[0], 1);
519         return;
520     }
521 
522     for (i = 0; i < s->num_priority_queues; ++i) {
523         if (s->regs[GEM_INT_Q1_STATUS + i]) {
524             DB_PRINT("asserting int. (q=%d)\n", i);
525             qemu_set_irq(s->irq[i], 1);
526         }
527     }
528 }
529 
530 /*
531  * gem_receive_updatestats:
532  * Increment receive statistics.
533  */
534 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
535                                     unsigned bytes)
536 {
537     uint64_t octets;
538 
539     /* Total octets (bytes) received */
540     octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
541              s->regs[GEM_OCTRXHI];
542     octets += bytes;
543     s->regs[GEM_OCTRXLO] = octets >> 32;
544     s->regs[GEM_OCTRXHI] = octets;
545 
546     /* Error-free Frames received */
547     s->regs[GEM_RXCNT]++;
548 
549     /* Error-free Broadcast Frames counter */
550     if (!memcmp(packet, broadcast_addr, 6)) {
551         s->regs[GEM_RXBROADCNT]++;
552     }
553 
554     /* Error-free Multicast Frames counter */
555     if (packet[0] == 0x01) {
556         s->regs[GEM_RXMULTICNT]++;
557     }
558 
559     if (bytes <= 64) {
560         s->regs[GEM_RX64CNT]++;
561     } else if (bytes <= 127) {
562         s->regs[GEM_RX65CNT]++;
563     } else if (bytes <= 255) {
564         s->regs[GEM_RX128CNT]++;
565     } else if (bytes <= 511) {
566         s->regs[GEM_RX256CNT]++;
567     } else if (bytes <= 1023) {
568         s->regs[GEM_RX512CNT]++;
569     } else if (bytes <= 1518) {
570         s->regs[GEM_RX1024CNT]++;
571     } else {
572         s->regs[GEM_RX1519CNT]++;
573     }
574 }
575 
576 /*
577  * Get the MAC Address bit from the specified position
578  */
579 static unsigned get_bit(const uint8_t *mac, unsigned bit)
580 {
581     unsigned byte;
582 
583     byte = mac[bit / 8];
584     byte >>= (bit & 0x7);
585     byte &= 1;
586 
587     return byte;
588 }
589 
590 /*
591  * Calculate a GEM MAC Address hash index
592  */
593 static unsigned calc_mac_hash(const uint8_t *mac)
594 {
595     int index_bit, mac_bit;
596     unsigned hash_index;
597 
598     hash_index = 0;
599     mac_bit = 5;
600     for (index_bit = 5; index_bit >= 0; index_bit--) {
601         hash_index |= (get_bit(mac,  mac_bit) ^
602                                get_bit(mac, mac_bit + 6) ^
603                                get_bit(mac, mac_bit + 12) ^
604                                get_bit(mac, mac_bit + 18) ^
605                                get_bit(mac, mac_bit + 24) ^
606                                get_bit(mac, mac_bit + 30) ^
607                                get_bit(mac, mac_bit + 36) ^
608                                get_bit(mac, mac_bit + 42)) << index_bit;
609         mac_bit--;
610     }
611 
612     return hash_index;
613 }
614 
615 /*
616  * gem_mac_address_filter:
617  * Accept or reject this destination address?
618  * Returns:
619  * GEM_RX_REJECT: reject
620  * >= 0: Specific address accept (which matched SAR is returned)
621  * others for various other modes of accept:
622  * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
623  * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
624  */
625 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
626 {
627     uint8_t *gem_spaddr;
628     int i;
629 
630     /* Promiscuous mode? */
631     if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
632         return GEM_RX_PROMISCUOUS_ACCEPT;
633     }
634 
635     if (!memcmp(packet, broadcast_addr, 6)) {
636         /* Reject broadcast packets? */
637         if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
638             return GEM_RX_REJECT;
639         }
640         return GEM_RX_BROADCAST_ACCEPT;
641     }
642 
643     /* Accept packets -w- hash match? */
644     if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
645         (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
646         unsigned hash_index;
647 
648         hash_index = calc_mac_hash(packet);
649         if (hash_index < 32) {
650             if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
651                 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
652                                            GEM_RX_UNICAST_HASH_ACCEPT;
653             }
654         } else {
655             hash_index -= 32;
656             if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
657                 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
658                                            GEM_RX_UNICAST_HASH_ACCEPT;
659             }
660         }
661     }
662 
663     /* Check all 4 specific addresses */
664     gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
665     for (i = 3; i >= 0; i--) {
666         if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
667             return GEM_RX_SAR_ACCEPT + i;
668         }
669     }
670 
671     /* No address match; reject the packet */
672     return GEM_RX_REJECT;
673 }
674 
675 /* Figure out which queue the received data should be sent to */
676 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
677                                  unsigned rxbufsize)
678 {
679     uint32_t reg;
680     bool matched, mismatched;
681     int i, j;
682 
683     for (i = 0; i < s->num_type1_screeners; i++) {
684         reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
685         matched = false;
686         mismatched = false;
687 
688         /* Screening is based on UDP Port */
689         if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
690             uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
691             if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
692                                            GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
693                 matched = true;
694             } else {
695                 mismatched = true;
696             }
697         }
698 
699         /* Screening is based on DS/TC */
700         if (reg & GEM_ST1R_DSTC_ENABLE) {
701             uint8_t dscp = rxbuf_ptr[14 + 1];
702             if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
703                                        GEM_ST1R_DSTC_MATCH_WIDTH)) {
704                 matched = true;
705             } else {
706                 mismatched = true;
707             }
708         }
709 
710         if (matched && !mismatched) {
711             return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
712         }
713     }
714 
715     for (i = 0; i < s->num_type2_screeners; i++) {
716         reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
717         matched = false;
718         mismatched = false;
719 
720         if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
721             uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
722             int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
723                                         GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
724 
725             if (et_idx > s->num_type2_screeners) {
726                 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
727                               "register index: %d\n", et_idx);
728             }
729             if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
730                                 et_idx]) {
731                 matched = true;
732             } else {
733                 mismatched = true;
734             }
735         }
736 
737         /* Compare A, B, C */
738         for (j = 0; j < 3; j++) {
739             uint32_t cr0, cr1, mask;
740             uint16_t rx_cmp;
741             int offset;
742             int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
743                                         GEM_ST2R_COMPARE_WIDTH);
744 
745             if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
746                 continue;
747             }
748             if (cr_idx > s->num_type2_screeners) {
749                 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
750                               "register index: %d\n", cr_idx);
751             }
752 
753             cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
754             cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
755             offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
756                                     GEM_T2CW1_OFFSET_VALUE_WIDTH);
757 
758             switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
759                                    GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
760             case 3: /* Skip UDP header */
761                 qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
762                               "unimplemented - assuming UDP\n");
763                 offset += 8;
764                 /* Fallthrough */
765             case 2: /* skip the IP header */
766                 offset += 20;
767                 /* Fallthrough */
768             case 1: /* Count from after the ethertype */
769                 offset += 14;
770                 break;
771             case 0:
772                 /* Offset from start of frame */
773                 break;
774             }
775 
776             rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
777             mask = extract32(cr0, 0, 16);
778 
779             if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
780                 matched = true;
781             } else {
782                 mismatched = true;
783             }
784         }
785 
786         if (matched && !mismatched) {
787             return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
788         }
789     }
790 
791     /* We made it here, assume it's queue 0 */
792     return 0;
793 }
794 
795 static void gem_get_rx_desc(CadenceGEMState *s, int q)
796 {
797     DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
798     /* read current descriptor */
799     cpu_physical_memory_read(s->rx_desc_addr[0],
800                              (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0]));
801 
802     /* Descriptor owned by software ? */
803     if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
804         DB_PRINT("descriptor 0x%x owned by sw.\n",
805                  (unsigned)s->rx_desc_addr[q]);
806         s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
807         s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
808         /* Handle interrupt consequences */
809         gem_update_int_status(s);
810     }
811 }
812 
813 /*
814  * gem_receive:
815  * Fit a packet handed to us by QEMU into the receive descriptor ring.
816  */
817 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
818 {
819     CadenceGEMState *s;
820     unsigned   rxbufsize, bytes_to_copy;
821     unsigned   rxbuf_offset;
822     uint8_t    rxbuf[2048];
823     uint8_t   *rxbuf_ptr;
824     bool first_desc = true;
825     int maf;
826     int q = 0;
827 
828     s = qemu_get_nic_opaque(nc);
829 
830     /* Is this destination MAC address "for us" ? */
831     maf = gem_mac_address_filter(s, buf);
832     if (maf == GEM_RX_REJECT) {
833         return -1;
834     }
835 
836     /* Discard packets with receive length error enabled ? */
837     if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
838         unsigned type_len;
839 
840         /* Fish the ethertype / length field out of the RX packet */
841         type_len = buf[12] << 8 | buf[13];
842         /* It is a length field, not an ethertype */
843         if (type_len < 0x600) {
844             if (size < type_len) {
845                 /* discard */
846                 return -1;
847             }
848         }
849     }
850 
851     /*
852      * Determine configured receive buffer offset (probably 0)
853      */
854     rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
855                    GEM_NWCFG_BUFF_OFST_S;
856 
857     /* The configure size of each receive buffer.  Determines how many
858      * buffers needed to hold this packet.
859      */
860     rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
861                  GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
862     bytes_to_copy = size;
863 
864     /* Hardware allows a zero value here but warns against it. To avoid QEMU
865      * indefinite loops we enforce a minimum value here
866      */
867     if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
868         rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
869     }
870 
871     /* Pad to minimum length. Assume FCS field is stripped, logic
872      * below will increment it to the real minimum of 64 when
873      * not FCS stripping
874      */
875     if (size < 60) {
876         size = 60;
877     }
878 
879     /* Strip of FCS field ? (usually yes) */
880     if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
881         rxbuf_ptr = (void *)buf;
882     } else {
883         unsigned crc_val;
884 
885         if (size > sizeof(rxbuf) - sizeof(crc_val)) {
886             size = sizeof(rxbuf) - sizeof(crc_val);
887         }
888         bytes_to_copy = size;
889         /* The application wants the FCS field, which QEMU does not provide.
890          * We must try and calculate one.
891          */
892 
893         memcpy(rxbuf, buf, size);
894         memset(rxbuf + size, 0, sizeof(rxbuf) - size);
895         rxbuf_ptr = rxbuf;
896         crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
897         memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
898 
899         bytes_to_copy += 4;
900         size += 4;
901     }
902 
903     DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
904 
905     /* Find which queue we are targetting */
906     q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
907 
908     while (bytes_to_copy) {
909         /* Do nothing if receive is not enabled. */
910         if (!gem_can_receive(nc)) {
911             assert(!first_desc);
912             return -1;
913         }
914 
915         DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
916                 rx_desc_get_buffer(s->rx_desc[q]));
917 
918         /* Copy packet data to emulated DMA buffer */
919         cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) +
920                                                                  rxbuf_offset,
921                                   rxbuf_ptr, MIN(bytes_to_copy, rxbufsize));
922         rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
923         bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
924 
925         /* Update the descriptor.  */
926         if (first_desc) {
927             rx_desc_set_sof(s->rx_desc[q]);
928             first_desc = false;
929         }
930         if (bytes_to_copy == 0) {
931             rx_desc_set_eof(s->rx_desc[q]);
932             rx_desc_set_length(s->rx_desc[q], size);
933         }
934         rx_desc_set_ownership(s->rx_desc[q]);
935 
936         switch (maf) {
937         case GEM_RX_PROMISCUOUS_ACCEPT:
938             break;
939         case GEM_RX_BROADCAST_ACCEPT:
940             rx_desc_set_broadcast(s->rx_desc[q]);
941             break;
942         case GEM_RX_UNICAST_HASH_ACCEPT:
943             rx_desc_set_unicast_hash(s->rx_desc[q]);
944             break;
945         case GEM_RX_MULTICAST_HASH_ACCEPT:
946             rx_desc_set_multicast_hash(s->rx_desc[q]);
947             break;
948         case GEM_RX_REJECT:
949             abort();
950         default: /* SAR */
951             rx_desc_set_sar(s->rx_desc[q], maf);
952         }
953 
954         /* Descriptor write-back.  */
955         cpu_physical_memory_write(s->rx_desc_addr[q],
956                                   (uint8_t *)s->rx_desc[q],
957                                   sizeof(s->rx_desc[q]));
958 
959         /* Next descriptor */
960         if (rx_desc_get_wrap(s->rx_desc[q])) {
961             DB_PRINT("wrapping RX descriptor list\n");
962             s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
963         } else {
964             DB_PRINT("incrementing RX descriptor list\n");
965             s->rx_desc_addr[q] += 8;
966         }
967 
968         gem_get_rx_desc(s, q);
969     }
970 
971     /* Count it */
972     gem_receive_updatestats(s, buf, size);
973 
974     s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
975     s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
976 
977     /* Handle interrupt consequences */
978     gem_update_int_status(s);
979 
980     return size;
981 }
982 
983 /*
984  * gem_transmit_updatestats:
985  * Increment transmit statistics.
986  */
987 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
988                                      unsigned bytes)
989 {
990     uint64_t octets;
991 
992     /* Total octets (bytes) transmitted */
993     octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
994              s->regs[GEM_OCTTXHI];
995     octets += bytes;
996     s->regs[GEM_OCTTXLO] = octets >> 32;
997     s->regs[GEM_OCTTXHI] = octets;
998 
999     /* Error-free Frames transmitted */
1000     s->regs[GEM_TXCNT]++;
1001 
1002     /* Error-free Broadcast Frames counter */
1003     if (!memcmp(packet, broadcast_addr, 6)) {
1004         s->regs[GEM_TXBCNT]++;
1005     }
1006 
1007     /* Error-free Multicast Frames counter */
1008     if (packet[0] == 0x01) {
1009         s->regs[GEM_TXMCNT]++;
1010     }
1011 
1012     if (bytes <= 64) {
1013         s->regs[GEM_TX64CNT]++;
1014     } else if (bytes <= 127) {
1015         s->regs[GEM_TX65CNT]++;
1016     } else if (bytes <= 255) {
1017         s->regs[GEM_TX128CNT]++;
1018     } else if (bytes <= 511) {
1019         s->regs[GEM_TX256CNT]++;
1020     } else if (bytes <= 1023) {
1021         s->regs[GEM_TX512CNT]++;
1022     } else if (bytes <= 1518) {
1023         s->regs[GEM_TX1024CNT]++;
1024     } else {
1025         s->regs[GEM_TX1519CNT]++;
1026     }
1027 }
1028 
1029 /*
1030  * gem_transmit:
1031  * Fish packets out of the descriptor ring and feed them to QEMU
1032  */
1033 static void gem_transmit(CadenceGEMState *s)
1034 {
1035     unsigned    desc[2];
1036     hwaddr packet_desc_addr;
1037     uint8_t     tx_packet[2048];
1038     uint8_t     *p;
1039     unsigned    total_bytes;
1040     int q = 0;
1041 
1042     /* Do nothing if transmit is not enabled. */
1043     if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1044         return;
1045     }
1046 
1047     DB_PRINT("\n");
1048 
1049     /* The packet we will hand off to QEMU.
1050      * Packets scattered across multiple descriptors are gathered to this
1051      * one contiguous buffer first.
1052      */
1053     p = tx_packet;
1054     total_bytes = 0;
1055 
1056     for (q = s->num_priority_queues - 1; q >= 0; q--) {
1057         /* read current descriptor */
1058         packet_desc_addr = s->tx_desc_addr[q];
1059 
1060         DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1061         cpu_physical_memory_read(packet_desc_addr,
1062                                  (uint8_t *)desc, sizeof(desc));
1063         /* Handle all descriptors owned by hardware */
1064         while (tx_desc_get_used(desc) == 0) {
1065 
1066             /* Do nothing if transmit is not enabled. */
1067             if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1068                 return;
1069             }
1070             print_gem_tx_desc(desc, q);
1071 
1072             /* The real hardware would eat this (and possibly crash).
1073              * For QEMU let's lend a helping hand.
1074              */
1075             if ((tx_desc_get_buffer(desc) == 0) ||
1076                 (tx_desc_get_length(desc) == 0)) {
1077                 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
1078                          (unsigned)packet_desc_addr);
1079                 break;
1080             }
1081 
1082             if (tx_desc_get_length(desc) > sizeof(tx_packet) -
1083                                                (p - tx_packet)) {
1084                 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
1085                          "0x%x\n", (unsigned)packet_desc_addr,
1086                          (unsigned)tx_desc_get_length(desc),
1087                          sizeof(tx_packet) - (p - tx_packet));
1088                 break;
1089             }
1090 
1091             /* Gather this fragment of the packet from "dma memory" to our
1092              * contig buffer.
1093              */
1094             cpu_physical_memory_read(tx_desc_get_buffer(desc), p,
1095                                      tx_desc_get_length(desc));
1096             p += tx_desc_get_length(desc);
1097             total_bytes += tx_desc_get_length(desc);
1098 
1099             /* Last descriptor for this packet; hand the whole thing off */
1100             if (tx_desc_get_last(desc)) {
1101                 unsigned    desc_first[2];
1102 
1103                 /* Modify the 1st descriptor of this packet to be owned by
1104                  * the processor.
1105                  */
1106                 cpu_physical_memory_read(s->tx_desc_addr[q],
1107                                          (uint8_t *)desc_first,
1108                                          sizeof(desc_first));
1109                 tx_desc_set_used(desc_first);
1110                 cpu_physical_memory_write(s->tx_desc_addr[q],
1111                                           (uint8_t *)desc_first,
1112                                           sizeof(desc_first));
1113                 /* Advance the hardware current descriptor past this packet */
1114                 if (tx_desc_get_wrap(desc)) {
1115                     s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
1116                 } else {
1117                     s->tx_desc_addr[q] = packet_desc_addr + 8;
1118                 }
1119                 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
1120 
1121                 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
1122                 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
1123 
1124                 /* Update queue interrupt status */
1125                 if (s->num_priority_queues > 1) {
1126                     s->regs[GEM_INT_Q1_STATUS + q] |=
1127                             GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
1128                 }
1129 
1130                 /* Handle interrupt consequences */
1131                 gem_update_int_status(s);
1132 
1133                 /* Is checksum offload enabled? */
1134                 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
1135                     net_checksum_calculate(tx_packet, total_bytes);
1136                 }
1137 
1138                 /* Update MAC statistics */
1139                 gem_transmit_updatestats(s, tx_packet, total_bytes);
1140 
1141                 /* Send the packet somewhere */
1142                 if (s->phy_loop || (s->regs[GEM_NWCTRL] &
1143                                     GEM_NWCTRL_LOCALLOOP)) {
1144                     gem_receive(qemu_get_queue(s->nic), tx_packet,
1145                                 total_bytes);
1146                 } else {
1147                     qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
1148                                      total_bytes);
1149                 }
1150 
1151                 /* Prepare for next packet */
1152                 p = tx_packet;
1153                 total_bytes = 0;
1154             }
1155 
1156             /* read next descriptor */
1157             if (tx_desc_get_wrap(desc)) {
1158                 tx_desc_set_last(desc);
1159                 packet_desc_addr = s->regs[GEM_TXQBASE];
1160             } else {
1161                 packet_desc_addr += 8;
1162             }
1163             DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1164             cpu_physical_memory_read(packet_desc_addr,
1165                                      (uint8_t *)desc, sizeof(desc));
1166         }
1167 
1168         if (tx_desc_get_used(desc)) {
1169             s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
1170             s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
1171             gem_update_int_status(s);
1172         }
1173     }
1174 }
1175 
1176 static void gem_phy_reset(CadenceGEMState *s)
1177 {
1178     memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
1179     s->phy_regs[PHY_REG_CONTROL] = 0x1140;
1180     s->phy_regs[PHY_REG_STATUS] = 0x7969;
1181     s->phy_regs[PHY_REG_PHYID1] = 0x0141;
1182     s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
1183     s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
1184     s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
1185     s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
1186     s->phy_regs[PHY_REG_NEXTP] = 0x2001;
1187     s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
1188     s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
1189     s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
1190     s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
1191     s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
1192     s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
1193     s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
1194     s->phy_regs[PHY_REG_LED] = 0x4100;
1195     s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
1196     s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
1197 
1198     phy_update_link(s);
1199 }
1200 
1201 static void gem_reset(DeviceState *d)
1202 {
1203     int i;
1204     CadenceGEMState *s = CADENCE_GEM(d);
1205     const uint8_t *a;
1206 
1207     DB_PRINT("\n");
1208 
1209     /* Set post reset register values */
1210     memset(&s->regs[0], 0, sizeof(s->regs));
1211     s->regs[GEM_NWCFG] = 0x00080000;
1212     s->regs[GEM_NWSTATUS] = 0x00000006;
1213     s->regs[GEM_DMACFG] = 0x00020784;
1214     s->regs[GEM_IMR] = 0x07ffffff;
1215     s->regs[GEM_TXPAUSE] = 0x0000ffff;
1216     s->regs[GEM_TXPARTIALSF] = 0x000003ff;
1217     s->regs[GEM_RXPARTIALSF] = 0x000003ff;
1218     s->regs[GEM_MODID] = 0x00020118;
1219     s->regs[GEM_DESCONF] = 0x02500111;
1220     s->regs[GEM_DESCONF2] = 0x2ab13fff;
1221     s->regs[GEM_DESCONF5] = 0x002f2145;
1222     s->regs[GEM_DESCONF6] = 0x00000200;
1223 
1224     /* Set MAC address */
1225     a = &s->conf.macaddr.a[0];
1226     s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1227     s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1228 
1229     for (i = 0; i < 4; i++) {
1230         s->sar_active[i] = false;
1231     }
1232 
1233     gem_phy_reset(s);
1234 
1235     gem_update_int_status(s);
1236 }
1237 
1238 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
1239 {
1240     DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
1241     return s->phy_regs[reg_num];
1242 }
1243 
1244 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
1245 {
1246     DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
1247 
1248     switch (reg_num) {
1249     case PHY_REG_CONTROL:
1250         if (val & PHY_REG_CONTROL_RST) {
1251             /* Phy reset */
1252             gem_phy_reset(s);
1253             val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
1254             s->phy_loop = 0;
1255         }
1256         if (val & PHY_REG_CONTROL_ANEG) {
1257             /* Complete autonegotiation immediately */
1258             val &= ~PHY_REG_CONTROL_ANEG;
1259             s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
1260         }
1261         if (val & PHY_REG_CONTROL_LOOP) {
1262             DB_PRINT("PHY placed in loopback\n");
1263             s->phy_loop = 1;
1264         } else {
1265             s->phy_loop = 0;
1266         }
1267         break;
1268     }
1269     s->phy_regs[reg_num] = val;
1270 }
1271 
1272 /*
1273  * gem_read32:
1274  * Read a GEM register.
1275  */
1276 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1277 {
1278     CadenceGEMState *s;
1279     uint32_t retval;
1280     int i;
1281     s = (CadenceGEMState *)opaque;
1282 
1283     offset >>= 2;
1284     retval = s->regs[offset];
1285 
1286     DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1287 
1288     switch (offset) {
1289     case GEM_ISR:
1290         DB_PRINT("lowering irqs on ISR read\n");
1291         for (i = 0; i < s->num_priority_queues; ++i) {
1292             qemu_set_irq(s->irq[i], 0);
1293         }
1294         break;
1295     case GEM_PHYMNTNC:
1296         if (retval & GEM_PHYMNTNC_OP_R) {
1297             uint32_t phy_addr, reg_num;
1298 
1299             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1300             if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1301                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1302                 retval &= 0xFFFF0000;
1303                 retval |= gem_phy_read(s, reg_num);
1304             } else {
1305                 retval |= 0xFFFF; /* No device at this address */
1306             }
1307         }
1308         break;
1309     }
1310 
1311     /* Squash read to clear bits */
1312     s->regs[offset] &= ~(s->regs_rtc[offset]);
1313 
1314     /* Do not provide write only bits */
1315     retval &= ~(s->regs_wo[offset]);
1316 
1317     DB_PRINT("0x%08x\n", retval);
1318     gem_update_int_status(s);
1319     return retval;
1320 }
1321 
1322 /*
1323  * gem_write32:
1324  * Write a GEM register.
1325  */
1326 static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1327         unsigned size)
1328 {
1329     CadenceGEMState *s = (CadenceGEMState *)opaque;
1330     uint32_t readonly;
1331     int i;
1332 
1333     DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1334     offset >>= 2;
1335 
1336     /* Squash bits which are read only in write value */
1337     val &= ~(s->regs_ro[offset]);
1338     /* Preserve (only) bits which are read only and wtc in register */
1339     readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1340 
1341     /* Copy register write to backing store */
1342     s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1343 
1344     /* do w1c */
1345     s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1346 
1347     /* Handle register write side effects */
1348     switch (offset) {
1349     case GEM_NWCTRL:
1350         if (val & GEM_NWCTRL_RXENA) {
1351             for (i = 0; i < s->num_priority_queues; ++i) {
1352                 gem_get_rx_desc(s, i);
1353             }
1354         }
1355         if (val & GEM_NWCTRL_TXSTART) {
1356             gem_transmit(s);
1357         }
1358         if (!(val & GEM_NWCTRL_TXENA)) {
1359             /* Reset to start of Q when transmit disabled. */
1360             for (i = 0; i < s->num_priority_queues; i++) {
1361                 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
1362             }
1363         }
1364         if (gem_can_receive(qemu_get_queue(s->nic))) {
1365             qemu_flush_queued_packets(qemu_get_queue(s->nic));
1366         }
1367         break;
1368 
1369     case GEM_TXSTATUS:
1370         gem_update_int_status(s);
1371         break;
1372     case GEM_RXQBASE:
1373         s->rx_desc_addr[0] = val;
1374         break;
1375     case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q15_PTR:
1376         s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
1377         break;
1378     case GEM_TXQBASE:
1379         s->tx_desc_addr[0] = val;
1380         break;
1381     case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q15_PTR:
1382         s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
1383         break;
1384     case GEM_RXSTATUS:
1385         gem_update_int_status(s);
1386         break;
1387     case GEM_IER:
1388         s->regs[GEM_IMR] &= ~val;
1389         gem_update_int_status(s);
1390         break;
1391     case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
1392         s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
1393         gem_update_int_status(s);
1394         break;
1395     case GEM_INT_Q8_ENABLE ... GEM_INT_Q15_ENABLE:
1396         s->regs[GEM_INT_Q8_MASK + offset - GEM_INT_Q8_ENABLE] &= ~val;
1397         gem_update_int_status(s);
1398         break;
1399     case GEM_IDR:
1400         s->regs[GEM_IMR] |= val;
1401         gem_update_int_status(s);
1402         break;
1403     case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
1404         s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
1405         gem_update_int_status(s);
1406         break;
1407     case GEM_INT_Q8_DISABLE ... GEM_INT_Q15_DISABLE:
1408         s->regs[GEM_INT_Q8_MASK + offset - GEM_INT_Q8_DISABLE] |= val;
1409         gem_update_int_status(s);
1410         break;
1411     case GEM_SPADDR1LO:
1412     case GEM_SPADDR2LO:
1413     case GEM_SPADDR3LO:
1414     case GEM_SPADDR4LO:
1415         s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1416         break;
1417     case GEM_SPADDR1HI:
1418     case GEM_SPADDR2HI:
1419     case GEM_SPADDR3HI:
1420     case GEM_SPADDR4HI:
1421         s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1422         break;
1423     case GEM_PHYMNTNC:
1424         if (val & GEM_PHYMNTNC_OP_W) {
1425             uint32_t phy_addr, reg_num;
1426 
1427             phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1428             if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1429                 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1430                 gem_phy_write(s, reg_num, val);
1431             }
1432         }
1433         break;
1434     }
1435 
1436     DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1437 }
1438 
1439 static const MemoryRegionOps gem_ops = {
1440     .read = gem_read,
1441     .write = gem_write,
1442     .endianness = DEVICE_LITTLE_ENDIAN,
1443 };
1444 
1445 static void gem_set_link(NetClientState *nc)
1446 {
1447     CadenceGEMState *s = qemu_get_nic_opaque(nc);
1448 
1449     DB_PRINT("\n");
1450     phy_update_link(s);
1451     gem_update_int_status(s);
1452 }
1453 
1454 static NetClientInfo net_gem_info = {
1455     .type = NET_CLIENT_DRIVER_NIC,
1456     .size = sizeof(NICState),
1457     .can_receive = gem_can_receive,
1458     .receive = gem_receive,
1459     .link_status_changed = gem_set_link,
1460 };
1461 
1462 static void gem_realize(DeviceState *dev, Error **errp)
1463 {
1464     CadenceGEMState *s = CADENCE_GEM(dev);
1465     int i;
1466 
1467     if (s->num_priority_queues == 0 ||
1468         s->num_priority_queues > MAX_PRIORITY_QUEUES) {
1469         error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
1470                    s->num_priority_queues);
1471         return;
1472     } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
1473         error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8,
1474                    s->num_type1_screeners);
1475         return;
1476     } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
1477         error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8,
1478                    s->num_type2_screeners);
1479         return;
1480     }
1481 
1482     for (i = 0; i < s->num_priority_queues; ++i) {
1483         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1484     }
1485 
1486     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1487 
1488     s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1489                           object_get_typename(OBJECT(dev)), dev->id, s);
1490 }
1491 
1492 static void gem_init(Object *obj)
1493 {
1494     CadenceGEMState *s = CADENCE_GEM(obj);
1495     DeviceState *dev = DEVICE(obj);
1496 
1497     DB_PRINT("\n");
1498 
1499     gem_init_register_masks(s);
1500     memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1501                           "enet", sizeof(s->regs));
1502 
1503     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1504 }
1505 
1506 static const VMStateDescription vmstate_cadence_gem = {
1507     .name = "cadence_gem",
1508     .version_id = 4,
1509     .minimum_version_id = 4,
1510     .fields = (VMStateField[]) {
1511         VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1512         VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
1513         VMSTATE_UINT8(phy_loop, CadenceGEMState),
1514         VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
1515                              MAX_PRIORITY_QUEUES),
1516         VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
1517                              MAX_PRIORITY_QUEUES),
1518         VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1519         VMSTATE_END_OF_LIST(),
1520     }
1521 };
1522 
1523 static Property gem_properties[] = {
1524     DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1525     DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1526                       num_priority_queues, 1),
1527     DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
1528                       num_type1_screeners, 4),
1529     DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
1530                       num_type2_screeners, 4),
1531     DEFINE_PROP_END_OF_LIST(),
1532 };
1533 
1534 static void gem_class_init(ObjectClass *klass, void *data)
1535 {
1536     DeviceClass *dc = DEVICE_CLASS(klass);
1537 
1538     dc->realize = gem_realize;
1539     dc->props = gem_properties;
1540     dc->vmsd = &vmstate_cadence_gem;
1541     dc->reset = gem_reset;
1542 }
1543 
1544 static const TypeInfo gem_info = {
1545     .name  = TYPE_CADENCE_GEM,
1546     .parent = TYPE_SYS_BUS_DEVICE,
1547     .instance_size  = sizeof(CadenceGEMState),
1548     .instance_init = gem_init,
1549     .class_init = gem_class_init,
1550 };
1551 
1552 static void gem_register_types(void)
1553 {
1554     type_register_static(&gem_info);
1555 }
1556 
1557 type_init(gem_register_types)
1558