1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/net/cadence_gem.h" 29 #include "qapi/error.h" 30 #include "qemu/log.h" 31 #include "net/checksum.h" 32 33 #ifdef CADENCE_GEM_ERR_DEBUG 34 #define DB_PRINT(...) do { \ 35 fprintf(stderr, ": %s: ", __func__); \ 36 fprintf(stderr, ## __VA_ARGS__); \ 37 } while (0); 38 #else 39 #define DB_PRINT(...) 40 #endif 41 42 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 43 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 44 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 45 #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 46 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 47 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 48 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 49 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 50 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 51 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 52 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 53 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 54 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 55 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 56 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 57 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 58 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 59 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 60 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 61 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 62 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 63 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 64 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 65 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 66 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 67 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 68 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 69 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 70 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 71 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 72 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 73 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 74 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 75 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 76 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 77 #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 78 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 79 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 80 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 81 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 82 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 83 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 84 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 85 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 86 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 87 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 88 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 89 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 90 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 91 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 92 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 93 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 94 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 95 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 96 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 97 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 98 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 99 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 100 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 101 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 102 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 103 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 104 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 105 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 106 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 107 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 108 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 109 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 110 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 111 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 112 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 113 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 114 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 115 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 116 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 117 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 118 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 119 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 120 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 121 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 122 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 123 124 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 125 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 126 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 127 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 128 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 129 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 130 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 131 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 132 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 133 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 134 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 135 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 136 137 /* Design Configuration Registers */ 138 #define GEM_DESCONF (0x00000280/4) 139 #define GEM_DESCONF2 (0x00000284/4) 140 #define GEM_DESCONF3 (0x00000288/4) 141 #define GEM_DESCONF4 (0x0000028C/4) 142 #define GEM_DESCONF5 (0x00000290/4) 143 #define GEM_DESCONF6 (0x00000294/4) 144 #define GEM_DESCONF7 (0x00000298/4) 145 146 #define GEM_INT_Q1_STATUS (0x00000400 / 4) 147 #define GEM_INT_Q1_MASK (0x00000640 / 4) 148 149 #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 150 #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 151 152 #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 153 #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 154 155 #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 156 #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 157 158 #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 159 #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 160 161 #define GEM_INT_Q1_MASK (0x00000640 / 4) 162 #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 163 164 #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 165 166 #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 167 #define GEM_ST1R_DSTC_ENABLE (1 << 28) 168 #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 169 #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 170 #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 171 #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 172 #define GEM_ST1R_QUEUE_SHIFT (0) 173 #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 174 175 #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 176 177 #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 178 #define GEM_ST2R_COMPARE_A_SHIFT (13) 179 #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 180 #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 181 #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 182 #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 183 + 1) 184 #define GEM_ST2R_QUEUE_SHIFT (0) 185 #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 186 187 #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 188 #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 189 190 #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 191 #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 192 #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 193 #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 194 195 /*****************************************/ 196 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 197 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 198 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 199 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 200 201 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 202 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 203 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 204 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 205 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 206 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 207 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 208 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 209 210 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 211 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 212 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 213 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 214 215 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 216 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 217 218 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 219 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 220 221 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 222 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 223 #define GEM_INT_TXUSED 0x00000008 224 #define GEM_INT_RXUSED 0x00000004 225 #define GEM_INT_RXCMPL 0x00000002 226 227 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 228 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 229 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 230 #define GEM_PHYMNTNC_ADDR_SHFT 23 231 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 232 #define GEM_PHYMNTNC_REG_SHIFT 18 233 234 /* Marvell PHY definitions */ 235 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 236 237 #define PHY_REG_CONTROL 0 238 #define PHY_REG_STATUS 1 239 #define PHY_REG_PHYID1 2 240 #define PHY_REG_PHYID2 3 241 #define PHY_REG_ANEGADV 4 242 #define PHY_REG_LINKPABIL 5 243 #define PHY_REG_ANEGEXP 6 244 #define PHY_REG_NEXTP 7 245 #define PHY_REG_LINKPNEXTP 8 246 #define PHY_REG_100BTCTRL 9 247 #define PHY_REG_1000BTSTAT 10 248 #define PHY_REG_EXTSTAT 15 249 #define PHY_REG_PHYSPCFC_CTL 16 250 #define PHY_REG_PHYSPCFC_ST 17 251 #define PHY_REG_INT_EN 18 252 #define PHY_REG_INT_ST 19 253 #define PHY_REG_EXT_PHYSPCFC_CTL 20 254 #define PHY_REG_RXERR 21 255 #define PHY_REG_EACD 22 256 #define PHY_REG_LED 24 257 #define PHY_REG_LED_OVRD 25 258 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 259 #define PHY_REG_EXT_PHYSPCFC_ST 27 260 #define PHY_REG_CABLE_DIAG 28 261 262 #define PHY_REG_CONTROL_RST 0x8000 263 #define PHY_REG_CONTROL_LOOP 0x4000 264 #define PHY_REG_CONTROL_ANEG 0x1000 265 266 #define PHY_REG_STATUS_LINK 0x0004 267 #define PHY_REG_STATUS_ANEGCMPL 0x0020 268 269 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 270 #define PHY_REG_INT_ST_LINKC 0x0400 271 #define PHY_REG_INT_ST_ENERGY 0x0010 272 273 /***********************************************************************/ 274 #define GEM_RX_REJECT (-1) 275 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 276 #define GEM_RX_BROADCAST_ACCEPT (-3) 277 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 278 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 279 280 #define GEM_RX_SAR_ACCEPT 0 281 282 /***********************************************************************/ 283 284 #define DESC_1_USED 0x80000000 285 #define DESC_1_LENGTH 0x00001FFF 286 287 #define DESC_1_TX_WRAP 0x40000000 288 #define DESC_1_TX_LAST 0x00008000 289 290 #define DESC_0_RX_WRAP 0x00000002 291 #define DESC_0_RX_OWNERSHIP 0x00000001 292 293 #define R_DESC_1_RX_SAR_SHIFT 25 294 #define R_DESC_1_RX_SAR_LENGTH 2 295 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 296 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 297 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 298 #define R_DESC_1_RX_BROADCAST (1 << 31) 299 300 #define DESC_1_RX_SOF 0x00004000 301 #define DESC_1_RX_EOF 0x00008000 302 303 static inline unsigned tx_desc_get_buffer(unsigned *desc) 304 { 305 return desc[0]; 306 } 307 308 static inline unsigned tx_desc_get_used(unsigned *desc) 309 { 310 return (desc[1] & DESC_1_USED) ? 1 : 0; 311 } 312 313 static inline void tx_desc_set_used(unsigned *desc) 314 { 315 desc[1] |= DESC_1_USED; 316 } 317 318 static inline unsigned tx_desc_get_wrap(unsigned *desc) 319 { 320 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 321 } 322 323 static inline unsigned tx_desc_get_last(unsigned *desc) 324 { 325 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 326 } 327 328 static inline void tx_desc_set_last(unsigned *desc) 329 { 330 desc[1] |= DESC_1_TX_LAST; 331 } 332 333 static inline unsigned tx_desc_get_length(unsigned *desc) 334 { 335 return desc[1] & DESC_1_LENGTH; 336 } 337 338 static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) 339 { 340 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 341 DB_PRINT("bufaddr: 0x%08x\n", *desc); 342 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 343 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 344 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 345 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 346 } 347 348 static inline unsigned rx_desc_get_buffer(unsigned *desc) 349 { 350 return desc[0] & ~0x3UL; 351 } 352 353 static inline unsigned rx_desc_get_wrap(unsigned *desc) 354 { 355 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 356 } 357 358 static inline unsigned rx_desc_get_ownership(unsigned *desc) 359 { 360 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 361 } 362 363 static inline void rx_desc_set_ownership(unsigned *desc) 364 { 365 desc[0] |= DESC_0_RX_OWNERSHIP; 366 } 367 368 static inline void rx_desc_set_sof(unsigned *desc) 369 { 370 desc[1] |= DESC_1_RX_SOF; 371 } 372 373 static inline void rx_desc_set_eof(unsigned *desc) 374 { 375 desc[1] |= DESC_1_RX_EOF; 376 } 377 378 static inline void rx_desc_set_length(unsigned *desc, unsigned len) 379 { 380 desc[1] &= ~DESC_1_LENGTH; 381 desc[1] |= len; 382 } 383 384 static inline void rx_desc_set_broadcast(unsigned *desc) 385 { 386 desc[1] |= R_DESC_1_RX_BROADCAST; 387 } 388 389 static inline void rx_desc_set_unicast_hash(unsigned *desc) 390 { 391 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 392 } 393 394 static inline void rx_desc_set_multicast_hash(unsigned *desc) 395 { 396 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 397 } 398 399 static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) 400 { 401 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 402 sar_idx); 403 desc[1] |= R_DESC_1_RX_SAR_MATCH; 404 } 405 406 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 407 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 408 409 /* 410 * gem_init_register_masks: 411 * One time initialization. 412 * Set masks to identify which register bits have magical clear properties 413 */ 414 static void gem_init_register_masks(CadenceGEMState *s) 415 { 416 /* Mask of register bits which are read only */ 417 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 418 s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 419 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 420 s->regs_ro[GEM_DMACFG] = 0xFE00F000; 421 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 422 s->regs_ro[GEM_RXQBASE] = 0x00000003; 423 s->regs_ro[GEM_TXQBASE] = 0x00000003; 424 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 425 s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 426 s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 427 s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 428 429 /* Mask of register bits which are clear on read */ 430 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 431 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 432 433 /* Mask of register bits which are write 1 to clear */ 434 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 435 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 436 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 437 438 /* Mask of register bits which are write only */ 439 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 440 s->regs_wo[GEM_NWCTRL] = 0x00073E60; 441 s->regs_wo[GEM_IER] = 0x07FFFFFF; 442 s->regs_wo[GEM_IDR] = 0x07FFFFFF; 443 } 444 445 /* 446 * phy_update_link: 447 * Make the emulated PHY link state match the QEMU "interface" state. 448 */ 449 static void phy_update_link(CadenceGEMState *s) 450 { 451 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 452 453 /* Autonegotiation status mirrors link status. */ 454 if (qemu_get_queue(s->nic)->link_down) { 455 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 456 PHY_REG_STATUS_LINK); 457 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 458 } else { 459 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 460 PHY_REG_STATUS_LINK); 461 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 462 PHY_REG_INT_ST_ANEGCMPL | 463 PHY_REG_INT_ST_ENERGY); 464 } 465 } 466 467 static int gem_can_receive(NetClientState *nc) 468 { 469 CadenceGEMState *s; 470 int i; 471 472 s = qemu_get_nic_opaque(nc); 473 474 /* Do nothing if receive is not enabled. */ 475 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 476 if (s->can_rx_state != 1) { 477 s->can_rx_state = 1; 478 DB_PRINT("can't receive - no enable\n"); 479 } 480 return 0; 481 } 482 483 for (i = 0; i < s->num_priority_queues; i++) { 484 if (rx_desc_get_ownership(s->rx_desc[i]) == 1) { 485 if (s->can_rx_state != 2) { 486 s->can_rx_state = 2; 487 DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n", 488 i, s->rx_desc_addr[i]); 489 } 490 return 0; 491 } 492 } 493 494 if (s->can_rx_state != 0) { 495 s->can_rx_state = 0; 496 DB_PRINT("can receive\n"); 497 } 498 return 1; 499 } 500 501 /* 502 * gem_update_int_status: 503 * Raise or lower interrupt based on current status. 504 */ 505 static void gem_update_int_status(CadenceGEMState *s) 506 { 507 int i; 508 509 if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) { 510 /* No priority queues, just trigger the interrupt */ 511 DB_PRINT("asserting int.\n", i); 512 qemu_set_irq(s->irq[0], 1); 513 return; 514 } 515 516 for (i = 0; i < s->num_priority_queues; ++i) { 517 if (s->regs[GEM_INT_Q1_STATUS + i]) { 518 DB_PRINT("asserting int. (q=%d)\n", i); 519 qemu_set_irq(s->irq[i], 1); 520 } 521 } 522 } 523 524 /* 525 * gem_receive_updatestats: 526 * Increment receive statistics. 527 */ 528 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 529 unsigned bytes) 530 { 531 uint64_t octets; 532 533 /* Total octets (bytes) received */ 534 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 535 s->regs[GEM_OCTRXHI]; 536 octets += bytes; 537 s->regs[GEM_OCTRXLO] = octets >> 32; 538 s->regs[GEM_OCTRXHI] = octets; 539 540 /* Error-free Frames received */ 541 s->regs[GEM_RXCNT]++; 542 543 /* Error-free Broadcast Frames counter */ 544 if (!memcmp(packet, broadcast_addr, 6)) { 545 s->regs[GEM_RXBROADCNT]++; 546 } 547 548 /* Error-free Multicast Frames counter */ 549 if (packet[0] == 0x01) { 550 s->regs[GEM_RXMULTICNT]++; 551 } 552 553 if (bytes <= 64) { 554 s->regs[GEM_RX64CNT]++; 555 } else if (bytes <= 127) { 556 s->regs[GEM_RX65CNT]++; 557 } else if (bytes <= 255) { 558 s->regs[GEM_RX128CNT]++; 559 } else if (bytes <= 511) { 560 s->regs[GEM_RX256CNT]++; 561 } else if (bytes <= 1023) { 562 s->regs[GEM_RX512CNT]++; 563 } else if (bytes <= 1518) { 564 s->regs[GEM_RX1024CNT]++; 565 } else { 566 s->regs[GEM_RX1519CNT]++; 567 } 568 } 569 570 /* 571 * Get the MAC Address bit from the specified position 572 */ 573 static unsigned get_bit(const uint8_t *mac, unsigned bit) 574 { 575 unsigned byte; 576 577 byte = mac[bit / 8]; 578 byte >>= (bit & 0x7); 579 byte &= 1; 580 581 return byte; 582 } 583 584 /* 585 * Calculate a GEM MAC Address hash index 586 */ 587 static unsigned calc_mac_hash(const uint8_t *mac) 588 { 589 int index_bit, mac_bit; 590 unsigned hash_index; 591 592 hash_index = 0; 593 mac_bit = 5; 594 for (index_bit = 5; index_bit >= 0; index_bit--) { 595 hash_index |= (get_bit(mac, mac_bit) ^ 596 get_bit(mac, mac_bit + 6) ^ 597 get_bit(mac, mac_bit + 12) ^ 598 get_bit(mac, mac_bit + 18) ^ 599 get_bit(mac, mac_bit + 24) ^ 600 get_bit(mac, mac_bit + 30) ^ 601 get_bit(mac, mac_bit + 36) ^ 602 get_bit(mac, mac_bit + 42)) << index_bit; 603 mac_bit--; 604 } 605 606 return hash_index; 607 } 608 609 /* 610 * gem_mac_address_filter: 611 * Accept or reject this destination address? 612 * Returns: 613 * GEM_RX_REJECT: reject 614 * >= 0: Specific address accept (which matched SAR is returned) 615 * others for various other modes of accept: 616 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 617 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 618 */ 619 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 620 { 621 uint8_t *gem_spaddr; 622 int i; 623 624 /* Promiscuous mode? */ 625 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 626 return GEM_RX_PROMISCUOUS_ACCEPT; 627 } 628 629 if (!memcmp(packet, broadcast_addr, 6)) { 630 /* Reject broadcast packets? */ 631 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 632 return GEM_RX_REJECT; 633 } 634 return GEM_RX_BROADCAST_ACCEPT; 635 } 636 637 /* Accept packets -w- hash match? */ 638 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 639 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 640 unsigned hash_index; 641 642 hash_index = calc_mac_hash(packet); 643 if (hash_index < 32) { 644 if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 645 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 646 GEM_RX_UNICAST_HASH_ACCEPT; 647 } 648 } else { 649 hash_index -= 32; 650 if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 651 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 652 GEM_RX_UNICAST_HASH_ACCEPT; 653 } 654 } 655 } 656 657 /* Check all 4 specific addresses */ 658 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 659 for (i = 3; i >= 0; i--) { 660 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 661 return GEM_RX_SAR_ACCEPT + i; 662 } 663 } 664 665 /* No address match; reject the packet */ 666 return GEM_RX_REJECT; 667 } 668 669 /* Figure out which queue the received data should be sent to */ 670 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 671 unsigned rxbufsize) 672 { 673 uint32_t reg; 674 bool matched, mismatched; 675 int i, j; 676 677 for (i = 0; i < s->num_type1_screeners; i++) { 678 reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 679 matched = false; 680 mismatched = false; 681 682 /* Screening is based on UDP Port */ 683 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 684 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 685 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 686 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 687 matched = true; 688 } else { 689 mismatched = true; 690 } 691 } 692 693 /* Screening is based on DS/TC */ 694 if (reg & GEM_ST1R_DSTC_ENABLE) { 695 uint8_t dscp = rxbuf_ptr[14 + 1]; 696 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 697 GEM_ST1R_DSTC_MATCH_WIDTH)) { 698 matched = true; 699 } else { 700 mismatched = true; 701 } 702 } 703 704 if (matched && !mismatched) { 705 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 706 } 707 } 708 709 for (i = 0; i < s->num_type2_screeners; i++) { 710 reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 711 matched = false; 712 mismatched = false; 713 714 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 715 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 716 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 717 GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 718 719 if (et_idx > s->num_type2_screeners) { 720 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 721 "register index: %d\n", et_idx); 722 } 723 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 724 et_idx]) { 725 matched = true; 726 } else { 727 mismatched = true; 728 } 729 } 730 731 /* Compare A, B, C */ 732 for (j = 0; j < 3; j++) { 733 uint32_t cr0, cr1, mask; 734 uint16_t rx_cmp; 735 int offset; 736 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 737 GEM_ST2R_COMPARE_WIDTH); 738 739 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 740 continue; 741 } 742 if (cr_idx > s->num_type2_screeners) { 743 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 744 "register index: %d\n", cr_idx); 745 } 746 747 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 748 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 749 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 750 GEM_T2CW1_OFFSET_VALUE_WIDTH); 751 752 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 753 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 754 case 3: /* Skip UDP header */ 755 qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 756 "unimplemented - assuming UDP\n"); 757 offset += 8; 758 /* Fallthrough */ 759 case 2: /* skip the IP header */ 760 offset += 20; 761 /* Fallthrough */ 762 case 1: /* Count from after the ethertype */ 763 offset += 14; 764 break; 765 case 0: 766 /* Offset from start of frame */ 767 break; 768 } 769 770 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 771 mask = extract32(cr0, 0, 16); 772 773 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 774 matched = true; 775 } else { 776 mismatched = true; 777 } 778 } 779 780 if (matched && !mismatched) { 781 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 782 } 783 } 784 785 /* We made it here, assume it's queue 0 */ 786 return 0; 787 } 788 789 static void gem_get_rx_desc(CadenceGEMState *s, int q) 790 { 791 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); 792 /* read current descriptor */ 793 cpu_physical_memory_read(s->rx_desc_addr[0], 794 (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0])); 795 796 /* Descriptor owned by software ? */ 797 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 798 DB_PRINT("descriptor 0x%x owned by sw.\n", 799 (unsigned)s->rx_desc_addr[q]); 800 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 801 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 802 /* Handle interrupt consequences */ 803 gem_update_int_status(s); 804 } 805 } 806 807 /* 808 * gem_receive: 809 * Fit a packet handed to us by QEMU into the receive descriptor ring. 810 */ 811 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 812 { 813 CadenceGEMState *s; 814 unsigned rxbufsize, bytes_to_copy; 815 unsigned rxbuf_offset; 816 uint8_t rxbuf[2048]; 817 uint8_t *rxbuf_ptr; 818 bool first_desc = true; 819 int maf; 820 int q = 0; 821 822 s = qemu_get_nic_opaque(nc); 823 824 /* Is this destination MAC address "for us" ? */ 825 maf = gem_mac_address_filter(s, buf); 826 if (maf == GEM_RX_REJECT) { 827 return -1; 828 } 829 830 /* Discard packets with receive length error enabled ? */ 831 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 832 unsigned type_len; 833 834 /* Fish the ethertype / length field out of the RX packet */ 835 type_len = buf[12] << 8 | buf[13]; 836 /* It is a length field, not an ethertype */ 837 if (type_len < 0x600) { 838 if (size < type_len) { 839 /* discard */ 840 return -1; 841 } 842 } 843 } 844 845 /* 846 * Determine configured receive buffer offset (probably 0) 847 */ 848 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 849 GEM_NWCFG_BUFF_OFST_S; 850 851 /* The configure size of each receive buffer. Determines how many 852 * buffers needed to hold this packet. 853 */ 854 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 855 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 856 bytes_to_copy = size; 857 858 /* Hardware allows a zero value here but warns against it. To avoid QEMU 859 * indefinite loops we enforce a minimum value here 860 */ 861 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 862 rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 863 } 864 865 /* Pad to minimum length. Assume FCS field is stripped, logic 866 * below will increment it to the real minimum of 64 when 867 * not FCS stripping 868 */ 869 if (size < 60) { 870 size = 60; 871 } 872 873 /* Strip of FCS field ? (usually yes) */ 874 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 875 rxbuf_ptr = (void *)buf; 876 } else { 877 unsigned crc_val; 878 879 if (size > sizeof(rxbuf) - sizeof(crc_val)) { 880 size = sizeof(rxbuf) - sizeof(crc_val); 881 } 882 bytes_to_copy = size; 883 /* The application wants the FCS field, which QEMU does not provide. 884 * We must try and calculate one. 885 */ 886 887 memcpy(rxbuf, buf, size); 888 memset(rxbuf + size, 0, sizeof(rxbuf) - size); 889 rxbuf_ptr = rxbuf; 890 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 891 memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 892 893 bytes_to_copy += 4; 894 size += 4; 895 } 896 897 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 898 899 /* Find which queue we are targetting */ 900 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 901 902 while (bytes_to_copy) { 903 /* Do nothing if receive is not enabled. */ 904 if (!gem_can_receive(nc)) { 905 assert(!first_desc); 906 return -1; 907 } 908 909 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 910 rx_desc_get_buffer(s->rx_desc[q])); 911 912 /* Copy packet data to emulated DMA buffer */ 913 cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) + 914 rxbuf_offset, 915 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 916 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 917 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 918 919 /* Update the descriptor. */ 920 if (first_desc) { 921 rx_desc_set_sof(s->rx_desc[q]); 922 first_desc = false; 923 } 924 if (bytes_to_copy == 0) { 925 rx_desc_set_eof(s->rx_desc[q]); 926 rx_desc_set_length(s->rx_desc[q], size); 927 } 928 rx_desc_set_ownership(s->rx_desc[q]); 929 930 switch (maf) { 931 case GEM_RX_PROMISCUOUS_ACCEPT: 932 break; 933 case GEM_RX_BROADCAST_ACCEPT: 934 rx_desc_set_broadcast(s->rx_desc[q]); 935 break; 936 case GEM_RX_UNICAST_HASH_ACCEPT: 937 rx_desc_set_unicast_hash(s->rx_desc[q]); 938 break; 939 case GEM_RX_MULTICAST_HASH_ACCEPT: 940 rx_desc_set_multicast_hash(s->rx_desc[q]); 941 break; 942 case GEM_RX_REJECT: 943 abort(); 944 default: /* SAR */ 945 rx_desc_set_sar(s->rx_desc[q], maf); 946 } 947 948 /* Descriptor write-back. */ 949 cpu_physical_memory_write(s->rx_desc_addr[q], 950 (uint8_t *)s->rx_desc[q], 951 sizeof(s->rx_desc[q])); 952 953 /* Next descriptor */ 954 if (rx_desc_get_wrap(s->rx_desc[q])) { 955 DB_PRINT("wrapping RX descriptor list\n"); 956 s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; 957 } else { 958 DB_PRINT("incrementing RX descriptor list\n"); 959 s->rx_desc_addr[q] += 8; 960 } 961 962 gem_get_rx_desc(s, q); 963 } 964 965 /* Count it */ 966 gem_receive_updatestats(s, buf, size); 967 968 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 969 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 970 971 /* Handle interrupt consequences */ 972 gem_update_int_status(s); 973 974 return size; 975 } 976 977 /* 978 * gem_transmit_updatestats: 979 * Increment transmit statistics. 980 */ 981 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 982 unsigned bytes) 983 { 984 uint64_t octets; 985 986 /* Total octets (bytes) transmitted */ 987 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 988 s->regs[GEM_OCTTXHI]; 989 octets += bytes; 990 s->regs[GEM_OCTTXLO] = octets >> 32; 991 s->regs[GEM_OCTTXHI] = octets; 992 993 /* Error-free Frames transmitted */ 994 s->regs[GEM_TXCNT]++; 995 996 /* Error-free Broadcast Frames counter */ 997 if (!memcmp(packet, broadcast_addr, 6)) { 998 s->regs[GEM_TXBCNT]++; 999 } 1000 1001 /* Error-free Multicast Frames counter */ 1002 if (packet[0] == 0x01) { 1003 s->regs[GEM_TXMCNT]++; 1004 } 1005 1006 if (bytes <= 64) { 1007 s->regs[GEM_TX64CNT]++; 1008 } else if (bytes <= 127) { 1009 s->regs[GEM_TX65CNT]++; 1010 } else if (bytes <= 255) { 1011 s->regs[GEM_TX128CNT]++; 1012 } else if (bytes <= 511) { 1013 s->regs[GEM_TX256CNT]++; 1014 } else if (bytes <= 1023) { 1015 s->regs[GEM_TX512CNT]++; 1016 } else if (bytes <= 1518) { 1017 s->regs[GEM_TX1024CNT]++; 1018 } else { 1019 s->regs[GEM_TX1519CNT]++; 1020 } 1021 } 1022 1023 /* 1024 * gem_transmit: 1025 * Fish packets out of the descriptor ring and feed them to QEMU 1026 */ 1027 static void gem_transmit(CadenceGEMState *s) 1028 { 1029 unsigned desc[2]; 1030 hwaddr packet_desc_addr; 1031 uint8_t tx_packet[2048]; 1032 uint8_t *p; 1033 unsigned total_bytes; 1034 int q = 0; 1035 1036 /* Do nothing if transmit is not enabled. */ 1037 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 1038 return; 1039 } 1040 1041 DB_PRINT("\n"); 1042 1043 /* The packet we will hand off to QEMU. 1044 * Packets scattered across multiple descriptors are gathered to this 1045 * one contiguous buffer first. 1046 */ 1047 p = tx_packet; 1048 total_bytes = 0; 1049 1050 for (q = s->num_priority_queues - 1; q >= 0; q--) { 1051 /* read current descriptor */ 1052 packet_desc_addr = s->tx_desc_addr[q]; 1053 1054 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1055 cpu_physical_memory_read(packet_desc_addr, 1056 (uint8_t *)desc, sizeof(desc)); 1057 /* Handle all descriptors owned by hardware */ 1058 while (tx_desc_get_used(desc) == 0) { 1059 1060 /* Do nothing if transmit is not enabled. */ 1061 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 1062 return; 1063 } 1064 print_gem_tx_desc(desc, q); 1065 1066 /* The real hardware would eat this (and possibly crash). 1067 * For QEMU let's lend a helping hand. 1068 */ 1069 if ((tx_desc_get_buffer(desc) == 0) || 1070 (tx_desc_get_length(desc) == 0)) { 1071 DB_PRINT("Invalid TX descriptor @ 0x%x\n", 1072 (unsigned)packet_desc_addr); 1073 break; 1074 } 1075 1076 if (tx_desc_get_length(desc) > sizeof(tx_packet) - 1077 (p - tx_packet)) { 1078 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \ 1079 "0x%x\n", (unsigned)packet_desc_addr, 1080 (unsigned)tx_desc_get_length(desc), 1081 sizeof(tx_packet) - (p - tx_packet)); 1082 break; 1083 } 1084 1085 /* Gather this fragment of the packet from "dma memory" to our 1086 * contig buffer. 1087 */ 1088 cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 1089 tx_desc_get_length(desc)); 1090 p += tx_desc_get_length(desc); 1091 total_bytes += tx_desc_get_length(desc); 1092 1093 /* Last descriptor for this packet; hand the whole thing off */ 1094 if (tx_desc_get_last(desc)) { 1095 unsigned desc_first[2]; 1096 1097 /* Modify the 1st descriptor of this packet to be owned by 1098 * the processor. 1099 */ 1100 cpu_physical_memory_read(s->tx_desc_addr[q], 1101 (uint8_t *)desc_first, 1102 sizeof(desc_first)); 1103 tx_desc_set_used(desc_first); 1104 cpu_physical_memory_write(s->tx_desc_addr[q], 1105 (uint8_t *)desc_first, 1106 sizeof(desc_first)); 1107 /* Advance the hardware current descriptor past this packet */ 1108 if (tx_desc_get_wrap(desc)) { 1109 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; 1110 } else { 1111 s->tx_desc_addr[q] = packet_desc_addr + 8; 1112 } 1113 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 1114 1115 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 1116 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 1117 1118 /* Update queue interrupt status */ 1119 if (s->num_priority_queues > 1) { 1120 s->regs[GEM_INT_Q1_STATUS + q] |= 1121 GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]); 1122 } 1123 1124 /* Handle interrupt consequences */ 1125 gem_update_int_status(s); 1126 1127 /* Is checksum offload enabled? */ 1128 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1129 net_checksum_calculate(tx_packet, total_bytes); 1130 } 1131 1132 /* Update MAC statistics */ 1133 gem_transmit_updatestats(s, tx_packet, total_bytes); 1134 1135 /* Send the packet somewhere */ 1136 if (s->phy_loop || (s->regs[GEM_NWCTRL] & 1137 GEM_NWCTRL_LOCALLOOP)) { 1138 gem_receive(qemu_get_queue(s->nic), tx_packet, 1139 total_bytes); 1140 } else { 1141 qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 1142 total_bytes); 1143 } 1144 1145 /* Prepare for next packet */ 1146 p = tx_packet; 1147 total_bytes = 0; 1148 } 1149 1150 /* read next descriptor */ 1151 if (tx_desc_get_wrap(desc)) { 1152 tx_desc_set_last(desc); 1153 packet_desc_addr = s->regs[GEM_TXQBASE]; 1154 } else { 1155 packet_desc_addr += 8; 1156 } 1157 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1158 cpu_physical_memory_read(packet_desc_addr, 1159 (uint8_t *)desc, sizeof(desc)); 1160 } 1161 1162 if (tx_desc_get_used(desc)) { 1163 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 1164 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 1165 gem_update_int_status(s); 1166 } 1167 } 1168 } 1169 1170 static void gem_phy_reset(CadenceGEMState *s) 1171 { 1172 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 1173 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 1174 s->phy_regs[PHY_REG_STATUS] = 0x7969; 1175 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 1176 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 1177 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 1178 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 1179 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 1180 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 1181 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 1182 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 1183 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 1184 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 1185 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 1186 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 1187 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 1188 s->phy_regs[PHY_REG_LED] = 0x4100; 1189 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 1190 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 1191 1192 phy_update_link(s); 1193 } 1194 1195 static void gem_reset(DeviceState *d) 1196 { 1197 int i; 1198 CadenceGEMState *s = CADENCE_GEM(d); 1199 const uint8_t *a; 1200 1201 DB_PRINT("\n"); 1202 1203 /* Set post reset register values */ 1204 memset(&s->regs[0], 0, sizeof(s->regs)); 1205 s->regs[GEM_NWCFG] = 0x00080000; 1206 s->regs[GEM_NWSTATUS] = 0x00000006; 1207 s->regs[GEM_DMACFG] = 0x00020784; 1208 s->regs[GEM_IMR] = 0x07ffffff; 1209 s->regs[GEM_TXPAUSE] = 0x0000ffff; 1210 s->regs[GEM_TXPARTIALSF] = 0x000003ff; 1211 s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1212 s->regs[GEM_MODID] = 0x00020118; 1213 s->regs[GEM_DESCONF] = 0x02500111; 1214 s->regs[GEM_DESCONF2] = 0x2ab13fff; 1215 s->regs[GEM_DESCONF5] = 0x002f2145; 1216 s->regs[GEM_DESCONF6] = 0x00000200; 1217 1218 /* Set MAC address */ 1219 a = &s->conf.macaddr.a[0]; 1220 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1221 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1222 1223 for (i = 0; i < 4; i++) { 1224 s->sar_active[i] = false; 1225 } 1226 1227 gem_phy_reset(s); 1228 1229 gem_update_int_status(s); 1230 } 1231 1232 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1233 { 1234 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1235 return s->phy_regs[reg_num]; 1236 } 1237 1238 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1239 { 1240 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1241 1242 switch (reg_num) { 1243 case PHY_REG_CONTROL: 1244 if (val & PHY_REG_CONTROL_RST) { 1245 /* Phy reset */ 1246 gem_phy_reset(s); 1247 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1248 s->phy_loop = 0; 1249 } 1250 if (val & PHY_REG_CONTROL_ANEG) { 1251 /* Complete autonegotiation immediately */ 1252 val &= ~PHY_REG_CONTROL_ANEG; 1253 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1254 } 1255 if (val & PHY_REG_CONTROL_LOOP) { 1256 DB_PRINT("PHY placed in loopback\n"); 1257 s->phy_loop = 1; 1258 } else { 1259 s->phy_loop = 0; 1260 } 1261 break; 1262 } 1263 s->phy_regs[reg_num] = val; 1264 } 1265 1266 /* 1267 * gem_read32: 1268 * Read a GEM register. 1269 */ 1270 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1271 { 1272 CadenceGEMState *s; 1273 uint32_t retval; 1274 int i; 1275 s = (CadenceGEMState *)opaque; 1276 1277 offset >>= 2; 1278 retval = s->regs[offset]; 1279 1280 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1281 1282 switch (offset) { 1283 case GEM_ISR: 1284 DB_PRINT("lowering irqs on ISR read\n"); 1285 for (i = 0; i < s->num_priority_queues; ++i) { 1286 qemu_set_irq(s->irq[i], 0); 1287 } 1288 break; 1289 case GEM_PHYMNTNC: 1290 if (retval & GEM_PHYMNTNC_OP_R) { 1291 uint32_t phy_addr, reg_num; 1292 1293 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1294 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1295 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1296 retval &= 0xFFFF0000; 1297 retval |= gem_phy_read(s, reg_num); 1298 } else { 1299 retval |= 0xFFFF; /* No device at this address */ 1300 } 1301 } 1302 break; 1303 } 1304 1305 /* Squash read to clear bits */ 1306 s->regs[offset] &= ~(s->regs_rtc[offset]); 1307 1308 /* Do not provide write only bits */ 1309 retval &= ~(s->regs_wo[offset]); 1310 1311 DB_PRINT("0x%08x\n", retval); 1312 gem_update_int_status(s); 1313 return retval; 1314 } 1315 1316 /* 1317 * gem_write32: 1318 * Write a GEM register. 1319 */ 1320 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1321 unsigned size) 1322 { 1323 CadenceGEMState *s = (CadenceGEMState *)opaque; 1324 uint32_t readonly; 1325 int i; 1326 1327 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1328 offset >>= 2; 1329 1330 /* Squash bits which are read only in write value */ 1331 val &= ~(s->regs_ro[offset]); 1332 /* Preserve (only) bits which are read only and wtc in register */ 1333 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1334 1335 /* Copy register write to backing store */ 1336 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1337 1338 /* do w1c */ 1339 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1340 1341 /* Handle register write side effects */ 1342 switch (offset) { 1343 case GEM_NWCTRL: 1344 if (val & GEM_NWCTRL_RXENA) { 1345 for (i = 0; i < s->num_priority_queues; ++i) { 1346 gem_get_rx_desc(s, i); 1347 } 1348 } 1349 if (val & GEM_NWCTRL_TXSTART) { 1350 gem_transmit(s); 1351 } 1352 if (!(val & GEM_NWCTRL_TXENA)) { 1353 /* Reset to start of Q when transmit disabled. */ 1354 for (i = 0; i < s->num_priority_queues; i++) { 1355 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE]; 1356 } 1357 } 1358 if (gem_can_receive(qemu_get_queue(s->nic))) { 1359 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1360 } 1361 break; 1362 1363 case GEM_TXSTATUS: 1364 gem_update_int_status(s); 1365 break; 1366 case GEM_RXQBASE: 1367 s->rx_desc_addr[0] = val; 1368 break; 1369 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 1370 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 1371 break; 1372 case GEM_TXQBASE: 1373 s->tx_desc_addr[0] = val; 1374 break; 1375 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 1376 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 1377 break; 1378 case GEM_RXSTATUS: 1379 gem_update_int_status(s); 1380 break; 1381 case GEM_IER: 1382 s->regs[GEM_IMR] &= ~val; 1383 gem_update_int_status(s); 1384 break; 1385 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 1386 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 1387 gem_update_int_status(s); 1388 break; 1389 case GEM_IDR: 1390 s->regs[GEM_IMR] |= val; 1391 gem_update_int_status(s); 1392 break; 1393 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 1394 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 1395 gem_update_int_status(s); 1396 break; 1397 case GEM_SPADDR1LO: 1398 case GEM_SPADDR2LO: 1399 case GEM_SPADDR3LO: 1400 case GEM_SPADDR4LO: 1401 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 1402 break; 1403 case GEM_SPADDR1HI: 1404 case GEM_SPADDR2HI: 1405 case GEM_SPADDR3HI: 1406 case GEM_SPADDR4HI: 1407 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 1408 break; 1409 case GEM_PHYMNTNC: 1410 if (val & GEM_PHYMNTNC_OP_W) { 1411 uint32_t phy_addr, reg_num; 1412 1413 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1414 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1415 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1416 gem_phy_write(s, reg_num, val); 1417 } 1418 } 1419 break; 1420 } 1421 1422 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1423 } 1424 1425 static const MemoryRegionOps gem_ops = { 1426 .read = gem_read, 1427 .write = gem_write, 1428 .endianness = DEVICE_LITTLE_ENDIAN, 1429 }; 1430 1431 static void gem_set_link(NetClientState *nc) 1432 { 1433 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1434 1435 DB_PRINT("\n"); 1436 phy_update_link(s); 1437 gem_update_int_status(s); 1438 } 1439 1440 static NetClientInfo net_gem_info = { 1441 .type = NET_CLIENT_DRIVER_NIC, 1442 .size = sizeof(NICState), 1443 .can_receive = gem_can_receive, 1444 .receive = gem_receive, 1445 .link_status_changed = gem_set_link, 1446 }; 1447 1448 static void gem_realize(DeviceState *dev, Error **errp) 1449 { 1450 CadenceGEMState *s = CADENCE_GEM(dev); 1451 int i; 1452 1453 if (s->num_priority_queues == 0 || 1454 s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1455 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1456 s->num_priority_queues); 1457 return; 1458 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1459 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1460 s->num_type1_screeners); 1461 return; 1462 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1463 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1464 s->num_type2_screeners); 1465 return; 1466 } 1467 1468 for (i = 0; i < s->num_priority_queues; ++i) { 1469 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1470 } 1471 1472 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1473 1474 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1475 object_get_typename(OBJECT(dev)), dev->id, s); 1476 } 1477 1478 static void gem_init(Object *obj) 1479 { 1480 CadenceGEMState *s = CADENCE_GEM(obj); 1481 DeviceState *dev = DEVICE(obj); 1482 1483 DB_PRINT("\n"); 1484 1485 gem_init_register_masks(s); 1486 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1487 "enet", sizeof(s->regs)); 1488 1489 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1490 } 1491 1492 static const VMStateDescription vmstate_cadence_gem = { 1493 .name = "cadence_gem", 1494 .version_id = 4, 1495 .minimum_version_id = 4, 1496 .fields = (VMStateField[]) { 1497 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1498 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1499 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1500 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1501 MAX_PRIORITY_QUEUES), 1502 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1503 MAX_PRIORITY_QUEUES), 1504 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1505 VMSTATE_END_OF_LIST(), 1506 } 1507 }; 1508 1509 static Property gem_properties[] = { 1510 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1511 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1512 num_priority_queues, 1), 1513 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1514 num_type1_screeners, 4), 1515 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1516 num_type2_screeners, 4), 1517 DEFINE_PROP_END_OF_LIST(), 1518 }; 1519 1520 static void gem_class_init(ObjectClass *klass, void *data) 1521 { 1522 DeviceClass *dc = DEVICE_CLASS(klass); 1523 1524 dc->realize = gem_realize; 1525 dc->props = gem_properties; 1526 dc->vmsd = &vmstate_cadence_gem; 1527 dc->reset = gem_reset; 1528 } 1529 1530 static const TypeInfo gem_info = { 1531 .name = TYPE_CADENCE_GEM, 1532 .parent = TYPE_SYS_BUS_DEVICE, 1533 .instance_size = sizeof(CadenceGEMState), 1534 .instance_init = gem_init, 1535 .class_init = gem_class_init, 1536 }; 1537 1538 static void gem_register_types(void) 1539 { 1540 type_register_static(&gem_info); 1541 } 1542 1543 type_init(gem_register_types) 1544