1 /* 2 * QEMU Xilinx GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include <zlib.h> /* For crc32 */ 26 27 #include "hw/sysbus.h" 28 #include "net/net.h" 29 #include "net/checksum.h" 30 31 #ifdef CADENCE_GEM_ERR_DEBUG 32 #define DB_PRINT(...) do { \ 33 fprintf(stderr, ": %s: ", __func__); \ 34 fprintf(stderr, ## __VA_ARGS__); \ 35 } while (0); 36 #else 37 #define DB_PRINT(...) 38 #endif 39 40 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 41 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 42 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 43 #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 44 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 45 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 46 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 47 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 48 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 49 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 50 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 51 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 52 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 53 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintaince reg */ 54 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 55 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 56 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 57 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 58 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 59 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 60 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 61 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 62 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 63 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 64 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 65 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 66 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 67 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 68 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 69 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 70 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 71 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 72 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 73 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 74 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 75 #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 76 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 77 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 78 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 79 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 80 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 81 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 82 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 83 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 84 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 85 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 86 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 87 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 88 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 89 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 90 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 91 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 92 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 93 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 94 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 95 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 96 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 97 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 98 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 99 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 100 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 101 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 102 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 103 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 104 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 105 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 106 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 107 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 108 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 109 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 110 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 111 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 112 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 113 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 114 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 115 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 116 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 117 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 118 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 119 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 120 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 121 122 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 123 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 124 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 125 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 126 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 127 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 128 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 129 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 130 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 131 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 132 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 133 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 134 135 /* Design Configuration Registers */ 136 #define GEM_DESCONF (0x00000280/4) 137 #define GEM_DESCONF2 (0x00000284/4) 138 #define GEM_DESCONF3 (0x00000288/4) 139 #define GEM_DESCONF4 (0x0000028C/4) 140 #define GEM_DESCONF5 (0x00000290/4) 141 #define GEM_DESCONF6 (0x00000294/4) 142 #define GEM_DESCONF7 (0x00000298/4) 143 144 #define GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ 145 146 /*****************************************/ 147 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 148 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 149 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 150 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 151 152 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 153 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with lenth err */ 154 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 155 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 156 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 157 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 158 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 159 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 160 161 #define GEM_DMACFG_RBUFSZ_M 0x007F0000 /* DMA RX Buffer Size mask */ 162 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 163 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 164 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 165 166 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 167 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 168 169 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 170 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 171 172 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 173 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 174 #define GEM_INT_TXUSED 0x00000008 175 #define GEM_INT_RXUSED 0x00000004 176 #define GEM_INT_RXCMPL 0x00000002 177 178 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 179 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 180 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 181 #define GEM_PHYMNTNC_ADDR_SHFT 23 182 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 183 #define GEM_PHYMNTNC_REG_SHIFT 18 184 185 /* Marvell PHY definitions */ 186 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 187 188 #define PHY_REG_CONTROL 0 189 #define PHY_REG_STATUS 1 190 #define PHY_REG_PHYID1 2 191 #define PHY_REG_PHYID2 3 192 #define PHY_REG_ANEGADV 4 193 #define PHY_REG_LINKPABIL 5 194 #define PHY_REG_ANEGEXP 6 195 #define PHY_REG_NEXTP 7 196 #define PHY_REG_LINKPNEXTP 8 197 #define PHY_REG_100BTCTRL 9 198 #define PHY_REG_1000BTSTAT 10 199 #define PHY_REG_EXTSTAT 15 200 #define PHY_REG_PHYSPCFC_CTL 16 201 #define PHY_REG_PHYSPCFC_ST 17 202 #define PHY_REG_INT_EN 18 203 #define PHY_REG_INT_ST 19 204 #define PHY_REG_EXT_PHYSPCFC_CTL 20 205 #define PHY_REG_RXERR 21 206 #define PHY_REG_EACD 22 207 #define PHY_REG_LED 24 208 #define PHY_REG_LED_OVRD 25 209 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 210 #define PHY_REG_EXT_PHYSPCFC_ST 27 211 #define PHY_REG_CABLE_DIAG 28 212 213 #define PHY_REG_CONTROL_RST 0x8000 214 #define PHY_REG_CONTROL_LOOP 0x4000 215 #define PHY_REG_CONTROL_ANEG 0x1000 216 217 #define PHY_REG_STATUS_LINK 0x0004 218 #define PHY_REG_STATUS_ANEGCMPL 0x0020 219 220 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 221 #define PHY_REG_INT_ST_LINKC 0x0400 222 #define PHY_REG_INT_ST_ENERGY 0x0010 223 224 /***********************************************************************/ 225 #define GEM_RX_REJECT 1 226 #define GEM_RX_ACCEPT 0 227 228 /***********************************************************************/ 229 230 #define DESC_1_USED 0x80000000 231 #define DESC_1_LENGTH 0x00001FFF 232 233 #define DESC_1_TX_WRAP 0x40000000 234 #define DESC_1_TX_LAST 0x00008000 235 236 #define DESC_0_RX_WRAP 0x00000002 237 #define DESC_0_RX_OWNERSHIP 0x00000001 238 239 #define DESC_1_RX_SOF 0x00004000 240 #define DESC_1_RX_EOF 0x00008000 241 242 static inline unsigned tx_desc_get_buffer(unsigned *desc) 243 { 244 return desc[0]; 245 } 246 247 static inline unsigned tx_desc_get_used(unsigned *desc) 248 { 249 return (desc[1] & DESC_1_USED) ? 1 : 0; 250 } 251 252 static inline void tx_desc_set_used(unsigned *desc) 253 { 254 desc[1] |= DESC_1_USED; 255 } 256 257 static inline unsigned tx_desc_get_wrap(unsigned *desc) 258 { 259 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 260 } 261 262 static inline unsigned tx_desc_get_last(unsigned *desc) 263 { 264 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 265 } 266 267 static inline unsigned tx_desc_get_length(unsigned *desc) 268 { 269 return desc[1] & DESC_1_LENGTH; 270 } 271 272 static inline void print_gem_tx_desc(unsigned *desc) 273 { 274 DB_PRINT("TXDESC:\n"); 275 DB_PRINT("bufaddr: 0x%08x\n", *desc); 276 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 277 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 278 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 279 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 280 } 281 282 static inline unsigned rx_desc_get_buffer(unsigned *desc) 283 { 284 return desc[0] & ~0x3UL; 285 } 286 287 static inline unsigned rx_desc_get_wrap(unsigned *desc) 288 { 289 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 290 } 291 292 static inline unsigned rx_desc_get_ownership(unsigned *desc) 293 { 294 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 295 } 296 297 static inline void rx_desc_set_ownership(unsigned *desc) 298 { 299 desc[0] |= DESC_0_RX_OWNERSHIP; 300 } 301 302 static inline void rx_desc_set_sof(unsigned *desc) 303 { 304 desc[1] |= DESC_1_RX_SOF; 305 } 306 307 static inline void rx_desc_set_eof(unsigned *desc) 308 { 309 desc[1] |= DESC_1_RX_EOF; 310 } 311 312 static inline void rx_desc_set_length(unsigned *desc, unsigned len) 313 { 314 desc[1] &= ~DESC_1_LENGTH; 315 desc[1] |= len; 316 } 317 318 typedef struct { 319 SysBusDevice busdev; 320 MemoryRegion iomem; 321 NICState *nic; 322 NICConf conf; 323 qemu_irq irq; 324 325 /* GEM registers backing store */ 326 uint32_t regs[GEM_MAXREG]; 327 /* Mask of register bits which are write only */ 328 uint32_t regs_wo[GEM_MAXREG]; 329 /* Mask of register bits which are read only */ 330 uint32_t regs_ro[GEM_MAXREG]; 331 /* Mask of register bits which are clear on read */ 332 uint32_t regs_rtc[GEM_MAXREG]; 333 /* Mask of register bits which are write 1 to clear */ 334 uint32_t regs_w1c[GEM_MAXREG]; 335 336 /* PHY registers backing store */ 337 uint16_t phy_regs[32]; 338 339 uint8_t phy_loop; /* Are we in phy loopback? */ 340 341 /* The current DMA descriptor pointers */ 342 uint32_t rx_desc_addr; 343 uint32_t tx_desc_addr; 344 345 } GemState; 346 347 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 348 const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 349 350 /* 351 * gem_init_register_masks: 352 * One time initialization. 353 * Set masks to identify which register bits have magical clear properties 354 */ 355 static void gem_init_register_masks(GemState *s) 356 { 357 /* Mask of register bits which are read only*/ 358 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 359 s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 360 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 361 s->regs_ro[GEM_DMACFG] = 0xFE00F000; 362 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 363 s->regs_ro[GEM_RXQBASE] = 0x00000003; 364 s->regs_ro[GEM_TXQBASE] = 0x00000003; 365 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 366 s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 367 s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 368 s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 369 370 /* Mask of register bits which are clear on read */ 371 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 372 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 373 374 /* Mask of register bits which are write 1 to clear */ 375 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 376 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 377 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 378 379 /* Mask of register bits which are write only */ 380 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 381 s->regs_wo[GEM_NWCTRL] = 0x00073E60; 382 s->regs_wo[GEM_IER] = 0x07FFFFFF; 383 s->regs_wo[GEM_IDR] = 0x07FFFFFF; 384 } 385 386 /* 387 * phy_update_link: 388 * Make the emulated PHY link state match the QEMU "interface" state. 389 */ 390 static void phy_update_link(GemState *s) 391 { 392 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 393 394 /* Autonegotiation status mirrors link status. */ 395 if (qemu_get_queue(s->nic)->link_down) { 396 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 397 PHY_REG_STATUS_LINK); 398 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 399 } else { 400 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 401 PHY_REG_STATUS_LINK); 402 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 403 PHY_REG_INT_ST_ANEGCMPL | 404 PHY_REG_INT_ST_ENERGY); 405 } 406 } 407 408 static int gem_can_receive(NetClientState *nc) 409 { 410 GemState *s; 411 412 s = qemu_get_nic_opaque(nc); 413 414 DB_PRINT("\n"); 415 416 /* Do nothing if receive is not enabled. */ 417 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 418 return 0; 419 } 420 421 return 1; 422 } 423 424 /* 425 * gem_update_int_status: 426 * Raise or lower interrupt based on current status. 427 */ 428 static void gem_update_int_status(GemState *s) 429 { 430 if (s->regs[GEM_ISR]) { 431 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]); 432 qemu_set_irq(s->irq, 1); 433 } 434 } 435 436 /* 437 * gem_receive_updatestats: 438 * Increment receive statistics. 439 */ 440 static void gem_receive_updatestats(GemState *s, const uint8_t *packet, 441 unsigned bytes) 442 { 443 uint64_t octets; 444 445 /* Total octets (bytes) received */ 446 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 447 s->regs[GEM_OCTRXHI]; 448 octets += bytes; 449 s->regs[GEM_OCTRXLO] = octets >> 32; 450 s->regs[GEM_OCTRXHI] = octets; 451 452 /* Error-free Frames received */ 453 s->regs[GEM_RXCNT]++; 454 455 /* Error-free Broadcast Frames counter */ 456 if (!memcmp(packet, broadcast_addr, 6)) { 457 s->regs[GEM_RXBROADCNT]++; 458 } 459 460 /* Error-free Multicast Frames counter */ 461 if (packet[0] == 0x01) { 462 s->regs[GEM_RXMULTICNT]++; 463 } 464 465 if (bytes <= 64) { 466 s->regs[GEM_RX64CNT]++; 467 } else if (bytes <= 127) { 468 s->regs[GEM_RX65CNT]++; 469 } else if (bytes <= 255) { 470 s->regs[GEM_RX128CNT]++; 471 } else if (bytes <= 511) { 472 s->regs[GEM_RX256CNT]++; 473 } else if (bytes <= 1023) { 474 s->regs[GEM_RX512CNT]++; 475 } else if (bytes <= 1518) { 476 s->regs[GEM_RX1024CNT]++; 477 } else { 478 s->regs[GEM_RX1519CNT]++; 479 } 480 } 481 482 /* 483 * Get the MAC Address bit from the specified position 484 */ 485 static unsigned get_bit(const uint8_t *mac, unsigned bit) 486 { 487 unsigned byte; 488 489 byte = mac[bit / 8]; 490 byte >>= (bit & 0x7); 491 byte &= 1; 492 493 return byte; 494 } 495 496 /* 497 * Calculate a GEM MAC Address hash index 498 */ 499 static unsigned calc_mac_hash(const uint8_t *mac) 500 { 501 int index_bit, mac_bit; 502 unsigned hash_index; 503 504 hash_index = 0; 505 mac_bit = 5; 506 for (index_bit = 5; index_bit >= 0; index_bit--) { 507 hash_index |= (get_bit(mac, mac_bit) ^ 508 get_bit(mac, mac_bit + 6) ^ 509 get_bit(mac, mac_bit + 12) ^ 510 get_bit(mac, mac_bit + 18) ^ 511 get_bit(mac, mac_bit + 24) ^ 512 get_bit(mac, mac_bit + 30) ^ 513 get_bit(mac, mac_bit + 36) ^ 514 get_bit(mac, mac_bit + 42)) << index_bit; 515 mac_bit--; 516 } 517 518 return hash_index; 519 } 520 521 /* 522 * gem_mac_address_filter: 523 * Accept or reject this destination address? 524 * Returns: 525 * GEM_RX_REJECT: reject 526 * GEM_RX_ACCEPT: accept 527 */ 528 static int gem_mac_address_filter(GemState *s, const uint8_t *packet) 529 { 530 uint8_t *gem_spaddr; 531 int i; 532 533 /* Promiscuous mode? */ 534 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 535 return GEM_RX_ACCEPT; 536 } 537 538 if (!memcmp(packet, broadcast_addr, 6)) { 539 /* Reject broadcast packets? */ 540 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 541 return GEM_RX_REJECT; 542 } 543 return GEM_RX_ACCEPT; 544 } 545 546 /* Accept packets -w- hash match? */ 547 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 548 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 549 unsigned hash_index; 550 551 hash_index = calc_mac_hash(packet); 552 if (hash_index < 32) { 553 if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 554 return GEM_RX_ACCEPT; 555 } 556 } else { 557 hash_index -= 32; 558 if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 559 return GEM_RX_ACCEPT; 560 } 561 } 562 } 563 564 /* Check all 4 specific addresses */ 565 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 566 for (i = 0; i < 4; i++) { 567 if (!memcmp(packet, gem_spaddr, 6)) { 568 return GEM_RX_ACCEPT; 569 } 570 571 gem_spaddr += 8; 572 } 573 574 /* No address match; reject the packet */ 575 return GEM_RX_REJECT; 576 } 577 578 /* 579 * gem_receive: 580 * Fit a packet handed to us by QEMU into the receive descriptor ring. 581 */ 582 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 583 { 584 unsigned desc[2]; 585 hwaddr packet_desc_addr, last_desc_addr; 586 GemState *s; 587 unsigned rxbufsize, bytes_to_copy; 588 unsigned rxbuf_offset; 589 uint8_t rxbuf[2048]; 590 uint8_t *rxbuf_ptr; 591 592 s = qemu_get_nic_opaque(nc); 593 594 /* Do nothing if receive is not enabled. */ 595 if (!gem_can_receive(nc)) { 596 return -1; 597 } 598 599 /* Is this destination MAC address "for us" ? */ 600 if (gem_mac_address_filter(s, buf) == GEM_RX_REJECT) { 601 return -1; 602 } 603 604 /* Discard packets with receive length error enabled ? */ 605 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 606 unsigned type_len; 607 608 /* Fish the ethertype / length field out of the RX packet */ 609 type_len = buf[12] << 8 | buf[13]; 610 /* It is a length field, not an ethertype */ 611 if (type_len < 0x600) { 612 if (size < type_len) { 613 /* discard */ 614 return -1; 615 } 616 } 617 } 618 619 /* 620 * Determine configured receive buffer offset (probably 0) 621 */ 622 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 623 GEM_NWCFG_BUFF_OFST_S; 624 625 /* The configure size of each receive buffer. Determines how many 626 * buffers needed to hold this packet. 627 */ 628 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 629 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 630 bytes_to_copy = size; 631 632 /* Strip of FCS field ? (usually yes) */ 633 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 634 rxbuf_ptr = (void *)buf; 635 } else { 636 unsigned crc_val; 637 int crc_offset; 638 639 /* The application wants the FCS field, which QEMU does not provide. 640 * We must try and caclculate one. 641 */ 642 643 memcpy(rxbuf, buf, size); 644 memset(rxbuf + size, 0, sizeof(rxbuf) - size); 645 rxbuf_ptr = rxbuf; 646 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 647 if (size < 60) { 648 crc_offset = 60; 649 } else { 650 crc_offset = size; 651 } 652 memcpy(rxbuf + crc_offset, &crc_val, sizeof(crc_val)); 653 654 bytes_to_copy += 4; 655 size += 4; 656 } 657 658 /* Pad to minimum length */ 659 if (size < 64) { 660 size = 64; 661 } 662 663 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 664 665 packet_desc_addr = s->rx_desc_addr; 666 while (1) { 667 DB_PRINT("read descriptor 0x%x\n", (unsigned)packet_desc_addr); 668 /* read current descriptor */ 669 cpu_physical_memory_read(packet_desc_addr, 670 (uint8_t *)&desc[0], sizeof(desc)); 671 672 /* Descriptor owned by software ? */ 673 if (rx_desc_get_ownership(desc) == 1) { 674 DB_PRINT("descriptor 0x%x owned by sw.\n", 675 (unsigned)packet_desc_addr); 676 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 677 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 678 /* Handle interrupt consequences */ 679 gem_update_int_status(s); 680 return -1; 681 } 682 683 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 684 rx_desc_get_buffer(desc)); 685 686 /* 687 * Let's have QEMU lend a helping hand. 688 */ 689 if (rx_desc_get_buffer(desc) == 0) { 690 DB_PRINT("Invalid RX buffer (NULL) for descriptor 0x%x\n", 691 (unsigned)packet_desc_addr); 692 break; 693 } 694 695 /* Copy packet data to emulated DMA buffer */ 696 cpu_physical_memory_write(rx_desc_get_buffer(desc) + rxbuf_offset, 697 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 698 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 699 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 700 if (bytes_to_copy == 0) { 701 break; 702 } 703 704 /* Next descriptor */ 705 if (rx_desc_get_wrap(desc)) { 706 packet_desc_addr = s->regs[GEM_RXQBASE]; 707 } else { 708 packet_desc_addr += 8; 709 } 710 } 711 712 DB_PRINT("set length: %ld, EOF on descriptor 0x%x\n", size, 713 (unsigned)packet_desc_addr); 714 715 /* Update last descriptor with EOF and total length */ 716 rx_desc_set_eof(desc); 717 rx_desc_set_length(desc, size); 718 cpu_physical_memory_write(packet_desc_addr, 719 (uint8_t *)&desc[0], sizeof(desc)); 720 721 /* Advance RX packet descriptor Q */ 722 last_desc_addr = packet_desc_addr; 723 packet_desc_addr = s->rx_desc_addr; 724 s->rx_desc_addr = last_desc_addr; 725 if (rx_desc_get_wrap(desc)) { 726 s->rx_desc_addr = s->regs[GEM_RXQBASE]; 727 DB_PRINT("wrapping RX descriptor list\n"); 728 } else { 729 DB_PRINT("incrementing RX descriptor list\n"); 730 s->rx_desc_addr += 8; 731 } 732 733 DB_PRINT("set SOF, OWN on descriptor 0x%08x\n", (unsigned)packet_desc_addr); 734 735 /* Count it */ 736 gem_receive_updatestats(s, buf, size); 737 738 /* Update first descriptor (which could also be the last) */ 739 /* read descriptor */ 740 cpu_physical_memory_read(packet_desc_addr, 741 (uint8_t *)&desc[0], sizeof(desc)); 742 rx_desc_set_sof(desc); 743 rx_desc_set_ownership(desc); 744 cpu_physical_memory_write(packet_desc_addr, 745 (uint8_t *)&desc[0], sizeof(desc)); 746 747 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 748 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 749 750 /* Handle interrupt consequences */ 751 gem_update_int_status(s); 752 753 return size; 754 } 755 756 /* 757 * gem_transmit_updatestats: 758 * Increment transmit statistics. 759 */ 760 static void gem_transmit_updatestats(GemState *s, const uint8_t *packet, 761 unsigned bytes) 762 { 763 uint64_t octets; 764 765 /* Total octets (bytes) transmitted */ 766 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 767 s->regs[GEM_OCTTXHI]; 768 octets += bytes; 769 s->regs[GEM_OCTTXLO] = octets >> 32; 770 s->regs[GEM_OCTTXHI] = octets; 771 772 /* Error-free Frames transmitted */ 773 s->regs[GEM_TXCNT]++; 774 775 /* Error-free Broadcast Frames counter */ 776 if (!memcmp(packet, broadcast_addr, 6)) { 777 s->regs[GEM_TXBCNT]++; 778 } 779 780 /* Error-free Multicast Frames counter */ 781 if (packet[0] == 0x01) { 782 s->regs[GEM_TXMCNT]++; 783 } 784 785 if (bytes <= 64) { 786 s->regs[GEM_TX64CNT]++; 787 } else if (bytes <= 127) { 788 s->regs[GEM_TX65CNT]++; 789 } else if (bytes <= 255) { 790 s->regs[GEM_TX128CNT]++; 791 } else if (bytes <= 511) { 792 s->regs[GEM_TX256CNT]++; 793 } else if (bytes <= 1023) { 794 s->regs[GEM_TX512CNT]++; 795 } else if (bytes <= 1518) { 796 s->regs[GEM_TX1024CNT]++; 797 } else { 798 s->regs[GEM_TX1519CNT]++; 799 } 800 } 801 802 /* 803 * gem_transmit: 804 * Fish packets out of the descriptor ring and feed them to QEMU 805 */ 806 static void gem_transmit(GemState *s) 807 { 808 unsigned desc[2]; 809 hwaddr packet_desc_addr; 810 uint8_t tx_packet[2048]; 811 uint8_t *p; 812 unsigned total_bytes; 813 814 /* Do nothing if transmit is not enabled. */ 815 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 816 return; 817 } 818 819 DB_PRINT("\n"); 820 821 /* The packet we will hand off to qemu. 822 * Packets scattered across multiple descriptors are gathered to this 823 * one contiguous buffer first. 824 */ 825 p = tx_packet; 826 total_bytes = 0; 827 828 /* read current descriptor */ 829 packet_desc_addr = s->tx_desc_addr; 830 cpu_physical_memory_read(packet_desc_addr, 831 (uint8_t *)&desc[0], sizeof(desc)); 832 /* Handle all descriptors owned by hardware */ 833 while (tx_desc_get_used(desc) == 0) { 834 835 /* Do nothing if transmit is not enabled. */ 836 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 837 return; 838 } 839 print_gem_tx_desc(desc); 840 841 /* The real hardware would eat this (and possibly crash). 842 * For QEMU let's lend a helping hand. 843 */ 844 if ((tx_desc_get_buffer(desc) == 0) || 845 (tx_desc_get_length(desc) == 0)) { 846 DB_PRINT("Invalid TX descriptor @ 0x%x\n", 847 (unsigned)packet_desc_addr); 848 break; 849 } 850 851 /* Gather this fragment of the packet from "dma memory" to our contig. 852 * buffer. 853 */ 854 cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 855 tx_desc_get_length(desc)); 856 p += tx_desc_get_length(desc); 857 total_bytes += tx_desc_get_length(desc); 858 859 /* Last descriptor for this packet; hand the whole thing off */ 860 if (tx_desc_get_last(desc)) { 861 /* Modify the 1st descriptor of this packet to be owned by 862 * the processor. 863 */ 864 cpu_physical_memory_read(s->tx_desc_addr, 865 (uint8_t *)&desc[0], sizeof(desc)); 866 tx_desc_set_used(desc); 867 cpu_physical_memory_write(s->tx_desc_addr, 868 (uint8_t *)&desc[0], sizeof(desc)); 869 /* Advance the hardare current descriptor past this packet */ 870 if (tx_desc_get_wrap(desc)) { 871 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 872 } else { 873 s->tx_desc_addr = packet_desc_addr + 8; 874 } 875 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr); 876 877 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 878 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 879 880 /* Handle interrupt consequences */ 881 gem_update_int_status(s); 882 883 /* Is checksum offload enabled? */ 884 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 885 net_checksum_calculate(tx_packet, total_bytes); 886 } 887 888 /* Update MAC statistics */ 889 gem_transmit_updatestats(s, tx_packet, total_bytes); 890 891 /* Send the packet somewhere */ 892 if (s->phy_loop) { 893 gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes); 894 } else { 895 qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 896 total_bytes); 897 } 898 899 /* Prepare for next packet */ 900 p = tx_packet; 901 total_bytes = 0; 902 } 903 904 /* read next descriptor */ 905 if (tx_desc_get_wrap(desc)) { 906 packet_desc_addr = s->regs[GEM_TXQBASE]; 907 } else { 908 packet_desc_addr += 8; 909 } 910 cpu_physical_memory_read(packet_desc_addr, 911 (uint8_t *)&desc[0], sizeof(desc)); 912 } 913 914 if (tx_desc_get_used(desc)) { 915 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 916 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 917 gem_update_int_status(s); 918 } 919 } 920 921 static void gem_phy_reset(GemState *s) 922 { 923 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 924 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 925 s->phy_regs[PHY_REG_STATUS] = 0x7969; 926 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 927 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 928 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 929 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 930 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 931 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 932 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 933 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 934 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 935 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 936 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 937 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00; 938 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 939 s->phy_regs[PHY_REG_LED] = 0x4100; 940 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 941 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 942 943 phy_update_link(s); 944 } 945 946 static void gem_reset(DeviceState *d) 947 { 948 GemState *s = FROM_SYSBUS(GemState, SYS_BUS_DEVICE(d)); 949 950 DB_PRINT("\n"); 951 952 /* Set post reset register values */ 953 memset(&s->regs[0], 0, sizeof(s->regs)); 954 s->regs[GEM_NWCFG] = 0x00080000; 955 s->regs[GEM_NWSTATUS] = 0x00000006; 956 s->regs[GEM_DMACFG] = 0x00020784; 957 s->regs[GEM_IMR] = 0x07ffffff; 958 s->regs[GEM_TXPAUSE] = 0x0000ffff; 959 s->regs[GEM_TXPARTIALSF] = 0x000003ff; 960 s->regs[GEM_RXPARTIALSF] = 0x000003ff; 961 s->regs[GEM_MODID] = 0x00020118; 962 s->regs[GEM_DESCONF] = 0x02500111; 963 s->regs[GEM_DESCONF2] = 0x2ab13fff; 964 s->regs[GEM_DESCONF5] = 0x002f2145; 965 s->regs[GEM_DESCONF6] = 0x00000200; 966 967 gem_phy_reset(s); 968 969 gem_update_int_status(s); 970 } 971 972 static uint16_t gem_phy_read(GemState *s, unsigned reg_num) 973 { 974 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 975 return s->phy_regs[reg_num]; 976 } 977 978 static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val) 979 { 980 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 981 982 switch (reg_num) { 983 case PHY_REG_CONTROL: 984 if (val & PHY_REG_CONTROL_RST) { 985 /* Phy reset */ 986 gem_phy_reset(s); 987 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 988 s->phy_loop = 0; 989 } 990 if (val & PHY_REG_CONTROL_ANEG) { 991 /* Complete autonegotiation immediately */ 992 val &= ~PHY_REG_CONTROL_ANEG; 993 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 994 } 995 if (val & PHY_REG_CONTROL_LOOP) { 996 DB_PRINT("PHY placed in loopback\n"); 997 s->phy_loop = 1; 998 } else { 999 s->phy_loop = 0; 1000 } 1001 break; 1002 } 1003 s->phy_regs[reg_num] = val; 1004 } 1005 1006 /* 1007 * gem_read32: 1008 * Read a GEM register. 1009 */ 1010 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1011 { 1012 GemState *s; 1013 uint32_t retval; 1014 1015 s = (GemState *)opaque; 1016 1017 offset >>= 2; 1018 retval = s->regs[offset]; 1019 1020 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1021 1022 switch (offset) { 1023 case GEM_ISR: 1024 DB_PRINT("lowering irq on ISR read\n"); 1025 qemu_set_irq(s->irq, 0); 1026 break; 1027 case GEM_PHYMNTNC: 1028 if (retval & GEM_PHYMNTNC_OP_R) { 1029 uint32_t phy_addr, reg_num; 1030 1031 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1032 if (phy_addr == BOARD_PHY_ADDRESS) { 1033 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1034 retval &= 0xFFFF0000; 1035 retval |= gem_phy_read(s, reg_num); 1036 } else { 1037 retval |= 0xFFFF; /* No device at this address */ 1038 } 1039 } 1040 break; 1041 } 1042 1043 /* Squash read to clear bits */ 1044 s->regs[offset] &= ~(s->regs_rtc[offset]); 1045 1046 /* Do not provide write only bits */ 1047 retval &= ~(s->regs_wo[offset]); 1048 1049 DB_PRINT("0x%08x\n", retval); 1050 return retval; 1051 } 1052 1053 /* 1054 * gem_write32: 1055 * Write a GEM register. 1056 */ 1057 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1058 unsigned size) 1059 { 1060 GemState *s = (GemState *)opaque; 1061 uint32_t readonly; 1062 1063 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1064 offset >>= 2; 1065 1066 /* Squash bits which are read only in write value */ 1067 val &= ~(s->regs_ro[offset]); 1068 /* Preserve (only) bits which are read only in register */ 1069 readonly = s->regs[offset]; 1070 readonly &= s->regs_ro[offset]; 1071 1072 /* Squash bits which are write 1 to clear */ 1073 val &= ~(s->regs_w1c[offset] & val); 1074 1075 /* Copy register write to backing store */ 1076 s->regs[offset] = val | readonly; 1077 1078 /* Handle register write side effects */ 1079 switch (offset) { 1080 case GEM_NWCTRL: 1081 if (val & GEM_NWCTRL_TXSTART) { 1082 gem_transmit(s); 1083 } 1084 if (!(val & GEM_NWCTRL_TXENA)) { 1085 /* Reset to start of Q when transmit disabled. */ 1086 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 1087 } 1088 if (val & GEM_NWCTRL_RXENA) { 1089 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1090 } 1091 break; 1092 1093 case GEM_TXSTATUS: 1094 gem_update_int_status(s); 1095 break; 1096 case GEM_RXQBASE: 1097 s->rx_desc_addr = val; 1098 break; 1099 case GEM_TXQBASE: 1100 s->tx_desc_addr = val; 1101 break; 1102 case GEM_RXSTATUS: 1103 gem_update_int_status(s); 1104 break; 1105 case GEM_IER: 1106 s->regs[GEM_IMR] &= ~val; 1107 gem_update_int_status(s); 1108 break; 1109 case GEM_IDR: 1110 s->regs[GEM_IMR] |= val; 1111 gem_update_int_status(s); 1112 break; 1113 case GEM_PHYMNTNC: 1114 if (val & GEM_PHYMNTNC_OP_W) { 1115 uint32_t phy_addr, reg_num; 1116 1117 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1118 if (phy_addr == BOARD_PHY_ADDRESS) { 1119 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1120 gem_phy_write(s, reg_num, val); 1121 } 1122 } 1123 break; 1124 } 1125 1126 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1127 } 1128 1129 static const MemoryRegionOps gem_ops = { 1130 .read = gem_read, 1131 .write = gem_write, 1132 .endianness = DEVICE_LITTLE_ENDIAN, 1133 }; 1134 1135 static void gem_cleanup(NetClientState *nc) 1136 { 1137 GemState *s = qemu_get_nic_opaque(nc); 1138 1139 DB_PRINT("\n"); 1140 s->nic = NULL; 1141 } 1142 1143 static void gem_set_link(NetClientState *nc) 1144 { 1145 DB_PRINT("\n"); 1146 phy_update_link(qemu_get_nic_opaque(nc)); 1147 } 1148 1149 static NetClientInfo net_gem_info = { 1150 .type = NET_CLIENT_OPTIONS_KIND_NIC, 1151 .size = sizeof(NICState), 1152 .can_receive = gem_can_receive, 1153 .receive = gem_receive, 1154 .cleanup = gem_cleanup, 1155 .link_status_changed = gem_set_link, 1156 }; 1157 1158 static int gem_init(SysBusDevice *dev) 1159 { 1160 GemState *s; 1161 1162 DB_PRINT("\n"); 1163 1164 s = FROM_SYSBUS(GemState, dev); 1165 gem_init_register_masks(s); 1166 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1167 "enet", sizeof(s->regs)); 1168 sysbus_init_mmio(dev, &s->iomem); 1169 sysbus_init_irq(dev, &s->irq); 1170 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1171 1172 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1173 object_get_typename(OBJECT(dev)), dev->qdev.id, s); 1174 1175 return 0; 1176 } 1177 1178 static const VMStateDescription vmstate_cadence_gem = { 1179 .name = "cadence_gem", 1180 .version_id = 1, 1181 .minimum_version_id = 1, 1182 .minimum_version_id_old = 1, 1183 .fields = (VMStateField[]) { 1184 VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG), 1185 VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32), 1186 VMSTATE_UINT8(phy_loop, GemState), 1187 VMSTATE_UINT32(rx_desc_addr, GemState), 1188 VMSTATE_UINT32(tx_desc_addr, GemState), 1189 } 1190 }; 1191 1192 static Property gem_properties[] = { 1193 DEFINE_NIC_PROPERTIES(GemState, conf), 1194 DEFINE_PROP_END_OF_LIST(), 1195 }; 1196 1197 static void gem_class_init(ObjectClass *klass, void *data) 1198 { 1199 DeviceClass *dc = DEVICE_CLASS(klass); 1200 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1201 1202 sdc->init = gem_init; 1203 dc->props = gem_properties; 1204 dc->vmsd = &vmstate_cadence_gem; 1205 dc->reset = gem_reset; 1206 } 1207 1208 static const TypeInfo gem_info = { 1209 .class_init = gem_class_init, 1210 .name = "cadence_gem", 1211 .parent = TYPE_SYS_BUS_DEVICE, 1212 .instance_size = sizeof(GemState), 1213 }; 1214 1215 static void gem_register_types(void) 1216 { 1217 type_register_static(&gem_info); 1218 } 1219 1220 type_init(gem_register_types) 1221